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1/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
3/*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30#include <linux/acpi.h>
31#include <linux/device.h>
32#include <linux/oom.h>
33#include <linux/module.h>
34#include <linux/pci.h>
35#include <linux/pm.h>
36#include <linux/pm_runtime.h>
37#include <linux/pnp.h>
38#include <linux/slab.h>
39#include <linux/vga_switcheroo.h>
40#include <linux/vt.h>
41#include <acpi/video.h>
42
43#include <drm/drm_atomic_helper.h>
44#include <drm/drm_ioctl.h>
45#include <drm/drm_irq.h>
46#include <drm/drm_managed.h>
47#include <drm/drm_probe_helper.h>
48
49#include "display/intel_acpi.h"
50#include "display/intel_audio.h"
51#include "display/intel_bw.h"
52#include "display/intel_cdclk.h"
53#include "display/intel_csr.h"
54#include "display/intel_display_debugfs.h"
55#include "display/intel_display_types.h"
56#include "display/intel_dp.h"
57#include "display/intel_fbdev.h"
58#include "display/intel_hotplug.h"
59#include "display/intel_overlay.h"
60#include "display/intel_pipe_crc.h"
61#include "display/intel_psr.h"
62#include "display/intel_sprite.h"
63#include "display/intel_vga.h"
64
65#include "gem/i915_gem_context.h"
66#include "gem/i915_gem_ioctls.h"
67#include "gem/i915_gem_mman.h"
68#include "gt/intel_gt.h"
69#include "gt/intel_gt_pm.h"
70#include "gt/intel_rc6.h"
71
72#include "i915_debugfs.h"
73#include "i915_drv.h"
74#include "i915_ioc32.h"
75#include "i915_irq.h"
76#include "i915_memcpy.h"
77#include "i915_perf.h"
78#include "i915_query.h"
79#include "i915_suspend.h"
80#include "i915_switcheroo.h"
81#include "i915_sysfs.h"
82#include "i915_trace.h"
83#include "i915_vgpu.h"
84#include "intel_dram.h"
85#include "intel_gvt.h"
86#include "intel_memory_region.h"
87#include "intel_pm.h"
88#include "vlv_suspend.h"
89
90static struct drm_driver driver;
91
92static int i915_get_bridge_dev(struct drm_i915_private *dev_priv)
93{
94 int domain = pci_domain_nr(dev_priv->drm.pdev->bus);
95
96 dev_priv->bridge_dev =
97 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
98 if (!dev_priv->bridge_dev) {
99 drm_err(&dev_priv->drm, "bridge device not found\n");
100 return -1;
101 }
102 return 0;
103}
104
105/* Allocate space for the MCH regs if needed, return nonzero on error */
106static int
107intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv)
108{
109 int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
110 u32 temp_lo, temp_hi = 0;
111 u64 mchbar_addr;
112 int ret;
113
114 if (INTEL_GEN(dev_priv) >= 4)
115 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
116 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
117 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
118
119 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
120#ifdef CONFIG_PNP
121 if (mchbar_addr &&
122 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
123 return 0;
124#endif
125
126 /* Get some space for it */
127 dev_priv->mch_res.name = "i915 MCHBAR";
128 dev_priv->mch_res.flags = IORESOURCE_MEM;
129 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
130 &dev_priv->mch_res,
131 MCHBAR_SIZE, MCHBAR_SIZE,
132 PCIBIOS_MIN_MEM,
133 0, pcibios_align_resource,
134 dev_priv->bridge_dev);
135 if (ret) {
136 drm_dbg(&dev_priv->drm, "failed bus alloc: %d\n", ret);
137 dev_priv->mch_res.start = 0;
138 return ret;
139 }
140
141 if (INTEL_GEN(dev_priv) >= 4)
142 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
143 upper_32_bits(dev_priv->mch_res.start));
144
145 pci_write_config_dword(dev_priv->bridge_dev, reg,
146 lower_32_bits(dev_priv->mch_res.start));
147 return 0;
148}
149
150/* Setup MCHBAR if possible, return true if we should disable it again */
151static void
152intel_setup_mchbar(struct drm_i915_private *dev_priv)
153{
154 int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
155 u32 temp;
156 bool enabled;
157
158 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
159 return;
160
161 dev_priv->mchbar_need_disable = false;
162
163 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
164 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
165 enabled = !!(temp & DEVEN_MCHBAR_EN);
166 } else {
167 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
168 enabled = temp & 1;
169 }
170
171 /* If it's already enabled, don't have to do anything */
172 if (enabled)
173 return;
174
175 if (intel_alloc_mchbar_resource(dev_priv))
176 return;
177
178 dev_priv->mchbar_need_disable = true;
179
180 /* Space is allocated or reserved, so enable it. */
181 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
182 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
183 temp | DEVEN_MCHBAR_EN);
184 } else {
185 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
186 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
187 }
188}
189
190static void
191intel_teardown_mchbar(struct drm_i915_private *dev_priv)
192{
193 int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
194
195 if (dev_priv->mchbar_need_disable) {
196 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
197 u32 deven_val;
198
199 pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
200 &deven_val);
201 deven_val &= ~DEVEN_MCHBAR_EN;
202 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
203 deven_val);
204 } else {
205 u32 mchbar_val;
206
207 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
208 &mchbar_val);
209 mchbar_val &= ~1;
210 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
211 mchbar_val);
212 }
213 }
214
215 if (dev_priv->mch_res.start)
216 release_resource(&dev_priv->mch_res);
217}
218
219/* part #1: call before irq install */
220static int i915_driver_modeset_probe_noirq(struct drm_i915_private *i915)
221{
222 int ret;
223
224 if (i915_inject_probe_failure(i915))
225 return -ENODEV;
226
227 if (HAS_DISPLAY(i915) && INTEL_DISPLAY_ENABLED(i915)) {
228 ret = drm_vblank_init(&i915->drm,
229 INTEL_NUM_PIPES(i915));
230 if (ret)
231 return ret;
232 }
233
234 intel_bios_init(i915);
235
236 ret = intel_vga_register(i915);
237 if (ret)
238 goto cleanup_bios;
239
240 intel_power_domains_init_hw(i915, false);
241
242 intel_csr_ucode_init(i915);
243
244 ret = intel_modeset_init_noirq(i915);
245 if (ret)
246 goto cleanup_vga_client_pw_domain_csr;
247
248 return 0;
249
250cleanup_vga_client_pw_domain_csr:
251 intel_csr_ucode_fini(i915);
252 intel_power_domains_driver_remove(i915);
253 intel_vga_unregister(i915);
254cleanup_bios:
255 intel_bios_driver_remove(i915);
256 return ret;
257}
258
259/* part #2: call after irq install */
260static int i915_driver_modeset_probe(struct drm_i915_private *i915)
261{
262 int ret;
263
264 /* Important: The output setup functions called by modeset_init need
265 * working irqs for e.g. gmbus and dp aux transfers. */
266 ret = intel_modeset_init(i915);
267 if (ret)
268 goto out;
269
270 ret = i915_gem_init(i915);
271 if (ret)
272 goto cleanup_modeset;
273
274 intel_overlay_setup(i915);
275
276 if (!HAS_DISPLAY(i915) || !INTEL_DISPLAY_ENABLED(i915))
277 return 0;
278
279 ret = intel_fbdev_init(&i915->drm);
280 if (ret)
281 goto cleanup_gem;
282
283 /* Only enable hotplug handling once the fbdev is fully set up. */
284 intel_hpd_init(i915);
285
286 intel_init_ipc(i915);
287
288 intel_psr_set_force_mode_changed(i915->psr.dp);
289
290 return 0;
291
292cleanup_gem:
293 i915_gem_suspend(i915);
294 i915_gem_driver_remove(i915);
295 i915_gem_driver_release(i915);
296cleanup_modeset:
297 /* FIXME */
298 intel_modeset_driver_remove(i915);
299 intel_irq_uninstall(i915);
300 intel_modeset_driver_remove_noirq(i915);
301out:
302 return ret;
303}
304
305/* part #1: call before irq uninstall */
306static void i915_driver_modeset_remove(struct drm_i915_private *i915)
307{
308 intel_modeset_driver_remove(i915);
309}
310
311/* part #2: call after irq uninstall */
312static void i915_driver_modeset_remove_noirq(struct drm_i915_private *i915)
313{
314 intel_csr_ucode_fini(i915);
315
316 intel_power_domains_driver_remove(i915);
317
318 intel_vga_unregister(i915);
319
320 intel_bios_driver_remove(i915);
321}
322
323static void intel_init_dpio(struct drm_i915_private *dev_priv)
324{
325 /*
326 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
327 * CHV x1 PHY (DP/HDMI D)
328 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
329 */
330 if (IS_CHERRYVIEW(dev_priv)) {
331 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
332 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
333 } else if (IS_VALLEYVIEW(dev_priv)) {
334 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
335 }
336}
337
338static int i915_workqueues_init(struct drm_i915_private *dev_priv)
339{
340 /*
341 * The i915 workqueue is primarily used for batched retirement of
342 * requests (and thus managing bo) once the task has been completed
343 * by the GPU. i915_retire_requests() is called directly when we
344 * need high-priority retirement, such as waiting for an explicit
345 * bo.
346 *
347 * It is also used for periodic low-priority events, such as
348 * idle-timers and recording error state.
349 *
350 * All tasks on the workqueue are expected to acquire the dev mutex
351 * so there is no point in running more than one instance of the
352 * workqueue at any time. Use an ordered one.
353 */
354 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
355 if (dev_priv->wq == NULL)
356 goto out_err;
357
358 dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
359 if (dev_priv->hotplug.dp_wq == NULL)
360 goto out_free_wq;
361
362 return 0;
363
364out_free_wq:
365 destroy_workqueue(dev_priv->wq);
366out_err:
367 drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n");
368
369 return -ENOMEM;
370}
371
372static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
373{
374 destroy_workqueue(dev_priv->hotplug.dp_wq);
375 destroy_workqueue(dev_priv->wq);
376}
377
378/*
379 * We don't keep the workarounds for pre-production hardware, so we expect our
380 * driver to fail on these machines in one way or another. A little warning on
381 * dmesg may help both the user and the bug triagers.
382 *
383 * Our policy for removing pre-production workarounds is to keep the
384 * current gen workarounds as a guide to the bring-up of the next gen
385 * (workarounds have a habit of persisting!). Anything older than that
386 * should be removed along with the complications they introduce.
387 */
388static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
389{
390 bool pre = false;
391
392 pre |= IS_HSW_EARLY_SDV(dev_priv);
393 pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
394 pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
395 pre |= IS_KBL_REVID(dev_priv, 0, KBL_REVID_A0);
396 pre |= IS_GLK_REVID(dev_priv, 0, GLK_REVID_A2);
397
398 if (pre) {
399 drm_err(&dev_priv->drm, "This is a pre-production stepping. "
400 "It may not be fully functional.\n");
401 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
402 }
403}
404
405static void sanitize_gpu(struct drm_i915_private *i915)
406{
407 if (!INTEL_INFO(i915)->gpu_reset_clobbers_display)
408 __intel_gt_reset(&i915->gt, ALL_ENGINES);
409}
410
411/**
412 * i915_driver_early_probe - setup state not requiring device access
413 * @dev_priv: device private
414 *
415 * Initialize everything that is a "SW-only" state, that is state not
416 * requiring accessing the device or exposing the driver via kernel internal
417 * or userspace interfaces. Example steps belonging here: lock initialization,
418 * system memory allocation, setting up device specific attributes and
419 * function hooks not requiring accessing the device.
420 */
421static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
422{
423 int ret = 0;
424
425 if (i915_inject_probe_failure(dev_priv))
426 return -ENODEV;
427
428 intel_device_info_subplatform_init(dev_priv);
429
430 intel_uncore_mmio_debug_init_early(&dev_priv->mmio_debug);
431 intel_uncore_init_early(&dev_priv->uncore, dev_priv);
432
433 spin_lock_init(&dev_priv->irq_lock);
434 spin_lock_init(&dev_priv->gpu_error.lock);
435 mutex_init(&dev_priv->backlight_lock);
436
437 mutex_init(&dev_priv->sb_lock);
438 cpu_latency_qos_add_request(&dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE);
439
440 mutex_init(&dev_priv->av_mutex);
441 mutex_init(&dev_priv->wm.wm_mutex);
442 mutex_init(&dev_priv->pps_mutex);
443 mutex_init(&dev_priv->hdcp_comp_mutex);
444
445 i915_memcpy_init_early(dev_priv);
446 intel_runtime_pm_init_early(&dev_priv->runtime_pm);
447
448 ret = i915_workqueues_init(dev_priv);
449 if (ret < 0)
450 return ret;
451
452 ret = vlv_suspend_init(dev_priv);
453 if (ret < 0)
454 goto err_workqueues;
455
456 intel_wopcm_init_early(&dev_priv->wopcm);
457
458 intel_gt_init_early(&dev_priv->gt, dev_priv);
459
460 i915_gem_init_early(dev_priv);
461
462 /* This must be called before any calls to HAS_PCH_* */
463 intel_detect_pch(dev_priv);
464
465 intel_pm_setup(dev_priv);
466 intel_init_dpio(dev_priv);
467 ret = intel_power_domains_init(dev_priv);
468 if (ret < 0)
469 goto err_gem;
470 intel_irq_init(dev_priv);
471 intel_init_display_hooks(dev_priv);
472 intel_init_clock_gating_hooks(dev_priv);
473 intel_init_audio_hooks(dev_priv);
474
475 intel_detect_preproduction_hw(dev_priv);
476
477 return 0;
478
479err_gem:
480 i915_gem_cleanup_early(dev_priv);
481 intel_gt_driver_late_release(&dev_priv->gt);
482 vlv_suspend_cleanup(dev_priv);
483err_workqueues:
484 i915_workqueues_cleanup(dev_priv);
485 return ret;
486}
487
488/**
489 * i915_driver_late_release - cleanup the setup done in
490 * i915_driver_early_probe()
491 * @dev_priv: device private
492 */
493static void i915_driver_late_release(struct drm_i915_private *dev_priv)
494{
495 intel_irq_fini(dev_priv);
496 intel_power_domains_cleanup(dev_priv);
497 i915_gem_cleanup_early(dev_priv);
498 intel_gt_driver_late_release(&dev_priv->gt);
499 vlv_suspend_cleanup(dev_priv);
500 i915_workqueues_cleanup(dev_priv);
501
502 cpu_latency_qos_remove_request(&dev_priv->sb_qos);
503 mutex_destroy(&dev_priv->sb_lock);
504
505 i915_params_free(&dev_priv->params);
506}
507
508/**
509 * i915_driver_mmio_probe - setup device MMIO
510 * @dev_priv: device private
511 *
512 * Setup minimal device state necessary for MMIO accesses later in the
513 * initialization sequence. The setup here should avoid any other device-wide
514 * side effects or exposing the driver via kernel internal or user space
515 * interfaces.
516 */
517static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
518{
519 int ret;
520
521 if (i915_inject_probe_failure(dev_priv))
522 return -ENODEV;
523
524 if (i915_get_bridge_dev(dev_priv))
525 return -EIO;
526
527 ret = intel_uncore_init_mmio(&dev_priv->uncore);
528 if (ret < 0)
529 goto err_bridge;
530
531 /* Try to make sure MCHBAR is enabled before poking at it */
532 intel_setup_mchbar(dev_priv);
533
534 ret = intel_gt_init_mmio(&dev_priv->gt);
535 if (ret)
536 goto err_uncore;
537
538 /* As early as possible, scrub existing GPU state before clobbering */
539 sanitize_gpu(dev_priv);
540
541 return 0;
542
543err_uncore:
544 intel_teardown_mchbar(dev_priv);
545 intel_uncore_fini_mmio(&dev_priv->uncore);
546err_bridge:
547 pci_dev_put(dev_priv->bridge_dev);
548
549 return ret;
550}
551
552/**
553 * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe()
554 * @dev_priv: device private
555 */
556static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
557{
558 intel_teardown_mchbar(dev_priv);
559 intel_uncore_fini_mmio(&dev_priv->uncore);
560 pci_dev_put(dev_priv->bridge_dev);
561}
562
563static void intel_sanitize_options(struct drm_i915_private *dev_priv)
564{
565 intel_gvt_sanitize_options(dev_priv);
566}
567
568/**
569 * i915_set_dma_info - set all relevant PCI dma info as configured for the
570 * platform
571 * @i915: valid i915 instance
572 *
573 * Set the dma max segment size, device and coherent masks. The dma mask set
574 * needs to occur before i915_ggtt_probe_hw.
575 *
576 * A couple of platforms have special needs. Address them as well.
577 *
578 */
579static int i915_set_dma_info(struct drm_i915_private *i915)
580{
581 struct pci_dev *pdev = i915->drm.pdev;
582 unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size;
583 int ret;
584
585 GEM_BUG_ON(!mask_size);
586
587 /*
588 * We don't have a max segment size, so set it to the max so sg's
589 * debugging layer doesn't complain
590 */
591 dma_set_max_seg_size(&pdev->dev, UINT_MAX);
592
593 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(mask_size));
594 if (ret)
595 goto mask_err;
596
597 /* overlay on gen2 is broken and can't address above 1G */
598 if (IS_GEN(i915, 2))
599 mask_size = 30;
600
601 /*
602 * 965GM sometimes incorrectly writes to hardware status page (HWS)
603 * using 32bit addressing, overwriting memory if HWS is located
604 * above 4GB.
605 *
606 * The documentation also mentions an issue with undefined
607 * behaviour if any general state is accessed within a page above 4GB,
608 * which also needs to be handled carefully.
609 */
610 if (IS_I965G(i915) || IS_I965GM(i915))
611 mask_size = 32;
612
613 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(mask_size));
614 if (ret)
615 goto mask_err;
616
617 return 0;
618
619mask_err:
620 drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n", ret);
621 return ret;
622}
623
624/**
625 * i915_driver_hw_probe - setup state requiring device access
626 * @dev_priv: device private
627 *
628 * Setup state that requires accessing the device, but doesn't require
629 * exposing the driver via kernel internal or userspace interfaces.
630 */
631static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
632{
633 struct pci_dev *pdev = dev_priv->drm.pdev;
634 int ret;
635
636 if (i915_inject_probe_failure(dev_priv))
637 return -ENODEV;
638
639 intel_device_info_runtime_init(dev_priv);
640
641 if (HAS_PPGTT(dev_priv)) {
642 if (intel_vgpu_active(dev_priv) &&
643 !intel_vgpu_has_full_ppgtt(dev_priv)) {
644 i915_report_error(dev_priv,
645 "incompatible vGPU found, support for isolated ppGTT required\n");
646 return -ENXIO;
647 }
648 }
649
650 if (HAS_EXECLISTS(dev_priv)) {
651 /*
652 * Older GVT emulation depends upon intercepting CSB mmio,
653 * which we no longer use, preferring to use the HWSP cache
654 * instead.
655 */
656 if (intel_vgpu_active(dev_priv) &&
657 !intel_vgpu_has_hwsp_emulation(dev_priv)) {
658 i915_report_error(dev_priv,
659 "old vGPU host found, support for HWSP emulation required\n");
660 return -ENXIO;
661 }
662 }
663
664 intel_sanitize_options(dev_priv);
665
666 /* needs to be done before ggtt probe */
667 intel_dram_edram_detect(dev_priv);
668
669 ret = i915_set_dma_info(dev_priv);
670 if (ret)
671 return ret;
672
673 i915_perf_init(dev_priv);
674
675 ret = i915_ggtt_probe_hw(dev_priv);
676 if (ret)
677 goto err_perf;
678
679 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "inteldrmfb");
680 if (ret)
681 goto err_ggtt;
682
683 ret = i915_ggtt_init_hw(dev_priv);
684 if (ret)
685 goto err_ggtt;
686
687 ret = intel_memory_regions_hw_probe(dev_priv);
688 if (ret)
689 goto err_ggtt;
690
691 intel_gt_init_hw_early(&dev_priv->gt, &dev_priv->ggtt);
692
693 ret = i915_ggtt_enable_hw(dev_priv);
694 if (ret) {
695 drm_err(&dev_priv->drm, "failed to enable GGTT\n");
696 goto err_mem_regions;
697 }
698
699 pci_set_master(pdev);
700
701 cpu_latency_qos_add_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
702
703 intel_gt_init_workarounds(dev_priv);
704
705 /* On the 945G/GM, the chipset reports the MSI capability on the
706 * integrated graphics even though the support isn't actually there
707 * according to the published specs. It doesn't appear to function
708 * correctly in testing on 945G.
709 * This may be a side effect of MSI having been made available for PEG
710 * and the registers being closely associated.
711 *
712 * According to chipset errata, on the 965GM, MSI interrupts may
713 * be lost or delayed, and was defeatured. MSI interrupts seem to
714 * get lost on g4x as well, and interrupt delivery seems to stay
715 * properly dead afterwards. So we'll just disable them for all
716 * pre-gen5 chipsets.
717 *
718 * dp aux and gmbus irq on gen4 seems to be able to generate legacy
719 * interrupts even when in MSI mode. This results in spurious
720 * interrupt warnings if the legacy irq no. is shared with another
721 * device. The kernel then disables that interrupt source and so
722 * prevents the other device from working properly.
723 */
724 if (INTEL_GEN(dev_priv) >= 5) {
725 if (pci_enable_msi(pdev) < 0)
726 drm_dbg(&dev_priv->drm, "can't enable MSI");
727 }
728
729 ret = intel_gvt_init(dev_priv);
730 if (ret)
731 goto err_msi;
732
733 intel_opregion_setup(dev_priv);
734 /*
735 * Fill the dram structure to get the system raw bandwidth and
736 * dram info. This will be used for memory latency calculation.
737 */
738 intel_dram_detect(dev_priv);
739
740 intel_bw_init_hw(dev_priv);
741
742 return 0;
743
744err_msi:
745 if (pdev->msi_enabled)
746 pci_disable_msi(pdev);
747 cpu_latency_qos_remove_request(&dev_priv->pm_qos);
748err_mem_regions:
749 intel_memory_regions_driver_release(dev_priv);
750err_ggtt:
751 i915_ggtt_driver_release(dev_priv);
752err_perf:
753 i915_perf_fini(dev_priv);
754 return ret;
755}
756
757/**
758 * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe()
759 * @dev_priv: device private
760 */
761static void i915_driver_hw_remove(struct drm_i915_private *dev_priv)
762{
763 struct pci_dev *pdev = dev_priv->drm.pdev;
764
765 i915_perf_fini(dev_priv);
766
767 if (pdev->msi_enabled)
768 pci_disable_msi(pdev);
769
770 cpu_latency_qos_remove_request(&dev_priv->pm_qos);
771}
772
773/**
774 * i915_driver_register - register the driver with the rest of the system
775 * @dev_priv: device private
776 *
777 * Perform any steps necessary to make the driver available via kernel
778 * internal or userspace interfaces.
779 */
780static void i915_driver_register(struct drm_i915_private *dev_priv)
781{
782 struct drm_device *dev = &dev_priv->drm;
783
784 i915_gem_driver_register(dev_priv);
785 i915_pmu_register(dev_priv);
786
787 intel_vgpu_register(dev_priv);
788
789 /* Reveal our presence to userspace */
790 if (drm_dev_register(dev, 0) == 0) {
791 i915_debugfs_register(dev_priv);
792 intel_display_debugfs_register(dev_priv);
793 i915_setup_sysfs(dev_priv);
794
795 /* Depends on sysfs having been initialized */
796 i915_perf_register(dev_priv);
797 } else
798 drm_err(&dev_priv->drm,
799 "Failed to register driver for userspace access!\n");
800
801 if (HAS_DISPLAY(dev_priv) && INTEL_DISPLAY_ENABLED(dev_priv)) {
802 /* Must be done after probing outputs */
803 intel_opregion_register(dev_priv);
804 acpi_video_register();
805 }
806
807 intel_gt_driver_register(&dev_priv->gt);
808
809 intel_audio_init(dev_priv);
810
811 /*
812 * Some ports require correctly set-up hpd registers for detection to
813 * work properly (leading to ghost connected connector status), e.g. VGA
814 * on gm45. Hence we can only set up the initial fbdev config after hpd
815 * irqs are fully enabled. We do it last so that the async config
816 * cannot run before the connectors are registered.
817 */
818 intel_fbdev_initial_config_async(dev);
819
820 /*
821 * We need to coordinate the hotplugs with the asynchronous fbdev
822 * configuration, for which we use the fbdev->async_cookie.
823 */
824 if (HAS_DISPLAY(dev_priv) && INTEL_DISPLAY_ENABLED(dev_priv))
825 drm_kms_helper_poll_init(dev);
826
827 intel_power_domains_enable(dev_priv);
828 intel_runtime_pm_enable(&dev_priv->runtime_pm);
829
830 intel_register_dsm_handler();
831
832 if (i915_switcheroo_register(dev_priv))
833 drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n");
834}
835
836/**
837 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
838 * @dev_priv: device private
839 */
840static void i915_driver_unregister(struct drm_i915_private *dev_priv)
841{
842 i915_switcheroo_unregister(dev_priv);
843
844 intel_unregister_dsm_handler();
845
846 intel_runtime_pm_disable(&dev_priv->runtime_pm);
847 intel_power_domains_disable(dev_priv);
848
849 intel_fbdev_unregister(dev_priv);
850 intel_audio_deinit(dev_priv);
851
852 /*
853 * After flushing the fbdev (incl. a late async config which will
854 * have delayed queuing of a hotplug event), then flush the hotplug
855 * events.
856 */
857 drm_kms_helper_poll_fini(&dev_priv->drm);
858
859 intel_gt_driver_unregister(&dev_priv->gt);
860 acpi_video_unregister();
861 intel_opregion_unregister(dev_priv);
862
863 i915_perf_unregister(dev_priv);
864 i915_pmu_unregister(dev_priv);
865
866 i915_teardown_sysfs(dev_priv);
867 drm_dev_unplug(&dev_priv->drm);
868
869 i915_gem_driver_unregister(dev_priv);
870}
871
872static void i915_welcome_messages(struct drm_i915_private *dev_priv)
873{
874 if (drm_debug_enabled(DRM_UT_DRIVER)) {
875 struct drm_printer p = drm_debug_printer("i915 device info:");
876
877 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
878 INTEL_DEVID(dev_priv),
879 INTEL_REVID(dev_priv),
880 intel_platform_name(INTEL_INFO(dev_priv)->platform),
881 intel_subplatform(RUNTIME_INFO(dev_priv),
882 INTEL_INFO(dev_priv)->platform),
883 INTEL_GEN(dev_priv));
884
885 intel_device_info_print_static(INTEL_INFO(dev_priv), &p);
886 intel_device_info_print_runtime(RUNTIME_INFO(dev_priv), &p);
887 intel_gt_info_print(&dev_priv->gt.info, &p);
888 }
889
890 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
891 drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n");
892 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
893 drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n");
894 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
895 drm_info(&dev_priv->drm,
896 "DRM_I915_DEBUG_RUNTIME_PM enabled\n");
897}
898
899static struct drm_i915_private *
900i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
901{
902 const struct intel_device_info *match_info =
903 (struct intel_device_info *)ent->driver_data;
904 struct intel_device_info *device_info;
905 struct drm_i915_private *i915;
906
907 i915 = devm_drm_dev_alloc(&pdev->dev, &driver,
908 struct drm_i915_private, drm);
909 if (IS_ERR(i915))
910 return i915;
911
912 i915->drm.pdev = pdev;
913 pci_set_drvdata(pdev, i915);
914
915 /* Device parameters start as a copy of module parameters. */
916 i915_params_copy(&i915->params, &i915_modparams);
917
918 /* Setup the write-once "constant" device info */
919 device_info = mkwrite_device_info(i915);
920 memcpy(device_info, match_info, sizeof(*device_info));
921 RUNTIME_INFO(i915)->device_id = pdev->device;
922
923 BUG_ON(device_info->gen > BITS_PER_TYPE(device_info->gen_mask));
924
925 return i915;
926}
927
928/**
929 * i915_driver_probe - setup chip and create an initial config
930 * @pdev: PCI device
931 * @ent: matching PCI ID entry
932 *
933 * The driver probe routine has to do several things:
934 * - drive output discovery via intel_modeset_init()
935 * - initialize the memory manager
936 * - allocate initial config memory
937 * - setup the DRM framebuffer with the allocated memory
938 */
939int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
940{
941 const struct intel_device_info *match_info =
942 (struct intel_device_info *)ent->driver_data;
943 struct drm_i915_private *i915;
944 int ret;
945
946 i915 = i915_driver_create(pdev, ent);
947 if (IS_ERR(i915))
948 return PTR_ERR(i915);
949
950 /* Disable nuclear pageflip by default on pre-ILK */
951 if (!i915->params.nuclear_pageflip && match_info->gen < 5)
952 i915->drm.driver_features &= ~DRIVER_ATOMIC;
953
954 /*
955 * Check if we support fake LMEM -- for now we only unleash this for
956 * the live selftests(test-and-exit).
957 */
958#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
959 if (IS_ENABLED(CONFIG_DRM_I915_UNSTABLE_FAKE_LMEM)) {
960 if (INTEL_GEN(i915) >= 9 && i915_selftest.live < 0 &&
961 i915->params.fake_lmem_start) {
962 mkwrite_device_info(i915)->memory_regions =
963 REGION_SMEM | REGION_LMEM | REGION_STOLEN;
964 mkwrite_device_info(i915)->is_dgfx = true;
965 GEM_BUG_ON(!HAS_LMEM(i915));
966 GEM_BUG_ON(!IS_DGFX(i915));
967 }
968 }
969#endif
970
971 ret = pci_enable_device(pdev);
972 if (ret)
973 goto out_fini;
974
975 ret = i915_driver_early_probe(i915);
976 if (ret < 0)
977 goto out_pci_disable;
978
979 disable_rpm_wakeref_asserts(&i915->runtime_pm);
980
981 intel_vgpu_detect(i915);
982
983 ret = i915_driver_mmio_probe(i915);
984 if (ret < 0)
985 goto out_runtime_pm_put;
986
987 ret = i915_driver_hw_probe(i915);
988 if (ret < 0)
989 goto out_cleanup_mmio;
990
991 ret = i915_driver_modeset_probe_noirq(i915);
992 if (ret < 0)
993 goto out_cleanup_hw;
994
995 ret = intel_irq_install(i915);
996 if (ret)
997 goto out_cleanup_modeset;
998
999 ret = i915_driver_modeset_probe(i915);
1000 if (ret < 0)
1001 goto out_cleanup_irq;
1002
1003 i915_driver_register(i915);
1004
1005 enable_rpm_wakeref_asserts(&i915->runtime_pm);
1006
1007 i915_welcome_messages(i915);
1008
1009 i915->do_release = true;
1010
1011 return 0;
1012
1013out_cleanup_irq:
1014 intel_irq_uninstall(i915);
1015out_cleanup_modeset:
1016 i915_driver_modeset_remove_noirq(i915);
1017out_cleanup_hw:
1018 i915_driver_hw_remove(i915);
1019 intel_memory_regions_driver_release(i915);
1020 i915_ggtt_driver_release(i915);
1021out_cleanup_mmio:
1022 i915_driver_mmio_release(i915);
1023out_runtime_pm_put:
1024 enable_rpm_wakeref_asserts(&i915->runtime_pm);
1025 i915_driver_late_release(i915);
1026out_pci_disable:
1027 pci_disable_device(pdev);
1028out_fini:
1029 i915_probe_error(i915, "Device initialization failed (%d)\n", ret);
1030 return ret;
1031}
1032
1033void i915_driver_remove(struct drm_i915_private *i915)
1034{
1035 disable_rpm_wakeref_asserts(&i915->runtime_pm);
1036
1037 i915_driver_unregister(i915);
1038
1039 /* Flush any external code that still may be under the RCU lock */
1040 synchronize_rcu();
1041
1042 i915_gem_suspend(i915);
1043
1044 drm_atomic_helper_shutdown(&i915->drm);
1045
1046 intel_gvt_driver_remove(i915);
1047
1048 i915_driver_modeset_remove(i915);
1049
1050 intel_irq_uninstall(i915);
1051
1052 intel_modeset_driver_remove_noirq(i915);
1053
1054 i915_reset_error_state(i915);
1055 i915_gem_driver_remove(i915);
1056
1057 i915_driver_modeset_remove_noirq(i915);
1058
1059 i915_driver_hw_remove(i915);
1060
1061 enable_rpm_wakeref_asserts(&i915->runtime_pm);
1062}
1063
1064static void i915_driver_release(struct drm_device *dev)
1065{
1066 struct drm_i915_private *dev_priv = to_i915(dev);
1067 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1068
1069 if (!dev_priv->do_release)
1070 return;
1071
1072 disable_rpm_wakeref_asserts(rpm);
1073
1074 i915_gem_driver_release(dev_priv);
1075
1076 intel_memory_regions_driver_release(dev_priv);
1077 i915_ggtt_driver_release(dev_priv);
1078
1079 i915_driver_mmio_release(dev_priv);
1080
1081 enable_rpm_wakeref_asserts(rpm);
1082 intel_runtime_pm_driver_release(rpm);
1083
1084 i915_driver_late_release(dev_priv);
1085}
1086
1087static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1088{
1089 struct drm_i915_private *i915 = to_i915(dev);
1090 int ret;
1091
1092 ret = i915_gem_open(i915, file);
1093 if (ret)
1094 return ret;
1095
1096 return 0;
1097}
1098
1099/**
1100 * i915_driver_lastclose - clean up after all DRM clients have exited
1101 * @dev: DRM device
1102 *
1103 * Take care of cleaning up after all DRM clients have exited. In the
1104 * mode setting case, we want to restore the kernel's initial mode (just
1105 * in case the last client left us in a bad state).
1106 *
1107 * Additionally, in the non-mode setting case, we'll tear down the GTT
1108 * and DMA structures, since the kernel won't be using them, and clea
1109 * up any GEM state.
1110 */
1111static void i915_driver_lastclose(struct drm_device *dev)
1112{
1113 intel_fbdev_restore_mode(dev);
1114 vga_switcheroo_process_delayed_switch();
1115}
1116
1117static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1118{
1119 struct drm_i915_file_private *file_priv = file->driver_priv;
1120
1121 i915_gem_context_close(file);
1122 i915_gem_release(dev, file);
1123
1124 kfree_rcu(file_priv, rcu);
1125
1126 /* Catch up with all the deferred frees from "this" client */
1127 i915_gem_flush_free_objects(to_i915(dev));
1128}
1129
1130static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1131{
1132 struct drm_device *dev = &dev_priv->drm;
1133 struct intel_encoder *encoder;
1134
1135 drm_modeset_lock_all(dev);
1136 for_each_intel_encoder(dev, encoder)
1137 if (encoder->suspend)
1138 encoder->suspend(encoder);
1139 drm_modeset_unlock_all(dev);
1140}
1141
1142static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1143{
1144#if IS_ENABLED(CONFIG_ACPI_SLEEP)
1145 if (acpi_target_system_state() < ACPI_STATE_S3)
1146 return true;
1147#endif
1148 return false;
1149}
1150
1151static int i915_drm_prepare(struct drm_device *dev)
1152{
1153 struct drm_i915_private *i915 = to_i915(dev);
1154
1155 /*
1156 * NB intel_display_suspend() may issue new requests after we've
1157 * ostensibly marked the GPU as ready-to-sleep here. We need to
1158 * split out that work and pull it forward so that after point,
1159 * the GPU is not woken again.
1160 */
1161 i915_gem_suspend(i915);
1162
1163 return 0;
1164}
1165
1166static int i915_drm_suspend(struct drm_device *dev)
1167{
1168 struct drm_i915_private *dev_priv = to_i915(dev);
1169 struct pci_dev *pdev = dev_priv->drm.pdev;
1170 pci_power_t opregion_target_state;
1171
1172 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1173
1174 /* We do a lot of poking in a lot of registers, make sure they work
1175 * properly. */
1176 intel_power_domains_disable(dev_priv);
1177
1178 drm_kms_helper_poll_disable(dev);
1179
1180 pci_save_state(pdev);
1181
1182 intel_display_suspend(dev);
1183
1184 intel_dp_mst_suspend(dev_priv);
1185
1186 intel_runtime_pm_disable_interrupts(dev_priv);
1187 intel_hpd_cancel_work(dev_priv);
1188
1189 intel_suspend_encoders(dev_priv);
1190
1191 intel_suspend_hw(dev_priv);
1192
1193 i915_ggtt_suspend(&dev_priv->ggtt);
1194
1195 i915_save_state(dev_priv);
1196
1197 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1198 intel_opregion_suspend(dev_priv, opregion_target_state);
1199
1200 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1201
1202 dev_priv->suspend_count++;
1203
1204 intel_csr_ucode_suspend(dev_priv);
1205
1206 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1207
1208 return 0;
1209}
1210
1211static enum i915_drm_suspend_mode
1212get_suspend_mode(struct drm_i915_private *dev_priv, bool hibernate)
1213{
1214 if (hibernate)
1215 return I915_DRM_SUSPEND_HIBERNATE;
1216
1217 if (suspend_to_idle(dev_priv))
1218 return I915_DRM_SUSPEND_IDLE;
1219
1220 return I915_DRM_SUSPEND_MEM;
1221}
1222
1223static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1224{
1225 struct drm_i915_private *dev_priv = to_i915(dev);
1226 struct pci_dev *pdev = dev_priv->drm.pdev;
1227 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1228 int ret;
1229
1230 disable_rpm_wakeref_asserts(rpm);
1231
1232 i915_gem_suspend_late(dev_priv);
1233
1234 intel_uncore_suspend(&dev_priv->uncore);
1235
1236 intel_power_domains_suspend(dev_priv,
1237 get_suspend_mode(dev_priv, hibernation));
1238
1239 intel_display_power_suspend_late(dev_priv);
1240
1241 ret = vlv_suspend_complete(dev_priv);
1242 if (ret) {
1243 drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret);
1244 intel_power_domains_resume(dev_priv);
1245
1246 goto out;
1247 }
1248
1249 pci_disable_device(pdev);
1250 /*
1251 * During hibernation on some platforms the BIOS may try to access
1252 * the device even though it's already in D3 and hang the machine. So
1253 * leave the device in D0 on those platforms and hope the BIOS will
1254 * power down the device properly. The issue was seen on multiple old
1255 * GENs with different BIOS vendors, so having an explicit blacklist
1256 * is inpractical; apply the workaround on everything pre GEN6. The
1257 * platforms where the issue was seen:
1258 * Lenovo Thinkpad X301, X61s, X60, T60, X41
1259 * Fujitsu FSC S7110
1260 * Acer Aspire 1830T
1261 */
1262 if (!(hibernation && INTEL_GEN(dev_priv) < 6))
1263 pci_set_power_state(pdev, PCI_D3hot);
1264
1265out:
1266 enable_rpm_wakeref_asserts(rpm);
1267 if (!dev_priv->uncore.user_forcewake_count)
1268 intel_runtime_pm_driver_release(rpm);
1269
1270 return ret;
1271}
1272
1273int i915_suspend_switcheroo(struct drm_i915_private *i915, pm_message_t state)
1274{
1275 int error;
1276
1277 if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND &&
1278 state.event != PM_EVENT_FREEZE))
1279 return -EINVAL;
1280
1281 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1282 return 0;
1283
1284 error = i915_drm_suspend(&i915->drm);
1285 if (error)
1286 return error;
1287
1288 return i915_drm_suspend_late(&i915->drm, false);
1289}
1290
1291static int i915_drm_resume(struct drm_device *dev)
1292{
1293 struct drm_i915_private *dev_priv = to_i915(dev);
1294 int ret;
1295
1296 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1297
1298 sanitize_gpu(dev_priv);
1299
1300 ret = i915_ggtt_enable_hw(dev_priv);
1301 if (ret)
1302 drm_err(&dev_priv->drm, "failed to re-enable GGTT\n");
1303
1304 i915_ggtt_resume(&dev_priv->ggtt);
1305
1306 intel_csr_ucode_resume(dev_priv);
1307
1308 i915_restore_state(dev_priv);
1309 intel_pps_unlock_regs_wa(dev_priv);
1310
1311 intel_init_pch_refclk(dev_priv);
1312
1313 /*
1314 * Interrupts have to be enabled before any batches are run. If not the
1315 * GPU will hang. i915_gem_init_hw() will initiate batches to
1316 * update/restore the context.
1317 *
1318 * drm_mode_config_reset() needs AUX interrupts.
1319 *
1320 * Modeset enabling in intel_modeset_init_hw() also needs working
1321 * interrupts.
1322 */
1323 intel_runtime_pm_enable_interrupts(dev_priv);
1324
1325 drm_mode_config_reset(dev);
1326
1327 i915_gem_resume(dev_priv);
1328
1329 intel_modeset_init_hw(dev_priv);
1330 intel_init_clock_gating(dev_priv);
1331
1332 spin_lock_irq(&dev_priv->irq_lock);
1333 if (dev_priv->display.hpd_irq_setup)
1334 dev_priv->display.hpd_irq_setup(dev_priv);
1335 spin_unlock_irq(&dev_priv->irq_lock);
1336
1337 intel_dp_mst_resume(dev_priv);
1338
1339 intel_display_resume(dev);
1340
1341 drm_kms_helper_poll_enable(dev);
1342
1343 /*
1344 * ... but also need to make sure that hotplug processing
1345 * doesn't cause havoc. Like in the driver load code we don't
1346 * bother with the tiny race here where we might lose hotplug
1347 * notifications.
1348 * */
1349 intel_hpd_init(dev_priv);
1350
1351 intel_opregion_resume(dev_priv);
1352
1353 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1354
1355 intel_power_domains_enable(dev_priv);
1356
1357 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1358
1359 return 0;
1360}
1361
1362static int i915_drm_resume_early(struct drm_device *dev)
1363{
1364 struct drm_i915_private *dev_priv = to_i915(dev);
1365 struct pci_dev *pdev = dev_priv->drm.pdev;
1366 int ret;
1367
1368 /*
1369 * We have a resume ordering issue with the snd-hda driver also
1370 * requiring our device to be power up. Due to the lack of a
1371 * parent/child relationship we currently solve this with an early
1372 * resume hook.
1373 *
1374 * FIXME: This should be solved with a special hdmi sink device or
1375 * similar so that power domains can be employed.
1376 */
1377
1378 /*
1379 * Note that we need to set the power state explicitly, since we
1380 * powered off the device during freeze and the PCI core won't power
1381 * it back up for us during thaw. Powering off the device during
1382 * freeze is not a hard requirement though, and during the
1383 * suspend/resume phases the PCI core makes sure we get here with the
1384 * device powered on. So in case we change our freeze logic and keep
1385 * the device powered we can also remove the following set power state
1386 * call.
1387 */
1388 ret = pci_set_power_state(pdev, PCI_D0);
1389 if (ret) {
1390 drm_err(&dev_priv->drm,
1391 "failed to set PCI D0 power state (%d)\n", ret);
1392 return ret;
1393 }
1394
1395 /*
1396 * Note that pci_enable_device() first enables any parent bridge
1397 * device and only then sets the power state for this device. The
1398 * bridge enabling is a nop though, since bridge devices are resumed
1399 * first. The order of enabling power and enabling the device is
1400 * imposed by the PCI core as described above, so here we preserve the
1401 * same order for the freeze/thaw phases.
1402 *
1403 * TODO: eventually we should remove pci_disable_device() /
1404 * pci_enable_enable_device() from suspend/resume. Due to how they
1405 * depend on the device enable refcount we can't anyway depend on them
1406 * disabling/enabling the device.
1407 */
1408 if (pci_enable_device(pdev))
1409 return -EIO;
1410
1411 pci_set_master(pdev);
1412
1413 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1414
1415 ret = vlv_resume_prepare(dev_priv, false);
1416 if (ret)
1417 drm_err(&dev_priv->drm,
1418 "Resume prepare failed: %d, continuing anyway\n", ret);
1419
1420 intel_uncore_resume_early(&dev_priv->uncore);
1421
1422 intel_gt_check_and_clear_faults(&dev_priv->gt);
1423
1424 intel_display_power_resume_early(dev_priv);
1425
1426 intel_power_domains_resume(dev_priv);
1427
1428 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1429
1430 return ret;
1431}
1432
1433int i915_resume_switcheroo(struct drm_i915_private *i915)
1434{
1435 int ret;
1436
1437 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1438 return 0;
1439
1440 ret = i915_drm_resume_early(&i915->drm);
1441 if (ret)
1442 return ret;
1443
1444 return i915_drm_resume(&i915->drm);
1445}
1446
1447static int i915_pm_prepare(struct device *kdev)
1448{
1449 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1450
1451 if (!i915) {
1452 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1453 return -ENODEV;
1454 }
1455
1456 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1457 return 0;
1458
1459 return i915_drm_prepare(&i915->drm);
1460}
1461
1462static int i915_pm_suspend(struct device *kdev)
1463{
1464 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1465
1466 if (!i915) {
1467 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1468 return -ENODEV;
1469 }
1470
1471 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1472 return 0;
1473
1474 return i915_drm_suspend(&i915->drm);
1475}
1476
1477static int i915_pm_suspend_late(struct device *kdev)
1478{
1479 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1480
1481 /*
1482 * We have a suspend ordering issue with the snd-hda driver also
1483 * requiring our device to be power up. Due to the lack of a
1484 * parent/child relationship we currently solve this with an late
1485 * suspend hook.
1486 *
1487 * FIXME: This should be solved with a special hdmi sink device or
1488 * similar so that power domains can be employed.
1489 */
1490 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1491 return 0;
1492
1493 return i915_drm_suspend_late(&i915->drm, false);
1494}
1495
1496static int i915_pm_poweroff_late(struct device *kdev)
1497{
1498 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1499
1500 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1501 return 0;
1502
1503 return i915_drm_suspend_late(&i915->drm, true);
1504}
1505
1506static int i915_pm_resume_early(struct device *kdev)
1507{
1508 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1509
1510 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1511 return 0;
1512
1513 return i915_drm_resume_early(&i915->drm);
1514}
1515
1516static int i915_pm_resume(struct device *kdev)
1517{
1518 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1519
1520 if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1521 return 0;
1522
1523 return i915_drm_resume(&i915->drm);
1524}
1525
1526/* freeze: before creating the hibernation_image */
1527static int i915_pm_freeze(struct device *kdev)
1528{
1529 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1530 int ret;
1531
1532 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1533 ret = i915_drm_suspend(&i915->drm);
1534 if (ret)
1535 return ret;
1536 }
1537
1538 ret = i915_gem_freeze(i915);
1539 if (ret)
1540 return ret;
1541
1542 return 0;
1543}
1544
1545static int i915_pm_freeze_late(struct device *kdev)
1546{
1547 struct drm_i915_private *i915 = kdev_to_i915(kdev);
1548 int ret;
1549
1550 if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1551 ret = i915_drm_suspend_late(&i915->drm, true);
1552 if (ret)
1553 return ret;
1554 }
1555
1556 ret = i915_gem_freeze_late(i915);
1557 if (ret)
1558 return ret;
1559
1560 return 0;
1561}
1562
1563/* thaw: called after creating the hibernation image, but before turning off. */
1564static int i915_pm_thaw_early(struct device *kdev)
1565{
1566 return i915_pm_resume_early(kdev);
1567}
1568
1569static int i915_pm_thaw(struct device *kdev)
1570{
1571 return i915_pm_resume(kdev);
1572}
1573
1574/* restore: called after loading the hibernation image. */
1575static int i915_pm_restore_early(struct device *kdev)
1576{
1577 return i915_pm_resume_early(kdev);
1578}
1579
1580static int i915_pm_restore(struct device *kdev)
1581{
1582 return i915_pm_resume(kdev);
1583}
1584
1585static int intel_runtime_suspend(struct device *kdev)
1586{
1587 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1588 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1589 int ret;
1590
1591 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1592 return -ENODEV;
1593
1594 drm_dbg_kms(&dev_priv->drm, "Suspending device\n");
1595
1596 disable_rpm_wakeref_asserts(rpm);
1597
1598 /*
1599 * We are safe here against re-faults, since the fault handler takes
1600 * an RPM reference.
1601 */
1602 i915_gem_runtime_suspend(dev_priv);
1603
1604 intel_gt_runtime_suspend(&dev_priv->gt);
1605
1606 intel_runtime_pm_disable_interrupts(dev_priv);
1607
1608 intel_uncore_suspend(&dev_priv->uncore);
1609
1610 intel_display_power_suspend(dev_priv);
1611
1612 ret = vlv_suspend_complete(dev_priv);
1613 if (ret) {
1614 drm_err(&dev_priv->drm,
1615 "Runtime suspend failed, disabling it (%d)\n", ret);
1616 intel_uncore_runtime_resume(&dev_priv->uncore);
1617
1618 intel_runtime_pm_enable_interrupts(dev_priv);
1619
1620 intel_gt_runtime_resume(&dev_priv->gt);
1621
1622 enable_rpm_wakeref_asserts(rpm);
1623
1624 return ret;
1625 }
1626
1627 enable_rpm_wakeref_asserts(rpm);
1628 intel_runtime_pm_driver_release(rpm);
1629
1630 if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))
1631 drm_err(&dev_priv->drm,
1632 "Unclaimed access detected prior to suspending\n");
1633
1634 rpm->suspended = true;
1635
1636 /*
1637 * FIXME: We really should find a document that references the arguments
1638 * used below!
1639 */
1640 if (IS_BROADWELL(dev_priv)) {
1641 /*
1642 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1643 * being detected, and the call we do at intel_runtime_resume()
1644 * won't be able to restore them. Since PCI_D3hot matches the
1645 * actual specification and appears to be working, use it.
1646 */
1647 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
1648 } else {
1649 /*
1650 * current versions of firmware which depend on this opregion
1651 * notification have repurposed the D1 definition to mean
1652 * "runtime suspended" vs. what you would normally expect (D3)
1653 * to distinguish it from notifications that might be sent via
1654 * the suspend path.
1655 */
1656 intel_opregion_notify_adapter(dev_priv, PCI_D1);
1657 }
1658
1659 assert_forcewakes_inactive(&dev_priv->uncore);
1660
1661 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
1662 intel_hpd_poll_init(dev_priv);
1663
1664 drm_dbg_kms(&dev_priv->drm, "Device suspended\n");
1665 return 0;
1666}
1667
1668static int intel_runtime_resume(struct device *kdev)
1669{
1670 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1671 struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1672 int ret;
1673
1674 if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1675 return -ENODEV;
1676
1677 drm_dbg_kms(&dev_priv->drm, "Resuming device\n");
1678
1679 drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count));
1680 disable_rpm_wakeref_asserts(rpm);
1681
1682 intel_opregion_notify_adapter(dev_priv, PCI_D0);
1683 rpm->suspended = false;
1684 if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
1685 drm_dbg(&dev_priv->drm,
1686 "Unclaimed access during suspend, bios?\n");
1687
1688 intel_display_power_resume(dev_priv);
1689
1690 ret = vlv_resume_prepare(dev_priv, true);
1691
1692 intel_uncore_runtime_resume(&dev_priv->uncore);
1693
1694 intel_runtime_pm_enable_interrupts(dev_priv);
1695
1696 /*
1697 * No point of rolling back things in case of an error, as the best
1698 * we can do is to hope that things will still work (and disable RPM).
1699 */
1700 intel_gt_runtime_resume(&dev_priv->gt);
1701
1702 /*
1703 * On VLV/CHV display interrupts are part of the display
1704 * power well, so hpd is reinitialized from there. For
1705 * everyone else do it here.
1706 */
1707 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
1708 intel_hpd_init(dev_priv);
1709
1710 intel_enable_ipc(dev_priv);
1711
1712 enable_rpm_wakeref_asserts(rpm);
1713
1714 if (ret)
1715 drm_err(&dev_priv->drm,
1716 "Runtime resume failed, disabling it (%d)\n", ret);
1717 else
1718 drm_dbg_kms(&dev_priv->drm, "Device resumed\n");
1719
1720 return ret;
1721}
1722
1723const struct dev_pm_ops i915_pm_ops = {
1724 /*
1725 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1726 * PMSG_RESUME]
1727 */
1728 .prepare = i915_pm_prepare,
1729 .suspend = i915_pm_suspend,
1730 .suspend_late = i915_pm_suspend_late,
1731 .resume_early = i915_pm_resume_early,
1732 .resume = i915_pm_resume,
1733
1734 /*
1735 * S4 event handlers
1736 * @freeze, @freeze_late : called (1) before creating the
1737 * hibernation image [PMSG_FREEZE] and
1738 * (2) after rebooting, before restoring
1739 * the image [PMSG_QUIESCE]
1740 * @thaw, @thaw_early : called (1) after creating the hibernation
1741 * image, before writing it [PMSG_THAW]
1742 * and (2) after failing to create or
1743 * restore the image [PMSG_RECOVER]
1744 * @poweroff, @poweroff_late: called after writing the hibernation
1745 * image, before rebooting [PMSG_HIBERNATE]
1746 * @restore, @restore_early : called after rebooting and restoring the
1747 * hibernation image [PMSG_RESTORE]
1748 */
1749 .freeze = i915_pm_freeze,
1750 .freeze_late = i915_pm_freeze_late,
1751 .thaw_early = i915_pm_thaw_early,
1752 .thaw = i915_pm_thaw,
1753 .poweroff = i915_pm_suspend,
1754 .poweroff_late = i915_pm_poweroff_late,
1755 .restore_early = i915_pm_restore_early,
1756 .restore = i915_pm_restore,
1757
1758 /* S0ix (via runtime suspend) event handlers */
1759 .runtime_suspend = intel_runtime_suspend,
1760 .runtime_resume = intel_runtime_resume,
1761};
1762
1763static const struct file_operations i915_driver_fops = {
1764 .owner = THIS_MODULE,
1765 .open = drm_open,
1766 .release = drm_release_noglobal,
1767 .unlocked_ioctl = drm_ioctl,
1768 .mmap = i915_gem_mmap,
1769 .poll = drm_poll,
1770 .read = drm_read,
1771 .compat_ioctl = i915_ioc32_compat_ioctl,
1772 .llseek = noop_llseek,
1773};
1774
1775static int
1776i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
1777 struct drm_file *file)
1778{
1779 return -ENODEV;
1780}
1781
1782static const struct drm_ioctl_desc i915_ioctls[] = {
1783 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1784 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1785 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1786 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1787 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1788 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1789 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW),
1790 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1791 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1792 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1793 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1794 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1795 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1796 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1797 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH),
1798 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1799 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1800 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1801 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer_ioctl, DRM_AUTH),
1802 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW),
1803 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1804 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1805 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW),
1806 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
1807 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
1808 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
1809 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1810 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1811 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
1812 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
1813 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
1814 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
1815 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW),
1816 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
1817 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
1818 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
1819 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
1820 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
1821 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
1822 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
1823 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
1824 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
1825 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
1826 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
1827 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW),
1828 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
1829 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
1830 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
1831 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
1832 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
1833 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
1834 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
1835 DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
1836 DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW),
1837 DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW),
1838 DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW),
1839 DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW),
1840 DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW),
1841};
1842
1843static struct drm_driver driver = {
1844 /* Don't use MTRRs here; the Xserver or userspace app should
1845 * deal with them for Intel hardware.
1846 */
1847 .driver_features =
1848 DRIVER_GEM |
1849 DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ,
1850 .release = i915_driver_release,
1851 .open = i915_driver_open,
1852 .lastclose = i915_driver_lastclose,
1853 .postclose = i915_driver_postclose,
1854
1855 .gem_close_object = i915_gem_close_object,
1856 .gem_free_object_unlocked = i915_gem_free_object,
1857
1858 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1859 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1860 .gem_prime_export = i915_gem_prime_export,
1861 .gem_prime_import = i915_gem_prime_import,
1862
1863 .dumb_create = i915_gem_dumb_create,
1864 .dumb_map_offset = i915_gem_dumb_mmap_offset,
1865
1866 .ioctls = i915_ioctls,
1867 .num_ioctls = ARRAY_SIZE(i915_ioctls),
1868 .fops = &i915_driver_fops,
1869 .name = DRIVER_NAME,
1870 .desc = DRIVER_DESC,
1871 .date = DRIVER_DATE,
1872 .major = DRIVER_MAJOR,
1873 .minor = DRIVER_MINOR,
1874 .patchlevel = DRIVER_PATCHLEVEL,
1875};