1/*
   2 * Copyright © 2008-2015 Intel Corporation
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice (including the next
  12 * paragraph) shall be included in all copies or substantial portions of the
  13 * Software.
  14 *
  15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21 * IN THE SOFTWARE.
  22 */
  23
  24#include <linux/debugfs.h>
  25
  26#include <drm/display/drm_dp_helper.h>
  27
  28#include "i915_drv.h"
  29#include "intel_display_types.h"
  30#include "intel_dp.h"
  31#include "intel_dp_link_training.h"
  32#include "intel_encoder.h"
  33#include "intel_hotplug.h"
  34#include "intel_panel.h"
  35
  36#define LT_MSG_PREFIX			"[CONNECTOR:%d:%s][ENCODER:%d:%s][%s] "
  37#define LT_MSG_ARGS(_intel_dp, _dp_phy)	(_intel_dp)->attached_connector->base.base.id, \
  38					(_intel_dp)->attached_connector->base.name, \
  39					dp_to_dig_port(_intel_dp)->base.base.base.id, \
  40					dp_to_dig_port(_intel_dp)->base.base.name, \
  41					drm_dp_phy_name(_dp_phy)
  42
  43#define lt_dbg(_intel_dp, _dp_phy, _format, ...) \
  44	drm_dbg_kms(to_intel_display(_intel_dp)->drm, \
  45		    LT_MSG_PREFIX _format, \
  46		    LT_MSG_ARGS(_intel_dp, _dp_phy), ## __VA_ARGS__)
  47
  48#define lt_err(_intel_dp, _dp_phy, _format, ...) do { \
  49	if (intel_digital_port_connected(&dp_to_dig_port(_intel_dp)->base)) \
  50		drm_err(to_intel_display(_intel_dp)->drm, \
  51			LT_MSG_PREFIX _format, \
  52			LT_MSG_ARGS(_intel_dp, _dp_phy), ## __VA_ARGS__); \
  53	else \
  54		lt_dbg(_intel_dp, _dp_phy, "Sink disconnected: " _format, ## __VA_ARGS__); \
  55} while (0)
  56
  57static void intel_dp_reset_lttpr_common_caps(struct intel_dp *intel_dp)
  58{
  59	memset(intel_dp->lttpr_common_caps, 0, sizeof(intel_dp->lttpr_common_caps));
  60}
  61
  62static void intel_dp_reset_lttpr_count(struct intel_dp *intel_dp)
  63{
  64	intel_dp->lttpr_common_caps[DP_PHY_REPEATER_CNT -
  65				    DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] = 0;
  66}
  67
  68static u8 *intel_dp_lttpr_phy_caps(struct intel_dp *intel_dp,
  69				   enum drm_dp_phy dp_phy)
  70{
  71	return intel_dp->lttpr_phy_caps[dp_phy - DP_PHY_LTTPR1];
  72}
  73
  74static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp,
  75					 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
  76					 enum drm_dp_phy dp_phy)
  77{
  78	u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);
  79
  80	if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dpcd, dp_phy, phy_caps) < 0) {
  81		lt_dbg(intel_dp, dp_phy, "failed to read the PHY caps\n");
  82		return;
  83	}
  84
  85	lt_dbg(intel_dp, dp_phy, "PHY capabilities: %*ph\n",
  86	       (int)sizeof(intel_dp->lttpr_phy_caps[0]),
  87	       phy_caps);
  88}
  89
  90static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp,
  91					    const u8 dpcd[DP_RECEIVER_CAP_SIZE])
  92{
  93	int ret;
  94
  95	ret = drm_dp_read_lttpr_common_caps(&intel_dp->aux, dpcd,
  96					    intel_dp->lttpr_common_caps);
  97	if (ret < 0)
  98		goto reset_caps;
  99
 100	lt_dbg(intel_dp, DP_PHY_DPRX, "LTTPR common capabilities: %*ph\n",
 101	       (int)sizeof(intel_dp->lttpr_common_caps),
 102	       intel_dp->lttpr_common_caps);
 103
 104	/* The minimum value of LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV is 1.4 */
 105	if (intel_dp->lttpr_common_caps[0] < 0x14)
 106		goto reset_caps;
 107
 108	return true;
 109
 110reset_caps:
 111	intel_dp_reset_lttpr_common_caps(intel_dp);
 112	return false;
 113}
 114
 115static bool
 116intel_dp_set_lttpr_transparent_mode(struct intel_dp *intel_dp, bool enable)
 117{
 118	u8 val = enable ? DP_PHY_REPEATER_MODE_TRANSPARENT :
 119			  DP_PHY_REPEATER_MODE_NON_TRANSPARENT;
 120
 121	if (drm_dp_dpcd_write(&intel_dp->aux, DP_PHY_REPEATER_MODE, &val, 1) != 1)
 122		return false;
 123
 124	intel_dp->lttpr_common_caps[DP_PHY_REPEATER_MODE -
 125				    DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] = val;
 126
 127	return true;
 128}
 129
 130static bool intel_dp_lttpr_transparent_mode_enabled(struct intel_dp *intel_dp)
 131{
 132	return intel_dp->lttpr_common_caps[DP_PHY_REPEATER_MODE -
 133					   DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] ==
 134		DP_PHY_REPEATER_MODE_TRANSPARENT;
 135}
 136
 137/*
 138 * Read the LTTPR common capabilities and switch the LTTPR PHYs to
 139 * non-transparent mode if this is supported. Preserve the
 140 * transparent/non-transparent mode on an active link.
 141 *
 142 * Return the number of detected LTTPRs in non-transparent mode or 0 if the
 143 * LTTPRs are in transparent mode or the detection failed.
 144 */
 145static int intel_dp_init_lttpr_phys(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE])
 146{
 147	int lttpr_count;
 148
 149	if (!intel_dp_read_lttpr_common_caps(intel_dp, dpcd))
 150		return 0;
 151
 152	lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);
 153	/*
 154	 * Prevent setting LTTPR transparent mode explicitly if no LTTPRs are
 155	 * detected as this breaks link training at least on the Dell WD19TB
 156	 * dock.
 157	 */
 158	if (lttpr_count == 0)
 159		return 0;
 160
 161	/*
 162	 * Don't change the mode on an active link, to prevent a loss of link
 163	 * synchronization. See DP Standard v2.0 3.6.7. about the LTTPR
 164	 * resetting its internal state when the mode is changed from
 165	 * non-transparent to transparent.
 166	 */
 167	if (intel_dp->link_trained) {
 168		if (lttpr_count < 0 || intel_dp_lttpr_transparent_mode_enabled(intel_dp))
 169			goto out_reset_lttpr_count;
 170
 171		return lttpr_count;
 172	}
 173
 174	/*
 175	 * See DP Standard v2.0 3.6.6.1. about the explicit disabling of
 176	 * non-transparent mode and the disable->enable non-transparent mode
 177	 * sequence.
 178	 */
 179	intel_dp_set_lttpr_transparent_mode(intel_dp, true);
 180
 181	/*
 182	 * In case of unsupported number of LTTPRs or failing to switch to
 183	 * non-transparent mode fall-back to transparent link training mode,
 184	 * still taking into account any LTTPR common lane- rate/count limits.
 185	 */
 186	if (lttpr_count < 0)
 187		goto out_reset_lttpr_count;
 188
 189	if (!intel_dp_set_lttpr_transparent_mode(intel_dp, false)) {
 190		lt_dbg(intel_dp, DP_PHY_DPRX,
 191		       "Switching to LTTPR non-transparent LT mode failed, fall-back to transparent mode\n");
 192
 193		intel_dp_set_lttpr_transparent_mode(intel_dp, true);
 194
 195		goto out_reset_lttpr_count;
 196	}
 197
 198	return lttpr_count;
 199
 200out_reset_lttpr_count:
 201	intel_dp_reset_lttpr_count(intel_dp);
 202
 203	return 0;
 204}
 205
 206static int intel_dp_init_lttpr(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE])
 207{
 208	int lttpr_count;
 209	int i;
 210
 211	lttpr_count = intel_dp_init_lttpr_phys(intel_dp, dpcd);
 212
 213	for (i = 0; i < lttpr_count; i++) {
 214		intel_dp_read_lttpr_phy_caps(intel_dp, dpcd, DP_PHY_LTTPR(i));
 215		drm_dp_dump_lttpr_desc(&intel_dp->aux, DP_PHY_LTTPR(i));
 216	}
 217
 218	return lttpr_count;
 219}
 220
 221int intel_dp_read_dprx_caps(struct intel_dp *intel_dp, u8 dpcd[DP_RECEIVER_CAP_SIZE])
 222{
 223	struct intel_display *display = to_intel_display(intel_dp);
 224	struct drm_i915_private *i915 = to_i915(display->drm);
 225
 226	if (intel_dp_is_edp(intel_dp))
 227		return 0;
 228
 229	/*
 230	 * Detecting LTTPRs must be avoided on platforms with an AUX timeout
 231	 * period < 3.2ms. (see DP Standard v2.0, 2.11.2, 3.6.6.1).
 232	 */
 233	if (DISPLAY_VER(display) >= 10 && !IS_GEMINILAKE(i915))
 234		if (drm_dp_dpcd_probe(&intel_dp->aux,
 235				      DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV))
 236			return -EIO;
 237
 238	if (drm_dp_read_dpcd_caps(&intel_dp->aux, dpcd))
 239		return -EIO;
 240
 241	return 0;
 242}
 243
 244/**
 245 * intel_dp_init_lttpr_and_dprx_caps - detect LTTPR and DPRX caps, init the LTTPR link training mode
 246 * @intel_dp: Intel DP struct
 247 *
 248 * Read the LTTPR common and DPRX capabilities and switch to non-transparent
 249 * link training mode if any is detected and read the PHY capabilities for all
 250 * detected LTTPRs. In case of an LTTPR detection error or if the number of
 251 * LTTPRs is more than is supported (8), fall back to the no-LTTPR,
 252 * transparent mode link training mode.
 253 *
 254 * Returns:
 255 *   >0  if LTTPRs were detected and the non-transparent LT mode was set. The
 256 *       DPRX capabilities are read out.
 257 *    0  if no LTTPRs or more than 8 LTTPRs were detected or in case of a
 258 *       detection failure and the transparent LT mode was set. The DPRX
 259 *       capabilities are read out.
 260 *   <0  Reading out the DPRX capabilities failed.
 261 */
 262int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp)
 263{
 264	struct intel_display *display = to_intel_display(intel_dp);
 265	struct drm_i915_private *i915 = to_i915(display->drm);
 266	int lttpr_count = 0;
 267
 268	/*
 269	 * Detecting LTTPRs must be avoided on platforms with an AUX timeout
 270	 * period < 3.2ms. (see DP Standard v2.0, 2.11.2, 3.6.6.1).
 271	 */
 272	if (!intel_dp_is_edp(intel_dp) &&
 273	    (DISPLAY_VER(display) >= 10 && !IS_GEMINILAKE(i915))) {
 274		u8 dpcd[DP_RECEIVER_CAP_SIZE];
 275		int err = intel_dp_read_dprx_caps(intel_dp, dpcd);
 276
 277		if (err != 0)
 278			return err;
 279
 280		lttpr_count = intel_dp_init_lttpr(intel_dp, dpcd);
 281	}
 282
 283	/*
 284	 * The DPTX shall read the DPRX caps after LTTPR detection, so re-read
 285	 * it here.
 286	 */
 287	if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd)) {
 288		intel_dp_reset_lttpr_common_caps(intel_dp);
 289		return -EIO;
 290	}
 291
 292	return lttpr_count;
 293}
 294
 295static u8 dp_voltage_max(u8 preemph)
 296{
 297	switch (preemph & DP_TRAIN_PRE_EMPHASIS_MASK) {
 298	case DP_TRAIN_PRE_EMPH_LEVEL_0:
 299		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
 300	case DP_TRAIN_PRE_EMPH_LEVEL_1:
 301		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
 302	case DP_TRAIN_PRE_EMPH_LEVEL_2:
 303		return DP_TRAIN_VOLTAGE_SWING_LEVEL_1;
 304	case DP_TRAIN_PRE_EMPH_LEVEL_3:
 305	default:
 306		return DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
 307	}
 308}
 309
 310static u8 intel_dp_lttpr_voltage_max(struct intel_dp *intel_dp,
 311				     enum drm_dp_phy dp_phy)
 312{
 313	const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);
 314
 315	if (drm_dp_lttpr_voltage_swing_level_3_supported(phy_caps))
 316		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
 317	else
 318		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
 319}
 320
 321static u8 intel_dp_lttpr_preemph_max(struct intel_dp *intel_dp,
 322				     enum drm_dp_phy dp_phy)
 323{
 324	const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);
 325
 326	if (drm_dp_lttpr_pre_emphasis_level_3_supported(phy_caps))
 327		return DP_TRAIN_PRE_EMPH_LEVEL_3;
 328	else
 329		return DP_TRAIN_PRE_EMPH_LEVEL_2;
 330}
 331
 332static bool
 333intel_dp_phy_is_downstream_of_source(struct intel_dp *intel_dp,
 334				     enum drm_dp_phy dp_phy)
 335{
 336	struct intel_display *display = to_intel_display(intel_dp);
 337	int lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);
 338
 339	drm_WARN_ON_ONCE(display->drm,
 340			 lttpr_count <= 0 && dp_phy != DP_PHY_DPRX);
 341
 342	return lttpr_count <= 0 || dp_phy == DP_PHY_LTTPR(lttpr_count - 1);
 343}
 344
 345static u8 intel_dp_phy_voltage_max(struct intel_dp *intel_dp,
 346				   const struct intel_crtc_state *crtc_state,
 347				   enum drm_dp_phy dp_phy)
 348{
 349	struct intel_display *display = to_intel_display(intel_dp);
 350	u8 voltage_max;
 351
 352	/*
 353	 * Get voltage_max from the DPTX_PHY (source or LTTPR) upstream from
 354	 * the DPRX_PHY we train.
 355	 */
 356	if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy))
 357		voltage_max = intel_dp->voltage_max(intel_dp, crtc_state);
 358	else
 359		voltage_max = intel_dp_lttpr_voltage_max(intel_dp, dp_phy + 1);
 360
 361	drm_WARN_ON_ONCE(display->drm,
 362			 voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_2 &&
 363			 voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_3);
 364
 365	return voltage_max;
 366}
 367
 368static u8 intel_dp_phy_preemph_max(struct intel_dp *intel_dp,
 369				   enum drm_dp_phy dp_phy)
 370{
 371	struct intel_display *display = to_intel_display(intel_dp);
 372	u8 preemph_max;
 373
 374	/*
 375	 * Get preemph_max from the DPTX_PHY (source or LTTPR) upstream from
 376	 * the DPRX_PHY we train.
 377	 */
 378	if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy))
 379		preemph_max = intel_dp->preemph_max(intel_dp);
 380	else
 381		preemph_max = intel_dp_lttpr_preemph_max(intel_dp, dp_phy + 1);
 382
 383	drm_WARN_ON_ONCE(display->drm,
 384			 preemph_max != DP_TRAIN_PRE_EMPH_LEVEL_2 &&
 385			 preemph_max != DP_TRAIN_PRE_EMPH_LEVEL_3);
 386
 387	return preemph_max;
 388}
 389
 390static bool has_per_lane_signal_levels(struct intel_dp *intel_dp,
 391				       enum drm_dp_phy dp_phy)
 392{
 393	struct intel_display *display = to_intel_display(intel_dp);
 394	struct drm_i915_private *i915 = to_i915(display->drm);
 395
 396	return !intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy) ||
 397		DISPLAY_VER(display) >= 10 || IS_BROXTON(i915);
 398}
 399
 400/* 128b/132b */
 401static u8 intel_dp_get_lane_adjust_tx_ffe_preset(struct intel_dp *intel_dp,
 402						 const struct intel_crtc_state *crtc_state,
 403						 enum drm_dp_phy dp_phy,
 404						 const u8 link_status[DP_LINK_STATUS_SIZE],
 405						 int lane)
 406{
 407	u8 tx_ffe = 0;
 408
 409	if (has_per_lane_signal_levels(intel_dp, dp_phy)) {
 410		lane = min(lane, crtc_state->lane_count - 1);
 411		tx_ffe = drm_dp_get_adjust_tx_ffe_preset(link_status, lane);
 412	} else {
 413		for (lane = 0; lane < crtc_state->lane_count; lane++)
 414			tx_ffe = max(tx_ffe, drm_dp_get_adjust_tx_ffe_preset(link_status, lane));
 415	}
 416
 417	return tx_ffe;
 418}
 419
 420/* 8b/10b */
 421static u8 intel_dp_get_lane_adjust_vswing_preemph(struct intel_dp *intel_dp,
 422						  const struct intel_crtc_state *crtc_state,
 423						  enum drm_dp_phy dp_phy,
 424						  const u8 link_status[DP_LINK_STATUS_SIZE],
 425						  int lane)
 426{
 
 427	u8 v = 0;
 428	u8 p = 0;
 
 429	u8 voltage_max;
 430	u8 preemph_max;
 431
 432	if (has_per_lane_signal_levels(intel_dp, dp_phy)) {
 433		lane = min(lane, crtc_state->lane_count - 1);
 434
 435		v = drm_dp_get_adjust_request_voltage(link_status, lane);
 436		p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
 437	} else {
 438		for (lane = 0; lane < crtc_state->lane_count; lane++) {
 439			v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane));
 440			p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane));
 441		}
 442	}
 443
 444	preemph_max = intel_dp_phy_preemph_max(intel_dp, dp_phy);
 
 
 
 
 445	if (p >= preemph_max)
 446		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
 447
 448	v = min(v, dp_voltage_max(p));
 449
 450	voltage_max = intel_dp_phy_voltage_max(intel_dp, crtc_state, dp_phy);
 
 
 
 
 451	if (v >= voltage_max)
 452		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
 453
 454	return v | p;
 455}
 456
 457static u8 intel_dp_get_lane_adjust_train(struct intel_dp *intel_dp,
 458					 const struct intel_crtc_state *crtc_state,
 459					 enum drm_dp_phy dp_phy,
 460					 const u8 link_status[DP_LINK_STATUS_SIZE],
 461					 int lane)
 462{
 463	if (intel_dp_is_uhbr(crtc_state))
 464		return intel_dp_get_lane_adjust_tx_ffe_preset(intel_dp, crtc_state,
 465							      dp_phy, link_status, lane);
 466	else
 467		return intel_dp_get_lane_adjust_vswing_preemph(intel_dp, crtc_state,
 468							       dp_phy, link_status, lane);
 469}
 470
 471#define TRAIN_REQ_FMT "%d/%d/%d/%d"
 472#define _TRAIN_REQ_VSWING_ARGS(link_status, lane) \
 473	(drm_dp_get_adjust_request_voltage((link_status), (lane)) >> DP_TRAIN_VOLTAGE_SWING_SHIFT)
 474#define TRAIN_REQ_VSWING_ARGS(link_status) \
 475	_TRAIN_REQ_VSWING_ARGS(link_status, 0), \
 476	_TRAIN_REQ_VSWING_ARGS(link_status, 1), \
 477	_TRAIN_REQ_VSWING_ARGS(link_status, 2), \
 478	_TRAIN_REQ_VSWING_ARGS(link_status, 3)
 479#define _TRAIN_REQ_PREEMPH_ARGS(link_status, lane) \
 480	(drm_dp_get_adjust_request_pre_emphasis((link_status), (lane)) >> DP_TRAIN_PRE_EMPHASIS_SHIFT)
 481#define TRAIN_REQ_PREEMPH_ARGS(link_status) \
 482	_TRAIN_REQ_PREEMPH_ARGS(link_status, 0), \
 483	_TRAIN_REQ_PREEMPH_ARGS(link_status, 1), \
 484	_TRAIN_REQ_PREEMPH_ARGS(link_status, 2), \
 485	_TRAIN_REQ_PREEMPH_ARGS(link_status, 3)
 486#define _TRAIN_REQ_TX_FFE_ARGS(link_status, lane) \
 487	drm_dp_get_adjust_tx_ffe_preset((link_status), (lane))
 488#define TRAIN_REQ_TX_FFE_ARGS(link_status) \
 489	_TRAIN_REQ_TX_FFE_ARGS(link_status, 0), \
 490	_TRAIN_REQ_TX_FFE_ARGS(link_status, 1), \
 491	_TRAIN_REQ_TX_FFE_ARGS(link_status, 2), \
 492	_TRAIN_REQ_TX_FFE_ARGS(link_status, 3)
 493
 494void
 495intel_dp_get_adjust_train(struct intel_dp *intel_dp,
 496			  const struct intel_crtc_state *crtc_state,
 497			  enum drm_dp_phy dp_phy,
 498			  const u8 link_status[DP_LINK_STATUS_SIZE])
 499{
 500	int lane;
 501
 502	if (intel_dp_is_uhbr(crtc_state)) {
 503		lt_dbg(intel_dp, dp_phy,
 504		       "128b/132b, lanes: %d, "
 505		       "TX FFE request: " TRAIN_REQ_FMT "\n",
 506		       crtc_state->lane_count,
 507		       TRAIN_REQ_TX_FFE_ARGS(link_status));
 508	} else {
 509		lt_dbg(intel_dp, dp_phy,
 510		       "8b/10b, lanes: %d, "
 511		       "vswing request: " TRAIN_REQ_FMT ", "
 512		       "pre-emphasis request: " TRAIN_REQ_FMT "\n",
 513		       crtc_state->lane_count,
 514		       TRAIN_REQ_VSWING_ARGS(link_status),
 515		       TRAIN_REQ_PREEMPH_ARGS(link_status));
 516	}
 517
 518	for (lane = 0; lane < 4; lane++)
 519		intel_dp->train_set[lane] =
 520			intel_dp_get_lane_adjust_train(intel_dp, crtc_state,
 521						       dp_phy, link_status, lane);
 522}
 523
 524static int intel_dp_training_pattern_set_reg(struct intel_dp *intel_dp,
 525					     enum drm_dp_phy dp_phy)
 526{
 527	return dp_phy == DP_PHY_DPRX ?
 528		DP_TRAINING_PATTERN_SET :
 529		DP_TRAINING_PATTERN_SET_PHY_REPEATER(dp_phy);
 530}
 531
 532static bool
 533intel_dp_set_link_train(struct intel_dp *intel_dp,
 534			const struct intel_crtc_state *crtc_state,
 535			enum drm_dp_phy dp_phy,
 536			u8 dp_train_pat)
 537{
 538	int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy);
 539	u8 buf[sizeof(intel_dp->train_set) + 1];
 540	int len;
 541
 542	intel_dp_program_link_training_pattern(intel_dp, crtc_state,
 543					       dp_phy, dp_train_pat);
 544
 545	buf[0] = dp_train_pat;
 546	/* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
 547	memcpy(buf + 1, intel_dp->train_set, crtc_state->lane_count);
 548	len = crtc_state->lane_count + 1;
 549
 550	return drm_dp_dpcd_write(&intel_dp->aux, reg, buf, len) == len;
 551}
 552
 553static char dp_training_pattern_name(u8 train_pat)
 554{
 555	switch (train_pat) {
 556	case DP_TRAINING_PATTERN_1:
 557	case DP_TRAINING_PATTERN_2:
 558	case DP_TRAINING_PATTERN_3:
 559		return '0' + train_pat;
 560	case DP_TRAINING_PATTERN_4:
 561		return '4';
 562	default:
 563		MISSING_CASE(train_pat);
 564		return '?';
 565	}
 566}
 567
 568void
 569intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
 570				       const struct intel_crtc_state *crtc_state,
 571				       enum drm_dp_phy dp_phy,
 572				       u8 dp_train_pat)
 573{
 574	u8 train_pat = intel_dp_training_pattern_symbol(dp_train_pat);
 575
 576	if (train_pat != DP_TRAINING_PATTERN_DISABLE)
 577		lt_dbg(intel_dp, dp_phy, "Using DP training pattern TPS%c\n",
 578		       dp_training_pattern_name(train_pat));
 579
 580	intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat);
 581}
 582
 583#define TRAIN_SET_FMT "%d%s/%d%s/%d%s/%d%s"
 584#define _TRAIN_SET_VSWING_ARGS(train_set) \
 585	((train_set) & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT, \
 586	(train_set) & DP_TRAIN_MAX_SWING_REACHED ? "(max)" : ""
 587#define TRAIN_SET_VSWING_ARGS(train_set) \
 588	_TRAIN_SET_VSWING_ARGS((train_set)[0]), \
 589	_TRAIN_SET_VSWING_ARGS((train_set)[1]), \
 590	_TRAIN_SET_VSWING_ARGS((train_set)[2]), \
 591	_TRAIN_SET_VSWING_ARGS((train_set)[3])
 592#define _TRAIN_SET_PREEMPH_ARGS(train_set) \
 593	((train_set) & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT, \
 594	(train_set) & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ? "(max)" : ""
 595#define TRAIN_SET_PREEMPH_ARGS(train_set) \
 596	_TRAIN_SET_PREEMPH_ARGS((train_set)[0]), \
 597	_TRAIN_SET_PREEMPH_ARGS((train_set)[1]), \
 598	_TRAIN_SET_PREEMPH_ARGS((train_set)[2]), \
 599	_TRAIN_SET_PREEMPH_ARGS((train_set)[3])
 600#define _TRAIN_SET_TX_FFE_ARGS(train_set) \
 601	((train_set) & DP_TX_FFE_PRESET_VALUE_MASK), ""
 602#define TRAIN_SET_TX_FFE_ARGS(train_set) \
 603	_TRAIN_SET_TX_FFE_ARGS((train_set)[0]), \
 604	_TRAIN_SET_TX_FFE_ARGS((train_set)[1]), \
 605	_TRAIN_SET_TX_FFE_ARGS((train_set)[2]), \
 606	_TRAIN_SET_TX_FFE_ARGS((train_set)[3])
 607
 608void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
 609				const struct intel_crtc_state *crtc_state,
 610				enum drm_dp_phy dp_phy)
 611{
 612	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
 613
 614	if (intel_dp_is_uhbr(crtc_state)) {
 615		lt_dbg(intel_dp, dp_phy,
 616		       "128b/132b, lanes: %d, "
 617		       "TX FFE presets: " TRAIN_SET_FMT "\n",
 618		       crtc_state->lane_count,
 619		       TRAIN_SET_TX_FFE_ARGS(intel_dp->train_set));
 620	} else {
 621		lt_dbg(intel_dp, dp_phy,
 622		       "8b/10b, lanes: %d, "
 623		       "vswing levels: " TRAIN_SET_FMT ", "
 624		       "pre-emphasis levels: " TRAIN_SET_FMT "\n",
 625		       crtc_state->lane_count,
 626		       TRAIN_SET_VSWING_ARGS(intel_dp->train_set),
 627		       TRAIN_SET_PREEMPH_ARGS(intel_dp->train_set));
 628	}
 629
 630	if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy))
 631		encoder->set_signal_levels(encoder, crtc_state);
 
 
 632}
 633
 634static bool
 635intel_dp_reset_link_train(struct intel_dp *intel_dp,
 636			  const struct intel_crtc_state *crtc_state,
 637			  enum drm_dp_phy dp_phy,
 638			  u8 dp_train_pat)
 639{
 640	memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
 641	intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy);
 642	return intel_dp_set_link_train(intel_dp, crtc_state, dp_phy, dp_train_pat);
 643}
 644
 645static bool
 646intel_dp_update_link_train(struct intel_dp *intel_dp,
 647			   const struct intel_crtc_state *crtc_state,
 648			   enum drm_dp_phy dp_phy)
 649{
 650	int reg = dp_phy == DP_PHY_DPRX ?
 651			    DP_TRAINING_LANE0_SET :
 652			    DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy);
 653	int ret;
 654
 655	intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy);
 656
 657	ret = drm_dp_dpcd_write(&intel_dp->aux, reg,
 658				intel_dp->train_set, crtc_state->lane_count);
 659
 660	return ret == crtc_state->lane_count;
 661}
 662
 663/* 128b/132b */
 664static bool intel_dp_lane_max_tx_ffe_reached(u8 train_set_lane)
 665{
 666	return (train_set_lane & DP_TX_FFE_PRESET_VALUE_MASK) ==
 667		DP_TX_FFE_PRESET_VALUE_MASK;
 668}
 669
 670/*
 671 * 8b/10b
 672 *
 673 * FIXME: The DP spec is very confusing here, also the Link CTS spec seems to
 674 * have self contradicting tests around this area.
 675 *
 676 * In lieu of better ideas let's just stop when we've reached the max supported
 677 * vswing with its max pre-emphasis, which is either 2+1 or 3+0 depending on
 678 * whether vswing level 3 is supported or not.
 679 */
 680static bool intel_dp_lane_max_vswing_reached(u8 train_set_lane)
 681{
 682	u8 v = (train_set_lane & DP_TRAIN_VOLTAGE_SWING_MASK) >>
 683		DP_TRAIN_VOLTAGE_SWING_SHIFT;
 684	u8 p = (train_set_lane & DP_TRAIN_PRE_EMPHASIS_MASK) >>
 685		DP_TRAIN_PRE_EMPHASIS_SHIFT;
 686
 687	if ((train_set_lane & DP_TRAIN_MAX_SWING_REACHED) == 0)
 688		return false;
 689
 690	if (v + p != 3)
 691		return false;
 692
 693	return true;
 694}
 695
 696static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp,
 697					     const struct intel_crtc_state *crtc_state)
 698{
 699	int lane;
 700
 701	for (lane = 0; lane < crtc_state->lane_count; lane++) {
 702		u8 train_set_lane = intel_dp->train_set[lane];
 703
 704		if (intel_dp_is_uhbr(crtc_state)) {
 705			if (!intel_dp_lane_max_tx_ffe_reached(train_set_lane))
 706				return false;
 707		} else {
 708			if (!intel_dp_lane_max_vswing_reached(train_set_lane))
 709				return false;
 710		}
 711	}
 712
 713	return true;
 714}
 715
 716void intel_dp_link_training_set_mode(struct intel_dp *intel_dp, int link_rate, bool is_vrr)
 717{
 718	u8 link_config[2];
 719
 720	link_config[0] = is_vrr ? DP_MSA_TIMING_PAR_IGNORE_EN : 0;
 721	link_config[1] = drm_dp_is_uhbr_rate(link_rate) ?
 722			 DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B;
 723	drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
 724}
 725
 726static void intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp,
 727					    const struct intel_crtc_state *crtc_state)
 728{
 729	intel_dp_link_training_set_mode(intel_dp,
 730					crtc_state->port_clock, crtc_state->vrr.flipline);
 731}
 732
 733void intel_dp_link_training_set_bw(struct intel_dp *intel_dp,
 734				   int link_bw, int rate_select, int lane_count,
 735				   bool enhanced_framing)
 736{
 737	if (enhanced_framing)
 738		lane_count |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 739
 740	if (link_bw) {
 741		/* DP and eDP v1.3 and earlier link bw set method. */
 742		u8 link_config[] = { link_bw, lane_count };
 743
 744		drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config,
 745				  ARRAY_SIZE(link_config));
 746	} else {
 747		/*
 748		 * eDP v1.4 and later link rate set method.
 749		 *
 750		 * eDP v1.4x sinks shall ignore DP_LINK_RATE_SET if
 751		 * DP_LINK_BW_SET is set. Avoid writing DP_LINK_BW_SET.
 752		 *
 753		 * eDP v1.5 sinks allow choosing either, and the last choice
 754		 * shall be active.
 755		 */
 756		drm_dp_dpcd_writeb(&intel_dp->aux, DP_LANE_COUNT_SET, lane_count);
 757		drm_dp_dpcd_writeb(&intel_dp->aux, DP_LINK_RATE_SET, rate_select);
 758	}
 759}
 760
 761static void intel_dp_update_link_bw_set(struct intel_dp *intel_dp,
 762					const struct intel_crtc_state *crtc_state,
 763					u8 link_bw, u8 rate_select)
 764{
 765	intel_dp_link_training_set_bw(intel_dp, link_bw, rate_select, crtc_state->lane_count,
 766				      crtc_state->enhanced_framing);
 767}
 768
 769/*
 770 * Prepare link training by configuring the link parameters. On DDI platforms
 771 * also enable the port here.
 772 */
 773static bool
 774intel_dp_prepare_link_train(struct intel_dp *intel_dp,
 775			    const struct intel_crtc_state *crtc_state)
 776{
 
 
 
 
 
 777	u8 link_bw, rate_select;
 778
 779	if (intel_dp->prepare_link_retrain)
 780		intel_dp->prepare_link_retrain(intel_dp, crtc_state);
 781
 782	intel_dp_compute_rate(intel_dp, crtc_state->port_clock,
 783			      &link_bw, &rate_select);
 784
 785	/*
 786	 * WaEdpLinkRateDataReload
 787	 *
 788	 * Parade PS8461E MUX (used on varius TGL+ laptops) needs
 789	 * to snoop the link rates reported by the sink when we
 790	 * use LINK_RATE_SET in order to operate in jitter cleaning
 791	 * mode (as opposed to redriver mode). Unfortunately it
 792	 * loses track of the snooped link rates when powered down,
 793	 * so we need to make it re-snoop often. Without this high
 794	 * link rates are not stable.
 795	 */
 796	if (!link_bw) {
 797		__le16 sink_rates[DP_MAX_SUPPORTED_RATES];
 798
 799		lt_dbg(intel_dp, DP_PHY_DPRX, "Reloading eDP link rates\n");
 800
 801		drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
 802				 sink_rates, sizeof(sink_rates));
 803	}
 804
 805	if (link_bw)
 806		lt_dbg(intel_dp, DP_PHY_DPRX, "Using LINK_BW_SET value %02x\n",
 807		       link_bw);
 808	else
 809		lt_dbg(intel_dp, DP_PHY_DPRX,
 810		       "Using LINK_RATE_SET value %02x\n",
 811		       rate_select);
 812	/*
 813	 * Spec DP2.1 Section 3.5.2.16
 814	 * Prior to LT DPTX should set 128b/132b DP Channel coding and then set link rate
 815	 */
 816	intel_dp_update_downspread_ctrl(intel_dp, crtc_state);
 817	intel_dp_update_link_bw_set(intel_dp, crtc_state, link_bw,
 818				    rate_select);
 819
 820	return true;
 821}
 822
 823static bool intel_dp_adjust_request_changed(const struct intel_crtc_state *crtc_state,
 824					    const u8 old_link_status[DP_LINK_STATUS_SIZE],
 825					    const u8 new_link_status[DP_LINK_STATUS_SIZE])
 826{
 827	int lane;
 828
 829	for (lane = 0; lane < crtc_state->lane_count; lane++) {
 830		u8 old, new;
 831
 832		if (intel_dp_is_uhbr(crtc_state)) {
 833			old = drm_dp_get_adjust_tx_ffe_preset(old_link_status, lane);
 834			new = drm_dp_get_adjust_tx_ffe_preset(new_link_status, lane);
 835		} else {
 836			old = drm_dp_get_adjust_request_voltage(old_link_status, lane) |
 837				drm_dp_get_adjust_request_pre_emphasis(old_link_status, lane);
 838			new = drm_dp_get_adjust_request_voltage(new_link_status, lane) |
 839				drm_dp_get_adjust_request_pre_emphasis(new_link_status, lane);
 840		}
 
 
 841
 842		if (old != new)
 843			return true;
 844	}
 845
 846	return false;
 847}
 848
 849void
 850intel_dp_dump_link_status(struct intel_dp *intel_dp, enum drm_dp_phy dp_phy,
 851			  const u8 link_status[DP_LINK_STATUS_SIZE])
 852{
 853	lt_dbg(intel_dp, dp_phy,
 854	       "ln0_1:0x%x ln2_3:0x%x align:0x%x sink:0x%x adj_req0_1:0x%x adj_req2_3:0x%x\n",
 855	       link_status[0], link_status[1], link_status[2],
 856	       link_status[3], link_status[4], link_status[5]);
 857}
 858
 859/*
 860 * Perform the link training clock recovery phase on the given DP PHY using
 861 * training pattern 1.
 862 */
 863static bool
 864intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
 865				      const struct intel_crtc_state *crtc_state,
 866				      enum drm_dp_phy dp_phy)
 867{
 868	u8 old_link_status[DP_LINK_STATUS_SIZE] = {};
 869	int voltage_tries, cr_tries, max_cr_tries;
 870	u8 link_status[DP_LINK_STATUS_SIZE];
 871	bool max_vswing_reached = false;
 872	int delay_us;
 873
 874	delay_us = drm_dp_read_clock_recovery_delay(&intel_dp->aux,
 875						    intel_dp->dpcd, dp_phy,
 876						    intel_dp_is_uhbr(crtc_state));
 877
 878	/* clock recovery */
 879	if (!intel_dp_reset_link_train(intel_dp, crtc_state, dp_phy,
 880				       DP_TRAINING_PATTERN_1 |
 881				       DP_LINK_SCRAMBLING_DISABLE)) {
 882		lt_err(intel_dp, dp_phy, "Failed to enable link training\n");
 883		return false;
 884	}
 885
 886	/*
 887	 * The DP 1.4 spec defines the max clock recovery retries value
 888	 * as 10 but for pre-DP 1.4 devices we set a very tolerant
 889	 * retry limit of 80 (4 voltage levels x 4 preemphasis levels x
 890	 * x 5 identical voltage retries). Since the previous specs didn't
 891	 * define a limit and created the possibility of an infinite loop
 892	 * we want to prevent any sync from triggering that corner case.
 893	 */
 894	if (intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
 895		max_cr_tries = 10;
 896	else
 897		max_cr_tries = 80;
 898
 899	voltage_tries = 1;
 900	for (cr_tries = 0; cr_tries < max_cr_tries; ++cr_tries) {
 901		usleep_range(delay_us, 2 * delay_us);
 
 
 902
 903		if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy,
 904						     link_status) < 0) {
 905			lt_err(intel_dp, dp_phy, "Failed to get link status\n");
 906			return false;
 907		}
 908
 909		if (drm_dp_clock_recovery_ok(link_status, crtc_state->lane_count)) {
 910			lt_dbg(intel_dp, dp_phy, "Clock recovery OK\n");
 911			return true;
 912		}
 913
 914		if (voltage_tries == 5) {
 915			intel_dp_dump_link_status(intel_dp, dp_phy, link_status);
 916			lt_dbg(intel_dp, dp_phy, "Same voltage tried 5 times\n");
 917			return false;
 918		}
 919
 920		if (max_vswing_reached) {
 921			intel_dp_dump_link_status(intel_dp, dp_phy, link_status);
 922			lt_dbg(intel_dp, dp_phy, "Max Voltage Swing reached\n");
 923			return false;
 924		}
 925
 
 
 926		/* Update training set as requested by target */
 927		intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy,
 928					  link_status);
 929		if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) {
 930			lt_err(intel_dp, dp_phy, "Failed to update link training\n");
 931			return false;
 932		}
 933
 934		if (!intel_dp_adjust_request_changed(crtc_state, old_link_status, link_status))
 
 935			++voltage_tries;
 936		else
 937			voltage_tries = 1;
 938
 939		memcpy(old_link_status, link_status, sizeof(link_status));
 940
 941		if (intel_dp_link_max_vswing_reached(intel_dp, crtc_state))
 942			max_vswing_reached = true;
 943	}
 944
 945	intel_dp_dump_link_status(intel_dp, dp_phy, link_status);
 946	lt_err(intel_dp, dp_phy, "Failed clock recovery %d times, giving up!\n",
 947	       max_cr_tries);
 948
 
 
 
 949	return false;
 950}
 951
 952/*
 953 * Pick Training Pattern Sequence (TPS) for channel equalization. 128b/132b TPS2
 954 * for UHBR+, TPS4 for HBR3 or for 1.4 devices that support it, TPS3 for HBR2 or
 955 * 1.2 devices that support it, TPS2 otherwise.
 956 */
 957static u32 intel_dp_training_pattern(struct intel_dp *intel_dp,
 958				     const struct intel_crtc_state *crtc_state,
 959				     enum drm_dp_phy dp_phy)
 960{
 961	struct intel_display *display = to_intel_display(intel_dp);
 962	struct drm_i915_private *i915 = to_i915(display->drm);
 963	bool source_tps3, sink_tps3, source_tps4, sink_tps4;
 964
 965	/* UHBR+ use separate 128b/132b TPS2 */
 966	if (intel_dp_is_uhbr(crtc_state))
 967		return DP_TRAINING_PATTERN_2;
 968
 969	/*
 970	 * TPS4 support is mandatory for all downstream devices that
 971	 * support HBR3. There are no known eDP panels that support
 972	 * TPS4 as of Feb 2018 as per VESA eDP_v1.4b_E1 specification.
 973	 * LTTPRs must support TPS4.
 974	 */
 975	source_tps4 = intel_dp_source_supports_tps4(i915);
 976	sink_tps4 = dp_phy != DP_PHY_DPRX ||
 977		    drm_dp_tps4_supported(intel_dp->dpcd);
 978	if (source_tps4 && sink_tps4) {
 979		return DP_TRAINING_PATTERN_4;
 980	} else if (crtc_state->port_clock == 810000) {
 981		if (!source_tps4)
 982			lt_dbg(intel_dp, dp_phy,
 983			       "8.1 Gbps link rate without source TPS4 support\n");
 984		if (!sink_tps4)
 985			lt_dbg(intel_dp, dp_phy,
 986			       "8.1 Gbps link rate without sink TPS4 support\n");
 987	}
 988
 989	/*
 990	 * TPS3 support is mandatory for downstream devices that
 991	 * support HBR2. However, not all sinks follow the spec.
 
 992	 */
 993	source_tps3 = intel_dp_source_supports_tps3(i915);
 994	sink_tps3 = dp_phy != DP_PHY_DPRX ||
 995		    drm_dp_tps3_supported(intel_dp->dpcd);
 996	if (source_tps3 && sink_tps3) {
 997		return  DP_TRAINING_PATTERN_3;
 998	} else if (crtc_state->port_clock >= 540000) {
 999		if (!source_tps3)
1000			lt_dbg(intel_dp, dp_phy,
1001			       ">=5.4/6.48 Gbps link rate without source TPS3 support\n");
1002		if (!sink_tps3)
1003			lt_dbg(intel_dp, dp_phy,
1004			       ">=5.4/6.48 Gbps link rate without sink TPS3 support\n");
1005	}
1006
1007	return DP_TRAINING_PATTERN_2;
1008}
1009
1010/*
1011 * Perform the link training channel equalization phase on the given DP PHY
1012 * using one of training pattern 2, 3 or 4 depending on the source and
1013 * sink capabilities.
1014 */
1015static bool
1016intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
1017					    const struct intel_crtc_state *crtc_state,
1018					    enum drm_dp_phy dp_phy)
1019{
 
1020	int tries;
1021	u32 training_pattern;
1022	u8 link_status[DP_LINK_STATUS_SIZE];
1023	bool channel_eq = false;
1024	int delay_us;
1025
1026	delay_us = drm_dp_read_channel_eq_delay(&intel_dp->aux,
1027						intel_dp->dpcd, dp_phy,
1028						intel_dp_is_uhbr(crtc_state));
1029
1030	training_pattern = intel_dp_training_pattern(intel_dp, crtc_state, dp_phy);
1031	/* Scrambling is disabled for TPS2/3 and enabled for TPS4 */
1032	if (training_pattern != DP_TRAINING_PATTERN_4)
1033		training_pattern |= DP_LINK_SCRAMBLING_DISABLE;
1034
1035	/* channel equalization */
1036	if (!intel_dp_set_link_train(intel_dp, crtc_state, dp_phy,
1037				     training_pattern)) {
1038		lt_err(intel_dp, dp_phy, "Failed to start channel equalization\n");
1039		return false;
1040	}
1041
1042	for (tries = 0; tries < 5; tries++) {
1043		usleep_range(delay_us, 2 * delay_us);
1044
1045		if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy,
1046						     link_status) < 0) {
1047			lt_err(intel_dp, dp_phy, "Failed to get link status\n");
 
1048			break;
1049		}
1050
1051		/* Make sure clock is still ok */
1052		if (!drm_dp_clock_recovery_ok(link_status,
1053					      crtc_state->lane_count)) {
1054			intel_dp_dump_link_status(intel_dp, dp_phy, link_status);
1055			lt_dbg(intel_dp, dp_phy,
1056			       "Clock recovery check failed, cannot continue channel equalization\n");
 
1057			break;
1058		}
1059
1060		if (drm_dp_channel_eq_ok(link_status,
1061					 crtc_state->lane_count)) {
1062			channel_eq = true;
1063			lt_dbg(intel_dp, dp_phy, "Channel EQ done. DP Training successful\n");
 
1064			break;
1065		}
1066
1067		/* Update training set as requested by target */
1068		intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy,
1069					  link_status);
1070		if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) {
1071			lt_err(intel_dp, dp_phy, "Failed to update link training\n");
1072			break;
1073		}
1074	}
1075
1076	/* Try 5 times, else fail and try at lower BW */
1077	if (tries == 5) {
1078		intel_dp_dump_link_status(intel_dp, dp_phy, link_status);
1079		lt_dbg(intel_dp, dp_phy, "Channel equalization failed 5 times\n");
 
1080	}
1081
1082	return channel_eq;
1083}
1084
1085static bool intel_dp_disable_dpcd_training_pattern(struct intel_dp *intel_dp,
1086						   enum drm_dp_phy dp_phy)
1087{
1088	int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy);
1089	u8 val = DP_TRAINING_PATTERN_DISABLE;
1090
1091	return drm_dp_dpcd_write(&intel_dp->aux, reg, &val, 1) == 1;
1092}
1093
1094static int
1095intel_dp_128b132b_intra_hop(struct intel_dp *intel_dp,
1096			    const struct intel_crtc_state *crtc_state)
1097{
1098	u8 sink_status;
1099	int ret;
1100
1101	ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_STATUS, &sink_status);
1102	if (ret != 1) {
1103		lt_dbg(intel_dp, DP_PHY_DPRX, "Failed to read sink status\n");
1104		return ret < 0 ? ret : -EIO;
1105	}
1106
1107	return sink_status & DP_INTRA_HOP_AUX_REPLY_INDICATION ? 1 : 0;
1108}
1109
1110/**
1111 * intel_dp_stop_link_train - stop link training
1112 * @intel_dp: DP struct
1113 * @crtc_state: state for CRTC attached to the encoder
1114 *
1115 * Stop the link training of the @intel_dp port, disabling the training
1116 * pattern in the sink's DPCD, and disabling the test pattern symbol
1117 * generation on the port.
1118 *
1119 * What symbols are output on the port after this point is
1120 * platform specific: On DDI/VLV/CHV platforms it will be the idle pattern
1121 * with the pipe being disabled, on older platforms it's HW specific if/how an
1122 * idle pattern is generated, as the pipe is already enabled here for those.
1123 *
1124 * This function must be called after intel_dp_start_link_train().
1125 */
1126void intel_dp_stop_link_train(struct intel_dp *intel_dp,
1127			      const struct intel_crtc_state *crtc_state)
1128{
1129	intel_dp->link_trained = true;
1130
1131	intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX);
1132	intel_dp_program_link_training_pattern(intel_dp, crtc_state, DP_PHY_DPRX,
1133					       DP_TRAINING_PATTERN_DISABLE);
1134
1135	if (intel_dp_is_uhbr(crtc_state) &&
1136	    wait_for(intel_dp_128b132b_intra_hop(intel_dp, crtc_state) == 0, 500)) {
1137		lt_dbg(intel_dp, DP_PHY_DPRX, "128b/132b intra-hop not clearing\n");
1138	}
1139}
1140
1141static bool
1142intel_dp_link_train_phy(struct intel_dp *intel_dp,
1143			const struct intel_crtc_state *crtc_state,
1144			enum drm_dp_phy dp_phy)
1145{
1146	bool ret = false;
1147
1148	if (!intel_dp_link_training_clock_recovery(intel_dp, crtc_state, dp_phy))
1149		goto out;
1150
1151	if (!intel_dp_link_training_channel_equalization(intel_dp, crtc_state, dp_phy))
1152		goto out;
1153
1154	ret = true;
1155
1156out:
1157	lt_dbg(intel_dp, dp_phy,
1158	       "Link Training %s at link rate = %d, lane count = %d\n",
1159	       ret ? "passed" : "failed",
1160	       crtc_state->port_clock, crtc_state->lane_count);
1161
1162	return ret;
1163}
1164
1165static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
1166						     int link_rate,
1167						     u8 lane_count)
1168{
1169	/* FIXME figure out what we actually want here */
1170	const struct drm_display_mode *fixed_mode =
1171		intel_panel_preferred_fixed_mode(intel_dp->attached_connector);
1172	int mode_rate, max_rate;
1173
1174	mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
1175	max_rate = intel_dp_max_link_data_rate(intel_dp, link_rate, lane_count);
1176	if (mode_rate > max_rate)
1177		return false;
1178
1179	return true;
1180}
1181
1182static bool reduce_link_params_in_bw_order(struct intel_dp *intel_dp,
1183					   const struct intel_crtc_state *crtc_state,
1184					   int *new_link_rate, int *new_lane_count)
1185{
1186	int link_rate;
1187	int lane_count;
1188	int i;
1189
1190	i = intel_dp_link_config_index(intel_dp, crtc_state->port_clock, crtc_state->lane_count);
1191	for (i--; i >= 0; i--) {
1192		intel_dp_link_config_get(intel_dp, i, &link_rate, &lane_count);
1193
1194		if ((intel_dp->link.force_rate &&
1195		     intel_dp->link.force_rate != link_rate) ||
1196		    (intel_dp->link.force_lane_count &&
1197		     intel_dp->link.force_lane_count != lane_count))
1198			continue;
1199
1200		break;
1201	}
1202
1203	if (i < 0)
1204		return false;
1205
1206	*new_link_rate = link_rate;
1207	*new_lane_count = lane_count;
1208
1209	return true;
1210}
1211
1212static int reduce_link_rate(struct intel_dp *intel_dp, int current_rate)
1213{
1214	int rate_index;
1215	int new_rate;
1216
1217	if (intel_dp->link.force_rate)
1218		return -1;
1219
1220	rate_index = intel_dp_rate_index(intel_dp->common_rates,
1221					 intel_dp->num_common_rates,
1222					 current_rate);
1223
1224	if (rate_index <= 0)
1225		return -1;
1226
1227	new_rate = intel_dp_common_rate(intel_dp, rate_index - 1);
1228
1229	/* TODO: Make switching from UHBR to non-UHBR rates work. */
1230	if (drm_dp_is_uhbr_rate(current_rate) != drm_dp_is_uhbr_rate(new_rate))
1231		return -1;
1232
1233	return new_rate;
1234}
1235
1236static int reduce_lane_count(struct intel_dp *intel_dp, int current_lane_count)
1237{
1238	if (intel_dp->link.force_lane_count)
1239		return -1;
1240
1241	if (current_lane_count == 1)
1242		return -1;
1243
1244	return current_lane_count >> 1;
1245}
1246
1247static bool reduce_link_params_in_rate_lane_order(struct intel_dp *intel_dp,
1248						  const struct intel_crtc_state *crtc_state,
1249						  int *new_link_rate, int *new_lane_count)
1250{
1251	int link_rate;
1252	int lane_count;
1253
1254	lane_count = crtc_state->lane_count;
1255	link_rate = reduce_link_rate(intel_dp, crtc_state->port_clock);
1256	if (link_rate < 0) {
1257		lane_count = reduce_lane_count(intel_dp, crtc_state->lane_count);
1258		link_rate = intel_dp_max_common_rate(intel_dp);
1259	}
1260
1261	if (lane_count < 0)
1262		return false;
1263
1264	*new_link_rate = link_rate;
1265	*new_lane_count = lane_count;
1266
1267	return true;
1268}
1269
1270static bool reduce_link_params(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state,
1271			       int *new_link_rate, int *new_lane_count)
1272{
1273	/* TODO: Use the same fallback logic on SST as on MST. */
1274	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
1275		return reduce_link_params_in_bw_order(intel_dp, crtc_state,
1276						      new_link_rate, new_lane_count);
1277	else
1278		return reduce_link_params_in_rate_lane_order(intel_dp, crtc_state,
1279							     new_link_rate, new_lane_count);
1280}
1281
1282static int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
1283						   const struct intel_crtc_state *crtc_state)
1284{
1285	int new_link_rate;
1286	int new_lane_count;
1287
1288	if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) {
1289		lt_dbg(intel_dp, DP_PHY_DPRX,
1290		       "Retrying Link training for eDP with max parameters\n");
1291		intel_dp->use_max_params = true;
1292		return 0;
1293	}
1294
1295	if (!reduce_link_params(intel_dp, crtc_state, &new_link_rate, &new_lane_count))
1296		return -1;
1297
1298	if (intel_dp_is_edp(intel_dp) &&
1299	    !intel_dp_can_link_train_fallback_for_edp(intel_dp, new_link_rate, new_lane_count)) {
1300		lt_dbg(intel_dp, DP_PHY_DPRX,
1301		       "Retrying Link training for eDP with same parameters\n");
1302		return 0;
1303	}
1304
1305	lt_dbg(intel_dp, DP_PHY_DPRX,
1306	       "Reducing link parameters from %dx%d to %dx%d\n",
1307	       crtc_state->lane_count, crtc_state->port_clock,
1308	       new_lane_count, new_link_rate);
1309
1310	intel_dp->link.max_rate = new_link_rate;
1311	intel_dp->link.max_lane_count = new_lane_count;
1312
1313	return 0;
1314}
1315
1316static bool intel_dp_schedule_fallback_link_training(struct intel_atomic_state *state,
1317						     struct intel_dp *intel_dp,
1318						     const struct intel_crtc_state *crtc_state)
1319{
1320	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1321
1322	if (!intel_digital_port_connected(&dp_to_dig_port(intel_dp)->base)) {
1323		lt_dbg(intel_dp, DP_PHY_DPRX, "Link Training failed on disconnected sink.\n");
1324		return true;
1325	}
1326
1327	if (intel_dp->hobl_active) {
1328		lt_dbg(intel_dp, DP_PHY_DPRX,
1329		       "Link Training failed with HOBL active, not enabling it from now on\n");
1330		intel_dp->hobl_failed = true;
1331	} else if (intel_dp_get_link_train_fallback_values(intel_dp, crtc_state)) {
1332		return false;
1333	}
1334
1335	/* Schedule a Hotplug Uevent to userspace to start modeset */
1336	intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state);
1337
1338	return true;
1339}
1340
1341/* Perform the link training on all LTTPRs and the DPRX on a link. */
1342static bool
1343intel_dp_link_train_all_phys(struct intel_dp *intel_dp,
1344			     const struct intel_crtc_state *crtc_state,
1345			     int lttpr_count)
1346{
1347	bool ret = true;
1348	int i;
1349
1350	for (i = lttpr_count - 1; i >= 0; i--) {
1351		enum drm_dp_phy dp_phy = DP_PHY_LTTPR(i);
1352
1353		ret = intel_dp_link_train_phy(intel_dp, crtc_state, dp_phy);
1354		intel_dp_disable_dpcd_training_pattern(intel_dp, dp_phy);
1355
1356		if (!ret)
1357			break;
1358	}
1359
1360	if (ret)
1361		ret = intel_dp_link_train_phy(intel_dp, crtc_state, DP_PHY_DPRX);
1362
1363	if (intel_dp->set_idle_link_train)
1364		intel_dp->set_idle_link_train(intel_dp, crtc_state);
1365
1366	return ret;
1367}
1368
1369/*
1370 * 128b/132b DP LANEx_EQ_DONE Sequence (DP 2.0 E11 3.5.2.16.1)
1371 */
1372static bool
1373intel_dp_128b132b_lane_eq(struct intel_dp *intel_dp,
1374			  const struct intel_crtc_state *crtc_state)
1375{
1376	u8 link_status[DP_LINK_STATUS_SIZE];
1377	int delay_us;
1378	int try, max_tries = 20;
1379	unsigned long deadline;
1380	bool timeout = false;
1381
1382	/*
1383	 * Reset signal levels. Start transmitting 128b/132b TPS1.
1384	 *
1385	 * Put DPRX and LTTPRs (if any) into intra-hop AUX mode by writing TPS1
1386	 * in DP_TRAINING_PATTERN_SET.
1387	 */
1388	if (!intel_dp_reset_link_train(intel_dp, crtc_state, DP_PHY_DPRX,
1389				       DP_TRAINING_PATTERN_1)) {
1390		lt_err(intel_dp, DP_PHY_DPRX, "Failed to start 128b/132b TPS1\n");
1391		return false;
1392	}
1393
1394	delay_us = drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux);
1395
1396	/* Read the initial TX FFE settings. */
1397	if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) {
1398		lt_err(intel_dp, DP_PHY_DPRX, "Failed to read TX FFE presets\n");
1399		return false;
1400	}
1401
1402	/* Update signal levels and training set as requested. */
1403	intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, link_status);
1404	if (!intel_dp_update_link_train(intel_dp, crtc_state, DP_PHY_DPRX)) {
1405		lt_err(intel_dp, DP_PHY_DPRX, "Failed to set initial TX FFE settings\n");
1406		return false;
1407	}
1408
1409	/* Start transmitting 128b/132b TPS2. */
1410	if (!intel_dp_set_link_train(intel_dp, crtc_state, DP_PHY_DPRX,
1411				     DP_TRAINING_PATTERN_2)) {
1412		lt_err(intel_dp, DP_PHY_DPRX, "Failed to start 128b/132b TPS2\n");
1413		return false;
1414	}
1415
1416	/* Time budget for the LANEx_EQ_DONE Sequence */
1417	deadline = jiffies + msecs_to_jiffies_timeout(400);
1418
1419	for (try = 0; try < max_tries; try++) {
1420		usleep_range(delay_us, 2 * delay_us);
1421
1422		/*
1423		 * The delay may get updated. The transmitter shall read the
1424		 * delay before link status during link training.
1425		 */
1426		delay_us = drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux);
1427
1428		if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) {
1429			lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n");
1430			return false;
1431		}
1432
1433		if (drm_dp_128b132b_link_training_failed(link_status)) {
1434			intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
1435			lt_err(intel_dp, DP_PHY_DPRX,
1436			       "Downstream link training failure\n");
1437			return false;
1438		}
1439
1440		if (drm_dp_128b132b_lane_channel_eq_done(link_status, crtc_state->lane_count)) {
1441			lt_dbg(intel_dp, DP_PHY_DPRX, "Lane channel eq done\n");
1442			break;
1443		}
1444
1445		if (timeout) {
1446			intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
1447			lt_err(intel_dp, DP_PHY_DPRX, "Lane channel eq timeout\n");
1448			return false;
1449		}
1450
1451		if (time_after(jiffies, deadline))
1452			timeout = true; /* try one last time after deadline */
1453
1454		/* Update signal levels and training set as requested. */
1455		intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, link_status);
1456		if (!intel_dp_update_link_train(intel_dp, crtc_state, DP_PHY_DPRX)) {
1457			lt_err(intel_dp, DP_PHY_DPRX, "Failed to update TX FFE settings\n");
1458			return false;
1459		}
1460	}
1461
1462	if (try == max_tries) {
1463		intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
1464		lt_err(intel_dp, DP_PHY_DPRX, "Max loop count reached\n");
1465		return false;
1466	}
1467
1468	for (;;) {
1469		if (time_after(jiffies, deadline))
1470			timeout = true; /* try one last time after deadline */
1471
1472		if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) {
1473			lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n");
1474			return false;
1475		}
1476
1477		if (drm_dp_128b132b_link_training_failed(link_status)) {
1478			intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
1479			lt_err(intel_dp, DP_PHY_DPRX, "Downstream link training failure\n");
1480			return false;
1481		}
1482
1483		if (drm_dp_128b132b_eq_interlane_align_done(link_status)) {
1484			lt_dbg(intel_dp, DP_PHY_DPRX, "Interlane align done\n");
1485			break;
1486		}
1487
1488		if (timeout) {
1489			intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
1490			lt_err(intel_dp, DP_PHY_DPRX, "Interlane align timeout\n");
1491			return false;
1492		}
1493
1494		usleep_range(2000, 3000);
1495	}
1496
1497	return true;
1498}
1499
1500/*
1501 * 128b/132b DP LANEx_CDS_DONE Sequence (DP 2.0 E11 3.5.2.16.2)
1502 */
1503static bool
1504intel_dp_128b132b_lane_cds(struct intel_dp *intel_dp,
1505			   const struct intel_crtc_state *crtc_state,
1506			   int lttpr_count)
1507{
1508	u8 link_status[DP_LINK_STATUS_SIZE];
1509	unsigned long deadline;
1510
1511	if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
1512			       DP_TRAINING_PATTERN_2_CDS) != 1) {
1513		lt_err(intel_dp, DP_PHY_DPRX, "Failed to start 128b/132b TPS2 CDS\n");
1514		return false;
1515	}
1516
1517	/* Time budget for the LANEx_CDS_DONE Sequence */
1518	deadline = jiffies + msecs_to_jiffies_timeout((lttpr_count + 1) * 20);
1519
1520	for (;;) {
1521		bool timeout = false;
1522
1523		if (time_after(jiffies, deadline))
1524			timeout = true; /* try one last time after deadline */
1525
1526		usleep_range(2000, 3000);
1527
1528		if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) {
1529			lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n");
1530			return false;
1531		}
1532
1533		if (drm_dp_128b132b_eq_interlane_align_done(link_status) &&
1534		    drm_dp_128b132b_cds_interlane_align_done(link_status) &&
1535		    drm_dp_128b132b_lane_symbol_locked(link_status, crtc_state->lane_count)) {
1536			lt_dbg(intel_dp, DP_PHY_DPRX, "CDS interlane align done\n");
1537			break;
1538		}
1539
1540		if (drm_dp_128b132b_link_training_failed(link_status)) {
1541			intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
1542			lt_err(intel_dp, DP_PHY_DPRX, "Downstream link training failure\n");
1543			return false;
1544		}
1545
1546		if (timeout) {
1547			intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
1548			lt_err(intel_dp, DP_PHY_DPRX, "CDS timeout\n");
1549			return false;
1550		}
1551	}
1552
1553	return true;
1554}
1555
1556/*
1557 * 128b/132b link training sequence. (DP 2.0 E11 SCR on link training.)
1558 */
1559static bool
1560intel_dp_128b132b_link_train(struct intel_dp *intel_dp,
1561			     const struct intel_crtc_state *crtc_state,
1562			     int lttpr_count)
1563{
1564	bool passed = false;
1565
1566	if (wait_for(intel_dp_128b132b_intra_hop(intel_dp, crtc_state) == 0, 500)) {
1567		lt_err(intel_dp, DP_PHY_DPRX, "128b/132b intra-hop not clear\n");
1568		goto out;
1569	}
1570
1571	if (intel_dp_128b132b_lane_eq(intel_dp, crtc_state) &&
1572	    intel_dp_128b132b_lane_cds(intel_dp, crtc_state, lttpr_count))
1573		passed = true;
1574
1575	lt_dbg(intel_dp, DP_PHY_DPRX,
1576	       "128b/132b Link Training %s at link rate = %d, lane count = %d\n",
1577	       passed ? "passed" : "failed",
1578	       crtc_state->port_clock, crtc_state->lane_count);
1579
1580out:
1581	/*
1582	 * Ensure that the training pattern does get set to TPS2 even in case
1583	 * of a failure, as is the case at the end of a passing link training
1584	 * and what is expected by the transcoder. Leaving TPS1 set (and
1585	 * disabling the link train mode in DP_TP_CTL later from TPS1 directly)
1586	 * would result in a stuck transcoder HW state and flip-done timeouts
1587	 * later in the modeset sequence.
1588	 */
1589	if (!passed)
1590		intel_dp_program_link_training_pattern(intel_dp, crtc_state,
1591						       DP_PHY_DPRX, DP_TRAINING_PATTERN_2);
1592
1593	return passed;
1594}
1595
1596/**
1597 * intel_dp_start_link_train - start link training
1598 * @state: Atomic state
1599 * @intel_dp: DP struct
1600 * @crtc_state: state for CRTC attached to the encoder
1601 *
1602 * Start the link training of the @intel_dp port, scheduling a fallback
1603 * retraining with reduced link rate/lane parameters if the link training
1604 * fails.
1605 * After calling this function intel_dp_stop_link_train() must be called.
1606 */
1607void intel_dp_start_link_train(struct intel_atomic_state *state,
1608			       struct intel_dp *intel_dp,
1609			       const struct intel_crtc_state *crtc_state)
1610{
1611	struct intel_display *display = to_intel_display(state);
1612	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1613	struct intel_encoder *encoder = &dig_port->base;
1614	bool passed;
1615	/*
1616	 * Reinit the LTTPRs here to ensure that they are switched to
1617	 * non-transparent mode. During an earlier LTTPR detection this
1618	 * could've been prevented by an active link.
1619	 */
1620	int lttpr_count = intel_dp_init_lttpr_and_dprx_caps(intel_dp);
1621
1622	if (lttpr_count < 0)
1623		/* Still continue with enabling the port and link training. */
1624		lttpr_count = 0;
1625
1626	intel_dp_prepare_link_train(intel_dp, crtc_state);
1627
1628	if (intel_dp_is_uhbr(crtc_state))
1629		passed = intel_dp_128b132b_link_train(intel_dp, crtc_state, lttpr_count);
1630	else
1631		passed = intel_dp_link_train_all_phys(intel_dp, crtc_state, lttpr_count);
1632
1633	if (intel_dp->link.force_train_failure) {
1634		intel_dp->link.force_train_failure--;
1635		lt_dbg(intel_dp, DP_PHY_DPRX, "Forcing link training failure\n");
1636	} else if (passed) {
1637		intel_dp->link.seq_train_failures = 0;
1638		intel_encoder_link_check_queue_work(encoder, 2000);
1639		return;
1640	}
1641
1642	intel_dp->link.seq_train_failures++;
1643
1644	/*
1645	 * Ignore the link failure in CI
1646	 *
1647	 * In fixed enviroments like CI, sometimes unexpected long HPDs are
1648	 * generated by the displays. If ignore_long_hpd flag is set, such long
1649	 * HPDs are ignored. And probably as a consequence of these ignored
1650	 * long HPDs, subsequent link trainings are failed resulting into CI
1651	 * execution failures.
1652	 *
1653	 * For test cases which rely on the link training or processing of HPDs
1654	 * ignore_long_hpd flag can unset from the testcase.
1655	 */
1656	if (display->hotplug.ignore_long_hpd) {
1657		lt_dbg(intel_dp, DP_PHY_DPRX, "Ignore the link failure\n");
1658		return;
1659	}
1660
1661	if (intel_dp->link.seq_train_failures < 2) {
1662		intel_encoder_link_check_queue_work(encoder, 0);
1663		return;
1664	}
1665
1666	if (intel_dp_schedule_fallback_link_training(state, intel_dp, crtc_state))
1667		return;
1668
1669	intel_dp->link.retrain_disabled = true;
1670
1671	if (!passed)
1672		lt_err(intel_dp, DP_PHY_DPRX, "Can't reduce link training parameters after failure\n");
1673	else
1674		lt_dbg(intel_dp, DP_PHY_DPRX, "Can't reduce link training parameters after forced failure\n");
1675}
1676
1677void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp,
1678				 const struct intel_crtc_state *crtc_state)
1679{
1680	/*
1681	 * VIDEO_DIP_CTL register bit 31 should be set to '0' to not
1682	 * disable SDP CRC. This is applicable for Display version 13.
1683	 * Default value of bit 31 is '0' hence discarding the write
1684	 * TODO: Corrective actions on SDP corruption yet to be defined
1685	 */
1686	if (!intel_dp_is_uhbr(crtc_state))
1687		return;
1688
1689	/* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */
1690	drm_dp_dpcd_writeb(&intel_dp->aux,
1691			   DP_SDP_ERROR_DETECTION_CONFIGURATION,
1692			   DP_SDP_CRC16_128B132B_EN);
1693
1694	lt_dbg(intel_dp, DP_PHY_DPRX, "DP2.0 SDP CRC16 for 128b/132b enabled\n");
1695}
1696
1697static int i915_dp_force_link_rate_show(struct seq_file *m, void *data)
1698{
1699	struct intel_connector *connector = to_intel_connector(m->private);
1700	struct intel_display *display = to_intel_display(connector);
1701	struct intel_dp *intel_dp = intel_attached_dp(connector);
1702	int current_rate = -1;
1703	int force_rate;
1704	int err;
1705	int i;
1706
1707	err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
1708	if (err)
1709		return err;
1710
1711	if (intel_dp->link_trained)
1712		current_rate = intel_dp->link_rate;
1713	force_rate = intel_dp->link.force_rate;
1714
1715	drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
1716
1717	seq_printf(m, "%sauto%s",
1718		   force_rate == 0 ? "[" : "",
1719		   force_rate == 0 ? "]" : "");
1720
1721	for (i = 0; i < intel_dp->num_source_rates; i++)
1722		seq_printf(m, " %s%d%s%s",
1723			   intel_dp->source_rates[i] == force_rate ? "[" : "",
1724			   intel_dp->source_rates[i],
1725			   intel_dp->source_rates[i] == current_rate ? "*" : "",
1726			   intel_dp->source_rates[i] == force_rate ? "]" : "");
1727
1728	seq_putc(m, '\n');
1729
1730	return 0;
1731}
1732
1733static int parse_link_rate(struct intel_dp *intel_dp, const char __user *ubuf, size_t len)
1734{
1735	char *kbuf;
1736	const char *p;
1737	int rate;
1738	int ret = 0;
1739
1740	kbuf = memdup_user_nul(ubuf, len);
1741	if (IS_ERR(kbuf))
1742		return PTR_ERR(kbuf);
1743
1744	p = strim(kbuf);
1745
1746	if (!strcmp(p, "auto")) {
1747		rate = 0;
1748	} else {
1749		ret = kstrtoint(p, 0, &rate);
1750		if (ret < 0)
1751			goto out_free;
1752
1753		if (intel_dp_rate_index(intel_dp->source_rates,
1754					intel_dp->num_source_rates,
1755					rate) < 0)
1756			ret = -EINVAL;
1757	}
1758
1759out_free:
1760	kfree(kbuf);
1761
1762	return ret < 0 ? ret : rate;
1763}
1764
1765static ssize_t i915_dp_force_link_rate_write(struct file *file,
1766					     const char __user *ubuf,
1767					     size_t len, loff_t *offp)
1768{
1769	struct seq_file *m = file->private_data;
1770	struct intel_connector *connector = to_intel_connector(m->private);
1771	struct intel_display *display = to_intel_display(connector);
1772	struct intel_dp *intel_dp = intel_attached_dp(connector);
1773	int rate;
1774	int err;
1775
1776	rate = parse_link_rate(intel_dp, ubuf, len);
1777	if (rate < 0)
1778		return rate;
1779
1780	err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
1781	if (err)
1782		return err;
1783
1784	intel_dp_reset_link_params(intel_dp);
1785	intel_dp->link.force_rate = rate;
1786
1787	drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
1788
1789	*offp += len;
1790
1791	return len;
1792}
1793DEFINE_SHOW_STORE_ATTRIBUTE(i915_dp_force_link_rate);
1794
1795static int i915_dp_force_lane_count_show(struct seq_file *m, void *data)
1796{
1797	struct intel_connector *connector = to_intel_connector(m->private);
1798	struct intel_display *display = to_intel_display(connector);
1799	struct intel_dp *intel_dp = intel_attached_dp(connector);
1800	int current_lane_count = -1;
1801	int force_lane_count;
1802	int err;
1803	int i;
1804
1805	err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
1806	if (err)
1807		return err;
1808
1809	if (intel_dp->link_trained)
1810		current_lane_count = intel_dp->lane_count;
1811	force_lane_count = intel_dp->link.force_lane_count;
1812
1813	drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
1814
1815	seq_printf(m, "%sauto%s",
1816		   force_lane_count == 0 ? "[" : "",
1817		   force_lane_count == 0 ? "]" : "");
1818
1819	for (i = 1; i <= 4; i <<= 1)
1820		seq_printf(m, " %s%d%s%s",
1821			   i == force_lane_count ? "[" : "",
1822			   i,
1823			   i == current_lane_count ? "*" : "",
1824			   i == force_lane_count ? "]" : "");
1825
1826	seq_putc(m, '\n');
1827
1828	return 0;
1829}
1830
1831static int parse_lane_count(const char __user *ubuf, size_t len)
1832{
1833	char *kbuf;
1834	const char *p;
1835	int lane_count;
1836	int ret = 0;
1837
1838	kbuf = memdup_user_nul(ubuf, len);
1839	if (IS_ERR(kbuf))
1840		return PTR_ERR(kbuf);
1841
1842	p = strim(kbuf);
1843
1844	if (!strcmp(p, "auto")) {
1845		lane_count = 0;
1846	} else {
1847		ret = kstrtoint(p, 0, &lane_count);
1848		if (ret < 0)
1849			goto out_free;
1850
1851		switch (lane_count) {
1852		case 1:
1853		case 2:
1854		case 4:
1855			break;
1856		default:
1857			ret = -EINVAL;
1858		}
1859	}
1860
1861out_free:
1862	kfree(kbuf);
1863
1864	return ret < 0 ? ret : lane_count;
1865}
1866
1867static ssize_t i915_dp_force_lane_count_write(struct file *file,
1868					      const char __user *ubuf,
1869					      size_t len, loff_t *offp)
1870{
1871	struct seq_file *m = file->private_data;
1872	struct intel_connector *connector = to_intel_connector(m->private);
1873	struct intel_display *display = to_intel_display(connector);
1874	struct intel_dp *intel_dp = intel_attached_dp(connector);
1875	int lane_count;
1876	int err;
1877
1878	lane_count = parse_lane_count(ubuf, len);
1879	if (lane_count < 0)
1880		return lane_count;
1881
1882	err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
1883	if (err)
1884		return err;
1885
1886	intel_dp_reset_link_params(intel_dp);
1887	intel_dp->link.force_lane_count = lane_count;
1888
1889	drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
1890
1891	*offp += len;
1892
1893	return len;
1894}
1895DEFINE_SHOW_STORE_ATTRIBUTE(i915_dp_force_lane_count);
1896
1897static int i915_dp_max_link_rate_show(void *data, u64 *val)
1898{
1899	struct intel_connector *connector = to_intel_connector(data);
1900	struct intel_display *display = to_intel_display(connector);
1901	struct intel_dp *intel_dp = intel_attached_dp(connector);
1902	int err;
1903
1904	err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
1905	if (err)
1906		return err;
1907
1908	*val = intel_dp->link.max_rate;
1909
1910	drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
1911
1912	return 0;
1913}
1914DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_max_link_rate_fops, i915_dp_max_link_rate_show, NULL, "%llu\n");
1915
1916static int i915_dp_max_lane_count_show(void *data, u64 *val)
1917{
1918	struct intel_connector *connector = to_intel_connector(data);
1919	struct intel_display *display = to_intel_display(connector);
1920	struct intel_dp *intel_dp = intel_attached_dp(connector);
1921	int err;
1922
1923	err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
1924	if (err)
1925		return err;
1926
1927	*val = intel_dp->link.max_lane_count;
1928
1929	drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
1930
1931	return 0;
1932}
1933DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_max_lane_count_fops, i915_dp_max_lane_count_show, NULL, "%llu\n");
1934
1935static int i915_dp_force_link_training_failure_show(void *data, u64 *val)
1936{
1937	struct intel_connector *connector = to_intel_connector(data);
1938	struct intel_display *display = to_intel_display(connector);
1939	struct intel_dp *intel_dp = intel_attached_dp(connector);
1940	int err;
1941
1942	err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
1943	if (err)
1944		return err;
1945
1946	*val = intel_dp->link.force_train_failure;
1947
1948	drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
1949
1950	return 0;
1951}
1952
1953static int i915_dp_force_link_training_failure_write(void *data, u64 val)
1954{
1955	struct intel_connector *connector = to_intel_connector(data);
1956	struct intel_display *display = to_intel_display(connector);
1957	struct intel_dp *intel_dp = intel_attached_dp(connector);
1958	int err;
1959
1960	if (val > 2)
1961		return -EINVAL;
1962
1963	err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
1964	if (err)
1965		return err;
1966
1967	intel_dp->link.force_train_failure = val;
1968
1969	drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
1970
1971	return 0;
1972}
1973DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_force_link_training_failure_fops,
1974			 i915_dp_force_link_training_failure_show,
1975			 i915_dp_force_link_training_failure_write, "%llu\n");
1976
1977static int i915_dp_force_link_retrain_show(void *data, u64 *val)
1978{
1979	struct intel_connector *connector = to_intel_connector(data);
1980	struct intel_display *display = to_intel_display(connector);
1981	struct intel_dp *intel_dp = intel_attached_dp(connector);
1982	int err;
1983
1984	err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
1985	if (err)
1986		return err;
1987
1988	*val = intel_dp->link.force_retrain;
1989
1990	drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
1991
1992	return 0;
1993}
1994
1995static int i915_dp_force_link_retrain_write(void *data, u64 val)
1996{
1997	struct intel_connector *connector = to_intel_connector(data);
1998	struct intel_display *display = to_intel_display(connector);
1999	struct intel_dp *intel_dp = intel_attached_dp(connector);
2000	int err;
2001
2002	err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
2003	if (err)
2004		return err;
2005
2006	intel_dp->link.force_retrain = val;
2007
2008	drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
2009
2010	intel_hpd_trigger_irq(dp_to_dig_port(intel_dp));
2011
2012	return 0;
2013}
2014DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_force_link_retrain_fops,
2015			 i915_dp_force_link_retrain_show,
2016			 i915_dp_force_link_retrain_write, "%llu\n");
2017
2018static int i915_dp_link_retrain_disabled_show(struct seq_file *m, void *data)
2019{
2020	struct intel_connector *connector = to_intel_connector(m->private);
2021	struct intel_display *display = to_intel_display(connector);
2022	struct intel_dp *intel_dp = intel_attached_dp(connector);
2023	int err;
2024
2025	err = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex);
2026	if (err)
2027		return err;
2028
2029	seq_printf(m, "%s\n", str_yes_no(intel_dp->link.retrain_disabled));
2030
2031	drm_modeset_unlock(&display->drm->mode_config.connection_mutex);
2032
2033	return 0;
2034}
2035DEFINE_SHOW_ATTRIBUTE(i915_dp_link_retrain_disabled);
2036
2037void intel_dp_link_training_debugfs_add(struct intel_connector *connector)
2038{
2039	struct dentry *root = connector->base.debugfs_entry;
2040
2041	if (connector->base.connector_type != DRM_MODE_CONNECTOR_DisplayPort &&
2042	    connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
2043		return;
2044
2045	debugfs_create_file("i915_dp_force_link_rate", 0644, root,
2046			    connector, &i915_dp_force_link_rate_fops);
2047
2048	debugfs_create_file("i915_dp_force_lane_count", 0644, root,
2049			    connector, &i915_dp_force_lane_count_fops);
2050
2051	debugfs_create_file("i915_dp_max_link_rate", 0444, root,
2052			    connector, &i915_dp_max_link_rate_fops);
2053
2054	debugfs_create_file("i915_dp_max_lane_count", 0444, root,
2055			    connector, &i915_dp_max_lane_count_fops);
2056
2057	debugfs_create_file("i915_dp_force_link_training_failure", 0644, root,
2058			    connector, &i915_dp_force_link_training_failure_fops);
2059
2060	debugfs_create_file("i915_dp_force_link_retrain", 0644, root,
2061			    connector, &i915_dp_force_link_retrain_fops);
2062
2063	debugfs_create_file("i915_dp_link_retrain_disabled", 0444, root,
2064			    connector, &i915_dp_link_retrain_disabled_fops);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
2065}