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1// SPDX-License-Identifier: GPL-2.0-only
2/**************************************************************************
3 * Copyright (c) 2007, Intel Corporation.
4 * All Rights Reserved.
5 *
6 * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
7 * develop this driver.
8 *
9 **************************************************************************/
10
11#include <drm/drm_drv.h>
12#include <drm/drm_vblank.h>
13
14#include "power.h"
15#include "psb_drv.h"
16#include "psb_intel_reg.h"
17#include "psb_irq.h"
18#include "psb_reg.h"
19
20/*
21 * inline functions
22 */
23
24static inline u32 gma_pipestat(int pipe)
25{
26 if (pipe == 0)
27 return PIPEASTAT;
28 if (pipe == 1)
29 return PIPEBSTAT;
30 if (pipe == 2)
31 return PIPECSTAT;
32 BUG();
33}
34
35static inline u32 gma_pipeconf(int pipe)
36{
37 if (pipe == 0)
38 return PIPEACONF;
39 if (pipe == 1)
40 return PIPEBCONF;
41 if (pipe == 2)
42 return PIPECCONF;
43 BUG();
44}
45
46void gma_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask)
47{
48 if ((dev_priv->pipestat[pipe] & mask) != mask) {
49 u32 reg = gma_pipestat(pipe);
50 dev_priv->pipestat[pipe] |= mask;
51 /* Enable the interrupt, clear any pending status */
52 if (gma_power_begin(&dev_priv->dev, false)) {
53 u32 writeVal = PSB_RVDC32(reg);
54 writeVal |= (mask | (mask >> 16));
55 PSB_WVDC32(writeVal, reg);
56 (void) PSB_RVDC32(reg);
57 gma_power_end(&dev_priv->dev);
58 }
59 }
60}
61
62void gma_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask)
63{
64 if ((dev_priv->pipestat[pipe] & mask) != 0) {
65 u32 reg = gma_pipestat(pipe);
66 dev_priv->pipestat[pipe] &= ~mask;
67 if (gma_power_begin(&dev_priv->dev, false)) {
68 u32 writeVal = PSB_RVDC32(reg);
69 writeVal &= ~mask;
70 PSB_WVDC32(writeVal, reg);
71 (void) PSB_RVDC32(reg);
72 gma_power_end(&dev_priv->dev);
73 }
74 }
75}
76
77/*
78 * Display controller interrupt handler for pipe event.
79 */
80static void gma_pipe_event_handler(struct drm_device *dev, int pipe)
81{
82 struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
83
84 uint32_t pipe_stat_val = 0;
85 uint32_t pipe_stat_reg = gma_pipestat(pipe);
86 uint32_t pipe_enable = dev_priv->pipestat[pipe];
87 uint32_t pipe_status = dev_priv->pipestat[pipe] >> 16;
88 uint32_t pipe_clear;
89 uint32_t i = 0;
90
91 spin_lock(&dev_priv->irqmask_lock);
92
93 pipe_stat_val = PSB_RVDC32(pipe_stat_reg);
94 pipe_stat_val &= pipe_enable | pipe_status;
95 pipe_stat_val &= pipe_stat_val >> 16;
96
97 spin_unlock(&dev_priv->irqmask_lock);
98
99 /* Clear the 2nd level interrupt status bits
100 * Sometimes the bits are very sticky so we repeat until they unstick */
101 for (i = 0; i < 0xffff; i++) {
102 PSB_WVDC32(PSB_RVDC32(pipe_stat_reg), pipe_stat_reg);
103 pipe_clear = PSB_RVDC32(pipe_stat_reg) & pipe_status;
104
105 if (pipe_clear == 0)
106 break;
107 }
108
109 if (pipe_clear)
110 dev_err(dev->dev,
111 "%s, can't clear status bits for pipe %d, its value = 0x%x.\n",
112 __func__, pipe, PSB_RVDC32(pipe_stat_reg));
113
114 if (pipe_stat_val & PIPE_VBLANK_STATUS) {
115 struct drm_crtc *crtc = drm_crtc_from_index(dev, pipe);
116 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
117 unsigned long flags;
118
119 drm_handle_vblank(dev, pipe);
120
121 spin_lock_irqsave(&dev->event_lock, flags);
122 if (gma_crtc->page_flip_event) {
123 drm_crtc_send_vblank_event(crtc,
124 gma_crtc->page_flip_event);
125 gma_crtc->page_flip_event = NULL;
126 drm_crtc_vblank_put(crtc);
127 }
128 spin_unlock_irqrestore(&dev->event_lock, flags);
129 }
130}
131
132/*
133 * Display controller interrupt handler.
134 */
135static void gma_vdc_interrupt(struct drm_device *dev, uint32_t vdc_stat)
136{
137 if (vdc_stat & _PSB_IRQ_ASLE)
138 psb_intel_opregion_asle_intr(dev);
139
140 if (vdc_stat & _PSB_VSYNC_PIPEA_FLAG)
141 gma_pipe_event_handler(dev, 0);
142
143 if (vdc_stat & _PSB_VSYNC_PIPEB_FLAG)
144 gma_pipe_event_handler(dev, 1);
145}
146
147/*
148 * SGX interrupt handler
149 */
150static void gma_sgx_interrupt(struct drm_device *dev, u32 stat_1, u32 stat_2)
151{
152 struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
153 u32 val, addr;
154
155 if (stat_1 & _PSB_CE_TWOD_COMPLETE)
156 val = PSB_RSGX32(PSB_CR_2D_BLIT_STATUS);
157
158 if (stat_2 & _PSB_CE2_BIF_REQUESTER_FAULT) {
159 val = PSB_RSGX32(PSB_CR_BIF_INT_STAT);
160 addr = PSB_RSGX32(PSB_CR_BIF_FAULT);
161 if (val) {
162 if (val & _PSB_CBI_STAT_PF_N_RW)
163 DRM_ERROR("SGX MMU page fault:");
164 else
165 DRM_ERROR("SGX MMU read / write protection fault:");
166
167 if (val & _PSB_CBI_STAT_FAULT_CACHE)
168 DRM_ERROR("\tCache requestor");
169 if (val & _PSB_CBI_STAT_FAULT_TA)
170 DRM_ERROR("\tTA requestor");
171 if (val & _PSB_CBI_STAT_FAULT_VDM)
172 DRM_ERROR("\tVDM requestor");
173 if (val & _PSB_CBI_STAT_FAULT_2D)
174 DRM_ERROR("\t2D requestor");
175 if (val & _PSB_CBI_STAT_FAULT_PBE)
176 DRM_ERROR("\tPBE requestor");
177 if (val & _PSB_CBI_STAT_FAULT_TSP)
178 DRM_ERROR("\tTSP requestor");
179 if (val & _PSB_CBI_STAT_FAULT_ISP)
180 DRM_ERROR("\tISP requestor");
181 if (val & _PSB_CBI_STAT_FAULT_USSEPDS)
182 DRM_ERROR("\tUSSEPDS requestor");
183 if (val & _PSB_CBI_STAT_FAULT_HOST)
184 DRM_ERROR("\tHost requestor");
185
186 DRM_ERROR("\tMMU failing address is 0x%08x.\n",
187 (unsigned int)addr);
188 }
189 }
190
191 /* Clear bits */
192 PSB_WSGX32(stat_1, PSB_CR_EVENT_HOST_CLEAR);
193 PSB_WSGX32(stat_2, PSB_CR_EVENT_HOST_CLEAR2);
194 PSB_RSGX32(PSB_CR_EVENT_HOST_CLEAR2);
195}
196
197static irqreturn_t gma_irq_handler(int irq, void *arg)
198{
199 struct drm_device *dev = arg;
200 struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
201 uint32_t vdc_stat, dsp_int = 0, sgx_int = 0, hotplug_int = 0;
202 u32 sgx_stat_1, sgx_stat_2;
203 int handled = 0;
204
205 spin_lock(&dev_priv->irqmask_lock);
206
207 vdc_stat = PSB_RVDC32(PSB_INT_IDENTITY_R);
208
209 if (vdc_stat & (_PSB_PIPE_EVENT_FLAG|_PSB_IRQ_ASLE))
210 dsp_int = 1;
211
212 if (vdc_stat & _PSB_IRQ_SGX_FLAG)
213 sgx_int = 1;
214 if (vdc_stat & _PSB_IRQ_DISP_HOTSYNC)
215 hotplug_int = 1;
216
217 vdc_stat &= dev_priv->vdc_irq_mask;
218 spin_unlock(&dev_priv->irqmask_lock);
219
220 if (dsp_int) {
221 gma_vdc_interrupt(dev, vdc_stat);
222 handled = 1;
223 }
224
225 if (sgx_int) {
226 sgx_stat_1 = PSB_RSGX32(PSB_CR_EVENT_STATUS);
227 sgx_stat_2 = PSB_RSGX32(PSB_CR_EVENT_STATUS2);
228 gma_sgx_interrupt(dev, sgx_stat_1, sgx_stat_2);
229 handled = 1;
230 }
231
232 /* Note: this bit has other meanings on some devices, so we will
233 need to address that later if it ever matters */
234 if (hotplug_int && dev_priv->ops->hotplug) {
235 handled = dev_priv->ops->hotplug(dev);
236 REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT));
237 }
238
239 PSB_WVDC32(vdc_stat, PSB_INT_IDENTITY_R);
240 (void) PSB_RVDC32(PSB_INT_IDENTITY_R);
241 rmb();
242
243 if (!handled)
244 return IRQ_NONE;
245
246 return IRQ_HANDLED;
247}
248
249void gma_irq_preinstall(struct drm_device *dev)
250{
251 struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
252 unsigned long irqflags;
253
254 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
255
256 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
257 PSB_WVDC32(0x00000000, PSB_INT_MASK_R);
258 PSB_WVDC32(0x00000000, PSB_INT_ENABLE_R);
259 PSB_WSGX32(0x00000000, PSB_CR_EVENT_HOST_ENABLE);
260 PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE);
261
262 if (dev->vblank[0].enabled)
263 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEA_FLAG;
264 if (dev->vblank[1].enabled)
265 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEB_FLAG;
266
267 /* Revisit this area - want per device masks ? */
268 if (dev_priv->ops->hotplug)
269 dev_priv->vdc_irq_mask |= _PSB_IRQ_DISP_HOTSYNC;
270 dev_priv->vdc_irq_mask |= _PSB_IRQ_ASLE | _PSB_IRQ_SGX_FLAG;
271
272 /* This register is safe even if display island is off */
273 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
274 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
275}
276
277void gma_irq_postinstall(struct drm_device *dev)
278{
279 struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
280 unsigned long irqflags;
281 unsigned int i;
282
283 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
284
285 /* Enable 2D and MMU fault interrupts */
286 PSB_WSGX32(_PSB_CE2_BIF_REQUESTER_FAULT, PSB_CR_EVENT_HOST_ENABLE2);
287 PSB_WSGX32(_PSB_CE_TWOD_COMPLETE, PSB_CR_EVENT_HOST_ENABLE);
288 PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE); /* Post */
289
290 /* This register is safe even if display island is off */
291 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
292 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
293
294 for (i = 0; i < dev->num_crtcs; ++i) {
295 if (dev->vblank[i].enabled)
296 gma_enable_pipestat(dev_priv, i, PIPE_VBLANK_INTERRUPT_ENABLE);
297 else
298 gma_disable_pipestat(dev_priv, i, PIPE_VBLANK_INTERRUPT_ENABLE);
299 }
300
301 if (dev_priv->ops->hotplug_enable)
302 dev_priv->ops->hotplug_enable(dev, true);
303
304 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
305}
306
307int gma_irq_install(struct drm_device *dev)
308{
309 struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
310 struct pci_dev *pdev = to_pci_dev(dev->dev);
311 int ret;
312
313 if (dev_priv->use_msi && pci_enable_msi(pdev)) {
314 dev_warn(dev->dev, "Enabling MSI failed!\n");
315 dev_priv->use_msi = false;
316 }
317
318 if (pdev->irq == IRQ_NOTCONNECTED)
319 return -ENOTCONN;
320
321 gma_irq_preinstall(dev);
322
323 /* PCI devices require shared interrupts. */
324 ret = request_irq(pdev->irq, gma_irq_handler, IRQF_SHARED, dev->driver->name, dev);
325 if (ret)
326 return ret;
327
328 gma_irq_postinstall(dev);
329
330 dev_priv->irq_enabled = true;
331
332 return 0;
333}
334
335void gma_irq_uninstall(struct drm_device *dev)
336{
337 struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
338 struct pci_dev *pdev = to_pci_dev(dev->dev);
339 unsigned long irqflags;
340 unsigned int i;
341
342 if (!dev_priv->irq_enabled)
343 return;
344
345 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
346
347 if (dev_priv->ops->hotplug_enable)
348 dev_priv->ops->hotplug_enable(dev, false);
349
350 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
351
352 for (i = 0; i < dev->num_crtcs; ++i) {
353 if (dev->vblank[i].enabled)
354 gma_disable_pipestat(dev_priv, i, PIPE_VBLANK_INTERRUPT_ENABLE);
355 }
356
357 dev_priv->vdc_irq_mask &= _PSB_IRQ_SGX_FLAG |
358 _PSB_IRQ_MSVDX_FLAG |
359 _LNC_IRQ_TOPAZ_FLAG;
360
361 /* These two registers are safe even if display island is off */
362 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
363 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
364
365 wmb();
366
367 /* This register is safe even if display island is off */
368 PSB_WVDC32(PSB_RVDC32(PSB_INT_IDENTITY_R), PSB_INT_IDENTITY_R);
369 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
370
371 free_irq(pdev->irq, dev);
372 if (dev_priv->use_msi)
373 pci_disable_msi(pdev);
374}
375
376int gma_crtc_enable_vblank(struct drm_crtc *crtc)
377{
378 struct drm_device *dev = crtc->dev;
379 unsigned int pipe = crtc->index;
380 struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
381 unsigned long irqflags;
382 uint32_t reg_val = 0;
383 uint32_t pipeconf_reg = gma_pipeconf(pipe);
384
385 if (gma_power_begin(dev, false)) {
386 reg_val = REG_READ(pipeconf_reg);
387 gma_power_end(dev);
388 }
389
390 if (!(reg_val & PIPEACONF_ENABLE))
391 return -EINVAL;
392
393 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
394
395 if (pipe == 0)
396 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEA_FLAG;
397 else if (pipe == 1)
398 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEB_FLAG;
399
400 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
401 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
402 gma_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE);
403
404 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
405
406 return 0;
407}
408
409void gma_crtc_disable_vblank(struct drm_crtc *crtc)
410{
411 struct drm_device *dev = crtc->dev;
412 unsigned int pipe = crtc->index;
413 struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
414 unsigned long irqflags;
415
416 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
417
418 if (pipe == 0)
419 dev_priv->vdc_irq_mask &= ~_PSB_VSYNC_PIPEA_FLAG;
420 else if (pipe == 1)
421 dev_priv->vdc_irq_mask &= ~_PSB_VSYNC_PIPEB_FLAG;
422
423 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
424 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
425 gma_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE);
426
427 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
428}
429
430/* Called from drm generic code, passed a 'crtc', which
431 * we use as a pipe index
432 */
433u32 gma_crtc_get_vblank_counter(struct drm_crtc *crtc)
434{
435 struct drm_device *dev = crtc->dev;
436 unsigned int pipe = crtc->index;
437 uint32_t high_frame = PIPEAFRAMEHIGH;
438 uint32_t low_frame = PIPEAFRAMEPIXEL;
439 uint32_t pipeconf_reg = PIPEACONF;
440 uint32_t reg_val = 0;
441 uint32_t high1 = 0, high2 = 0, low = 0, count = 0;
442
443 switch (pipe) {
444 case 0:
445 break;
446 case 1:
447 high_frame = PIPEBFRAMEHIGH;
448 low_frame = PIPEBFRAMEPIXEL;
449 pipeconf_reg = PIPEBCONF;
450 break;
451 case 2:
452 high_frame = PIPECFRAMEHIGH;
453 low_frame = PIPECFRAMEPIXEL;
454 pipeconf_reg = PIPECCONF;
455 break;
456 default:
457 dev_err(dev->dev, "%s, invalid pipe.\n", __func__);
458 return 0;
459 }
460
461 if (!gma_power_begin(dev, false))
462 return 0;
463
464 reg_val = REG_READ(pipeconf_reg);
465
466 if (!(reg_val & PIPEACONF_ENABLE)) {
467 dev_err(dev->dev, "trying to get vblank count for disabled pipe %u\n",
468 pipe);
469 goto err_gma_power_end;
470 }
471
472 /*
473 * High & low register fields aren't synchronized, so make sure
474 * we get a low value that's stable across two reads of the high
475 * register.
476 */
477 do {
478 high1 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
479 PIPE_FRAME_HIGH_SHIFT);
480 low = ((REG_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
481 PIPE_FRAME_LOW_SHIFT);
482 high2 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
483 PIPE_FRAME_HIGH_SHIFT);
484 } while (high1 != high2);
485
486 count = (high1 << 8) | low;
487
488err_gma_power_end:
489 gma_power_end(dev);
490
491 return count;
492}
493
1// SPDX-License-Identifier: GPL-2.0-only
2/**************************************************************************
3 * Copyright (c) 2007, Intel Corporation.
4 * All Rights Reserved.
5 *
6 * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
7 * develop this driver.
8 *
9 **************************************************************************/
10
11#include <drm/drm_vblank.h>
12
13#include "mdfld_output.h"
14#include "power.h"
15#include "psb_drv.h"
16#include "psb_intel_reg.h"
17#include "psb_irq.h"
18#include "psb_reg.h"
19
20/*
21 * inline functions
22 */
23
24static inline u32
25psb_pipestat(int pipe)
26{
27 if (pipe == 0)
28 return PIPEASTAT;
29 if (pipe == 1)
30 return PIPEBSTAT;
31 if (pipe == 2)
32 return PIPECSTAT;
33 BUG();
34}
35
36static inline u32
37mid_pipe_event(int pipe)
38{
39 if (pipe == 0)
40 return _PSB_PIPEA_EVENT_FLAG;
41 if (pipe == 1)
42 return _MDFLD_PIPEB_EVENT_FLAG;
43 if (pipe == 2)
44 return _MDFLD_PIPEC_EVENT_FLAG;
45 BUG();
46}
47
48static inline u32
49mid_pipe_vsync(int pipe)
50{
51 if (pipe == 0)
52 return _PSB_VSYNC_PIPEA_FLAG;
53 if (pipe == 1)
54 return _PSB_VSYNC_PIPEB_FLAG;
55 if (pipe == 2)
56 return _MDFLD_PIPEC_VBLANK_FLAG;
57 BUG();
58}
59
60static inline u32
61mid_pipeconf(int pipe)
62{
63 if (pipe == 0)
64 return PIPEACONF;
65 if (pipe == 1)
66 return PIPEBCONF;
67 if (pipe == 2)
68 return PIPECCONF;
69 BUG();
70}
71
72void
73psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask)
74{
75 if ((dev_priv->pipestat[pipe] & mask) != mask) {
76 u32 reg = psb_pipestat(pipe);
77 dev_priv->pipestat[pipe] |= mask;
78 /* Enable the interrupt, clear any pending status */
79 if (gma_power_begin(dev_priv->dev, false)) {
80 u32 writeVal = PSB_RVDC32(reg);
81 writeVal |= (mask | (mask >> 16));
82 PSB_WVDC32(writeVal, reg);
83 (void) PSB_RVDC32(reg);
84 gma_power_end(dev_priv->dev);
85 }
86 }
87}
88
89void
90psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask)
91{
92 if ((dev_priv->pipestat[pipe] & mask) != 0) {
93 u32 reg = psb_pipestat(pipe);
94 dev_priv->pipestat[pipe] &= ~mask;
95 if (gma_power_begin(dev_priv->dev, false)) {
96 u32 writeVal = PSB_RVDC32(reg);
97 writeVal &= ~mask;
98 PSB_WVDC32(writeVal, reg);
99 (void) PSB_RVDC32(reg);
100 gma_power_end(dev_priv->dev);
101 }
102 }
103}
104
105static void mid_enable_pipe_event(struct drm_psb_private *dev_priv, int pipe)
106{
107 if (gma_power_begin(dev_priv->dev, false)) {
108 u32 pipe_event = mid_pipe_event(pipe);
109 dev_priv->vdc_irq_mask |= pipe_event;
110 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
111 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
112 gma_power_end(dev_priv->dev);
113 }
114}
115
116static void mid_disable_pipe_event(struct drm_psb_private *dev_priv, int pipe)
117{
118 if (dev_priv->pipestat[pipe] == 0) {
119 if (gma_power_begin(dev_priv->dev, false)) {
120 u32 pipe_event = mid_pipe_event(pipe);
121 dev_priv->vdc_irq_mask &= ~pipe_event;
122 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
123 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
124 gma_power_end(dev_priv->dev);
125 }
126 }
127}
128
129/**
130 * Display controller interrupt handler for pipe event.
131 *
132 */
133static void mid_pipe_event_handler(struct drm_device *dev, int pipe)
134{
135 struct drm_psb_private *dev_priv =
136 (struct drm_psb_private *) dev->dev_private;
137
138 uint32_t pipe_stat_val = 0;
139 uint32_t pipe_stat_reg = psb_pipestat(pipe);
140 uint32_t pipe_enable = dev_priv->pipestat[pipe];
141 uint32_t pipe_status = dev_priv->pipestat[pipe] >> 16;
142 uint32_t pipe_clear;
143 uint32_t i = 0;
144
145 spin_lock(&dev_priv->irqmask_lock);
146
147 pipe_stat_val = PSB_RVDC32(pipe_stat_reg);
148 pipe_stat_val &= pipe_enable | pipe_status;
149 pipe_stat_val &= pipe_stat_val >> 16;
150
151 spin_unlock(&dev_priv->irqmask_lock);
152
153 /* Clear the 2nd level interrupt status bits
154 * Sometimes the bits are very sticky so we repeat until they unstick */
155 for (i = 0; i < 0xffff; i++) {
156 PSB_WVDC32(PSB_RVDC32(pipe_stat_reg), pipe_stat_reg);
157 pipe_clear = PSB_RVDC32(pipe_stat_reg) & pipe_status;
158
159 if (pipe_clear == 0)
160 break;
161 }
162
163 if (pipe_clear)
164 dev_err(dev->dev,
165 "%s, can't clear status bits for pipe %d, its value = 0x%x.\n",
166 __func__, pipe, PSB_RVDC32(pipe_stat_reg));
167
168 if (pipe_stat_val & PIPE_VBLANK_STATUS ||
169 (IS_MFLD(dev) && pipe_stat_val & PIPE_TE_STATUS)) {
170 struct drm_crtc *crtc = drm_crtc_from_index(dev, pipe);
171 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
172 unsigned long flags;
173
174 drm_handle_vblank(dev, pipe);
175
176 spin_lock_irqsave(&dev->event_lock, flags);
177 if (gma_crtc->page_flip_event) {
178 drm_crtc_send_vblank_event(crtc,
179 gma_crtc->page_flip_event);
180 gma_crtc->page_flip_event = NULL;
181 drm_crtc_vblank_put(crtc);
182 }
183 spin_unlock_irqrestore(&dev->event_lock, flags);
184 }
185}
186
187/*
188 * Display controller interrupt handler.
189 */
190static void psb_vdc_interrupt(struct drm_device *dev, uint32_t vdc_stat)
191{
192 if (vdc_stat & _PSB_IRQ_ASLE)
193 psb_intel_opregion_asle_intr(dev);
194
195 if (vdc_stat & _PSB_VSYNC_PIPEA_FLAG)
196 mid_pipe_event_handler(dev, 0);
197
198 if (vdc_stat & _PSB_VSYNC_PIPEB_FLAG)
199 mid_pipe_event_handler(dev, 1);
200}
201
202/*
203 * SGX interrupt handler
204 */
205static void psb_sgx_interrupt(struct drm_device *dev, u32 stat_1, u32 stat_2)
206{
207 struct drm_psb_private *dev_priv = dev->dev_private;
208 u32 val, addr;
209
210 if (stat_1 & _PSB_CE_TWOD_COMPLETE)
211 val = PSB_RSGX32(PSB_CR_2D_BLIT_STATUS);
212
213 if (stat_2 & _PSB_CE2_BIF_REQUESTER_FAULT) {
214 val = PSB_RSGX32(PSB_CR_BIF_INT_STAT);
215 addr = PSB_RSGX32(PSB_CR_BIF_FAULT);
216 if (val) {
217 if (val & _PSB_CBI_STAT_PF_N_RW)
218 DRM_ERROR("SGX MMU page fault:");
219 else
220 DRM_ERROR("SGX MMU read / write protection fault:");
221
222 if (val & _PSB_CBI_STAT_FAULT_CACHE)
223 DRM_ERROR("\tCache requestor");
224 if (val & _PSB_CBI_STAT_FAULT_TA)
225 DRM_ERROR("\tTA requestor");
226 if (val & _PSB_CBI_STAT_FAULT_VDM)
227 DRM_ERROR("\tVDM requestor");
228 if (val & _PSB_CBI_STAT_FAULT_2D)
229 DRM_ERROR("\t2D requestor");
230 if (val & _PSB_CBI_STAT_FAULT_PBE)
231 DRM_ERROR("\tPBE requestor");
232 if (val & _PSB_CBI_STAT_FAULT_TSP)
233 DRM_ERROR("\tTSP requestor");
234 if (val & _PSB_CBI_STAT_FAULT_ISP)
235 DRM_ERROR("\tISP requestor");
236 if (val & _PSB_CBI_STAT_FAULT_USSEPDS)
237 DRM_ERROR("\tUSSEPDS requestor");
238 if (val & _PSB_CBI_STAT_FAULT_HOST)
239 DRM_ERROR("\tHost requestor");
240
241 DRM_ERROR("\tMMU failing address is 0x%08x.\n",
242 (unsigned int)addr);
243 }
244 }
245
246 /* Clear bits */
247 PSB_WSGX32(stat_1, PSB_CR_EVENT_HOST_CLEAR);
248 PSB_WSGX32(stat_2, PSB_CR_EVENT_HOST_CLEAR2);
249 PSB_RSGX32(PSB_CR_EVENT_HOST_CLEAR2);
250}
251
252irqreturn_t psb_irq_handler(int irq, void *arg)
253{
254 struct drm_device *dev = arg;
255 struct drm_psb_private *dev_priv = dev->dev_private;
256 uint32_t vdc_stat, dsp_int = 0, sgx_int = 0, hotplug_int = 0;
257 u32 sgx_stat_1, sgx_stat_2;
258 int handled = 0;
259
260 spin_lock(&dev_priv->irqmask_lock);
261
262 vdc_stat = PSB_RVDC32(PSB_INT_IDENTITY_R);
263
264 if (vdc_stat & (_PSB_PIPE_EVENT_FLAG|_PSB_IRQ_ASLE))
265 dsp_int = 1;
266
267 /* FIXME: Handle Medfield
268 if (vdc_stat & _MDFLD_DISP_ALL_IRQ_FLAG)
269 dsp_int = 1;
270 */
271
272 if (vdc_stat & _PSB_IRQ_SGX_FLAG)
273 sgx_int = 1;
274 if (vdc_stat & _PSB_IRQ_DISP_HOTSYNC)
275 hotplug_int = 1;
276
277 vdc_stat &= dev_priv->vdc_irq_mask;
278 spin_unlock(&dev_priv->irqmask_lock);
279
280 if (dsp_int && gma_power_is_on(dev)) {
281 psb_vdc_interrupt(dev, vdc_stat);
282 handled = 1;
283 }
284
285 if (sgx_int) {
286 sgx_stat_1 = PSB_RSGX32(PSB_CR_EVENT_STATUS);
287 sgx_stat_2 = PSB_RSGX32(PSB_CR_EVENT_STATUS2);
288 psb_sgx_interrupt(dev, sgx_stat_1, sgx_stat_2);
289 handled = 1;
290 }
291
292 /* Note: this bit has other meanings on some devices, so we will
293 need to address that later if it ever matters */
294 if (hotplug_int && dev_priv->ops->hotplug) {
295 handled = dev_priv->ops->hotplug(dev);
296 REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT));
297 }
298
299 PSB_WVDC32(vdc_stat, PSB_INT_IDENTITY_R);
300 (void) PSB_RVDC32(PSB_INT_IDENTITY_R);
301 rmb();
302
303 if (!handled)
304 return IRQ_NONE;
305
306 return IRQ_HANDLED;
307}
308
309void psb_irq_preinstall(struct drm_device *dev)
310{
311 struct drm_psb_private *dev_priv =
312 (struct drm_psb_private *) dev->dev_private;
313 unsigned long irqflags;
314
315 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
316
317 if (gma_power_is_on(dev)) {
318 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
319 PSB_WVDC32(0x00000000, PSB_INT_MASK_R);
320 PSB_WVDC32(0x00000000, PSB_INT_ENABLE_R);
321 PSB_WSGX32(0x00000000, PSB_CR_EVENT_HOST_ENABLE);
322 PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE);
323 }
324 if (dev->vblank[0].enabled)
325 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEA_FLAG;
326 if (dev->vblank[1].enabled)
327 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEB_FLAG;
328
329 /* FIXME: Handle Medfield irq mask
330 if (dev->vblank[1].enabled)
331 dev_priv->vdc_irq_mask |= _MDFLD_PIPEB_EVENT_FLAG;
332 if (dev->vblank[2].enabled)
333 dev_priv->vdc_irq_mask |= _MDFLD_PIPEC_EVENT_FLAG;
334 */
335
336 /* Revisit this area - want per device masks ? */
337 if (dev_priv->ops->hotplug)
338 dev_priv->vdc_irq_mask |= _PSB_IRQ_DISP_HOTSYNC;
339 dev_priv->vdc_irq_mask |= _PSB_IRQ_ASLE | _PSB_IRQ_SGX_FLAG;
340
341 /* This register is safe even if display island is off */
342 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
343 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
344}
345
346int psb_irq_postinstall(struct drm_device *dev)
347{
348 struct drm_psb_private *dev_priv = dev->dev_private;
349 unsigned long irqflags;
350
351 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
352
353 /* Enable 2D and MMU fault interrupts */
354 PSB_WSGX32(_PSB_CE2_BIF_REQUESTER_FAULT, PSB_CR_EVENT_HOST_ENABLE2);
355 PSB_WSGX32(_PSB_CE_TWOD_COMPLETE, PSB_CR_EVENT_HOST_ENABLE);
356 PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE); /* Post */
357
358 /* This register is safe even if display island is off */
359 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
360 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
361
362 if (dev->vblank[0].enabled)
363 psb_enable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE);
364 else
365 psb_disable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE);
366
367 if (dev->vblank[1].enabled)
368 psb_enable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE);
369 else
370 psb_disable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE);
371
372 if (dev->vblank[2].enabled)
373 psb_enable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE);
374 else
375 psb_disable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE);
376
377 if (dev_priv->ops->hotplug_enable)
378 dev_priv->ops->hotplug_enable(dev, true);
379
380 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
381 return 0;
382}
383
384void psb_irq_uninstall(struct drm_device *dev)
385{
386 struct drm_psb_private *dev_priv = dev->dev_private;
387 unsigned long irqflags;
388
389 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
390
391 if (dev_priv->ops->hotplug_enable)
392 dev_priv->ops->hotplug_enable(dev, false);
393
394 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
395
396 if (dev->vblank[0].enabled)
397 psb_disable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE);
398
399 if (dev->vblank[1].enabled)
400 psb_disable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE);
401
402 if (dev->vblank[2].enabled)
403 psb_disable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE);
404
405 dev_priv->vdc_irq_mask &= _PSB_IRQ_SGX_FLAG |
406 _PSB_IRQ_MSVDX_FLAG |
407 _LNC_IRQ_TOPAZ_FLAG;
408
409 /* These two registers are safe even if display island is off */
410 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
411 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
412
413 wmb();
414
415 /* This register is safe even if display island is off */
416 PSB_WVDC32(PSB_RVDC32(PSB_INT_IDENTITY_R), PSB_INT_IDENTITY_R);
417 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
418}
419
420void psb_irq_turn_on_dpst(struct drm_device *dev)
421{
422 struct drm_psb_private *dev_priv =
423 (struct drm_psb_private *) dev->dev_private;
424 u32 hist_reg;
425 u32 pwm_reg;
426
427 if (gma_power_begin(dev, false)) {
428 PSB_WVDC32(1 << 31, HISTOGRAM_LOGIC_CONTROL);
429 hist_reg = PSB_RVDC32(HISTOGRAM_LOGIC_CONTROL);
430 PSB_WVDC32(1 << 31, HISTOGRAM_INT_CONTROL);
431 hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
432
433 PSB_WVDC32(0x80010100, PWM_CONTROL_LOGIC);
434 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
435 PSB_WVDC32(pwm_reg | PWM_PHASEIN_ENABLE
436 | PWM_PHASEIN_INT_ENABLE,
437 PWM_CONTROL_LOGIC);
438 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
439
440 psb_enable_pipestat(dev_priv, 0, PIPE_DPST_EVENT_ENABLE);
441
442 hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
443 PSB_WVDC32(hist_reg | HISTOGRAM_INT_CTRL_CLEAR,
444 HISTOGRAM_INT_CONTROL);
445 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
446 PSB_WVDC32(pwm_reg | 0x80010100 | PWM_PHASEIN_ENABLE,
447 PWM_CONTROL_LOGIC);
448
449 gma_power_end(dev);
450 }
451}
452
453int psb_irq_enable_dpst(struct drm_device *dev)
454{
455 struct drm_psb_private *dev_priv =
456 (struct drm_psb_private *) dev->dev_private;
457 unsigned long irqflags;
458
459 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
460
461 /* enable DPST */
462 mid_enable_pipe_event(dev_priv, 0);
463 psb_irq_turn_on_dpst(dev);
464
465 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
466 return 0;
467}
468
469void psb_irq_turn_off_dpst(struct drm_device *dev)
470{
471 struct drm_psb_private *dev_priv =
472 (struct drm_psb_private *) dev->dev_private;
473 u32 pwm_reg;
474
475 if (gma_power_begin(dev, false)) {
476 PSB_WVDC32(0x00000000, HISTOGRAM_INT_CONTROL);
477 PSB_RVDC32(HISTOGRAM_INT_CONTROL);
478
479 psb_disable_pipestat(dev_priv, 0, PIPE_DPST_EVENT_ENABLE);
480
481 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
482 PSB_WVDC32(pwm_reg & ~PWM_PHASEIN_INT_ENABLE,
483 PWM_CONTROL_LOGIC);
484 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
485
486 gma_power_end(dev);
487 }
488}
489
490int psb_irq_disable_dpst(struct drm_device *dev)
491{
492 struct drm_psb_private *dev_priv =
493 (struct drm_psb_private *) dev->dev_private;
494 unsigned long irqflags;
495
496 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
497
498 mid_disable_pipe_event(dev_priv, 0);
499 psb_irq_turn_off_dpst(dev);
500
501 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
502
503 return 0;
504}
505
506/*
507 * It is used to enable VBLANK interrupt
508 */
509int psb_enable_vblank(struct drm_crtc *crtc)
510{
511 struct drm_device *dev = crtc->dev;
512 unsigned int pipe = crtc->index;
513 struct drm_psb_private *dev_priv = dev->dev_private;
514 unsigned long irqflags;
515 uint32_t reg_val = 0;
516 uint32_t pipeconf_reg = mid_pipeconf(pipe);
517
518 /* Medfield is different - we should perhaps extract out vblank
519 and blacklight etc ops */
520 if (IS_MFLD(dev))
521 return mdfld_enable_te(dev, pipe);
522
523 if (gma_power_begin(dev, false)) {
524 reg_val = REG_READ(pipeconf_reg);
525 gma_power_end(dev);
526 }
527
528 if (!(reg_val & PIPEACONF_ENABLE))
529 return -EINVAL;
530
531 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
532
533 if (pipe == 0)
534 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEA_FLAG;
535 else if (pipe == 1)
536 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEB_FLAG;
537
538 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
539 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
540 psb_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE);
541
542 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
543
544 return 0;
545}
546
547/*
548 * It is used to disable VBLANK interrupt
549 */
550void psb_disable_vblank(struct drm_crtc *crtc)
551{
552 struct drm_device *dev = crtc->dev;
553 unsigned int pipe = crtc->index;
554 struct drm_psb_private *dev_priv = dev->dev_private;
555 unsigned long irqflags;
556
557 if (IS_MFLD(dev))
558 mdfld_disable_te(dev, pipe);
559 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
560
561 if (pipe == 0)
562 dev_priv->vdc_irq_mask &= ~_PSB_VSYNC_PIPEA_FLAG;
563 else if (pipe == 1)
564 dev_priv->vdc_irq_mask &= ~_PSB_VSYNC_PIPEB_FLAG;
565
566 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
567 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
568 psb_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE);
569
570 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
571}
572
573/*
574 * It is used to enable TE interrupt
575 */
576int mdfld_enable_te(struct drm_device *dev, int pipe)
577{
578 struct drm_psb_private *dev_priv =
579 (struct drm_psb_private *) dev->dev_private;
580 unsigned long irqflags;
581 uint32_t reg_val = 0;
582 uint32_t pipeconf_reg = mid_pipeconf(pipe);
583
584 if (gma_power_begin(dev, false)) {
585 reg_val = REG_READ(pipeconf_reg);
586 gma_power_end(dev);
587 }
588
589 if (!(reg_val & PIPEACONF_ENABLE))
590 return -EINVAL;
591
592 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
593
594 mid_enable_pipe_event(dev_priv, pipe);
595 psb_enable_pipestat(dev_priv, pipe, PIPE_TE_ENABLE);
596
597 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
598
599 return 0;
600}
601
602/*
603 * It is used to disable TE interrupt
604 */
605void mdfld_disable_te(struct drm_device *dev, int pipe)
606{
607 struct drm_psb_private *dev_priv =
608 (struct drm_psb_private *) dev->dev_private;
609 unsigned long irqflags;
610
611 if (!dev_priv->dsr_enable)
612 return;
613
614 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
615
616 mid_disable_pipe_event(dev_priv, pipe);
617 psb_disable_pipestat(dev_priv, pipe, PIPE_TE_ENABLE);
618
619 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
620}
621
622/* Called from drm generic code, passed a 'crtc', which
623 * we use as a pipe index
624 */
625u32 psb_get_vblank_counter(struct drm_crtc *crtc)
626{
627 struct drm_device *dev = crtc->dev;
628 unsigned int pipe = crtc->index;
629 uint32_t high_frame = PIPEAFRAMEHIGH;
630 uint32_t low_frame = PIPEAFRAMEPIXEL;
631 uint32_t pipeconf_reg = PIPEACONF;
632 uint32_t reg_val = 0;
633 uint32_t high1 = 0, high2 = 0, low = 0, count = 0;
634
635 switch (pipe) {
636 case 0:
637 break;
638 case 1:
639 high_frame = PIPEBFRAMEHIGH;
640 low_frame = PIPEBFRAMEPIXEL;
641 pipeconf_reg = PIPEBCONF;
642 break;
643 case 2:
644 high_frame = PIPECFRAMEHIGH;
645 low_frame = PIPECFRAMEPIXEL;
646 pipeconf_reg = PIPECCONF;
647 break;
648 default:
649 dev_err(dev->dev, "%s, invalid pipe.\n", __func__);
650 return 0;
651 }
652
653 if (!gma_power_begin(dev, false))
654 return 0;
655
656 reg_val = REG_READ(pipeconf_reg);
657
658 if (!(reg_val & PIPEACONF_ENABLE)) {
659 dev_err(dev->dev, "trying to get vblank count for disabled pipe %u\n",
660 pipe);
661 goto psb_get_vblank_counter_exit;
662 }
663
664 /*
665 * High & low register fields aren't synchronized, so make sure
666 * we get a low value that's stable across two reads of the high
667 * register.
668 */
669 do {
670 high1 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
671 PIPE_FRAME_HIGH_SHIFT);
672 low = ((REG_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
673 PIPE_FRAME_LOW_SHIFT);
674 high2 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
675 PIPE_FRAME_HIGH_SHIFT);
676 } while (high1 != high2);
677
678 count = (high1 << 8) | low;
679
680psb_get_vblank_counter_exit:
681
682 gma_power_end(dev);
683
684 return count;
685}
686