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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * TI composite clock support
4 *
5 * Copyright (C) 2013 Texas Instruments, Inc.
6 *
7 * Tero Kristo <t-kristo@ti.com>
8 */
9
10#include <linux/clk-provider.h>
11#include <linux/slab.h>
12#include <linux/io.h>
13#include <linux/of.h>
14#include <linux/of_address.h>
15#include <linux/clk/ti.h>
16#include <linux/list.h>
17
18#include "clock.h"
19
20#undef pr_fmt
21#define pr_fmt(fmt) "%s: " fmt, __func__
22
23static unsigned long ti_composite_recalc_rate(struct clk_hw *hw,
24 unsigned long parent_rate)
25{
26 return ti_clk_divider_ops.recalc_rate(hw, parent_rate);
27}
28
29static long ti_composite_round_rate(struct clk_hw *hw, unsigned long rate,
30 unsigned long *prate)
31{
32 return -EINVAL;
33}
34
35static int ti_composite_set_rate(struct clk_hw *hw, unsigned long rate,
36 unsigned long parent_rate)
37{
38 return -EINVAL;
39}
40
41static const struct clk_ops ti_composite_divider_ops = {
42 .recalc_rate = &ti_composite_recalc_rate,
43 .round_rate = &ti_composite_round_rate,
44 .set_rate = &ti_composite_set_rate,
45};
46
47static const struct clk_ops ti_composite_gate_ops = {
48 .enable = &omap2_dflt_clk_enable,
49 .disable = &omap2_dflt_clk_disable,
50 .is_enabled = &omap2_dflt_clk_is_enabled,
51};
52
53struct component_clk {
54 int num_parents;
55 const char **parent_names;
56 struct device_node *node;
57 int type;
58 struct clk_hw *hw;
59 struct list_head link;
60};
61
62static const char * const component_clk_types[] __initconst = {
63 "gate", "divider", "mux"
64};
65
66static LIST_HEAD(component_clks);
67
68static struct device_node *_get_component_node(struct device_node *node, int i)
69{
70 int rc;
71 struct of_phandle_args clkspec;
72
73 rc = of_parse_phandle_with_args(node, "clocks", "#clock-cells", i,
74 &clkspec);
75 if (rc)
76 return NULL;
77
78 return clkspec.np;
79}
80
81static struct component_clk *_lookup_component(struct device_node *node)
82{
83 struct component_clk *comp;
84
85 list_for_each_entry(comp, &component_clks, link) {
86 if (comp->node == node)
87 return comp;
88 }
89 return NULL;
90}
91
92struct clk_hw_omap_comp {
93 struct clk_hw hw;
94 struct device_node *comp_nodes[CLK_COMPONENT_TYPE_MAX];
95 struct component_clk *comp_clks[CLK_COMPONENT_TYPE_MAX];
96};
97
98static inline struct clk_hw *_get_hw(struct clk_hw_omap_comp *clk, int idx)
99{
100 if (!clk)
101 return NULL;
102
103 if (!clk->comp_clks[idx])
104 return NULL;
105
106 return clk->comp_clks[idx]->hw;
107}
108
109#define to_clk_hw_comp(_hw) container_of(_hw, struct clk_hw_omap_comp, hw)
110
111static void __init _register_composite(void *user,
112 struct device_node *node)
113{
114 struct clk_hw *hw = user;
115 struct clk *clk;
116 struct clk_hw_omap_comp *cclk = to_clk_hw_comp(hw);
117 struct component_clk *comp;
118 int num_parents = 0;
119 const char **parent_names = NULL;
120 const char *name;
121 int i;
122 int ret;
123
124 /* Check for presence of each component clock */
125 for (i = 0; i < CLK_COMPONENT_TYPE_MAX; i++) {
126 if (!cclk->comp_nodes[i])
127 continue;
128
129 comp = _lookup_component(cclk->comp_nodes[i]);
130 if (!comp) {
131 pr_debug("component %s not ready for %pOFn, retry\n",
132 cclk->comp_nodes[i]->name, node);
133 if (!ti_clk_retry_init(node, hw,
134 _register_composite))
135 return;
136
137 goto cleanup;
138 }
139 if (cclk->comp_clks[comp->type] != NULL) {
140 pr_err("duplicate component types for %pOFn (%s)!\n",
141 node, component_clk_types[comp->type]);
142 goto cleanup;
143 }
144
145 cclk->comp_clks[comp->type] = comp;
146
147 /* Mark this node as found */
148 cclk->comp_nodes[i] = NULL;
149 }
150
151 /* All components exists, proceed with registration */
152 for (i = CLK_COMPONENT_TYPE_MAX - 1; i >= 0; i--) {
153 comp = cclk->comp_clks[i];
154 if (!comp)
155 continue;
156 if (comp->num_parents) {
157 num_parents = comp->num_parents;
158 parent_names = comp->parent_names;
159 break;
160 }
161 }
162
163 if (!num_parents) {
164 pr_err("%s: no parents found for %pOFn!\n", __func__, node);
165 goto cleanup;
166 }
167
168 name = ti_dt_clk_name(node);
169 clk = clk_register_composite(NULL, name,
170 parent_names, num_parents,
171 _get_hw(cclk, CLK_COMPONENT_TYPE_MUX),
172 &ti_clk_mux_ops,
173 _get_hw(cclk, CLK_COMPONENT_TYPE_DIVIDER),
174 &ti_composite_divider_ops,
175 _get_hw(cclk, CLK_COMPONENT_TYPE_GATE),
176 &ti_composite_gate_ops, 0);
177
178 if (!IS_ERR(clk)) {
179 ret = ti_clk_add_alias(clk, name);
180 if (ret) {
181 clk_unregister(clk);
182 goto cleanup;
183 }
184 of_clk_add_provider(node, of_clk_src_simple_get, clk);
185 }
186
187cleanup:
188 /* Free component clock list entries */
189 for (i = 0; i < CLK_COMPONENT_TYPE_MAX; i++) {
190 if (!cclk->comp_clks[i])
191 continue;
192 list_del(&cclk->comp_clks[i]->link);
193 kfree(cclk->comp_clks[i]->parent_names);
194 kfree(cclk->comp_clks[i]);
195 }
196
197 kfree(cclk);
198}
199
200static void __init of_ti_composite_clk_setup(struct device_node *node)
201{
202 unsigned int num_clks;
203 int i;
204 struct clk_hw_omap_comp *cclk;
205
206 /* Number of component clocks to be put inside this clock */
207 num_clks = of_clk_get_parent_count(node);
208
209 if (!num_clks) {
210 pr_err("composite clk %pOFn must have component(s)\n", node);
211 return;
212 }
213
214 cclk = kzalloc(sizeof(*cclk), GFP_KERNEL);
215 if (!cclk)
216 return;
217
218 /* Get device node pointers for each component clock */
219 for (i = 0; i < num_clks; i++)
220 cclk->comp_nodes[i] = _get_component_node(node, i);
221
222 _register_composite(&cclk->hw, node);
223}
224CLK_OF_DECLARE(ti_composite_clock, "ti,composite-clock",
225 of_ti_composite_clk_setup);
226
227/**
228 * ti_clk_add_component - add a component clock to the pool
229 * @node: device node of the component clock
230 * @hw: hardware clock definition for the component clock
231 * @type: type of the component clock
232 *
233 * Adds a component clock to the list of available components, so that
234 * it can be registered by a composite clock.
235 */
236int __init ti_clk_add_component(struct device_node *node, struct clk_hw *hw,
237 int type)
238{
239 unsigned int num_parents;
240 const char **parent_names;
241 struct component_clk *clk;
242
243 num_parents = of_clk_get_parent_count(node);
244
245 if (!num_parents) {
246 pr_err("component-clock %pOFn must have parent(s)\n", node);
247 return -EINVAL;
248 }
249
250 parent_names = kcalloc(num_parents, sizeof(char *), GFP_KERNEL);
251 if (!parent_names)
252 return -ENOMEM;
253
254 of_clk_parent_fill(node, parent_names, num_parents);
255
256 clk = kzalloc(sizeof(*clk), GFP_KERNEL);
257 if (!clk) {
258 kfree(parent_names);
259 return -ENOMEM;
260 }
261
262 clk->num_parents = num_parents;
263 clk->parent_names = parent_names;
264 clk->hw = hw;
265 clk->node = node;
266 clk->type = type;
267 list_add(&clk->link, &component_clks);
268
269 return 0;
270}
1/*
2 * TI composite clock support
3 *
4 * Copyright (C) 2013 Texas Instruments, Inc.
5 *
6 * Tero Kristo <t-kristo@ti.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#include <linux/clk-provider.h>
19#include <linux/slab.h>
20#include <linux/io.h>
21#include <linux/of.h>
22#include <linux/of_address.h>
23#include <linux/clk/ti.h>
24#include <linux/list.h>
25
26#include "clock.h"
27
28#undef pr_fmt
29#define pr_fmt(fmt) "%s: " fmt, __func__
30
31static unsigned long ti_composite_recalc_rate(struct clk_hw *hw,
32 unsigned long parent_rate)
33{
34 return ti_clk_divider_ops.recalc_rate(hw, parent_rate);
35}
36
37static long ti_composite_round_rate(struct clk_hw *hw, unsigned long rate,
38 unsigned long *prate)
39{
40 return -EINVAL;
41}
42
43static int ti_composite_set_rate(struct clk_hw *hw, unsigned long rate,
44 unsigned long parent_rate)
45{
46 return -EINVAL;
47}
48
49static const struct clk_ops ti_composite_divider_ops = {
50 .recalc_rate = &ti_composite_recalc_rate,
51 .round_rate = &ti_composite_round_rate,
52 .set_rate = &ti_composite_set_rate,
53};
54
55static const struct clk_ops ti_composite_gate_ops = {
56 .enable = &omap2_dflt_clk_enable,
57 .disable = &omap2_dflt_clk_disable,
58 .is_enabled = &omap2_dflt_clk_is_enabled,
59};
60
61struct component_clk {
62 int num_parents;
63 const char **parent_names;
64 struct device_node *node;
65 int type;
66 struct clk_hw *hw;
67 struct list_head link;
68};
69
70static const char * const component_clk_types[] __initconst = {
71 "gate", "divider", "mux"
72};
73
74static LIST_HEAD(component_clks);
75
76static struct device_node *_get_component_node(struct device_node *node, int i)
77{
78 int rc;
79 struct of_phandle_args clkspec;
80
81 rc = of_parse_phandle_with_args(node, "clocks", "#clock-cells", i,
82 &clkspec);
83 if (rc)
84 return NULL;
85
86 return clkspec.np;
87}
88
89static struct component_clk *_lookup_component(struct device_node *node)
90{
91 struct component_clk *comp;
92
93 list_for_each_entry(comp, &component_clks, link) {
94 if (comp->node == node)
95 return comp;
96 }
97 return NULL;
98}
99
100struct clk_hw_omap_comp {
101 struct clk_hw hw;
102 struct device_node *comp_nodes[CLK_COMPONENT_TYPE_MAX];
103 struct component_clk *comp_clks[CLK_COMPONENT_TYPE_MAX];
104};
105
106static inline struct clk_hw *_get_hw(struct clk_hw_omap_comp *clk, int idx)
107{
108 if (!clk)
109 return NULL;
110
111 if (!clk->comp_clks[idx])
112 return NULL;
113
114 return clk->comp_clks[idx]->hw;
115}
116
117#define to_clk_hw_comp(_hw) container_of(_hw, struct clk_hw_omap_comp, hw)
118
119static void __init _register_composite(void *user,
120 struct device_node *node)
121{
122 struct clk_hw *hw = user;
123 struct clk *clk;
124 struct clk_hw_omap_comp *cclk = to_clk_hw_comp(hw);
125 struct component_clk *comp;
126 int num_parents = 0;
127 const char **parent_names = NULL;
128 int i;
129 int ret;
130
131 /* Check for presence of each component clock */
132 for (i = 0; i < CLK_COMPONENT_TYPE_MAX; i++) {
133 if (!cclk->comp_nodes[i])
134 continue;
135
136 comp = _lookup_component(cclk->comp_nodes[i]);
137 if (!comp) {
138 pr_debug("component %s not ready for %pOFn, retry\n",
139 cclk->comp_nodes[i]->name, node);
140 if (!ti_clk_retry_init(node, hw,
141 _register_composite))
142 return;
143
144 goto cleanup;
145 }
146 if (cclk->comp_clks[comp->type] != NULL) {
147 pr_err("duplicate component types for %pOFn (%s)!\n",
148 node, component_clk_types[comp->type]);
149 goto cleanup;
150 }
151
152 cclk->comp_clks[comp->type] = comp;
153
154 /* Mark this node as found */
155 cclk->comp_nodes[i] = NULL;
156 }
157
158 /* All components exists, proceed with registration */
159 for (i = CLK_COMPONENT_TYPE_MAX - 1; i >= 0; i--) {
160 comp = cclk->comp_clks[i];
161 if (!comp)
162 continue;
163 if (comp->num_parents) {
164 num_parents = comp->num_parents;
165 parent_names = comp->parent_names;
166 break;
167 }
168 }
169
170 if (!num_parents) {
171 pr_err("%s: no parents found for %pOFn!\n", __func__, node);
172 goto cleanup;
173 }
174
175 clk = clk_register_composite(NULL, node->name,
176 parent_names, num_parents,
177 _get_hw(cclk, CLK_COMPONENT_TYPE_MUX),
178 &ti_clk_mux_ops,
179 _get_hw(cclk, CLK_COMPONENT_TYPE_DIVIDER),
180 &ti_composite_divider_ops,
181 _get_hw(cclk, CLK_COMPONENT_TYPE_GATE),
182 &ti_composite_gate_ops, 0);
183
184 if (!IS_ERR(clk)) {
185 ret = ti_clk_add_alias(NULL, clk, node->name);
186 if (ret) {
187 clk_unregister(clk);
188 goto cleanup;
189 }
190 of_clk_add_provider(node, of_clk_src_simple_get, clk);
191 }
192
193cleanup:
194 /* Free component clock list entries */
195 for (i = 0; i < CLK_COMPONENT_TYPE_MAX; i++) {
196 if (!cclk->comp_clks[i])
197 continue;
198 list_del(&cclk->comp_clks[i]->link);
199 kfree(cclk->comp_clks[i]->parent_names);
200 kfree(cclk->comp_clks[i]);
201 }
202
203 kfree(cclk);
204}
205
206static void __init of_ti_composite_clk_setup(struct device_node *node)
207{
208 unsigned int num_clks;
209 int i;
210 struct clk_hw_omap_comp *cclk;
211
212 /* Number of component clocks to be put inside this clock */
213 num_clks = of_clk_get_parent_count(node);
214
215 if (!num_clks) {
216 pr_err("composite clk %pOFn must have component(s)\n", node);
217 return;
218 }
219
220 cclk = kzalloc(sizeof(*cclk), GFP_KERNEL);
221 if (!cclk)
222 return;
223
224 /* Get device node pointers for each component clock */
225 for (i = 0; i < num_clks; i++)
226 cclk->comp_nodes[i] = _get_component_node(node, i);
227
228 _register_composite(&cclk->hw, node);
229}
230CLK_OF_DECLARE(ti_composite_clock, "ti,composite-clock",
231 of_ti_composite_clk_setup);
232
233/**
234 * ti_clk_add_component - add a component clock to the pool
235 * @node: device node of the component clock
236 * @hw: hardware clock definition for the component clock
237 * @type: type of the component clock
238 *
239 * Adds a component clock to the list of available components, so that
240 * it can be registered by a composite clock.
241 */
242int __init ti_clk_add_component(struct device_node *node, struct clk_hw *hw,
243 int type)
244{
245 unsigned int num_parents;
246 const char **parent_names;
247 struct component_clk *clk;
248
249 num_parents = of_clk_get_parent_count(node);
250
251 if (!num_parents) {
252 pr_err("component-clock %pOFn must have parent(s)\n", node);
253 return -EINVAL;
254 }
255
256 parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL);
257 if (!parent_names)
258 return -ENOMEM;
259
260 of_clk_parent_fill(node, parent_names, num_parents);
261
262 clk = kzalloc(sizeof(*clk), GFP_KERNEL);
263 if (!clk) {
264 kfree(parent_names);
265 return -ENOMEM;
266 }
267
268 clk->num_parents = num_parents;
269 clk->parent_names = parent_names;
270 clk->hw = hw;
271 clk->node = node;
272 clk->type = type;
273 list_add(&clk->link, &component_clks);
274
275 return 0;
276}