1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
  4 */
  5#include <linux/init.h>
  6#include <linux/threads.h>
  7
  8#include <asm/addrspace.h>
  9#include <asm/asm.h>
 10#include <asm/asmmacro.h>
 11#include <asm/bug.h>
 12#include <asm/regdef.h>
 13#include <asm/loongarch.h>
 14#include <asm/stackframe.h>
 15
 16#ifdef CONFIG_EFI_STUB
 17
 18#include "efi-header.S"
 19
 20	__HEAD
 21
 22_head:
 23	.word	MZ_MAGIC		/* "MZ", MS-DOS header */
 24	.org	0x8
 25	.dword	_kernel_entry		/* Kernel entry point (physical address) */
 26	.dword	_kernel_asize		/* Kernel image effective size */
 27	.quad	PHYS_LINK_KADDR		/* Kernel image load offset from start of RAM */
 28	.org	0x38			/* 0x20 ~ 0x37 reserved */
 29	.long	LINUX_PE_MAGIC
 30	.long	pe_header - _head	/* Offset to the PE header */
 31
 32pe_header:
 33	__EFI_PE_HEADER
 34
 35SYM_DATA(kernel_asize, .long _kernel_asize);
 36SYM_DATA(kernel_fsize, .long _kernel_fsize);
 37
 38#endif
 39
 40	__REF
 41
 42	.align 12
 43
 44SYM_CODE_START(kernel_entry)			# kernel entry point
 45
 46	/* Config direct window and set PG */
 47	SETUP_DMWINS	t0
 48	JUMP_VIRT_ADDR	t0, t1
 49
 50	/* Enable PG */
 51	li.w		t0, 0xb0		# PLV=0, IE=0, PG=1
 52	csrwr		t0, LOONGARCH_CSR_CRMD
 53	li.w		t0, 0x04		# PLV=0, PIE=1, PWE=0
 54	csrwr		t0, LOONGARCH_CSR_PRMD
 55	li.w		t0, 0x00		# FPE=0, SXE=0, ASXE=0, BTE=0
 56	csrwr		t0, LOONGARCH_CSR_EUEN
 57
 58	la.pcrel	t0, __bss_start		# clear .bss
 59	st.d		zero, t0, 0
 60	la.pcrel	t1, __bss_stop - LONGSIZE
 611:
 62	addi.d		t0, t0, LONGSIZE
 63	st.d		zero, t0, 0
 64	bne		t0, t1, 1b
 65
 66	la.pcrel	t0, fw_arg0
 67	st.d		a0, t0, 0		# firmware arguments
 68	la.pcrel	t0, fw_arg1
 69	st.d		a1, t0, 0
 70	la.pcrel	t0, fw_arg2
 71	st.d		a2, t0, 0
 72
 73#ifdef CONFIG_PAGE_SIZE_4KB
 74	li.d		t0, 0
 75	li.d		t1, CSR_STFILL
 76	csrxchg		t0, t1, LOONGARCH_CSR_IMPCTL1
 77#endif
 78	/* KSave3 used for percpu base, initialized as 0 */
 79	csrwr		zero, PERCPU_BASE_KS
 80	/* GPR21 used for percpu base (runtime), initialized as 0 */
 81	move		u0, zero
 82
 83	la.pcrel	tp, init_thread_union
 84	/* Set the SP after an empty pt_regs.  */
 85	PTR_LI		sp, (_THREAD_SIZE - PT_SIZE)
 86	PTR_ADD		sp, sp, tp
 87	set_saved_sp	sp, t0, t1
 88
 89#ifdef CONFIG_RELOCATABLE
 90
 91	bl		relocate_kernel
 92
 93#ifdef CONFIG_RANDOMIZE_BASE
 94	/* Repoint the sp into the new kernel */
 95	PTR_LI		sp, (_THREAD_SIZE - PT_SIZE)
 96	PTR_ADD		sp, sp, tp
 97	set_saved_sp	sp, t0, t1
 98
 99	/* Jump to the new kernel: new_pc = current_pc + random_offset */
100	pcaddi		t0, 0
101	add.d		t0, t0, a0
102	jirl		zero, t0, 0xc
103#endif /* CONFIG_RANDOMIZE_BASE */
104
105#endif /* CONFIG_RELOCATABLE */
106
107#ifdef CONFIG_KASAN
108	bl		kasan_early_init
109#endif
110
111	bl		start_kernel
112	ASM_BUG()
113
114SYM_CODE_END(kernel_entry)
115
116#ifdef CONFIG_SMP
117
118/*
119 * SMP slave cpus entry point.	Board specific code for bootstrap calls this
120 * function after setting up the stack and tp registers.
121 */
122SYM_CODE_START(smpboot_entry)
123
124	SETUP_DMWINS	t0
125	JUMP_VIRT_ADDR	t0, t1
126
127#ifdef CONFIG_PAGE_SIZE_4KB
128	li.d		t0, 0
129	li.d		t1, CSR_STFILL
130	csrxchg		t0, t1, LOONGARCH_CSR_IMPCTL1
131#endif
132	/* Enable PG */
133	li.w		t0, 0xb0		# PLV=0, IE=0, PG=1
134	csrwr		t0, LOONGARCH_CSR_CRMD
135	li.w		t0, 0x04		# PLV=0, PIE=1, PWE=0
136	csrwr		t0, LOONGARCH_CSR_PRMD
137	li.w		t0, 0x00		# FPE=0, SXE=0, ASXE=0, BTE=0
138	csrwr		t0, LOONGARCH_CSR_EUEN
139
140	la.pcrel	t0, cpuboot_data
141	ld.d		sp, t0, CPU_BOOT_STACK
142	ld.d		tp, t0, CPU_BOOT_TINFO
143
144	bl		start_secondary
145	ASM_BUG()
146
147SYM_CODE_END(smpboot_entry)
148
149#endif /* CONFIG_SMP */
150
151SYM_ENTRY(kernel_entry_end, SYM_L_GLOBAL, SYM_A_NONE)