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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * linux/arch/arm/mach-omap1/mux.c
4 *
5 * OMAP1 pin multiplexing configurations
6 *
7 * Copyright (C) 2003 - 2008 Nokia Corporation
8 *
9 * Written by Tony Lindgren
10 */
11#include <linux/module.h>
12#include <linux/init.h>
13#include <linux/io.h>
14#include <linux/spinlock.h>
15#include <linux/soc/ti/omap1-io.h>
16
17#include "hardware.h"
18#include "mux.h"
19
20#ifdef CONFIG_OMAP_MUX
21
22static struct omap_mux_cfg arch_mux_cfg;
23
24#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
25static struct pin_config omap1xxx_pins[] = {
26/*
27 * description mux mode mux pull pull pull pu_pd pu dbg
28 * reg offset mode reg bit ena reg
29 */
30MUX_CFG("UART1_TX", 9, 21, 1, 2, 3, 0, NA, 0, 0)
31MUX_CFG("UART1_RTS", 9, 12, 1, 2, 0, 0, NA, 0, 0)
32
33/* UART2 (COM_UART_GATING), conflicts with USB2 */
34MUX_CFG("UART2_TX", C, 27, 1, 3, 3, 0, NA, 0, 0)
35MUX_CFG("UART2_RX", C, 18, 0, 3, 1, 1, NA, 0, 0)
36MUX_CFG("UART2_CTS", C, 21, 0, 3, 1, 1, NA, 0, 0)
37MUX_CFG("UART2_RTS", C, 24, 1, 3, 2, 0, NA, 0, 0)
38
39/* UART3 (GIGA_UART_GATING) */
40MUX_CFG("UART3_TX", 6, 0, 1, 0, 30, 0, NA, 0, 0)
41MUX_CFG("UART3_RX", 6, 3, 0, 0, 31, 1, NA, 0, 0)
42MUX_CFG("UART3_CTS", 5, 12, 2, 0, 24, 0, NA, 0, 0)
43MUX_CFG("UART3_RTS", 5, 15, 2, 0, 25, 0, NA, 0, 0)
44MUX_CFG("UART3_CLKREQ", 9, 27, 0, 2, 5, 0, NA, 0, 0)
45MUX_CFG("UART3_BCLK", A, 0, 0, 2, 6, 0, NA, 0, 0)
46MUX_CFG("Y15_1610_UART3_RTS", A, 0, 1, 2, 6, 0, NA, 0, 0)
47
48/* PWT & PWL, conflicts with UART3 */
49MUX_CFG("PWT", 6, 0, 2, 0, 30, 0, NA, 0, 0)
50MUX_CFG("PWL", 6, 3, 1, 0, 31, 1, NA, 0, 0)
51
52/* USB internal master generic */
53MUX_CFG("R18_USB_VBUS", 7, 9, 2, 1, 11, 0, NA, 0, 1)
54MUX_CFG("R18_1510_USB_GPIO0", 7, 9, 0, 1, 11, 1, NA, 0, 1)
55/* works around erratum: W4_USB_PUEN and W4_USB_PUDIS are switched! */
56MUX_CFG("W4_USB_PUEN", D, 3, 3, 3, 5, 1, NA, 0, 1)
57MUX_CFG("W4_USB_CLKO", D, 3, 1, 3, 5, 0, NA, 0, 1)
58MUX_CFG("W4_USB_HIGHZ", D, 3, 4, 3, 5, 0, 3, 0, 1)
59MUX_CFG("W4_GPIO58", D, 3, 7, 3, 5, 0, 3, 0, 1)
60
61/* USB1 master */
62MUX_CFG("USB1_SUSP", 8, 27, 2, 1, 27, 0, NA, 0, 1)
63MUX_CFG("USB1_SE0", 9, 0, 2, 1, 28, 0, NA, 0, 1)
64MUX_CFG("W13_1610_USB1_SE0", 9, 0, 4, 1, 28, 0, NA, 0, 1)
65MUX_CFG("USB1_TXEN", 9, 3, 2, 1, 29, 0, NA, 0, 1)
66MUX_CFG("USB1_TXD", 9, 24, 1, 2, 4, 0, NA, 0, 1)
67MUX_CFG("USB1_VP", A, 3, 1, 2, 7, 0, NA, 0, 1)
68MUX_CFG("USB1_VM", A, 6, 1, 2, 8, 0, NA, 0, 1)
69MUX_CFG("USB1_RCV", A, 9, 1, 2, 9, 0, NA, 0, 1)
70MUX_CFG("USB1_SPEED", A, 12, 2, 2, 10, 0, NA, 0, 1)
71MUX_CFG("R13_1610_USB1_SPEED", A, 12, 5, 2, 10, 0, NA, 0, 1)
72MUX_CFG("R13_1710_USB1_SEO", A, 12, 5, 2, 10, 0, NA, 0, 1)
73
74/* USB2 master */
75MUX_CFG("USB2_SUSP", B, 3, 1, 2, 17, 0, NA, 0, 1)
76MUX_CFG("USB2_VP", B, 6, 1, 2, 18, 0, NA, 0, 1)
77MUX_CFG("USB2_TXEN", B, 9, 1, 2, 19, 0, NA, 0, 1)
78MUX_CFG("USB2_VM", C, 18, 1, 3, 0, 0, NA, 0, 1)
79MUX_CFG("USB2_RCV", C, 21, 1, 3, 1, 0, NA, 0, 1)
80MUX_CFG("USB2_SE0", C, 24, 2, 3, 2, 0, NA, 0, 1)
81MUX_CFG("USB2_TXD", C, 27, 2, 3, 3, 0, NA, 0, 1)
82
83/* OMAP-1510 GPIO */
84MUX_CFG("R18_1510_GPIO0", 7, 9, 0, 1, 11, 1, 0, 0, 1)
85MUX_CFG("R19_1510_GPIO1", 7, 6, 0, 1, 10, 1, 0, 0, 1)
86MUX_CFG("M14_1510_GPIO2", 7, 3, 0, 1, 9, 1, 0, 0, 1)
87
88/* OMAP1610 GPIO */
89MUX_CFG("P18_1610_GPIO3", 7, 0, 0, 1, 8, 0, NA, 0, 1)
90MUX_CFG("Y15_1610_GPIO17", A, 0, 7, 2, 6, 0, NA, 0, 1)
91
92/* OMAP-1710 GPIO */
93MUX_CFG("R18_1710_GPIO0", 7, 9, 0, 1, 11, 1, 1, 1, 1)
94MUX_CFG("V2_1710_GPIO10", F, 27, 1, 4, 3, 1, 4, 1, 1)
95MUX_CFG("N21_1710_GPIO14", 6, 9, 0, 1, 1, 1, 1, 1, 1)
96MUX_CFG("W15_1710_GPIO40", 9, 27, 7, 2, 5, 1, 2, 1, 1)
97
98/* MPUIO */
99MUX_CFG("MPUIO2", 7, 18, 0, 1, 14, 1, NA, 0, 1)
100MUX_CFG("N15_1610_MPUIO2", 7, 18, 0, 1, 14, 1, 1, 0, 1)
101MUX_CFG("MPUIO4", 7, 15, 0, 1, 13, 1, NA, 0, 1)
102MUX_CFG("MPUIO5", 7, 12, 0, 1, 12, 1, NA, 0, 1)
103
104MUX_CFG("T20_1610_MPUIO5", 7, 12, 0, 1, 12, 0, 3, 0, 1)
105MUX_CFG("W11_1610_MPUIO6", 10, 15, 2, 3, 8, 0, 3, 0, 1)
106MUX_CFG("V10_1610_MPUIO7", A, 24, 2, 2, 14, 0, 2, 0, 1)
107MUX_CFG("W11_1610_MPUIO9", 10, 15, 1, 3, 8, 0, 3, 0, 1)
108MUX_CFG("V10_1610_MPUIO10", A, 24, 1, 2, 14, 0, 2, 0, 1)
109MUX_CFG("W10_1610_MPUIO11", A, 18, 2, 2, 11, 0, 2, 0, 1)
110MUX_CFG("E20_1610_MPUIO13", 3, 21, 1, 0, 7, 0, 0, 0, 1)
111MUX_CFG("U20_1610_MPUIO14", 9, 6, 6, 0, 30, 0, 0, 0, 1)
112MUX_CFG("E19_1610_MPUIO15", 3, 18, 1, 0, 6, 0, 0, 0, 1)
113
114/* MCBSP2 */
115MUX_CFG("MCBSP2_CLKR", C, 6, 0, 2, 27, 1, NA, 0, 1)
116MUX_CFG("MCBSP2_CLKX", C, 9, 0, 2, 29, 1, NA, 0, 1)
117MUX_CFG("MCBSP2_DR", C, 0, 0, 2, 26, 1, NA, 0, 1)
118MUX_CFG("MCBSP2_DX", C, 15, 0, 2, 31, 1, NA, 0, 1)
119MUX_CFG("MCBSP2_FSR", C, 12, 0, 2, 30, 1, NA, 0, 1)
120MUX_CFG("MCBSP2_FSX", C, 3, 0, 2, 27, 1, NA, 0, 1)
121
122/* MCBSP3 NOTE: Mode must 1 for clock */
123MUX_CFG("MCBSP3_CLKX", 9, 3, 1, 1, 29, 0, NA, 0, 1)
124
125/* Misc ballouts */
126MUX_CFG("BALLOUT_V8_ARMIO3", B, 18, 0, 2, 25, 1, NA, 0, 1)
127MUX_CFG("N20_HDQ", 6, 18, 1, 1, 4, 0, 1, 4, 0)
128
129/* OMAP-1610 MMC2 */
130MUX_CFG("W8_1610_MMC2_DAT0", B, 21, 6, 2, 23, 1, 2, 1, 1)
131MUX_CFG("V8_1610_MMC2_DAT1", B, 27, 6, 2, 25, 1, 2, 1, 1)
132MUX_CFG("W15_1610_MMC2_DAT2", 9, 12, 6, 2, 5, 1, 2, 1, 1)
133MUX_CFG("R10_1610_MMC2_DAT3", B, 18, 6, 2, 22, 1, 2, 1, 1)
134MUX_CFG("Y10_1610_MMC2_CLK", B, 3, 6, 2, 17, 0, 2, 0, 1)
135MUX_CFG("Y8_1610_MMC2_CMD", B, 24, 6, 2, 24, 1, 2, 1, 1)
136MUX_CFG("V9_1610_MMC2_CMDDIR", B, 12, 6, 2, 20, 0, 2, 1, 1)
137MUX_CFG("V5_1610_MMC2_DATDIR0", B, 15, 6, 2, 21, 0, 2, 1, 1)
138MUX_CFG("W19_1610_MMC2_DATDIR1", 8, 15, 6, 1, 23, 0, 1, 1, 1)
139MUX_CFG("R18_1610_MMC2_CLKIN", 7, 9, 6, 1, 11, 0, 1, 11, 1)
140
141/* OMAP-1610 External Trace Interface */
142MUX_CFG("M19_1610_ETM_PSTAT0", 5, 27, 1, 0, 29, 0, 0, 0, 1)
143MUX_CFG("L15_1610_ETM_PSTAT1", 5, 24, 1, 0, 28, 0, 0, 0, 1)
144MUX_CFG("L18_1610_ETM_PSTAT2", 5, 21, 1, 0, 27, 0, 0, 0, 1)
145MUX_CFG("L19_1610_ETM_D0", 5, 18, 1, 0, 26, 0, 0, 0, 1)
146MUX_CFG("J19_1610_ETM_D6", 5, 0, 1, 0, 20, 0, 0, 0, 1)
147MUX_CFG("J18_1610_ETM_D7", 5, 27, 1, 0, 19, 0, 0, 0, 1)
148
149/* OMAP16XX GPIO */
150MUX_CFG("P20_1610_GPIO4", 6, 27, 0, 1, 7, 0, 1, 1, 1)
151MUX_CFG("V9_1610_GPIO7", B, 12, 1, 2, 20, 0, 2, 1, 1)
152MUX_CFG("W8_1610_GPIO9", B, 21, 0, 2, 23, 0, 2, 1, 1)
153MUX_CFG("N20_1610_GPIO11", 6, 18, 0, 1, 4, 0, 1, 1, 1)
154MUX_CFG("N19_1610_GPIO13", 6, 12, 0, 1, 2, 0, 1, 1, 1)
155MUX_CFG("P10_1610_GPIO22", C, 0, 7, 2, 26, 0, 2, 1, 1)
156MUX_CFG("V5_1610_GPIO24", B, 15, 7, 2, 21, 0, 2, 1, 1)
157MUX_CFG("AA20_1610_GPIO_41", 9, 9, 7, 1, 31, 0, 1, 1, 1)
158MUX_CFG("W19_1610_GPIO48", 8, 15, 7, 1, 23, 1, 1, 0, 1)
159MUX_CFG("M7_1610_GPIO62", 10, 0, 0, 4, 24, 0, 4, 0, 1)
160MUX_CFG("V14_16XX_GPIO37", 9, 18, 7, 2, 2, 0, 2, 2, 0)
161MUX_CFG("R9_16XX_GPIO18", C, 18, 7, 3, 0, 0, 3, 0, 0)
162MUX_CFG("L14_16XX_GPIO49", 6, 3, 7, 0, 31, 0, 0, 31, 0)
163
164/* OMAP-1610 uWire */
165MUX_CFG("V19_1610_UWIRE_SCLK", 8, 6, 0, 1, 20, 0, 1, 1, 1)
166MUX_CFG("U18_1610_UWIRE_SDI", 8, 0, 0, 1, 18, 0, 1, 1, 1)
167MUX_CFG("W21_1610_UWIRE_SDO", 8, 3, 0, 1, 19, 0, 1, 1, 1)
168MUX_CFG("N14_1610_UWIRE_CS0", 8, 9, 1, 1, 21, 0, 1, 1, 1)
169MUX_CFG("P15_1610_UWIRE_CS3", 8, 12, 1, 1, 22, 0, 1, 1, 1)
170MUX_CFG("N15_1610_UWIRE_CS1", 7, 18, 2, 1, 14, 0, NA, 0, 1)
171
172/* OMAP-1610 SPI */
173MUX_CFG("U19_1610_SPIF_SCK", 7, 21, 6, 1, 15, 0, 1, 1, 1)
174MUX_CFG("U18_1610_SPIF_DIN", 8, 0, 6, 1, 18, 1, 1, 0, 1)
175MUX_CFG("P20_1610_SPIF_DIN", 6, 27, 4, 1, 7, 1, 1, 0, 1)
176MUX_CFG("W21_1610_SPIF_DOUT", 8, 3, 6, 1, 19, 0, 1, 0, 1)
177MUX_CFG("R18_1610_SPIF_DOUT", 7, 9, 3, 1, 11, 0, 1, 0, 1)
178MUX_CFG("N14_1610_SPIF_CS0", 8, 9, 6, 1, 21, 0, 1, 1, 1)
179MUX_CFG("N15_1610_SPIF_CS1", 7, 18, 6, 1, 14, 0, 1, 1, 1)
180MUX_CFG("T19_1610_SPIF_CS2", 7, 15, 4, 1, 13, 0, 1, 1, 1)
181MUX_CFG("P15_1610_SPIF_CS3", 8, 12, 3, 1, 22, 0, 1, 1, 1)
182
183/* OMAP-1610 Flash */
184MUX_CFG("L3_1610_FLASH_CS2B_OE",10, 6, 1, NA, 0, 0, NA, 0, 1)
185MUX_CFG("M8_1610_FLASH_CS2B_WE",10, 3, 1, NA, 0, 0, NA, 0, 1)
186
187/* First MMC interface, same on 1510, 1610 and 1710 */
188MUX_CFG("MMC_CMD", A, 27, 0, 2, 15, 1, 2, 1, 1)
189MUX_CFG("MMC_DAT1", A, 24, 0, 2, 14, 1, 2, 1, 1)
190MUX_CFG("MMC_DAT2", A, 18, 0, 2, 12, 1, 2, 1, 1)
191MUX_CFG("MMC_DAT0", B, 0, 0, 2, 16, 1, 2, 1, 1)
192MUX_CFG("MMC_CLK", A, 21, 0, NA, 0, 0, NA, 0, 1)
193MUX_CFG("MMC_DAT3", 10, 15, 0, 3, 8, 1, 3, 1, 1)
194MUX_CFG("M15_1710_MMC_CLKI", 6, 21, 2, 0, 0, 0, NA, 0, 1)
195MUX_CFG("P19_1710_MMC_CMDDIR", 6, 24, 6, 0, 0, 0, NA, 0, 1)
196MUX_CFG("P20_1710_MMC_DATDIR0", 6, 27, 5, 0, 0, 0, NA, 0, 1)
197
198/* OMAP-1610 USB0 alternate configuration */
199MUX_CFG("W9_USB0_TXEN", B, 9, 5, 2, 19, 0, 2, 0, 1)
200MUX_CFG("AA9_USB0_VP", B, 6, 5, 2, 18, 0, 2, 0, 1)
201MUX_CFG("Y5_USB0_RCV", C, 21, 5, 3, 1, 0, 1, 0, 1)
202MUX_CFG("R9_USB0_VM", C, 18, 5, 3, 0, 0, 3, 0, 1)
203MUX_CFG("V6_USB0_TXD", C, 27, 5, 3, 3, 0, 3, 0, 1)
204MUX_CFG("W5_USB0_SE0", C, 24, 5, 3, 2, 0, 3, 0, 1)
205MUX_CFG("V9_USB0_SPEED", B, 12, 5, 2, 20, 0, 2, 0, 1)
206MUX_CFG("Y10_USB0_SUSP", B, 3, 5, 2, 17, 0, 2, 0, 1)
207
208/* USB2 interface */
209MUX_CFG("W9_USB2_TXEN", B, 9, 1, NA, 0, 0, NA, 0, 1)
210MUX_CFG("AA9_USB2_VP", B, 6, 1, NA, 0, 0, NA, 0, 1)
211MUX_CFG("Y5_USB2_RCV", C, 21, 1, NA, 0, 0, NA, 0, 1)
212MUX_CFG("R9_USB2_VM", C, 18, 1, NA, 0, 0, NA, 0, 1)
213MUX_CFG("V6_USB2_TXD", C, 27, 2, NA, 0, 0, NA, 0, 1)
214MUX_CFG("W5_USB2_SE0", C, 24, 2, NA, 0, 0, NA, 0, 1)
215
216/* 16XX UART */
217MUX_CFG("R13_1610_UART1_TX", A, 12, 6, 2, 10, 0, 2, 10, 1)
218MUX_CFG("V14_16XX_UART1_RX", 9, 18, 0, 2, 2, 0, 2, 2, 1)
219MUX_CFG("R14_1610_UART1_CTS", 9, 15, 0, 2, 1, 0, 2, 1, 1)
220MUX_CFG("AA15_1610_UART1_RTS", 9, 12, 1, 2, 0, 0, 2, 0, 1)
221MUX_CFG("R9_16XX_UART2_RX", C, 18, 0, 3, 0, 0, 3, 0, 1)
222MUX_CFG("L14_16XX_UART3_RX", 6, 3, 0, 0, 31, 0, 0, 31, 1)
223
224/* I2C interface */
225MUX_CFG("I2C_SCL", 7, 24, 0, NA, 0, 0, NA, 0, 0)
226MUX_CFG("I2C_SDA", 7, 27, 0, NA, 0, 0, NA, 0, 0)
227
228/* Keypad */
229MUX_CFG("F18_1610_KBC0", 3, 15, 0, 0, 5, 1, 0, 0, 0)
230MUX_CFG("D20_1610_KBC1", 3, 12, 0, 0, 4, 1, 0, 0, 0)
231MUX_CFG("D19_1610_KBC2", 3, 9, 0, 0, 3, 1, 0, 0, 0)
232MUX_CFG("E18_1610_KBC3", 3, 6, 0, 0, 2, 1, 0, 0, 0)
233MUX_CFG("C21_1610_KBC4", 3, 3, 0, 0, 1, 1, 0, 0, 0)
234MUX_CFG("G18_1610_KBR0", 4, 0, 0, 0, 10, 1, 0, 1, 0)
235MUX_CFG("F19_1610_KBR1", 3, 27, 0, 0, 9, 1, 0, 1, 0)
236MUX_CFG("H14_1610_KBR2", 3, 24, 0, 0, 8, 1, 0, 1, 0)
237MUX_CFG("E20_1610_KBR3", 3, 21, 0, 0, 7, 1, 0, 1, 0)
238MUX_CFG("E19_1610_KBR4", 3, 18, 0, 0, 6, 1, 0, 1, 0)
239MUX_CFG("N19_1610_KBR5", 6, 12, 1, 1, 2, 1, 1, 1, 0)
240
241/* Power management */
242MUX_CFG("T20_1610_LOW_PWR", 7, 12, 1, NA, 0, 0, NA, 0, 0)
243
244/* MCLK Settings */
245MUX_CFG("V5_1710_MCLK_ON", B, 15, 0, NA, 0, 0, NA, 0, 0)
246MUX_CFG("V5_1710_MCLK_OFF", B, 15, 6, NA, 0, 0, NA, 0, 0)
247MUX_CFG("R10_1610_MCLK_ON", B, 18, 0, NA, 22, 0, NA, 1, 0)
248MUX_CFG("R10_1610_MCLK_OFF", B, 18, 6, 2, 22, 1, 2, 1, 1)
249
250/* CompactFlash controller, conflicts with MMC1 */
251MUX_CFG("P11_1610_CF_CD2", A, 27, 3, 2, 15, 1, 2, 1, 1)
252MUX_CFG("R11_1610_CF_IOIS16", B, 0, 3, 2, 16, 1, 2, 1, 1)
253MUX_CFG("V10_1610_CF_IREQ", A, 24, 3, 2, 14, 0, 2, 0, 1)
254MUX_CFG("W10_1610_CF_RESET", A, 18, 3, 2, 12, 1, 2, 1, 1)
255MUX_CFG("W11_1610_CF_CD1", 10, 15, 3, 3, 8, 1, 3, 1, 1)
256
257/* parallel camera */
258MUX_CFG("J15_1610_CAM_LCLK", 4, 24, 0, 0, 18, 1, 0, 0, 0)
259MUX_CFG("J18_1610_CAM_D7", 4, 27, 0, 0, 19, 1, 0, 0, 0)
260MUX_CFG("J19_1610_CAM_D6", 5, 0, 0, 0, 20, 1, 0, 0, 0)
261MUX_CFG("J14_1610_CAM_D5", 5, 3, 0, 0, 21, 1, 0, 0, 0)
262MUX_CFG("K18_1610_CAM_D4", 5, 6, 0, 0, 22, 1, 0, 0, 0)
263MUX_CFG("K19_1610_CAM_D3", 5, 9, 0, 0, 23, 1, 0, 0, 0)
264MUX_CFG("K15_1610_CAM_D2", 5, 12, 0, 0, 24, 1, 0, 0, 0)
265MUX_CFG("K14_1610_CAM_D1", 5, 15, 0, 0, 25, 1, 0, 0, 0)
266MUX_CFG("L19_1610_CAM_D0", 5, 18, 0, 0, 26, 1, 0, 0, 0)
267MUX_CFG("L18_1610_CAM_VS", 5, 21, 0, 0, 27, 1, 0, 0, 0)
268MUX_CFG("L15_1610_CAM_HS", 5, 24, 0, 0, 28, 1, 0, 0, 0)
269MUX_CFG("M19_1610_CAM_RSTZ", 5, 27, 0, 0, 29, 0, 0, 0, 0)
270MUX_CFG("Y15_1610_CAM_OUTCLK", A, 0, 6, 2, 6, 0, 2, 0, 0)
271
272/* serial camera */
273MUX_CFG("H19_1610_CAM_EXCLK", 4, 21, 0, 0, 17, 0, 0, 0, 0)
274 /* REVISIT 5912 spec sez CCP_* can't pullup or pulldown ... ? */
275MUX_CFG("Y12_1610_CCP_CLKP", 8, 18, 6, 1, 24, 1, 1, 0, 0)
276MUX_CFG("W13_1610_CCP_CLKM", 9, 0, 6, 1, 28, 1, 1, 0, 0)
277MUX_CFG("W14_1610_CCP_DATAP", 9, 24, 6, 2, 4, 1, 2, 0, 0)
278MUX_CFG("Y14_1610_CCP_DATAM", 9, 21, 6, 2, 3, 1, 2, 0, 0)
279};
280#define OMAP1XXX_PINS_SZ ARRAY_SIZE(omap1xxx_pins)
281#else
282#define omap1xxx_pins NULL
283#define OMAP1XXX_PINS_SZ 0
284#endif /* CONFIG_ARCH_OMAP15XX || CONFIG_ARCH_OMAP16XX */
285
286static int omap1_cfg_reg(const struct pin_config *cfg)
287{
288 static DEFINE_SPINLOCK(mux_spin_lock);
289 unsigned long flags;
290 unsigned int reg_orig = 0, reg = 0, pu_pd_orig = 0, pu_pd = 0,
291 pull_orig = 0, pull = 0;
292 unsigned int mask, warn = 0;
293
294 /* Check the mux register in question */
295 if (cfg->mux_reg) {
296 unsigned tmp1, tmp2;
297
298 spin_lock_irqsave(&mux_spin_lock, flags);
299 reg_orig = omap_readl(cfg->mux_reg);
300
301 /* The mux registers always seem to be 3 bits long */
302 mask = (0x7 << cfg->mask_offset);
303 tmp1 = reg_orig & mask;
304 reg = reg_orig & ~mask;
305
306 tmp2 = (cfg->mask << cfg->mask_offset);
307 reg |= tmp2;
308
309 if (tmp1 != tmp2)
310 warn = 1;
311
312 omap_writel(reg, cfg->mux_reg);
313 spin_unlock_irqrestore(&mux_spin_lock, flags);
314 }
315
316 /* Check for pull up or pull down selection on 1610 */
317 if (!cpu_is_omap15xx()) {
318 if (cfg->pu_pd_reg && cfg->pull_val) {
319 spin_lock_irqsave(&mux_spin_lock, flags);
320 pu_pd_orig = omap_readl(cfg->pu_pd_reg);
321 mask = 1 << cfg->pull_bit;
322
323 if (cfg->pu_pd_val) {
324 if (!(pu_pd_orig & mask))
325 warn = 1;
326 /* Use pull up */
327 pu_pd = pu_pd_orig | mask;
328 } else {
329 if (pu_pd_orig & mask)
330 warn = 1;
331 /* Use pull down */
332 pu_pd = pu_pd_orig & ~mask;
333 }
334 omap_writel(pu_pd, cfg->pu_pd_reg);
335 spin_unlock_irqrestore(&mux_spin_lock, flags);
336 }
337 }
338
339 /* Check for an associated pull down register */
340 if (cfg->pull_reg) {
341 spin_lock_irqsave(&mux_spin_lock, flags);
342 pull_orig = omap_readl(cfg->pull_reg);
343 mask = 1 << cfg->pull_bit;
344
345 if (cfg->pull_val) {
346 if (pull_orig & mask)
347 warn = 1;
348 /* Low bit = pull enabled */
349 pull = pull_orig & ~mask;
350 } else {
351 if (!(pull_orig & mask))
352 warn = 1;
353 /* High bit = pull disabled */
354 pull = pull_orig | mask;
355 }
356
357 omap_writel(pull, cfg->pull_reg);
358 spin_unlock_irqrestore(&mux_spin_lock, flags);
359 }
360
361 if (warn) {
362#ifdef CONFIG_OMAP_MUX_WARNINGS
363 printk(KERN_WARNING "MUX: initialized %s\n", cfg->name);
364#endif
365 }
366
367#ifdef CONFIG_OMAP_MUX_DEBUG
368 if (cfg->debug || warn) {
369 printk("MUX: Setting register %s\n", cfg->name);
370 printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
371 cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
372
373 if (!cpu_is_omap15xx()) {
374 if (cfg->pu_pd_reg && cfg->pull_val) {
375 printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
376 cfg->pu_pd_name, cfg->pu_pd_reg,
377 pu_pd_orig, pu_pd);
378 }
379 }
380
381 if (cfg->pull_reg)
382 printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
383 cfg->pull_name, cfg->pull_reg, pull_orig, pull);
384 }
385#endif
386
387#ifdef CONFIG_OMAP_MUX_WARNINGS
388 return warn ? -ETXTBSY : 0;
389#else
390 return 0;
391#endif
392}
393
394static struct omap_mux_cfg *mux_cfg;
395
396int __init omap_mux_register(struct omap_mux_cfg *arch_mux_cfg)
397{
398 if (!arch_mux_cfg || !arch_mux_cfg->pins || arch_mux_cfg->size == 0
399 || !arch_mux_cfg->cfg_reg) {
400 printk(KERN_ERR "Invalid pin table\n");
401 return -EINVAL;
402 }
403
404 mux_cfg = arch_mux_cfg;
405
406 return 0;
407}
408
409/*
410 * Sets the Omap MUX and PULL_DWN registers based on the table
411 */
412int omap_cfg_reg(const unsigned long index)
413{
414 struct pin_config *reg;
415
416 if (!cpu_class_is_omap1()) {
417 printk(KERN_ERR "mux: Broken omap_cfg_reg(%lu) entry\n",
418 index);
419 WARN_ON(1);
420 return -EINVAL;
421 }
422
423 if (mux_cfg == NULL) {
424 printk(KERN_ERR "Pin mux table not initialized\n");
425 return -ENODEV;
426 }
427
428 if (index >= mux_cfg->size) {
429 printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
430 index, mux_cfg->size);
431 dump_stack();
432 return -ENODEV;
433 }
434
435 reg = &mux_cfg->pins[index];
436
437 if (!mux_cfg->cfg_reg)
438 return -ENODEV;
439
440 return mux_cfg->cfg_reg(reg);
441}
442EXPORT_SYMBOL(omap_cfg_reg);
443
444int __init omap1_mux_init(void)
445{
446 if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
447 arch_mux_cfg.pins = omap1xxx_pins;
448 arch_mux_cfg.size = OMAP1XXX_PINS_SZ;
449 arch_mux_cfg.cfg_reg = omap1_cfg_reg;
450 }
451
452 return omap_mux_register(&arch_mux_cfg);
453}
454
455#else
456#define omap_mux_init() do {} while(0)
457#define omap_cfg_reg(x) do {} while(0)
458#endif /* CONFIG_OMAP_MUX */
459
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * linux/arch/arm/mach-omap1/mux.c
4 *
5 * OMAP1 pin multiplexing configurations
6 *
7 * Copyright (C) 2003 - 2008 Nokia Corporation
8 *
9 * Written by Tony Lindgren
10 */
11#include <linux/module.h>
12#include <linux/init.h>
13#include <linux/io.h>
14#include <linux/spinlock.h>
15
16#include <mach/hardware.h>
17
18#include <mach/mux.h>
19
20#ifdef CONFIG_OMAP_MUX
21
22static struct omap_mux_cfg arch_mux_cfg;
23
24#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
25static struct pin_config omap7xx_pins[] = {
26MUX_CFG_7XX("E2_7XX_KBR0", 12, 21, 0, 20, 1, 0)
27MUX_CFG_7XX("J7_7XX_KBR1", 12, 25, 0, 24, 1, 0)
28MUX_CFG_7XX("E1_7XX_KBR2", 12, 29, 0, 28, 1, 0)
29MUX_CFG_7XX("F3_7XX_KBR3", 13, 1, 0, 0, 1, 0)
30MUX_CFG_7XX("D2_7XX_KBR4", 13, 5, 0, 4, 1, 0)
31MUX_CFG_7XX("C2_7XX_KBC0", 13, 9, 0, 8, 1, 0)
32MUX_CFG_7XX("D3_7XX_KBC1", 13, 13, 0, 12, 1, 0)
33MUX_CFG_7XX("E4_7XX_KBC2", 13, 17, 0, 16, 1, 0)
34MUX_CFG_7XX("F4_7XX_KBC3", 13, 21, 0, 20, 1, 0)
35MUX_CFG_7XX("E3_7XX_KBC4", 13, 25, 0, 24, 1, 0)
36
37MUX_CFG_7XX("AA17_7XX_USB_DM", 2, 21, 0, 20, 0, 0)
38MUX_CFG_7XX("W16_7XX_USB_PU_EN", 2, 25, 0, 24, 0, 0)
39MUX_CFG_7XX("W17_7XX_USB_VBUSI", 2, 29, 6, 28, 1, 0)
40MUX_CFG_7XX("W18_7XX_USB_DMCK_OUT",3, 3, 1, 2, 0, 0)
41MUX_CFG_7XX("W19_7XX_USB_DCRST", 3, 7, 1, 6, 0, 0)
42
43/* MMC Pins */
44MUX_CFG_7XX("MMC_7XX_CMD", 2, 9, 0, 8, 1, 0)
45MUX_CFG_7XX("MMC_7XX_CLK", 2, 13, 0, 12, 1, 0)
46MUX_CFG_7XX("MMC_7XX_DAT0", 2, 17, 0, 16, 1, 0)
47
48/* I2C interface */
49MUX_CFG_7XX("I2C_7XX_SCL", 5, 1, 0, 0, 1, 0)
50MUX_CFG_7XX("I2C_7XX_SDA", 5, 5, 0, 0, 1, 0)
51
52/* SPI pins */
53MUX_CFG_7XX("SPI_7XX_1", 6, 5, 4, 4, 1, 0)
54MUX_CFG_7XX("SPI_7XX_2", 6, 9, 4, 8, 1, 0)
55MUX_CFG_7XX("SPI_7XX_3", 6, 13, 4, 12, 1, 0)
56MUX_CFG_7XX("SPI_7XX_4", 6, 17, 4, 16, 1, 0)
57MUX_CFG_7XX("SPI_7XX_5", 8, 25, 0, 24, 0, 0)
58MUX_CFG_7XX("SPI_7XX_6", 9, 5, 0, 4, 0, 0)
59
60/* UART pins */
61MUX_CFG_7XX("UART_7XX_1", 3, 21, 0, 20, 0, 0)
62MUX_CFG_7XX("UART_7XX_2", 8, 1, 6, 0, 0, 0)
63};
64#define OMAP7XX_PINS_SZ ARRAY_SIZE(omap7xx_pins)
65#else
66#define omap7xx_pins NULL
67#define OMAP7XX_PINS_SZ 0
68#endif /* CONFIG_ARCH_OMAP730 || CONFIG_ARCH_OMAP850 */
69
70#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
71static struct pin_config omap1xxx_pins[] = {
72/*
73 * description mux mode mux pull pull pull pu_pd pu dbg
74 * reg offset mode reg bit ena reg
75 */
76MUX_CFG("UART1_TX", 9, 21, 1, 2, 3, 0, NA, 0, 0)
77MUX_CFG("UART1_RTS", 9, 12, 1, 2, 0, 0, NA, 0, 0)
78
79/* UART2 (COM_UART_GATING), conflicts with USB2 */
80MUX_CFG("UART2_TX", C, 27, 1, 3, 3, 0, NA, 0, 0)
81MUX_CFG("UART2_RX", C, 18, 0, 3, 1, 1, NA, 0, 0)
82MUX_CFG("UART2_CTS", C, 21, 0, 3, 1, 1, NA, 0, 0)
83MUX_CFG("UART2_RTS", C, 24, 1, 3, 2, 0, NA, 0, 0)
84
85/* UART3 (GIGA_UART_GATING) */
86MUX_CFG("UART3_TX", 6, 0, 1, 0, 30, 0, NA, 0, 0)
87MUX_CFG("UART3_RX", 6, 3, 0, 0, 31, 1, NA, 0, 0)
88MUX_CFG("UART3_CTS", 5, 12, 2, 0, 24, 0, NA, 0, 0)
89MUX_CFG("UART3_RTS", 5, 15, 2, 0, 25, 0, NA, 0, 0)
90MUX_CFG("UART3_CLKREQ", 9, 27, 0, 2, 5, 0, NA, 0, 0)
91MUX_CFG("UART3_BCLK", A, 0, 0, 2, 6, 0, NA, 0, 0)
92MUX_CFG("Y15_1610_UART3_RTS", A, 0, 1, 2, 6, 0, NA, 0, 0)
93
94/* PWT & PWL, conflicts with UART3 */
95MUX_CFG("PWT", 6, 0, 2, 0, 30, 0, NA, 0, 0)
96MUX_CFG("PWL", 6, 3, 1, 0, 31, 1, NA, 0, 0)
97
98/* USB internal master generic */
99MUX_CFG("R18_USB_VBUS", 7, 9, 2, 1, 11, 0, NA, 0, 1)
100MUX_CFG("R18_1510_USB_GPIO0", 7, 9, 0, 1, 11, 1, NA, 0, 1)
101/* works around erratum: W4_USB_PUEN and W4_USB_PUDIS are switched! */
102MUX_CFG("W4_USB_PUEN", D, 3, 3, 3, 5, 1, NA, 0, 1)
103MUX_CFG("W4_USB_CLKO", D, 3, 1, 3, 5, 0, NA, 0, 1)
104MUX_CFG("W4_USB_HIGHZ", D, 3, 4, 3, 5, 0, 3, 0, 1)
105MUX_CFG("W4_GPIO58", D, 3, 7, 3, 5, 0, 3, 0, 1)
106
107/* USB1 master */
108MUX_CFG("USB1_SUSP", 8, 27, 2, 1, 27, 0, NA, 0, 1)
109MUX_CFG("USB1_SE0", 9, 0, 2, 1, 28, 0, NA, 0, 1)
110MUX_CFG("W13_1610_USB1_SE0", 9, 0, 4, 1, 28, 0, NA, 0, 1)
111MUX_CFG("USB1_TXEN", 9, 3, 2, 1, 29, 0, NA, 0, 1)
112MUX_CFG("USB1_TXD", 9, 24, 1, 2, 4, 0, NA, 0, 1)
113MUX_CFG("USB1_VP", A, 3, 1, 2, 7, 0, NA, 0, 1)
114MUX_CFG("USB1_VM", A, 6, 1, 2, 8, 0, NA, 0, 1)
115MUX_CFG("USB1_RCV", A, 9, 1, 2, 9, 0, NA, 0, 1)
116MUX_CFG("USB1_SPEED", A, 12, 2, 2, 10, 0, NA, 0, 1)
117MUX_CFG("R13_1610_USB1_SPEED", A, 12, 5, 2, 10, 0, NA, 0, 1)
118MUX_CFG("R13_1710_USB1_SEO", A, 12, 5, 2, 10, 0, NA, 0, 1)
119
120/* USB2 master */
121MUX_CFG("USB2_SUSP", B, 3, 1, 2, 17, 0, NA, 0, 1)
122MUX_CFG("USB2_VP", B, 6, 1, 2, 18, 0, NA, 0, 1)
123MUX_CFG("USB2_TXEN", B, 9, 1, 2, 19, 0, NA, 0, 1)
124MUX_CFG("USB2_VM", C, 18, 1, 3, 0, 0, NA, 0, 1)
125MUX_CFG("USB2_RCV", C, 21, 1, 3, 1, 0, NA, 0, 1)
126MUX_CFG("USB2_SE0", C, 24, 2, 3, 2, 0, NA, 0, 1)
127MUX_CFG("USB2_TXD", C, 27, 2, 3, 3, 0, NA, 0, 1)
128
129/* OMAP-1510 GPIO */
130MUX_CFG("R18_1510_GPIO0", 7, 9, 0, 1, 11, 1, 0, 0, 1)
131MUX_CFG("R19_1510_GPIO1", 7, 6, 0, 1, 10, 1, 0, 0, 1)
132MUX_CFG("M14_1510_GPIO2", 7, 3, 0, 1, 9, 1, 0, 0, 1)
133
134/* OMAP1610 GPIO */
135MUX_CFG("P18_1610_GPIO3", 7, 0, 0, 1, 8, 0, NA, 0, 1)
136MUX_CFG("Y15_1610_GPIO17", A, 0, 7, 2, 6, 0, NA, 0, 1)
137
138/* OMAP-1710 GPIO */
139MUX_CFG("R18_1710_GPIO0", 7, 9, 0, 1, 11, 1, 1, 1, 1)
140MUX_CFG("V2_1710_GPIO10", F, 27, 1, 4, 3, 1, 4, 1, 1)
141MUX_CFG("N21_1710_GPIO14", 6, 9, 0, 1, 1, 1, 1, 1, 1)
142MUX_CFG("W15_1710_GPIO40", 9, 27, 7, 2, 5, 1, 2, 1, 1)
143
144/* MPUIO */
145MUX_CFG("MPUIO2", 7, 18, 0, 1, 14, 1, NA, 0, 1)
146MUX_CFG("N15_1610_MPUIO2", 7, 18, 0, 1, 14, 1, 1, 0, 1)
147MUX_CFG("MPUIO4", 7, 15, 0, 1, 13, 1, NA, 0, 1)
148MUX_CFG("MPUIO5", 7, 12, 0, 1, 12, 1, NA, 0, 1)
149
150MUX_CFG("T20_1610_MPUIO5", 7, 12, 0, 1, 12, 0, 3, 0, 1)
151MUX_CFG("W11_1610_MPUIO6", 10, 15, 2, 3, 8, 0, 3, 0, 1)
152MUX_CFG("V10_1610_MPUIO7", A, 24, 2, 2, 14, 0, 2, 0, 1)
153MUX_CFG("W11_1610_MPUIO9", 10, 15, 1, 3, 8, 0, 3, 0, 1)
154MUX_CFG("V10_1610_MPUIO10", A, 24, 1, 2, 14, 0, 2, 0, 1)
155MUX_CFG("W10_1610_MPUIO11", A, 18, 2, 2, 11, 0, 2, 0, 1)
156MUX_CFG("E20_1610_MPUIO13", 3, 21, 1, 0, 7, 0, 0, 0, 1)
157MUX_CFG("U20_1610_MPUIO14", 9, 6, 6, 0, 30, 0, 0, 0, 1)
158MUX_CFG("E19_1610_MPUIO15", 3, 18, 1, 0, 6, 0, 0, 0, 1)
159
160/* MCBSP2 */
161MUX_CFG("MCBSP2_CLKR", C, 6, 0, 2, 27, 1, NA, 0, 1)
162MUX_CFG("MCBSP2_CLKX", C, 9, 0, 2, 29, 1, NA, 0, 1)
163MUX_CFG("MCBSP2_DR", C, 0, 0, 2, 26, 1, NA, 0, 1)
164MUX_CFG("MCBSP2_DX", C, 15, 0, 2, 31, 1, NA, 0, 1)
165MUX_CFG("MCBSP2_FSR", C, 12, 0, 2, 30, 1, NA, 0, 1)
166MUX_CFG("MCBSP2_FSX", C, 3, 0, 2, 27, 1, NA, 0, 1)
167
168/* MCBSP3 NOTE: Mode must 1 for clock */
169MUX_CFG("MCBSP3_CLKX", 9, 3, 1, 1, 29, 0, NA, 0, 1)
170
171/* Misc ballouts */
172MUX_CFG("BALLOUT_V8_ARMIO3", B, 18, 0, 2, 25, 1, NA, 0, 1)
173MUX_CFG("N20_HDQ", 6, 18, 1, 1, 4, 0, 1, 4, 0)
174
175/* OMAP-1610 MMC2 */
176MUX_CFG("W8_1610_MMC2_DAT0", B, 21, 6, 2, 23, 1, 2, 1, 1)
177MUX_CFG("V8_1610_MMC2_DAT1", B, 27, 6, 2, 25, 1, 2, 1, 1)
178MUX_CFG("W15_1610_MMC2_DAT2", 9, 12, 6, 2, 5, 1, 2, 1, 1)
179MUX_CFG("R10_1610_MMC2_DAT3", B, 18, 6, 2, 22, 1, 2, 1, 1)
180MUX_CFG("Y10_1610_MMC2_CLK", B, 3, 6, 2, 17, 0, 2, 0, 1)
181MUX_CFG("Y8_1610_MMC2_CMD", B, 24, 6, 2, 24, 1, 2, 1, 1)
182MUX_CFG("V9_1610_MMC2_CMDDIR", B, 12, 6, 2, 20, 0, 2, 1, 1)
183MUX_CFG("V5_1610_MMC2_DATDIR0", B, 15, 6, 2, 21, 0, 2, 1, 1)
184MUX_CFG("W19_1610_MMC2_DATDIR1", 8, 15, 6, 1, 23, 0, 1, 1, 1)
185MUX_CFG("R18_1610_MMC2_CLKIN", 7, 9, 6, 1, 11, 0, 1, 11, 1)
186
187/* OMAP-1610 External Trace Interface */
188MUX_CFG("M19_1610_ETM_PSTAT0", 5, 27, 1, 0, 29, 0, 0, 0, 1)
189MUX_CFG("L15_1610_ETM_PSTAT1", 5, 24, 1, 0, 28, 0, 0, 0, 1)
190MUX_CFG("L18_1610_ETM_PSTAT2", 5, 21, 1, 0, 27, 0, 0, 0, 1)
191MUX_CFG("L19_1610_ETM_D0", 5, 18, 1, 0, 26, 0, 0, 0, 1)
192MUX_CFG("J19_1610_ETM_D6", 5, 0, 1, 0, 20, 0, 0, 0, 1)
193MUX_CFG("J18_1610_ETM_D7", 5, 27, 1, 0, 19, 0, 0, 0, 1)
194
195/* OMAP16XX GPIO */
196MUX_CFG("P20_1610_GPIO4", 6, 27, 0, 1, 7, 0, 1, 1, 1)
197MUX_CFG("V9_1610_GPIO7", B, 12, 1, 2, 20, 0, 2, 1, 1)
198MUX_CFG("W8_1610_GPIO9", B, 21, 0, 2, 23, 0, 2, 1, 1)
199MUX_CFG("N20_1610_GPIO11", 6, 18, 0, 1, 4, 0, 1, 1, 1)
200MUX_CFG("N19_1610_GPIO13", 6, 12, 0, 1, 2, 0, 1, 1, 1)
201MUX_CFG("P10_1610_GPIO22", C, 0, 7, 2, 26, 0, 2, 1, 1)
202MUX_CFG("V5_1610_GPIO24", B, 15, 7, 2, 21, 0, 2, 1, 1)
203MUX_CFG("AA20_1610_GPIO_41", 9, 9, 7, 1, 31, 0, 1, 1, 1)
204MUX_CFG("W19_1610_GPIO48", 8, 15, 7, 1, 23, 1, 1, 0, 1)
205MUX_CFG("M7_1610_GPIO62", 10, 0, 0, 4, 24, 0, 4, 0, 1)
206MUX_CFG("V14_16XX_GPIO37", 9, 18, 7, 2, 2, 0, 2, 2, 0)
207MUX_CFG("R9_16XX_GPIO18", C, 18, 7, 3, 0, 0, 3, 0, 0)
208MUX_CFG("L14_16XX_GPIO49", 6, 3, 7, 0, 31, 0, 0, 31, 0)
209
210/* OMAP-1610 uWire */
211MUX_CFG("V19_1610_UWIRE_SCLK", 8, 6, 0, 1, 20, 0, 1, 1, 1)
212MUX_CFG("U18_1610_UWIRE_SDI", 8, 0, 0, 1, 18, 0, 1, 1, 1)
213MUX_CFG("W21_1610_UWIRE_SDO", 8, 3, 0, 1, 19, 0, 1, 1, 1)
214MUX_CFG("N14_1610_UWIRE_CS0", 8, 9, 1, 1, 21, 0, 1, 1, 1)
215MUX_CFG("P15_1610_UWIRE_CS3", 8, 12, 1, 1, 22, 0, 1, 1, 1)
216MUX_CFG("N15_1610_UWIRE_CS1", 7, 18, 2, 1, 14, 0, NA, 0, 1)
217
218/* OMAP-1610 SPI */
219MUX_CFG("U19_1610_SPIF_SCK", 7, 21, 6, 1, 15, 0, 1, 1, 1)
220MUX_CFG("U18_1610_SPIF_DIN", 8, 0, 6, 1, 18, 1, 1, 0, 1)
221MUX_CFG("P20_1610_SPIF_DIN", 6, 27, 4, 1, 7, 1, 1, 0, 1)
222MUX_CFG("W21_1610_SPIF_DOUT", 8, 3, 6, 1, 19, 0, 1, 0, 1)
223MUX_CFG("R18_1610_SPIF_DOUT", 7, 9, 3, 1, 11, 0, 1, 0, 1)
224MUX_CFG("N14_1610_SPIF_CS0", 8, 9, 6, 1, 21, 0, 1, 1, 1)
225MUX_CFG("N15_1610_SPIF_CS1", 7, 18, 6, 1, 14, 0, 1, 1, 1)
226MUX_CFG("T19_1610_SPIF_CS2", 7, 15, 4, 1, 13, 0, 1, 1, 1)
227MUX_CFG("P15_1610_SPIF_CS3", 8, 12, 3, 1, 22, 0, 1, 1, 1)
228
229/* OMAP-1610 Flash */
230MUX_CFG("L3_1610_FLASH_CS2B_OE",10, 6, 1, NA, 0, 0, NA, 0, 1)
231MUX_CFG("M8_1610_FLASH_CS2B_WE",10, 3, 1, NA, 0, 0, NA, 0, 1)
232
233/* First MMC interface, same on 1510, 1610 and 1710 */
234MUX_CFG("MMC_CMD", A, 27, 0, 2, 15, 1, 2, 1, 1)
235MUX_CFG("MMC_DAT1", A, 24, 0, 2, 14, 1, 2, 1, 1)
236MUX_CFG("MMC_DAT2", A, 18, 0, 2, 12, 1, 2, 1, 1)
237MUX_CFG("MMC_DAT0", B, 0, 0, 2, 16, 1, 2, 1, 1)
238MUX_CFG("MMC_CLK", A, 21, 0, NA, 0, 0, NA, 0, 1)
239MUX_CFG("MMC_DAT3", 10, 15, 0, 3, 8, 1, 3, 1, 1)
240MUX_CFG("M15_1710_MMC_CLKI", 6, 21, 2, 0, 0, 0, NA, 0, 1)
241MUX_CFG("P19_1710_MMC_CMDDIR", 6, 24, 6, 0, 0, 0, NA, 0, 1)
242MUX_CFG("P20_1710_MMC_DATDIR0", 6, 27, 5, 0, 0, 0, NA, 0, 1)
243
244/* OMAP-1610 USB0 alternate configuration */
245MUX_CFG("W9_USB0_TXEN", B, 9, 5, 2, 19, 0, 2, 0, 1)
246MUX_CFG("AA9_USB0_VP", B, 6, 5, 2, 18, 0, 2, 0, 1)
247MUX_CFG("Y5_USB0_RCV", C, 21, 5, 3, 1, 0, 1, 0, 1)
248MUX_CFG("R9_USB0_VM", C, 18, 5, 3, 0, 0, 3, 0, 1)
249MUX_CFG("V6_USB0_TXD", C, 27, 5, 3, 3, 0, 3, 0, 1)
250MUX_CFG("W5_USB0_SE0", C, 24, 5, 3, 2, 0, 3, 0, 1)
251MUX_CFG("V9_USB0_SPEED", B, 12, 5, 2, 20, 0, 2, 0, 1)
252MUX_CFG("Y10_USB0_SUSP", B, 3, 5, 2, 17, 0, 2, 0, 1)
253
254/* USB2 interface */
255MUX_CFG("W9_USB2_TXEN", B, 9, 1, NA, 0, 0, NA, 0, 1)
256MUX_CFG("AA9_USB2_VP", B, 6, 1, NA, 0, 0, NA, 0, 1)
257MUX_CFG("Y5_USB2_RCV", C, 21, 1, NA, 0, 0, NA, 0, 1)
258MUX_CFG("R9_USB2_VM", C, 18, 1, NA, 0, 0, NA, 0, 1)
259MUX_CFG("V6_USB2_TXD", C, 27, 2, NA, 0, 0, NA, 0, 1)
260MUX_CFG("W5_USB2_SE0", C, 24, 2, NA, 0, 0, NA, 0, 1)
261
262/* 16XX UART */
263MUX_CFG("R13_1610_UART1_TX", A, 12, 6, 2, 10, 0, 2, 10, 1)
264MUX_CFG("V14_16XX_UART1_RX", 9, 18, 0, 2, 2, 0, 2, 2, 1)
265MUX_CFG("R14_1610_UART1_CTS", 9, 15, 0, 2, 1, 0, 2, 1, 1)
266MUX_CFG("AA15_1610_UART1_RTS", 9, 12, 1, 2, 0, 0, 2, 0, 1)
267MUX_CFG("R9_16XX_UART2_RX", C, 18, 0, 3, 0, 0, 3, 0, 1)
268MUX_CFG("L14_16XX_UART3_RX", 6, 3, 0, 0, 31, 0, 0, 31, 1)
269
270/* I2C interface */
271MUX_CFG("I2C_SCL", 7, 24, 0, NA, 0, 0, NA, 0, 0)
272MUX_CFG("I2C_SDA", 7, 27, 0, NA, 0, 0, NA, 0, 0)
273
274/* Keypad */
275MUX_CFG("F18_1610_KBC0", 3, 15, 0, 0, 5, 1, 0, 0, 0)
276MUX_CFG("D20_1610_KBC1", 3, 12, 0, 0, 4, 1, 0, 0, 0)
277MUX_CFG("D19_1610_KBC2", 3, 9, 0, 0, 3, 1, 0, 0, 0)
278MUX_CFG("E18_1610_KBC3", 3, 6, 0, 0, 2, 1, 0, 0, 0)
279MUX_CFG("C21_1610_KBC4", 3, 3, 0, 0, 1, 1, 0, 0, 0)
280MUX_CFG("G18_1610_KBR0", 4, 0, 0, 0, 10, 1, 0, 1, 0)
281MUX_CFG("F19_1610_KBR1", 3, 27, 0, 0, 9, 1, 0, 1, 0)
282MUX_CFG("H14_1610_KBR2", 3, 24, 0, 0, 8, 1, 0, 1, 0)
283MUX_CFG("E20_1610_KBR3", 3, 21, 0, 0, 7, 1, 0, 1, 0)
284MUX_CFG("E19_1610_KBR4", 3, 18, 0, 0, 6, 1, 0, 1, 0)
285MUX_CFG("N19_1610_KBR5", 6, 12, 1, 1, 2, 1, 1, 1, 0)
286
287/* Power management */
288MUX_CFG("T20_1610_LOW_PWR", 7, 12, 1, NA, 0, 0, NA, 0, 0)
289
290/* MCLK Settings */
291MUX_CFG("V5_1710_MCLK_ON", B, 15, 0, NA, 0, 0, NA, 0, 0)
292MUX_CFG("V5_1710_MCLK_OFF", B, 15, 6, NA, 0, 0, NA, 0, 0)
293MUX_CFG("R10_1610_MCLK_ON", B, 18, 0, NA, 22, 0, NA, 1, 0)
294MUX_CFG("R10_1610_MCLK_OFF", B, 18, 6, 2, 22, 1, 2, 1, 1)
295
296/* CompactFlash controller, conflicts with MMC1 */
297MUX_CFG("P11_1610_CF_CD2", A, 27, 3, 2, 15, 1, 2, 1, 1)
298MUX_CFG("R11_1610_CF_IOIS16", B, 0, 3, 2, 16, 1, 2, 1, 1)
299MUX_CFG("V10_1610_CF_IREQ", A, 24, 3, 2, 14, 0, 2, 0, 1)
300MUX_CFG("W10_1610_CF_RESET", A, 18, 3, 2, 12, 1, 2, 1, 1)
301MUX_CFG("W11_1610_CF_CD1", 10, 15, 3, 3, 8, 1, 3, 1, 1)
302
303/* parallel camera */
304MUX_CFG("J15_1610_CAM_LCLK", 4, 24, 0, 0, 18, 1, 0, 0, 0)
305MUX_CFG("J18_1610_CAM_D7", 4, 27, 0, 0, 19, 1, 0, 0, 0)
306MUX_CFG("J19_1610_CAM_D6", 5, 0, 0, 0, 20, 1, 0, 0, 0)
307MUX_CFG("J14_1610_CAM_D5", 5, 3, 0, 0, 21, 1, 0, 0, 0)
308MUX_CFG("K18_1610_CAM_D4", 5, 6, 0, 0, 22, 1, 0, 0, 0)
309MUX_CFG("K19_1610_CAM_D3", 5, 9, 0, 0, 23, 1, 0, 0, 0)
310MUX_CFG("K15_1610_CAM_D2", 5, 12, 0, 0, 24, 1, 0, 0, 0)
311MUX_CFG("K14_1610_CAM_D1", 5, 15, 0, 0, 25, 1, 0, 0, 0)
312MUX_CFG("L19_1610_CAM_D0", 5, 18, 0, 0, 26, 1, 0, 0, 0)
313MUX_CFG("L18_1610_CAM_VS", 5, 21, 0, 0, 27, 1, 0, 0, 0)
314MUX_CFG("L15_1610_CAM_HS", 5, 24, 0, 0, 28, 1, 0, 0, 0)
315MUX_CFG("M19_1610_CAM_RSTZ", 5, 27, 0, 0, 29, 0, 0, 0, 0)
316MUX_CFG("Y15_1610_CAM_OUTCLK", A, 0, 6, 2, 6, 0, 2, 0, 0)
317
318/* serial camera */
319MUX_CFG("H19_1610_CAM_EXCLK", 4, 21, 0, 0, 17, 0, 0, 0, 0)
320 /* REVISIT 5912 spec sez CCP_* can't pullup or pulldown ... ? */
321MUX_CFG("Y12_1610_CCP_CLKP", 8, 18, 6, 1, 24, 1, 1, 0, 0)
322MUX_CFG("W13_1610_CCP_CLKM", 9, 0, 6, 1, 28, 1, 1, 0, 0)
323MUX_CFG("W14_1610_CCP_DATAP", 9, 24, 6, 2, 4, 1, 2, 0, 0)
324MUX_CFG("Y14_1610_CCP_DATAM", 9, 21, 6, 2, 3, 1, 2, 0, 0)
325};
326#define OMAP1XXX_PINS_SZ ARRAY_SIZE(omap1xxx_pins)
327#else
328#define omap1xxx_pins NULL
329#define OMAP1XXX_PINS_SZ 0
330#endif /* CONFIG_ARCH_OMAP15XX || CONFIG_ARCH_OMAP16XX */
331
332static int omap1_cfg_reg(const struct pin_config *cfg)
333{
334 static DEFINE_SPINLOCK(mux_spin_lock);
335 unsigned long flags;
336 unsigned int reg_orig = 0, reg = 0, pu_pd_orig = 0, pu_pd = 0,
337 pull_orig = 0, pull = 0;
338 unsigned int mask, warn = 0;
339
340 /* Check the mux register in question */
341 if (cfg->mux_reg) {
342 unsigned tmp1, tmp2;
343
344 spin_lock_irqsave(&mux_spin_lock, flags);
345 reg_orig = omap_readl(cfg->mux_reg);
346
347 /* The mux registers always seem to be 3 bits long */
348 mask = (0x7 << cfg->mask_offset);
349 tmp1 = reg_orig & mask;
350 reg = reg_orig & ~mask;
351
352 tmp2 = (cfg->mask << cfg->mask_offset);
353 reg |= tmp2;
354
355 if (tmp1 != tmp2)
356 warn = 1;
357
358 omap_writel(reg, cfg->mux_reg);
359 spin_unlock_irqrestore(&mux_spin_lock, flags);
360 }
361
362 /* Check for pull up or pull down selection on 1610 */
363 if (!cpu_is_omap15xx()) {
364 if (cfg->pu_pd_reg && cfg->pull_val) {
365 spin_lock_irqsave(&mux_spin_lock, flags);
366 pu_pd_orig = omap_readl(cfg->pu_pd_reg);
367 mask = 1 << cfg->pull_bit;
368
369 if (cfg->pu_pd_val) {
370 if (!(pu_pd_orig & mask))
371 warn = 1;
372 /* Use pull up */
373 pu_pd = pu_pd_orig | mask;
374 } else {
375 if (pu_pd_orig & mask)
376 warn = 1;
377 /* Use pull down */
378 pu_pd = pu_pd_orig & ~mask;
379 }
380 omap_writel(pu_pd, cfg->pu_pd_reg);
381 spin_unlock_irqrestore(&mux_spin_lock, flags);
382 }
383 }
384
385 /* Check for an associated pull down register */
386 if (cfg->pull_reg) {
387 spin_lock_irqsave(&mux_spin_lock, flags);
388 pull_orig = omap_readl(cfg->pull_reg);
389 mask = 1 << cfg->pull_bit;
390
391 if (cfg->pull_val) {
392 if (pull_orig & mask)
393 warn = 1;
394 /* Low bit = pull enabled */
395 pull = pull_orig & ~mask;
396 } else {
397 if (!(pull_orig & mask))
398 warn = 1;
399 /* High bit = pull disabled */
400 pull = pull_orig | mask;
401 }
402
403 omap_writel(pull, cfg->pull_reg);
404 spin_unlock_irqrestore(&mux_spin_lock, flags);
405 }
406
407 if (warn) {
408#ifdef CONFIG_OMAP_MUX_WARNINGS
409 printk(KERN_WARNING "MUX: initialized %s\n", cfg->name);
410#endif
411 }
412
413#ifdef CONFIG_OMAP_MUX_DEBUG
414 if (cfg->debug || warn) {
415 printk("MUX: Setting register %s\n", cfg->name);
416 printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
417 cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
418
419 if (!cpu_is_omap15xx()) {
420 if (cfg->pu_pd_reg && cfg->pull_val) {
421 printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
422 cfg->pu_pd_name, cfg->pu_pd_reg,
423 pu_pd_orig, pu_pd);
424 }
425 }
426
427 if (cfg->pull_reg)
428 printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
429 cfg->pull_name, cfg->pull_reg, pull_orig, pull);
430 }
431#endif
432
433#ifdef CONFIG_OMAP_MUX_WARNINGS
434 return warn ? -ETXTBSY : 0;
435#else
436 return 0;
437#endif
438}
439
440static struct omap_mux_cfg *mux_cfg;
441
442int __init omap_mux_register(struct omap_mux_cfg *arch_mux_cfg)
443{
444 if (!arch_mux_cfg || !arch_mux_cfg->pins || arch_mux_cfg->size == 0
445 || !arch_mux_cfg->cfg_reg) {
446 printk(KERN_ERR "Invalid pin table\n");
447 return -EINVAL;
448 }
449
450 mux_cfg = arch_mux_cfg;
451
452 return 0;
453}
454
455/*
456 * Sets the Omap MUX and PULL_DWN registers based on the table
457 */
458int omap_cfg_reg(const unsigned long index)
459{
460 struct pin_config *reg;
461
462 if (!cpu_class_is_omap1()) {
463 printk(KERN_ERR "mux: Broken omap_cfg_reg(%lu) entry\n",
464 index);
465 WARN_ON(1);
466 return -EINVAL;
467 }
468
469 if (mux_cfg == NULL) {
470 printk(KERN_ERR "Pin mux table not initialized\n");
471 return -ENODEV;
472 }
473
474 if (index >= mux_cfg->size) {
475 printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
476 index, mux_cfg->size);
477 dump_stack();
478 return -ENODEV;
479 }
480
481 reg = &mux_cfg->pins[index];
482
483 if (!mux_cfg->cfg_reg)
484 return -ENODEV;
485
486 return mux_cfg->cfg_reg(reg);
487}
488EXPORT_SYMBOL(omap_cfg_reg);
489
490int __init omap1_mux_init(void)
491{
492 if (cpu_is_omap7xx()) {
493 arch_mux_cfg.pins = omap7xx_pins;
494 arch_mux_cfg.size = OMAP7XX_PINS_SZ;
495 arch_mux_cfg.cfg_reg = omap1_cfg_reg;
496 }
497
498 if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
499 arch_mux_cfg.pins = omap1xxx_pins;
500 arch_mux_cfg.size = OMAP1XXX_PINS_SZ;
501 arch_mux_cfg.cfg_reg = omap1_cfg_reg;
502 }
503
504 return omap_mux_register(&arch_mux_cfg);
505}
506
507#else
508#define omap_mux_init() do {} while(0)
509#define omap_cfg_reg(x) do {} while(0)
510#endif /* CONFIG_OMAP_MUX */
511