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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * linux/arch/arm/mach-omap1/clock.h
4 *
5 * Copyright (C) 2004 - 2005, 2009 Nokia corporation
6 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
7 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
8 */
9
10#ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H
11#define __ARCH_ARM_MACH_OMAP1_CLOCK_H
12
13#include <linux/clk.h>
14#include <linux/clkdev.h>
15#include <linux/clk-provider.h>
16
17struct module;
18struct omap1_clk;
19
20struct omap_clk {
21 u16 cpu;
22 struct clk_lookup lk;
23};
24
25#define CLK(dev, con, ck, cp) \
26 { \
27 .cpu = cp, \
28 .lk = { \
29 .dev_id = dev, \
30 .con_id = con, \
31 .clk_hw = ck, \
32 }, \
33 }
34
35/* Platform flags for the clkdev-OMAP integration code */
36#define CK_310 (1 << 0)
37#define CK_7XX (1 << 1) /* 7xx, 850 */
38#define CK_1510 (1 << 2)
39#define CK_16XX (1 << 3) /* 16xx, 17xx, 5912 */
40#define CK_1710 (1 << 4) /* 1710 extra for rate selection */
41
42/**
43 * struct clkops - some clock function pointers
44 * @enable: fn ptr that enables the current clock in hardware
45 * @disable: fn ptr that enables the current clock in hardware
46 * @allow_idle: fn ptr that enables autoidle for the current clock in hardware
47 */
48struct clkops {
49 int (*enable)(struct omap1_clk *clk);
50 void (*disable)(struct omap1_clk *clk);
51};
52
53/*
54 * struct clk.flags possibilities
55 *
56 * XXX document the rest of the clock flags here
57 */
58#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */
59#define CLOCK_IDLE_CONTROL (1 << 1)
60#define CLOCK_NO_IDLE_PARENT (1 << 2)
61
62/**
63 * struct omap1_clk - OMAP1 struct clk
64 * @hw: struct clk_hw for common clock framework integration
65 * @ops: struct clkops * for this clock
66 * @rate: current clock rate
67 * @enable_reg: register to write to enable the clock (see @enable_bit)
68 * @recalc: fn ptr that returns the clock's current rate
69 * @set_rate: fn ptr that can change the clock's current rate
70 * @round_rate: fn ptr that can round the clock's current rate
71 * @init: fn ptr to do clock-specific initialization
72 * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
73 * @fixed_div: when > 0, this clock's rate is its parent's rate / @fixed_div
74 * @flags: see "struct clk.flags possibilities" above
75 * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
76 */
77struct omap1_clk {
78 struct clk_hw hw;
79 const struct clkops *ops;
80 unsigned long rate;
81 void __iomem *enable_reg;
82 unsigned long (*recalc)(struct omap1_clk *clk, unsigned long rate);
83 int (*set_rate)(struct omap1_clk *clk, unsigned long rate,
84 unsigned long p_rate);
85 long (*round_rate)(struct omap1_clk *clk, unsigned long rate,
86 unsigned long *p_rate);
87 int (*init)(struct omap1_clk *clk);
88 u8 enable_bit;
89 u8 fixed_div;
90 u8 flags;
91 u8 rate_offset;
92};
93#define to_omap1_clk(_hw) container_of(_hw, struct omap1_clk, hw)
94
95void propagate_rate(struct omap1_clk *clk);
96unsigned long followparent_recalc(struct omap1_clk *clk, unsigned long p_rate);
97unsigned long omap_fixed_divisor_recalc(struct omap1_clk *clk, unsigned long p_rate);
98
99extern struct omap1_clk dummy_ck;
100
101int omap1_clk_init(void);
102void omap1_clk_late_init(void);
103unsigned long omap1_ckctl_recalc(struct omap1_clk *clk, unsigned long p_rate);
104long omap1_round_sossi_rate(struct omap1_clk *clk, unsigned long rate, unsigned long *p_rate);
105int omap1_set_sossi_rate(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate);
106unsigned long omap1_sossi_recalc(struct omap1_clk *clk, unsigned long p_rate);
107unsigned long omap1_ckctl_recalc_dsp_domain(struct omap1_clk *clk, unsigned long p_rate);
108int omap1_clk_set_rate_dsp_domain(struct omap1_clk *clk, unsigned long rate,
109 unsigned long p_rate);
110long omap1_round_uart_rate(struct omap1_clk *clk, unsigned long rate, unsigned long *p_rate);
111int omap1_set_uart_rate(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate);
112unsigned long omap1_uart_recalc(struct omap1_clk *clk, unsigned long p_rate);
113int omap1_set_ext_clk_rate(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate);
114long omap1_round_ext_clk_rate(struct omap1_clk *clk, unsigned long rate, unsigned long *p_rate);
115int omap1_init_ext_clk(struct omap1_clk *clk);
116int omap1_select_table_rate(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate);
117long omap1_round_to_table_rate(struct omap1_clk *clk, unsigned long rate, unsigned long *p_rate);
118int omap1_clk_set_rate_ckctl_arm(struct omap1_clk *clk, unsigned long rate, unsigned long p_rate);
119long omap1_clk_round_rate_ckctl_arm(struct omap1_clk *clk, unsigned long rate,
120 unsigned long *p_rate);
121
122struct uart_clk {
123 struct omap1_clk clk;
124 unsigned long sysc_addr;
125};
126
127/* Provide a method for preventing idling some ARM IDLECT clocks */
128struct arm_idlect1_clk {
129 struct omap1_clk clk;
130 unsigned long no_idle_count;
131 __u8 idlect_shift;
132};
133
134/* ARM_CKCTL bit shifts */
135#define CKCTL_PERDIV_OFFSET 0
136#define CKCTL_LCDDIV_OFFSET 2
137#define CKCTL_ARMDIV_OFFSET 4
138#define CKCTL_DSPDIV_OFFSET 6
139#define CKCTL_TCDIV_OFFSET 8
140#define CKCTL_DSPMMUDIV_OFFSET 10
141/*#define ARM_TIMXO 12*/
142#define EN_DSPCK 13
143/*#define ARM_INTHCK_SEL 14*/ /* Divide-by-2 for mpu inth_ck */
144/* DSP_CKCTL bit shifts */
145#define CKCTL_DSPPERDIV_OFFSET 0
146
147/* ARM_IDLECT2 bit shifts */
148#define EN_WDTCK 0
149#define EN_XORPCK 1
150#define EN_PERCK 2
151#define EN_LCDCK 3
152#define EN_LBCK 4 /* Not on 1610/1710 */
153/*#define EN_HSABCK 5*/
154#define EN_APICK 6
155#define EN_TIMCK 7
156#define DMACK_REQ 8
157#define EN_GPIOCK 9 /* Not on 1610/1710 */
158/*#define EN_LBFREECK 10*/
159#define EN_CKOUT_ARM 11
160
161/* ARM_IDLECT3 bit shifts */
162#define EN_OCPI_CK 0
163#define EN_TC1_CK 2
164#define EN_TC2_CK 4
165
166/* DSP_IDLECT2 bit shifts (0,1,2 are same as for ARM_IDLECT2) */
167#define EN_DSPTIMCK 5
168
169/* Various register defines for clock controls scattered around OMAP chip */
170#define SDW_MCLK_INV_BIT 2 /* In ULPD_CLKC_CTRL */
171#define USB_MCLK_EN_BIT 4 /* In ULPD_CLKC_CTRL */
172#define USB_HOST_HHC_UHOST_EN 9 /* In MOD_CONF_CTRL_0 */
173#define SWD_ULPD_PLL_CLK_REQ 1 /* In SWD_CLK_DIV_CTRL_SEL */
174#define COM_ULPD_PLL_CLK_REQ 1 /* In COM_CLK_DIV_CTRL_SEL */
175#define SWD_CLK_DIV_CTRL_SEL 0xfffe0874
176#define COM_CLK_DIV_CTRL_SEL 0xfffe0878
177#define SOFT_REQ_REG 0xfffe0834
178#define SOFT_REQ_REG2 0xfffe0880
179
180extern __u32 arm_idlect1_mask;
181extern struct omap1_clk *api_ck_p, *ck_dpll1_p, *ck_ref_p;
182
183extern const struct clkops clkops_dspck;
184extern const struct clkops clkops_uart_16xx;
185extern const struct clkops clkops_generic;
186
187/* used for passing SoC type to omap1_{select,round_to}_table_rate() */
188extern u32 cpu_mask;
189
190extern const struct clk_ops omap1_clk_null_ops;
191extern const struct clk_ops omap1_clk_gate_ops;
192extern const struct clk_ops omap1_clk_rate_ops;
193extern const struct clk_ops omap1_clk_full_ops;
194
195#endif
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * linux/arch/arm/mach-omap1/clock.h
4 *
5 * Copyright (C) 2004 - 2005, 2009 Nokia corporation
6 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
7 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
8 */
9
10#ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H
11#define __ARCH_ARM_MACH_OMAP1_CLOCK_H
12
13#include <linux/clk.h>
14#include <linux/list.h>
15
16#include <linux/clkdev.h>
17
18struct module;
19struct clk;
20
21struct omap_clk {
22 u16 cpu;
23 struct clk_lookup lk;
24};
25
26#define CLK(dev, con, ck, cp) \
27 { \
28 .cpu = cp, \
29 .lk = { \
30 .dev_id = dev, \
31 .con_id = con, \
32 .clk = ck, \
33 }, \
34 }
35
36/* Platform flags for the clkdev-OMAP integration code */
37#define CK_310 (1 << 0)
38#define CK_7XX (1 << 1) /* 7xx, 850 */
39#define CK_1510 (1 << 2)
40#define CK_16XX (1 << 3) /* 16xx, 17xx, 5912 */
41#define CK_1710 (1 << 4) /* 1710 extra for rate selection */
42
43
44/* Temporary, needed during the common clock framework conversion */
45#define __clk_get_name(clk) (clk->name)
46#define __clk_get_parent(clk) (clk->parent)
47#define __clk_get_rate(clk) (clk->rate)
48
49/**
50 * struct clkops - some clock function pointers
51 * @enable: fn ptr that enables the current clock in hardware
52 * @disable: fn ptr that enables the current clock in hardware
53 * @find_idlest: function returning the IDLEST register for the clock's IP blk
54 * @find_companion: function returning the "companion" clk reg for the clock
55 * @allow_idle: fn ptr that enables autoidle for the current clock in hardware
56 * @deny_idle: fn ptr that disables autoidle for the current clock in hardware
57 *
58 * A "companion" clk is an accompanying clock to the one being queried
59 * that must be enabled for the IP module connected to the clock to
60 * become accessible by the hardware. Neither @find_idlest nor
61 * @find_companion should be needed; that information is IP
62 * block-specific; the hwmod code has been created to handle this, but
63 * until hwmod data is ready and drivers have been converted to use PM
64 * runtime calls in place of clk_enable()/clk_disable(), @find_idlest and
65 * @find_companion must, unfortunately, remain.
66 */
67struct clkops {
68 int (*enable)(struct clk *);
69 void (*disable)(struct clk *);
70 void (*find_idlest)(struct clk *, void __iomem **,
71 u8 *, u8 *);
72 void (*find_companion)(struct clk *, void __iomem **,
73 u8 *);
74 void (*allow_idle)(struct clk *);
75 void (*deny_idle)(struct clk *);
76};
77
78/*
79 * struct clk.flags possibilities
80 *
81 * XXX document the rest of the clock flags here
82 *
83 * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
84 * bits share the same register. This flag allows the
85 * omap4_dpllmx*() code to determine which GATE_CTRL bit field
86 * should be used. This is a temporary solution - a better approach
87 * would be to associate clock type-specific data with the clock,
88 * similar to the struct dpll_data approach.
89 */
90#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */
91#define CLOCK_IDLE_CONTROL (1 << 1)
92#define CLOCK_NO_IDLE_PARENT (1 << 2)
93#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */
94#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */
95#define CLOCK_CLKOUTX2 (1 << 5)
96
97/**
98 * struct clk - OMAP struct clk
99 * @node: list_head connecting this clock into the full clock list
100 * @ops: struct clkops * for this clock
101 * @name: the name of the clock in the hardware (used in hwmod data and debug)
102 * @parent: pointer to this clock's parent struct clk
103 * @children: list_head connecting to the child clks' @sibling list_heads
104 * @sibling: list_head connecting this clk to its parent clk's @children
105 * @rate: current clock rate
106 * @enable_reg: register to write to enable the clock (see @enable_bit)
107 * @recalc: fn ptr that returns the clock's current rate
108 * @set_rate: fn ptr that can change the clock's current rate
109 * @round_rate: fn ptr that can round the clock's current rate
110 * @init: fn ptr to do clock-specific initialization
111 * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
112 * @usecount: number of users that have requested this clock to be enabled
113 * @fixed_div: when > 0, this clock's rate is its parent's rate / @fixed_div
114 * @flags: see "struct clk.flags possibilities" above
115 * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
116 * @src_offset: bitshift for source selection bitfield (OMAP1 only)
117 *
118 * XXX @rate_offset, @src_offset should probably be removed and OMAP1
119 * clock code converted to use clksel.
120 *
121 * XXX @usecount is poorly named. It should be "enable_count" or
122 * something similar. "users" in the description refers to kernel
123 * code (core code or drivers) that have called clk_enable() and not
124 * yet called clk_disable(); the usecount of parent clocks is also
125 * incremented by the clock code when clk_enable() is called on child
126 * clocks and decremented by the clock code when clk_disable() is
127 * called on child clocks.
128 *
129 * XXX @clkdm, @usecount, @children, @sibling should be marked for
130 * internal use only.
131 *
132 * @children and @sibling are used to optimize parent-to-child clock
133 * tree traversals. (child-to-parent traversals use @parent.)
134 *
135 * XXX The notion of the clock's current rate probably needs to be
136 * separated from the clock's target rate.
137 */
138struct clk {
139 struct list_head node;
140 const struct clkops *ops;
141 const char *name;
142 struct clk *parent;
143 struct list_head children;
144 struct list_head sibling; /* node for children */
145 unsigned long rate;
146 void __iomem *enable_reg;
147 unsigned long (*recalc)(struct clk *);
148 int (*set_rate)(struct clk *, unsigned long);
149 long (*round_rate)(struct clk *, unsigned long);
150 void (*init)(struct clk *);
151 u8 enable_bit;
152 s8 usecount;
153 u8 fixed_div;
154 u8 flags;
155 u8 rate_offset;
156 u8 src_offset;
157#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
158 struct dentry *dent; /* For visible tree hierarchy */
159#endif
160};
161
162struct clk_functions {
163 int (*clk_enable)(struct clk *clk);
164 void (*clk_disable)(struct clk *clk);
165 long (*clk_round_rate)(struct clk *clk, unsigned long rate);
166 int (*clk_set_rate)(struct clk *clk, unsigned long rate);
167 int (*clk_set_parent)(struct clk *clk, struct clk *parent);
168 void (*clk_allow_idle)(struct clk *clk);
169 void (*clk_deny_idle)(struct clk *clk);
170 void (*clk_disable_unused)(struct clk *clk);
171};
172
173extern int clk_init(struct clk_functions *custom_clocks);
174extern void clk_preinit(struct clk *clk);
175extern int clk_register(struct clk *clk);
176extern void clk_reparent(struct clk *child, struct clk *parent);
177extern void clk_unregister(struct clk *clk);
178extern void propagate_rate(struct clk *clk);
179extern void recalculate_root_clocks(void);
180extern unsigned long followparent_recalc(struct clk *clk);
181extern void clk_enable_init_clocks(void);
182unsigned long omap_fixed_divisor_recalc(struct clk *clk);
183extern struct clk *omap_clk_get_by_name(const char *name);
184extern int omap_clk_enable_autoidle_all(void);
185extern int omap_clk_disable_autoidle_all(void);
186
187extern const struct clkops clkops_null;
188
189extern struct clk dummy_ck;
190
191int omap1_clk_init(void);
192void omap1_clk_late_init(void);
193extern int omap1_clk_enable(struct clk *clk);
194extern void omap1_clk_disable(struct clk *clk);
195extern long omap1_clk_round_rate(struct clk *clk, unsigned long rate);
196extern int omap1_clk_set_rate(struct clk *clk, unsigned long rate);
197extern unsigned long omap1_ckctl_recalc(struct clk *clk);
198extern int omap1_set_sossi_rate(struct clk *clk, unsigned long rate);
199extern unsigned long omap1_sossi_recalc(struct clk *clk);
200extern unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk);
201extern int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate);
202extern int omap1_set_uart_rate(struct clk *clk, unsigned long rate);
203extern unsigned long omap1_uart_recalc(struct clk *clk);
204extern int omap1_set_ext_clk_rate(struct clk *clk, unsigned long rate);
205extern long omap1_round_ext_clk_rate(struct clk *clk, unsigned long rate);
206extern void omap1_init_ext_clk(struct clk *clk);
207extern int omap1_select_table_rate(struct clk *clk, unsigned long rate);
208extern long omap1_round_to_table_rate(struct clk *clk, unsigned long rate);
209extern int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate);
210extern long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate);
211extern unsigned long omap1_watchdog_recalc(struct clk *clk);
212
213#ifdef CONFIG_OMAP_RESET_CLOCKS
214extern void omap1_clk_disable_unused(struct clk *clk);
215#else
216#define omap1_clk_disable_unused NULL
217#endif
218
219struct uart_clk {
220 struct clk clk;
221 unsigned long sysc_addr;
222};
223
224/* Provide a method for preventing idling some ARM IDLECT clocks */
225struct arm_idlect1_clk {
226 struct clk clk;
227 unsigned long no_idle_count;
228 __u8 idlect_shift;
229};
230
231/* ARM_CKCTL bit shifts */
232#define CKCTL_PERDIV_OFFSET 0
233#define CKCTL_LCDDIV_OFFSET 2
234#define CKCTL_ARMDIV_OFFSET 4
235#define CKCTL_DSPDIV_OFFSET 6
236#define CKCTL_TCDIV_OFFSET 8
237#define CKCTL_DSPMMUDIV_OFFSET 10
238/*#define ARM_TIMXO 12*/
239#define EN_DSPCK 13
240/*#define ARM_INTHCK_SEL 14*/ /* Divide-by-2 for mpu inth_ck */
241/* DSP_CKCTL bit shifts */
242#define CKCTL_DSPPERDIV_OFFSET 0
243
244/* ARM_IDLECT2 bit shifts */
245#define EN_WDTCK 0
246#define EN_XORPCK 1
247#define EN_PERCK 2
248#define EN_LCDCK 3
249#define EN_LBCK 4 /* Not on 1610/1710 */
250/*#define EN_HSABCK 5*/
251#define EN_APICK 6
252#define EN_TIMCK 7
253#define DMACK_REQ 8
254#define EN_GPIOCK 9 /* Not on 1610/1710 */
255/*#define EN_LBFREECK 10*/
256#define EN_CKOUT_ARM 11
257
258/* ARM_IDLECT3 bit shifts */
259#define EN_OCPI_CK 0
260#define EN_TC1_CK 2
261#define EN_TC2_CK 4
262
263/* DSP_IDLECT2 bit shifts (0,1,2 are same as for ARM_IDLECT2) */
264#define EN_DSPTIMCK 5
265
266/* Various register defines for clock controls scattered around OMAP chip */
267#define SDW_MCLK_INV_BIT 2 /* In ULPD_CLKC_CTRL */
268#define USB_MCLK_EN_BIT 4 /* In ULPD_CLKC_CTRL */
269#define USB_HOST_HHC_UHOST_EN 9 /* In MOD_CONF_CTRL_0 */
270#define SWD_ULPD_PLL_CLK_REQ 1 /* In SWD_CLK_DIV_CTRL_SEL */
271#define COM_ULPD_PLL_CLK_REQ 1 /* In COM_CLK_DIV_CTRL_SEL */
272#define SWD_CLK_DIV_CTRL_SEL 0xfffe0874
273#define COM_CLK_DIV_CTRL_SEL 0xfffe0878
274#define SOFT_REQ_REG 0xfffe0834
275#define SOFT_REQ_REG2 0xfffe0880
276
277extern __u32 arm_idlect1_mask;
278extern struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p;
279
280extern const struct clkops clkops_dspck;
281extern const struct clkops clkops_dummy;
282extern const struct clkops clkops_uart_16xx;
283extern const struct clkops clkops_generic;
284
285/* used for passing SoC type to omap1_{select,round_to}_table_rate() */
286extern u32 cpu_mask;
287
288#endif