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1/*
2 * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43#include <dt-bindings/interrupt-controller/arm-gic.h>
44#include <dt-bindings/clock/sun8i-v3s-ccu.h>
45#include <dt-bindings/reset/sun8i-v3s-ccu.h>
46
47/ {
48 #address-cells = <1>;
49 #size-cells = <1>;
50 interrupt-parent = <&gic>;
51
52 cpus {
53 #address-cells = <1>;
54 #size-cells = <0>;
55
56 cpu@0 {
57 compatible = "arm,cortex-a7";
58 device_type = "cpu";
59 reg = <0>;
60 clocks = <&ccu CLK_CPU>;
61 };
62 };
63
64 de: display-engine {
65 compatible = "allwinner,sun8i-v3s-display-engine";
66 allwinner,pipelines = <&mixer0>;
67 status = "disabled";
68 };
69
70 timer {
71 compatible = "arm,armv7-timer";
72 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
73 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
74 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
75 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
76 };
77
78 clocks {
79 #address-cells = <1>;
80 #size-cells = <1>;
81 ranges;
82
83 osc24M: osc24M_clk {
84 #clock-cells = <0>;
85 compatible = "fixed-clock";
86 clock-frequency = <24000000>;
87 clock-accuracy = <50000>;
88 clock-output-names = "osc24M";
89 };
90
91 osc32k: osc32k_clk {
92 #clock-cells = <0>;
93 compatible = "fixed-clock";
94 clock-frequency = <32768>;
95 clock-accuracy = <50000>;
96 clock-output-names = "ext-osc32k";
97 };
98 };
99
100 soc {
101 compatible = "simple-bus";
102 #address-cells = <1>;
103 #size-cells = <1>;
104 ranges;
105
106 display_clocks: clock@1000000 {
107 compatible = "allwinner,sun8i-v3s-de2-clk";
108 reg = <0x01000000 0x10000>;
109 clocks = <&ccu CLK_BUS_DE>,
110 <&ccu CLK_DE>;
111 clock-names = "bus",
112 "mod";
113 resets = <&ccu RST_BUS_DE>;
114 #clock-cells = <1>;
115 #reset-cells = <1>;
116 };
117
118 mixer0: mixer@1100000 {
119 compatible = "allwinner,sun8i-v3s-de2-mixer";
120 reg = <0x01100000 0x100000>;
121 clocks = <&display_clocks 0>,
122 <&display_clocks 6>;
123 clock-names = "bus",
124 "mod";
125 resets = <&display_clocks 0>;
126
127 ports {
128 #address-cells = <1>;
129 #size-cells = <0>;
130
131 mixer0_out: port@1 {
132 reg = <1>;
133
134 mixer0_out_tcon0: endpoint {
135 remote-endpoint = <&tcon0_in_mixer0>;
136 };
137 };
138 };
139 };
140
141 tcon0: lcd-controller@1c0c000 {
142 compatible = "allwinner,sun8i-v3s-tcon";
143 reg = <0x01c0c000 0x1000>;
144 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
145 clocks = <&ccu CLK_BUS_TCON0>,
146 <&ccu CLK_TCON0>;
147 clock-names = "ahb",
148 "tcon-ch0";
149 clock-output-names = "tcon-pixel-clock";
150 #clock-cells = <0>;
151 resets = <&ccu RST_BUS_TCON0>;
152 reset-names = "lcd";
153 status = "disabled";
154
155 ports {
156 #address-cells = <1>;
157 #size-cells = <0>;
158
159 tcon0_in: port@0 {
160 reg = <0>;
161
162 tcon0_in_mixer0: endpoint {
163 remote-endpoint = <&mixer0_out_tcon0>;
164 };
165 };
166
167 tcon0_out: port@1 {
168 #address-cells = <1>;
169 #size-cells = <0>;
170 reg = <1>;
171 };
172 };
173 };
174
175
176 mmc0: mmc@1c0f000 {
177 compatible = "allwinner,sun7i-a20-mmc";
178 reg = <0x01c0f000 0x1000>;
179 clocks = <&ccu CLK_BUS_MMC0>,
180 <&ccu CLK_MMC0>,
181 <&ccu CLK_MMC0_OUTPUT>,
182 <&ccu CLK_MMC0_SAMPLE>;
183 clock-names = "ahb",
184 "mmc",
185 "output",
186 "sample";
187 resets = <&ccu RST_BUS_MMC0>;
188 reset-names = "ahb";
189 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
190 pinctrl-names = "default";
191 pinctrl-0 = <&mmc0_pins>;
192 status = "disabled";
193 #address-cells = <1>;
194 #size-cells = <0>;
195 };
196
197 mmc1: mmc@1c10000 {
198 compatible = "allwinner,sun7i-a20-mmc";
199 reg = <0x01c10000 0x1000>;
200 clocks = <&ccu CLK_BUS_MMC1>,
201 <&ccu CLK_MMC1>,
202 <&ccu CLK_MMC1_OUTPUT>,
203 <&ccu CLK_MMC1_SAMPLE>;
204 clock-names = "ahb",
205 "mmc",
206 "output",
207 "sample";
208 resets = <&ccu RST_BUS_MMC1>;
209 reset-names = "ahb";
210 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
211 pinctrl-names = "default";
212 pinctrl-0 = <&mmc1_pins>;
213 status = "disabled";
214 #address-cells = <1>;
215 #size-cells = <0>;
216 };
217
218 mmc2: mmc@1c11000 {
219 compatible = "allwinner,sun7i-a20-mmc";
220 reg = <0x01c11000 0x1000>;
221 clocks = <&ccu CLK_BUS_MMC2>,
222 <&ccu CLK_MMC2>,
223 <&ccu CLK_MMC2_OUTPUT>,
224 <&ccu CLK_MMC2_SAMPLE>;
225 clock-names = "ahb",
226 "mmc",
227 "output",
228 "sample";
229 resets = <&ccu RST_BUS_MMC2>;
230 reset-names = "ahb";
231 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
232 status = "disabled";
233 #address-cells = <1>;
234 #size-cells = <0>;
235 };
236
237 usb_otg: usb@1c19000 {
238 compatible = "allwinner,sun8i-h3-musb";
239 reg = <0x01c19000 0x0400>;
240 clocks = <&ccu CLK_BUS_OTG>;
241 resets = <&ccu RST_BUS_OTG>;
242 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
243 interrupt-names = "mc";
244 phys = <&usbphy 0>;
245 phy-names = "usb";
246 extcon = <&usbphy 0>;
247 status = "disabled";
248 };
249
250 usbphy: phy@1c19400 {
251 compatible = "allwinner,sun8i-v3s-usb-phy";
252 reg = <0x01c19400 0x2c>,
253 <0x01c1a800 0x4>;
254 reg-names = "phy_ctrl",
255 "pmu0";
256 clocks = <&ccu CLK_USB_PHY0>;
257 clock-names = "usb0_phy";
258 resets = <&ccu RST_USB_PHY0>;
259 reset-names = "usb0_reset";
260 status = "disabled";
261 #phy-cells = <1>;
262 };
263
264 ccu: clock@1c20000 {
265 compatible = "allwinner,sun8i-v3s-ccu";
266 reg = <0x01c20000 0x400>;
267 clocks = <&osc24M>, <&rtc 0>;
268 clock-names = "hosc", "losc";
269 #clock-cells = <1>;
270 #reset-cells = <1>;
271 };
272
273 rtc: rtc@1c20400 {
274 #clock-cells = <1>;
275 compatible = "allwinner,sun8i-v3-rtc";
276 reg = <0x01c20400 0x54>;
277 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
278 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&osc32k>;
280 clock-output-names = "osc32k", "osc32k-out";
281 };
282
283 pio: pinctrl@1c20800 {
284 compatible = "allwinner,sun8i-v3s-pinctrl";
285 reg = <0x01c20800 0x400>;
286 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
287 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
289 clock-names = "apb", "hosc", "losc";
290 gpio-controller;
291 #gpio-cells = <3>;
292 interrupt-controller;
293 #interrupt-cells = <3>;
294
295 i2c0_pins: i2c0-pins {
296 pins = "PB6", "PB7";
297 function = "i2c0";
298 };
299
300 uart0_pb_pins: uart0-pb-pins {
301 pins = "PB8", "PB9";
302 function = "uart0";
303 };
304
305 mmc0_pins: mmc0-pins {
306 pins = "PF0", "PF1", "PF2", "PF3",
307 "PF4", "PF5";
308 function = "mmc0";
309 drive-strength = <30>;
310 bias-pull-up;
311 };
312
313 mmc1_pins: mmc1-pins {
314 pins = "PG0", "PG1", "PG2", "PG3",
315 "PG4", "PG5";
316 function = "mmc1";
317 drive-strength = <30>;
318 bias-pull-up;
319 };
320
321 spi0_pins: spi0-pins {
322 pins = "PC0", "PC1", "PC2", "PC3";
323 function = "spi0";
324 };
325 };
326
327 timer@1c20c00 {
328 compatible = "allwinner,sun8i-v3s-timer";
329 reg = <0x01c20c00 0xa0>;
330 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
331 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
332 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
333 clocks = <&osc24M>;
334 };
335
336 wdt0: watchdog@1c20ca0 {
337 compatible = "allwinner,sun6i-a31-wdt";
338 reg = <0x01c20ca0 0x20>;
339 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
340 clocks = <&osc24M>;
341 };
342
343 lradc: lradc@1c22800 {
344 compatible = "allwinner,sun4i-a10-lradc-keys";
345 reg = <0x01c22800 0x400>;
346 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
347 status = "disabled";
348 };
349
350 uart0: serial@1c28000 {
351 compatible = "snps,dw-apb-uart";
352 reg = <0x01c28000 0x400>;
353 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
354 reg-shift = <2>;
355 reg-io-width = <4>;
356 clocks = <&ccu CLK_BUS_UART0>;
357 resets = <&ccu RST_BUS_UART0>;
358 status = "disabled";
359 };
360
361 uart1: serial@1c28400 {
362 compatible = "snps,dw-apb-uart";
363 reg = <0x01c28400 0x400>;
364 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
365 reg-shift = <2>;
366 reg-io-width = <4>;
367 clocks = <&ccu CLK_BUS_UART1>;
368 resets = <&ccu RST_BUS_UART1>;
369 status = "disabled";
370 };
371
372 uart2: serial@1c28800 {
373 compatible = "snps,dw-apb-uart";
374 reg = <0x01c28800 0x400>;
375 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
376 reg-shift = <2>;
377 reg-io-width = <4>;
378 clocks = <&ccu CLK_BUS_UART2>;
379 resets = <&ccu RST_BUS_UART2>;
380 status = "disabled";
381 };
382
383 i2c0: i2c@1c2ac00 {
384 compatible = "allwinner,sun6i-a31-i2c";
385 reg = <0x01c2ac00 0x400>;
386 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&ccu CLK_BUS_I2C0>;
388 resets = <&ccu RST_BUS_I2C0>;
389 pinctrl-names = "default";
390 pinctrl-0 = <&i2c0_pins>;
391 status = "disabled";
392 #address-cells = <1>;
393 #size-cells = <0>;
394 };
395
396 i2c1: i2c@1c2b000 {
397 compatible = "allwinner,sun6i-a31-i2c";
398 reg = <0x01c2b000 0x400>;
399 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
400 clocks = <&ccu CLK_BUS_I2C1>;
401 resets = <&ccu RST_BUS_I2C1>;
402 status = "disabled";
403 #address-cells = <1>;
404 #size-cells = <0>;
405 };
406
407 spi0: spi@1c68000 {
408 compatible = "allwinner,sun8i-h3-spi";
409 reg = <0x01c68000 0x1000>;
410 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
411 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
412 clock-names = "ahb", "mod";
413 pinctrl-names = "default";
414 pinctrl-0 = <&spi0_pins>;
415 resets = <&ccu RST_BUS_SPI0>;
416 status = "disabled";
417 #address-cells = <1>;
418 #size-cells = <0>;
419 };
420
421 gic: interrupt-controller@1c81000 {
422 compatible = "arm,gic-400";
423 reg = <0x01c81000 0x1000>,
424 <0x01c82000 0x1000>,
425 <0x01c84000 0x2000>,
426 <0x01c86000 0x2000>;
427 interrupt-controller;
428 #interrupt-cells = <3>;
429 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
430 };
431 };
432};