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1// SPDX-License-Identifier: GPL-2.0
2//
3// rt700-sdw.c -- rt700 ALSA SoC audio driver
4//
5// Copyright(c) 2019 Realtek Semiconductor Corp.
6//
7//
8
9#include <linux/delay.h>
10#include <linux/device.h>
11#include <linux/mod_devicetable.h>
12#include <linux/soundwire/sdw.h>
13#include <linux/soundwire/sdw_type.h>
14#include <linux/soundwire/sdw_registers.h>
15#include <linux/module.h>
16#include <linux/pm_runtime.h>
17#include <linux/regmap.h>
18#include <sound/soc.h>
19#include "rt700.h"
20#include "rt700-sdw.h"
21
22static bool rt700_readable_register(struct device *dev, unsigned int reg)
23{
24 switch (reg) {
25 case 0x00e0:
26 case 0x00f0:
27 case 0x2000 ... 0x200e:
28 case 0x2012 ... 0x2016:
29 case 0x201a ... 0x2027:
30 case 0x2029 ... 0x202a:
31 case 0x202d ... 0x2034:
32 case 0x2200 ... 0x2204:
33 case 0x2206 ... 0x2212:
34 case 0x2220 ... 0x2223:
35 case 0x2230 ... 0x2231:
36 case 0x3000 ... 0x3fff:
37 case 0x7000 ... 0x7fff:
38 case 0x8300 ... 0x83ff:
39 case 0x9c00 ... 0x9cff:
40 case 0xb900 ... 0xb9ff:
41 case 0x75201a:
42 case 0x752045:
43 case 0x752046:
44 case 0x752048:
45 case 0x75204a:
46 case 0x75206b:
47 case 0x752080:
48 case 0x752081:
49 return true;
50 default:
51 return false;
52 }
53}
54
55static bool rt700_volatile_register(struct device *dev, unsigned int reg)
56{
57 switch (reg) {
58 case 0x2009:
59 case 0x2016:
60 case 0x201b:
61 case 0x201c:
62 case 0x201d:
63 case 0x201f:
64 case 0x2021:
65 case 0x2023:
66 case 0x2230:
67 case 0x200b ... 0x200e: /* i2c read */
68 case 0x2012 ... 0x2015: /* HD-A read */
69 case 0x202d ... 0x202f: /* BRA */
70 case 0x2201 ... 0x2212: /* i2c debug */
71 case 0x2220 ... 0x2223: /* decoded HD-A */
72 case 0x9c00 ... 0x9cff:
73 case 0xb900 ... 0xb9ff:
74 case 0xff01:
75 case 0x75201a:
76 case 0x752046:
77 case 0x752080:
78 case 0x752081:
79 return true;
80 default:
81 return false;
82 }
83}
84
85static int rt700_sdw_read(void *context, unsigned int reg, unsigned int *val)
86{
87 struct device *dev = context;
88 struct rt700_priv *rt700 = dev_get_drvdata(dev);
89 unsigned int sdw_data_3, sdw_data_2, sdw_data_1, sdw_data_0;
90 unsigned int reg2 = 0, reg3 = 0, reg4 = 0, mask, nid, val2;
91 unsigned int is_hda_reg = 1, is_index_reg = 0;
92 int ret;
93
94 if (reg > 0xffff)
95 is_index_reg = 1;
96
97 mask = reg & 0xf000;
98
99 if (is_index_reg) { /* index registers */
100 val2 = reg & 0xff;
101 reg = reg >> 8;
102 nid = reg & 0xff;
103 ret = regmap_write(rt700->sdw_regmap, reg, 0);
104 if (ret < 0)
105 return ret;
106 reg2 = reg + 0x1000;
107 reg2 |= 0x80;
108 ret = regmap_write(rt700->sdw_regmap, reg2, val2);
109 if (ret < 0)
110 return ret;
111
112 reg3 = RT700_PRIV_DATA_R_H | nid;
113 ret = regmap_write(rt700->sdw_regmap,
114 reg3, ((*val >> 8) & 0xff));
115 if (ret < 0)
116 return ret;
117 reg4 = reg3 + 0x1000;
118 reg4 |= 0x80;
119 ret = regmap_write(rt700->sdw_regmap, reg4, (*val & 0xff));
120 if (ret < 0)
121 return ret;
122 } else if (mask == 0x3000) {
123 reg += 0x8000;
124 ret = regmap_write(rt700->sdw_regmap, reg, *val);
125 if (ret < 0)
126 return ret;
127 } else if (mask == 0x7000) {
128 reg += 0x2000;
129 reg |= 0x800;
130 ret = regmap_write(rt700->sdw_regmap,
131 reg, ((*val >> 8) & 0xff));
132 if (ret < 0)
133 return ret;
134 reg2 = reg + 0x1000;
135 reg2 |= 0x80;
136 ret = regmap_write(rt700->sdw_regmap, reg2, (*val & 0xff));
137 if (ret < 0)
138 return ret;
139 } else if ((reg & 0xff00) == 0x8300) { /* for R channel */
140 reg2 = reg - 0x1000;
141 reg2 &= ~0x80;
142 ret = regmap_write(rt700->sdw_regmap,
143 reg2, ((*val >> 8) & 0xff));
144 if (ret < 0)
145 return ret;
146 ret = regmap_write(rt700->sdw_regmap, reg, (*val & 0xff));
147 if (ret < 0)
148 return ret;
149 } else if (mask == 0x9000) {
150 ret = regmap_write(rt700->sdw_regmap,
151 reg, ((*val >> 8) & 0xff));
152 if (ret < 0)
153 return ret;
154 reg2 = reg + 0x1000;
155 reg2 |= 0x80;
156 ret = regmap_write(rt700->sdw_regmap, reg2, (*val & 0xff));
157 if (ret < 0)
158 return ret;
159 } else if (mask == 0xb000) {
160 ret = regmap_write(rt700->sdw_regmap, reg, *val);
161 if (ret < 0)
162 return ret;
163 } else {
164 ret = regmap_read(rt700->sdw_regmap, reg, val);
165 if (ret < 0)
166 return ret;
167 is_hda_reg = 0;
168 }
169
170 if (is_hda_reg || is_index_reg) {
171 sdw_data_3 = 0;
172 sdw_data_2 = 0;
173 sdw_data_1 = 0;
174 sdw_data_0 = 0;
175 ret = regmap_read(rt700->sdw_regmap,
176 RT700_READ_HDA_3, &sdw_data_3);
177 if (ret < 0)
178 return ret;
179 ret = regmap_read(rt700->sdw_regmap,
180 RT700_READ_HDA_2, &sdw_data_2);
181 if (ret < 0)
182 return ret;
183 ret = regmap_read(rt700->sdw_regmap,
184 RT700_READ_HDA_1, &sdw_data_1);
185 if (ret < 0)
186 return ret;
187 ret = regmap_read(rt700->sdw_regmap,
188 RT700_READ_HDA_0, &sdw_data_0);
189 if (ret < 0)
190 return ret;
191 *val = ((sdw_data_3 & 0xff) << 24) |
192 ((sdw_data_2 & 0xff) << 16) |
193 ((sdw_data_1 & 0xff) << 8) | (sdw_data_0 & 0xff);
194 }
195
196 if (is_hda_reg == 0)
197 dev_dbg(dev, "[%s] %04x => %08x\n", __func__, reg, *val);
198 else if (is_index_reg)
199 dev_dbg(dev, "[%s] %04x %04x %04x %04x => %08x\n",
200 __func__, reg, reg2, reg3, reg4, *val);
201 else
202 dev_dbg(dev, "[%s] %04x %04x => %08x\n",
203 __func__, reg, reg2, *val);
204
205 return 0;
206}
207
208static int rt700_sdw_write(void *context, unsigned int reg, unsigned int val)
209{
210 struct device *dev = context;
211 struct rt700_priv *rt700 = dev_get_drvdata(dev);
212 unsigned int reg2 = 0, reg3, reg4, nid, mask, val2;
213 unsigned int is_index_reg = 0;
214 int ret;
215
216 if (reg > 0xffff)
217 is_index_reg = 1;
218
219 mask = reg & 0xf000;
220
221 if (is_index_reg) { /* index registers */
222 val2 = reg & 0xff;
223 reg = reg >> 8;
224 nid = reg & 0xff;
225 ret = regmap_write(rt700->sdw_regmap, reg, 0);
226 if (ret < 0)
227 return ret;
228 reg2 = reg + 0x1000;
229 reg2 |= 0x80;
230 ret = regmap_write(rt700->sdw_regmap, reg2, val2);
231 if (ret < 0)
232 return ret;
233
234 reg3 = RT700_PRIV_DATA_W_H | nid;
235 ret = regmap_write(rt700->sdw_regmap,
236 reg3, ((val >> 8) & 0xff));
237 if (ret < 0)
238 return ret;
239 reg4 = reg3 + 0x1000;
240 reg4 |= 0x80;
241 ret = regmap_write(rt700->sdw_regmap, reg4, (val & 0xff));
242 if (ret < 0)
243 return ret;
244 is_index_reg = 1;
245 } else if (reg < 0x4fff) {
246 ret = regmap_write(rt700->sdw_regmap, reg, val);
247 if (ret < 0)
248 return ret;
249 } else if (reg == 0xff01) {
250 ret = regmap_write(rt700->sdw_regmap, reg, val);
251 if (ret < 0)
252 return ret;
253 } else if (mask == 0x7000) {
254 ret = regmap_write(rt700->sdw_regmap,
255 reg, ((val >> 8) & 0xff));
256 if (ret < 0)
257 return ret;
258 reg2 = reg + 0x1000;
259 reg2 |= 0x80;
260 ret = regmap_write(rt700->sdw_regmap, reg2, (val & 0xff));
261 if (ret < 0)
262 return ret;
263 } else if ((reg & 0xff00) == 0x8300) { /* for R channel */
264 reg2 = reg - 0x1000;
265 reg2 &= ~0x80;
266 ret = regmap_write(rt700->sdw_regmap,
267 reg2, ((val >> 8) & 0xff));
268 if (ret < 0)
269 return ret;
270 ret = regmap_write(rt700->sdw_regmap, reg, (val & 0xff));
271 if (ret < 0)
272 return ret;
273 }
274
275 if (reg2 == 0)
276 dev_dbg(dev, "[%s] %04x <= %04x\n", __func__, reg, val);
277 else if (is_index_reg)
278 dev_dbg(dev, "[%s] %04x %04x %04x %04x <= %04x %04x\n",
279 __func__, reg, reg2, reg3, reg4, val2, val);
280 else
281 dev_dbg(dev, "[%s] %04x %04x <= %04x\n",
282 __func__, reg, reg2, val);
283
284 return 0;
285}
286
287static const struct regmap_config rt700_regmap = {
288 .reg_bits = 24,
289 .val_bits = 32,
290 .readable_reg = rt700_readable_register,
291 .volatile_reg = rt700_volatile_register,
292 .max_register = 0x755800,
293 .reg_defaults = rt700_reg_defaults,
294 .num_reg_defaults = ARRAY_SIZE(rt700_reg_defaults),
295 .cache_type = REGCACHE_MAPLE,
296 .use_single_read = true,
297 .use_single_write = true,
298 .reg_read = rt700_sdw_read,
299 .reg_write = rt700_sdw_write,
300};
301
302static const struct regmap_config rt700_sdw_regmap = {
303 .name = "sdw",
304 .reg_bits = 32,
305 .val_bits = 8,
306 .readable_reg = rt700_readable_register,
307 .max_register = 0xff01,
308 .cache_type = REGCACHE_NONE,
309 .use_single_read = true,
310 .use_single_write = true,
311};
312
313static int rt700_update_status(struct sdw_slave *slave,
314 enum sdw_slave_status status)
315{
316 struct rt700_priv *rt700 = dev_get_drvdata(&slave->dev);
317
318 if (status == SDW_SLAVE_UNATTACHED)
319 rt700->hw_init = false;
320
321 /*
322 * Perform initialization only if slave status is present and
323 * hw_init flag is false
324 */
325 if (rt700->hw_init || status != SDW_SLAVE_ATTACHED)
326 return 0;
327
328 /* perform I/O transfers required for Slave initialization */
329 return rt700_io_init(&slave->dev, slave);
330}
331
332static int rt700_read_prop(struct sdw_slave *slave)
333{
334 struct sdw_slave_prop *prop = &slave->prop;
335 int nval, i;
336 u32 bit;
337 unsigned long addr;
338 struct sdw_dpn_prop *dpn;
339
340 prop->scp_int1_mask = SDW_SCP_INT1_IMPL_DEF | SDW_SCP_INT1_BUS_CLASH |
341 SDW_SCP_INT1_PARITY;
342 prop->quirks = SDW_SLAVE_QUIRKS_INVALID_INITIAL_PARITY;
343
344 prop->paging_support = false;
345
346 /* first we need to allocate memory for set bits in port lists */
347 prop->source_ports = 0x14; /* BITMAP: 00010100 */
348 prop->sink_ports = 0xA; /* BITMAP: 00001010 */
349
350 nval = hweight32(prop->source_ports);
351 prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval,
352 sizeof(*prop->src_dpn_prop),
353 GFP_KERNEL);
354 if (!prop->src_dpn_prop)
355 return -ENOMEM;
356
357 i = 0;
358 dpn = prop->src_dpn_prop;
359 addr = prop->source_ports;
360 for_each_set_bit(bit, &addr, 32) {
361 dpn[i].num = bit;
362 dpn[i].type = SDW_DPN_FULL;
363 dpn[i].simple_ch_prep_sm = true;
364 dpn[i].ch_prep_timeout = 10;
365 i++;
366 }
367
368 /* do this again for sink now */
369 nval = hweight32(prop->sink_ports);
370 prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval,
371 sizeof(*prop->sink_dpn_prop),
372 GFP_KERNEL);
373 if (!prop->sink_dpn_prop)
374 return -ENOMEM;
375
376 i = 0;
377 dpn = prop->sink_dpn_prop;
378 addr = prop->sink_ports;
379 for_each_set_bit(bit, &addr, 32) {
380 dpn[i].num = bit;
381 dpn[i].type = SDW_DPN_FULL;
382 dpn[i].simple_ch_prep_sm = true;
383 dpn[i].ch_prep_timeout = 10;
384 i++;
385 }
386
387 /* set the timeout values */
388 prop->clk_stop_timeout = 20;
389
390 /* wake-up event */
391 prop->wake_capable = 1;
392
393 return 0;
394}
395
396static int rt700_bus_config(struct sdw_slave *slave,
397 struct sdw_bus_params *params)
398{
399 struct rt700_priv *rt700 = dev_get_drvdata(&slave->dev);
400 int ret;
401
402 memcpy(&rt700->params, params, sizeof(*params));
403
404 ret = rt700_clock_config(&slave->dev);
405 if (ret < 0)
406 dev_err(&slave->dev, "Invalid clk config");
407
408 return ret;
409}
410
411static int rt700_interrupt_callback(struct sdw_slave *slave,
412 struct sdw_slave_intr_status *status)
413{
414 struct rt700_priv *rt700 = dev_get_drvdata(&slave->dev);
415
416 dev_dbg(&slave->dev,
417 "%s control_port_stat=%x", __func__, status->control_port);
418
419 mutex_lock(&rt700->disable_irq_lock);
420 if (status->control_port & 0x4 && !rt700->disable_irq) {
421 mod_delayed_work(system_power_efficient_wq,
422 &rt700->jack_detect_work, msecs_to_jiffies(250));
423 }
424 mutex_unlock(&rt700->disable_irq_lock);
425
426 return 0;
427}
428
429/*
430 * slave_ops: callbacks for get_clock_stop_mode, clock_stop and
431 * port_prep are not defined for now
432 */
433static const struct sdw_slave_ops rt700_slave_ops = {
434 .read_prop = rt700_read_prop,
435 .interrupt_callback = rt700_interrupt_callback,
436 .update_status = rt700_update_status,
437 .bus_config = rt700_bus_config,
438};
439
440static int rt700_sdw_probe(struct sdw_slave *slave,
441 const struct sdw_device_id *id)
442{
443 struct regmap *sdw_regmap, *regmap;
444
445 /* Regmap Initialization */
446 sdw_regmap = devm_regmap_init_sdw(slave, &rt700_sdw_regmap);
447 if (IS_ERR(sdw_regmap))
448 return PTR_ERR(sdw_regmap);
449
450 regmap = devm_regmap_init(&slave->dev, NULL,
451 &slave->dev, &rt700_regmap);
452 if (IS_ERR(regmap))
453 return PTR_ERR(regmap);
454
455 return rt700_init(&slave->dev, sdw_regmap, regmap, slave);
456}
457
458static int rt700_sdw_remove(struct sdw_slave *slave)
459{
460 struct rt700_priv *rt700 = dev_get_drvdata(&slave->dev);
461
462 if (rt700->hw_init) {
463 cancel_delayed_work_sync(&rt700->jack_detect_work);
464 cancel_delayed_work_sync(&rt700->jack_btn_check_work);
465 }
466
467 pm_runtime_disable(&slave->dev);
468
469 return 0;
470}
471
472static const struct sdw_device_id rt700_id[] = {
473 SDW_SLAVE_ENTRY_EXT(0x025d, 0x700, 0x1, 0, 0),
474 {},
475};
476MODULE_DEVICE_TABLE(sdw, rt700_id);
477
478static int __maybe_unused rt700_dev_suspend(struct device *dev)
479{
480 struct rt700_priv *rt700 = dev_get_drvdata(dev);
481
482 if (!rt700->hw_init)
483 return 0;
484
485 cancel_delayed_work_sync(&rt700->jack_detect_work);
486 cancel_delayed_work_sync(&rt700->jack_btn_check_work);
487
488 regcache_cache_only(rt700->regmap, true);
489
490 return 0;
491}
492
493static int __maybe_unused rt700_dev_system_suspend(struct device *dev)
494{
495 struct sdw_slave *slave = dev_to_sdw_dev(dev);
496 struct rt700_priv *rt700 = dev_get_drvdata(dev);
497 int ret;
498
499 if (!rt700->hw_init)
500 return 0;
501
502 /*
503 * prevent new interrupts from being handled after the
504 * deferred work completes and before the parent disables
505 * interrupts on the link
506 */
507 mutex_lock(&rt700->disable_irq_lock);
508 rt700->disable_irq = true;
509 ret = sdw_update_no_pm(slave, SDW_SCP_INTMASK1,
510 SDW_SCP_INT1_IMPL_DEF, 0);
511 mutex_unlock(&rt700->disable_irq_lock);
512
513 if (ret < 0) {
514 /* log but don't prevent suspend from happening */
515 dev_dbg(&slave->dev, "%s: could not disable imp-def interrupts\n:", __func__);
516 }
517
518 return rt700_dev_suspend(dev);
519}
520
521#define RT700_PROBE_TIMEOUT 5000
522
523static int __maybe_unused rt700_dev_resume(struct device *dev)
524{
525 struct sdw_slave *slave = dev_to_sdw_dev(dev);
526 struct rt700_priv *rt700 = dev_get_drvdata(dev);
527 unsigned long time;
528
529 if (!rt700->first_hw_init)
530 return 0;
531
532 if (!slave->unattach_request)
533 goto regmap_sync;
534
535 time = wait_for_completion_timeout(&slave->initialization_complete,
536 msecs_to_jiffies(RT700_PROBE_TIMEOUT));
537 if (!time) {
538 dev_err(&slave->dev, "Initialization not complete, timed out\n");
539 sdw_show_ping_status(slave->bus, true);
540
541 return -ETIMEDOUT;
542 }
543
544regmap_sync:
545 slave->unattach_request = 0;
546 regcache_cache_only(rt700->regmap, false);
547 regcache_sync_region(rt700->regmap, 0x3000, 0x8fff);
548 regcache_sync_region(rt700->regmap, 0x752010, 0x75206b);
549
550 return 0;
551}
552
553static const struct dev_pm_ops rt700_pm = {
554 SET_SYSTEM_SLEEP_PM_OPS(rt700_dev_system_suspend, rt700_dev_resume)
555 SET_RUNTIME_PM_OPS(rt700_dev_suspend, rt700_dev_resume, NULL)
556};
557
558static struct sdw_driver rt700_sdw_driver = {
559 .driver = {
560 .name = "rt700",
561 .pm = &rt700_pm,
562 },
563 .probe = rt700_sdw_probe,
564 .remove = rt700_sdw_remove,
565 .ops = &rt700_slave_ops,
566 .id_table = rt700_id,
567};
568module_sdw_driver(rt700_sdw_driver);
569
570MODULE_DESCRIPTION("ASoC RT700 driver SDW");
571MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>");
572MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2//
3// rt700-sdw.c -- rt700 ALSA SoC audio driver
4//
5// Copyright(c) 2019 Realtek Semiconductor Corp.
6//
7//
8
9#include <linux/delay.h>
10#include <linux/device.h>
11#include <linux/mod_devicetable.h>
12#include <linux/soundwire/sdw.h>
13#include <linux/soundwire/sdw_type.h>
14#include <linux/module.h>
15#include <linux/regmap.h>
16#include <sound/soc.h>
17#include "rt700.h"
18#include "rt700-sdw.h"
19
20static bool rt700_readable_register(struct device *dev, unsigned int reg)
21{
22 switch (reg) {
23 case 0x00e0:
24 case 0x00f0:
25 case 0x2000 ... 0x200e:
26 case 0x2012 ... 0x2016:
27 case 0x201a ... 0x2027:
28 case 0x2029 ... 0x202a:
29 case 0x202d ... 0x2034:
30 case 0x2200 ... 0x2204:
31 case 0x2206 ... 0x2212:
32 case 0x2220 ... 0x2223:
33 case 0x2230 ... 0x2231:
34 case 0x3000 ... 0x3fff:
35 case 0x7000 ... 0x7fff:
36 case 0x8300 ... 0x83ff:
37 case 0x9c00 ... 0x9cff:
38 case 0xb900 ... 0xb9ff:
39 case 0x75201a:
40 case 0x752045:
41 case 0x752046:
42 case 0x752048:
43 case 0x75204a:
44 case 0x75206b:
45 case 0x752080:
46 case 0x752081:
47 return true;
48 default:
49 return false;
50 }
51}
52
53static bool rt700_volatile_register(struct device *dev, unsigned int reg)
54{
55 switch (reg) {
56 case 0x2009:
57 case 0x2016:
58 case 0x201b:
59 case 0x201c:
60 case 0x201d:
61 case 0x201f:
62 case 0x2021:
63 case 0x2023:
64 case 0x2230:
65 case 0x200b ... 0x200e: /* i2c read */
66 case 0x2012 ... 0x2015: /* HD-A read */
67 case 0x202d ... 0x202f: /* BRA */
68 case 0x2201 ... 0x2212: /* i2c debug */
69 case 0x2220 ... 0x2223: /* decoded HD-A */
70 case 0x9c00 ... 0x9cff:
71 case 0xb900 ... 0xb9ff:
72 case 0xff01:
73 case 0x75201a:
74 case 0x752046:
75 case 0x752080:
76 case 0x752081:
77 return true;
78 default:
79 return false;
80 }
81}
82
83static int rt700_sdw_read(void *context, unsigned int reg, unsigned int *val)
84{
85 struct device *dev = context;
86 struct rt700_priv *rt700 = dev_get_drvdata(dev);
87 unsigned int sdw_data_3, sdw_data_2, sdw_data_1, sdw_data_0;
88 unsigned int reg2 = 0, reg3 = 0, reg4 = 0, mask, nid, val2;
89 unsigned int is_hda_reg = 1, is_index_reg = 0;
90 int ret;
91
92 if (reg > 0xffff)
93 is_index_reg = 1;
94
95 mask = reg & 0xf000;
96
97 if (is_index_reg) { /* index registers */
98 val2 = reg & 0xff;
99 reg = reg >> 8;
100 nid = reg & 0xff;
101 ret = regmap_write(rt700->sdw_regmap, reg, 0);
102 if (ret < 0)
103 return ret;
104 reg2 = reg + 0x1000;
105 reg2 |= 0x80;
106 ret = regmap_write(rt700->sdw_regmap, reg2, val2);
107 if (ret < 0)
108 return ret;
109
110 reg3 = RT700_PRIV_DATA_R_H | nid;
111 ret = regmap_write(rt700->sdw_regmap,
112 reg3, ((*val >> 8) & 0xff));
113 if (ret < 0)
114 return ret;
115 reg4 = reg3 + 0x1000;
116 reg4 |= 0x80;
117 ret = regmap_write(rt700->sdw_regmap, reg4, (*val & 0xff));
118 if (ret < 0)
119 return ret;
120 } else if (mask == 0x3000) {
121 reg += 0x8000;
122 ret = regmap_write(rt700->sdw_regmap, reg, *val);
123 if (ret < 0)
124 return ret;
125 } else if (mask == 0x7000) {
126 reg += 0x2000;
127 reg |= 0x800;
128 ret = regmap_write(rt700->sdw_regmap,
129 reg, ((*val >> 8) & 0xff));
130 if (ret < 0)
131 return ret;
132 reg2 = reg + 0x1000;
133 reg2 |= 0x80;
134 ret = regmap_write(rt700->sdw_regmap, reg2, (*val & 0xff));
135 if (ret < 0)
136 return ret;
137 } else if ((reg & 0xff00) == 0x8300) { /* for R channel */
138 reg2 = reg - 0x1000;
139 reg2 &= ~0x80;
140 ret = regmap_write(rt700->sdw_regmap,
141 reg2, ((*val >> 8) & 0xff));
142 if (ret < 0)
143 return ret;
144 ret = regmap_write(rt700->sdw_regmap, reg, (*val & 0xff));
145 if (ret < 0)
146 return ret;
147 } else if (mask == 0x9000) {
148 ret = regmap_write(rt700->sdw_regmap,
149 reg, ((*val >> 8) & 0xff));
150 if (ret < 0)
151 return ret;
152 reg2 = reg + 0x1000;
153 reg2 |= 0x80;
154 ret = regmap_write(rt700->sdw_regmap, reg2, (*val & 0xff));
155 if (ret < 0)
156 return ret;
157 } else if (mask == 0xb000) {
158 ret = regmap_write(rt700->sdw_regmap, reg, *val);
159 if (ret < 0)
160 return ret;
161 } else {
162 ret = regmap_read(rt700->sdw_regmap, reg, val);
163 if (ret < 0)
164 return ret;
165 is_hda_reg = 0;
166 }
167
168 if (is_hda_reg || is_index_reg) {
169 sdw_data_3 = 0;
170 sdw_data_2 = 0;
171 sdw_data_1 = 0;
172 sdw_data_0 = 0;
173 ret = regmap_read(rt700->sdw_regmap,
174 RT700_READ_HDA_3, &sdw_data_3);
175 if (ret < 0)
176 return ret;
177 ret = regmap_read(rt700->sdw_regmap,
178 RT700_READ_HDA_2, &sdw_data_2);
179 if (ret < 0)
180 return ret;
181 ret = regmap_read(rt700->sdw_regmap,
182 RT700_READ_HDA_1, &sdw_data_1);
183 if (ret < 0)
184 return ret;
185 ret = regmap_read(rt700->sdw_regmap,
186 RT700_READ_HDA_0, &sdw_data_0);
187 if (ret < 0)
188 return ret;
189 *val = ((sdw_data_3 & 0xff) << 24) |
190 ((sdw_data_2 & 0xff) << 16) |
191 ((sdw_data_1 & 0xff) << 8) | (sdw_data_0 & 0xff);
192 }
193
194 if (is_hda_reg == 0)
195 dev_dbg(dev, "[%s] %04x => %08x\n", __func__, reg, *val);
196 else if (is_index_reg)
197 dev_dbg(dev, "[%s] %04x %04x %04x %04x => %08x\n",
198 __func__, reg, reg2, reg3, reg4, *val);
199 else
200 dev_dbg(dev, "[%s] %04x %04x => %08x\n",
201 __func__, reg, reg2, *val);
202
203 return 0;
204}
205
206static int rt700_sdw_write(void *context, unsigned int reg, unsigned int val)
207{
208 struct device *dev = context;
209 struct rt700_priv *rt700 = dev_get_drvdata(dev);
210 unsigned int reg2 = 0, reg3, reg4, nid, mask, val2;
211 unsigned int is_index_reg = 0;
212 int ret;
213
214 if (reg > 0xffff)
215 is_index_reg = 1;
216
217 mask = reg & 0xf000;
218
219 if (is_index_reg) { /* index registers */
220 val2 = reg & 0xff;
221 reg = reg >> 8;
222 nid = reg & 0xff;
223 ret = regmap_write(rt700->sdw_regmap, reg, 0);
224 if (ret < 0)
225 return ret;
226 reg2 = reg + 0x1000;
227 reg2 |= 0x80;
228 ret = regmap_write(rt700->sdw_regmap, reg2, val2);
229 if (ret < 0)
230 return ret;
231
232 reg3 = RT700_PRIV_DATA_W_H | nid;
233 ret = regmap_write(rt700->sdw_regmap,
234 reg3, ((val >> 8) & 0xff));
235 if (ret < 0)
236 return ret;
237 reg4 = reg3 + 0x1000;
238 reg4 |= 0x80;
239 ret = regmap_write(rt700->sdw_regmap, reg4, (val & 0xff));
240 if (ret < 0)
241 return ret;
242 is_index_reg = 1;
243 } else if (reg < 0x4fff) {
244 ret = regmap_write(rt700->sdw_regmap, reg, val);
245 if (ret < 0)
246 return ret;
247 } else if (reg == 0xff01) {
248 ret = regmap_write(rt700->sdw_regmap, reg, val);
249 if (ret < 0)
250 return ret;
251 } else if (mask == 0x7000) {
252 ret = regmap_write(rt700->sdw_regmap,
253 reg, ((val >> 8) & 0xff));
254 if (ret < 0)
255 return ret;
256 reg2 = reg + 0x1000;
257 reg2 |= 0x80;
258 ret = regmap_write(rt700->sdw_regmap, reg2, (val & 0xff));
259 if (ret < 0)
260 return ret;
261 } else if ((reg & 0xff00) == 0x8300) { /* for R channel */
262 reg2 = reg - 0x1000;
263 reg2 &= ~0x80;
264 ret = regmap_write(rt700->sdw_regmap,
265 reg2, ((val >> 8) & 0xff));
266 if (ret < 0)
267 return ret;
268 ret = regmap_write(rt700->sdw_regmap, reg, (val & 0xff));
269 if (ret < 0)
270 return ret;
271 }
272
273 if (reg2 == 0)
274 dev_dbg(dev, "[%s] %04x <= %04x\n", __func__, reg, val);
275 else if (is_index_reg)
276 dev_dbg(dev, "[%s] %04x %04x %04x %04x <= %04x %04x\n",
277 __func__, reg, reg2, reg3, reg4, val2, val);
278 else
279 dev_dbg(dev, "[%s] %04x %04x <= %04x\n",
280 __func__, reg, reg2, val);
281
282 return 0;
283}
284
285static const struct regmap_config rt700_regmap = {
286 .reg_bits = 24,
287 .val_bits = 32,
288 .readable_reg = rt700_readable_register,
289 .volatile_reg = rt700_volatile_register,
290 .max_register = 0x755800,
291 .reg_defaults = rt700_reg_defaults,
292 .num_reg_defaults = ARRAY_SIZE(rt700_reg_defaults),
293 .cache_type = REGCACHE_RBTREE,
294 .use_single_read = true,
295 .use_single_write = true,
296 .reg_read = rt700_sdw_read,
297 .reg_write = rt700_sdw_write,
298};
299
300static const struct regmap_config rt700_sdw_regmap = {
301 .name = "sdw",
302 .reg_bits = 32,
303 .val_bits = 8,
304 .readable_reg = rt700_readable_register,
305 .max_register = 0xff01,
306 .cache_type = REGCACHE_NONE,
307 .use_single_read = true,
308 .use_single_write = true,
309};
310
311static int rt700_update_status(struct sdw_slave *slave,
312 enum sdw_slave_status status)
313{
314 struct rt700_priv *rt700 = dev_get_drvdata(&slave->dev);
315
316 /* Update the status */
317 rt700->status = status;
318
319 if (status == SDW_SLAVE_UNATTACHED)
320 rt700->hw_init = false;
321
322 /*
323 * Perform initialization only if slave status is present and
324 * hw_init flag is false
325 */
326 if (rt700->hw_init || rt700->status != SDW_SLAVE_ATTACHED)
327 return 0;
328
329 /* perform I/O transfers required for Slave initialization */
330 return rt700_io_init(&slave->dev, slave);
331}
332
333static int rt700_read_prop(struct sdw_slave *slave)
334{
335 struct sdw_slave_prop *prop = &slave->prop;
336 int nval, i, num_of_ports = 1;
337 u32 bit;
338 unsigned long addr;
339 struct sdw_dpn_prop *dpn;
340
341 prop->paging_support = false;
342
343 /* first we need to allocate memory for set bits in port lists */
344 prop->source_ports = 0x14; /* BITMAP: 00010100 */
345 prop->sink_ports = 0xA; /* BITMAP: 00001010 */
346
347 nval = hweight32(prop->source_ports);
348 num_of_ports += nval;
349 prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval,
350 sizeof(*prop->src_dpn_prop),
351 GFP_KERNEL);
352 if (!prop->src_dpn_prop)
353 return -ENOMEM;
354
355 i = 0;
356 dpn = prop->src_dpn_prop;
357 addr = prop->source_ports;
358 for_each_set_bit(bit, &addr, 32) {
359 dpn[i].num = bit;
360 dpn[i].type = SDW_DPN_FULL;
361 dpn[i].simple_ch_prep_sm = true;
362 dpn[i].ch_prep_timeout = 10;
363 i++;
364 }
365
366 /* do this again for sink now */
367 nval = hweight32(prop->sink_ports);
368 num_of_ports += nval;
369 prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval,
370 sizeof(*prop->sink_dpn_prop),
371 GFP_KERNEL);
372 if (!prop->sink_dpn_prop)
373 return -ENOMEM;
374
375 i = 0;
376 dpn = prop->sink_dpn_prop;
377 addr = prop->sink_ports;
378 for_each_set_bit(bit, &addr, 32) {
379 dpn[i].num = bit;
380 dpn[i].type = SDW_DPN_FULL;
381 dpn[i].simple_ch_prep_sm = true;
382 dpn[i].ch_prep_timeout = 10;
383 i++;
384 }
385
386 /* Allocate port_ready based on num_of_ports */
387 slave->port_ready = devm_kcalloc(&slave->dev, num_of_ports,
388 sizeof(*slave->port_ready),
389 GFP_KERNEL);
390 if (!slave->port_ready)
391 return -ENOMEM;
392
393 /* Initialize completion */
394 for (i = 0; i < num_of_ports; i++)
395 init_completion(&slave->port_ready[i]);
396
397 /* set the timeout values */
398 prop->clk_stop_timeout = 20;
399
400 /* wake-up event */
401 prop->wake_capable = 1;
402
403 return 0;
404}
405
406static int rt700_bus_config(struct sdw_slave *slave,
407 struct sdw_bus_params *params)
408{
409 struct rt700_priv *rt700 = dev_get_drvdata(&slave->dev);
410 int ret;
411
412 memcpy(&rt700->params, params, sizeof(*params));
413
414 ret = rt700_clock_config(&slave->dev);
415 if (ret < 0)
416 dev_err(&slave->dev, "Invalid clk config");
417
418 return ret;
419}
420
421static int rt700_interrupt_callback(struct sdw_slave *slave,
422 struct sdw_slave_intr_status *status)
423{
424 struct rt700_priv *rt700 = dev_get_drvdata(&slave->dev);
425
426 dev_dbg(&slave->dev,
427 "%s control_port_stat=%x", __func__, status->control_port);
428
429 if (status->control_port & 0x4) {
430 mod_delayed_work(system_power_efficient_wq,
431 &rt700->jack_detect_work, msecs_to_jiffies(250));
432 }
433
434 return 0;
435}
436
437/*
438 * slave_ops: callbacks for get_clock_stop_mode, clock_stop and
439 * port_prep are not defined for now
440 */
441static struct sdw_slave_ops rt700_slave_ops = {
442 .read_prop = rt700_read_prop,
443 .interrupt_callback = rt700_interrupt_callback,
444 .update_status = rt700_update_status,
445 .bus_config = rt700_bus_config,
446};
447
448static int rt700_sdw_probe(struct sdw_slave *slave,
449 const struct sdw_device_id *id)
450{
451 struct regmap *sdw_regmap, *regmap;
452
453 /* Regmap Initialization */
454 sdw_regmap = devm_regmap_init_sdw(slave, &rt700_sdw_regmap);
455 if (IS_ERR(sdw_regmap))
456 return PTR_ERR(sdw_regmap);
457
458 regmap = devm_regmap_init(&slave->dev, NULL,
459 &slave->dev, &rt700_regmap);
460 if (IS_ERR(regmap))
461 return PTR_ERR(regmap);
462
463 rt700_init(&slave->dev, sdw_regmap, regmap, slave);
464
465 return 0;
466}
467
468static int rt700_sdw_remove(struct sdw_slave *slave)
469{
470 struct rt700_priv *rt700 = dev_get_drvdata(&slave->dev);
471
472 if (rt700 && rt700->hw_init) {
473 cancel_delayed_work(&rt700->jack_detect_work);
474 cancel_delayed_work(&rt700->jack_btn_check_work);
475 }
476
477 return 0;
478}
479
480static const struct sdw_device_id rt700_id[] = {
481 SDW_SLAVE_ENTRY(0x025d, 0x700, 0),
482 {},
483};
484MODULE_DEVICE_TABLE(sdw, rt700_id);
485
486static int __maybe_unused rt700_dev_suspend(struct device *dev)
487{
488 struct rt700_priv *rt700 = dev_get_drvdata(dev);
489
490 if (!rt700->hw_init)
491 return 0;
492
493 regcache_cache_only(rt700->regmap, true);
494
495 return 0;
496}
497
498#define RT700_PROBE_TIMEOUT 2000
499
500static int __maybe_unused rt700_dev_resume(struct device *dev)
501{
502 struct sdw_slave *slave = dev_to_sdw_dev(dev);
503 struct rt700_priv *rt700 = dev_get_drvdata(dev);
504 unsigned long time;
505
506 if (!rt700->hw_init)
507 return 0;
508
509 if (!slave->unattach_request)
510 goto regmap_sync;
511
512 time = wait_for_completion_timeout(&slave->initialization_complete,
513 msecs_to_jiffies(RT700_PROBE_TIMEOUT));
514 if (!time) {
515 dev_err(&slave->dev, "Initialization not complete, timed out\n");
516 return -ETIMEDOUT;
517 }
518
519regmap_sync:
520 slave->unattach_request = 0;
521 regcache_cache_only(rt700->regmap, false);
522 regcache_sync_region(rt700->regmap, 0x3000, 0x8fff);
523 regcache_sync_region(rt700->regmap, 0x752010, 0x75206b);
524
525 return 0;
526}
527
528static const struct dev_pm_ops rt700_pm = {
529 SET_SYSTEM_SLEEP_PM_OPS(rt700_dev_suspend, rt700_dev_resume)
530 SET_RUNTIME_PM_OPS(rt700_dev_suspend, rt700_dev_resume, NULL)
531};
532
533static struct sdw_driver rt700_sdw_driver = {
534 .driver = {
535 .name = "rt700",
536 .owner = THIS_MODULE,
537 .pm = &rt700_pm,
538 },
539 .probe = rt700_sdw_probe,
540 .remove = rt700_sdw_remove,
541 .ops = &rt700_slave_ops,
542 .id_table = rt700_id,
543};
544module_sdw_driver(rt700_sdw_driver);
545
546MODULE_DESCRIPTION("ASoC RT700 driver SDW");
547MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>");
548MODULE_LICENSE("GPL v2");