1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * max98088.c -- MAX98088 ALSA SoC Audio driver
   4 *
   5 * Copyright 2010 Maxim Integrated Products
   6 */
   7
   8#include <linux/module.h>
   9#include <linux/moduleparam.h>
  10#include <linux/kernel.h>
  11#include <linux/init.h>
  12#include <linux/delay.h>
  13#include <linux/pm.h>
  14#include <linux/i2c.h>
  15#include <linux/regmap.h>
  16#include <linux/clk.h>
  17#include <sound/core.h>
  18#include <sound/pcm.h>
  19#include <sound/pcm_params.h>
  20#include <sound/soc.h>
  21#include <sound/initval.h>
  22#include <sound/tlv.h>
  23#include <linux/slab.h>
  24#include <asm/div64.h>
  25#include <sound/max98088.h>
  26#include "max98088.h"
  27
  28enum max98088_type {
  29       MAX98088,
  30       MAX98089,
  31};
  32
  33struct max98088_cdata {
  34       unsigned int rate;
  35       unsigned int fmt;
  36       int eq_sel;
  37};
  38
  39struct max98088_priv {
  40	struct regmap *regmap;
  41	enum max98088_type devtype;
  42	struct max98088_pdata *pdata;
  43	struct clk *mclk;
  44	unsigned char mclk_prescaler;
  45	unsigned int sysclk;
  46	struct max98088_cdata dai[2];
  47	int eq_textcnt;
  48	const char **eq_texts;
  49	struct soc_enum eq_enum;
  50	u8 ina_state;
  51	u8 inb_state;
  52	unsigned int ex_mode;
  53	unsigned int digmic;
  54	unsigned int mic1pre;
  55	unsigned int mic2pre;
  56	unsigned int extmic_mode;
  57};
  58
  59static const struct reg_default max98088_reg[] = {
  60	{  0xf, 0x00 }, /* 0F interrupt enable */
  61
  62	{ 0x10, 0x00 }, /* 10 master clock */
  63	{ 0x11, 0x00 }, /* 11 DAI1 clock mode */
  64	{ 0x12, 0x00 }, /* 12 DAI1 clock control */
  65	{ 0x13, 0x00 }, /* 13 DAI1 clock control */
  66	{ 0x14, 0x00 }, /* 14 DAI1 format */
  67	{ 0x15, 0x00 }, /* 15 DAI1 clock */
  68	{ 0x16, 0x00 }, /* 16 DAI1 config */
  69	{ 0x17, 0x00 }, /* 17 DAI1 TDM */
  70	{ 0x18, 0x00 }, /* 18 DAI1 filters */
  71	{ 0x19, 0x00 }, /* 19 DAI2 clock mode */
  72	{ 0x1a, 0x00 }, /* 1A DAI2 clock control */
  73	{ 0x1b, 0x00 }, /* 1B DAI2 clock control */
  74	{ 0x1c, 0x00 }, /* 1C DAI2 format */
  75	{ 0x1d, 0x00 }, /* 1D DAI2 clock */
  76	{ 0x1e, 0x00 }, /* 1E DAI2 config */
  77	{ 0x1f, 0x00 }, /* 1F DAI2 TDM */
  78
  79	{ 0x20, 0x00 }, /* 20 DAI2 filters */
  80	{ 0x21, 0x00 }, /* 21 data config */
  81	{ 0x22, 0x00 }, /* 22 DAC mixer */
  82	{ 0x23, 0x00 }, /* 23 left ADC mixer */
  83	{ 0x24, 0x00 }, /* 24 right ADC mixer */
  84	{ 0x25, 0x00 }, /* 25 left HP mixer */
  85	{ 0x26, 0x00 }, /* 26 right HP mixer */
  86	{ 0x27, 0x00 }, /* 27 HP control */
  87	{ 0x28, 0x00 }, /* 28 left REC mixer */
  88	{ 0x29, 0x00 }, /* 29 right REC mixer */
  89	{ 0x2a, 0x00 }, /* 2A REC control */
  90	{ 0x2b, 0x00 }, /* 2B left SPK mixer */
  91	{ 0x2c, 0x00 }, /* 2C right SPK mixer */
  92	{ 0x2d, 0x00 }, /* 2D SPK control */
  93	{ 0x2e, 0x00 }, /* 2E sidetone */
  94	{ 0x2f, 0x00 }, /* 2F DAI1 playback level */
  95
  96	{ 0x30, 0x00 }, /* 30 DAI1 playback level */
  97	{ 0x31, 0x00 }, /* 31 DAI2 playback level */
  98	{ 0x32, 0x00 }, /* 32 DAI2 playbakc level */
  99	{ 0x33, 0x00 }, /* 33 left ADC level */
 100	{ 0x34, 0x00 }, /* 34 right ADC level */
 101	{ 0x35, 0x00 }, /* 35 MIC1 level */
 102	{ 0x36, 0x00 }, /* 36 MIC2 level */
 103	{ 0x37, 0x00 }, /* 37 INA level */
 104	{ 0x38, 0x00 }, /* 38 INB level */
 105	{ 0x39, 0x00 }, /* 39 left HP volume */
 106	{ 0x3a, 0x00 }, /* 3A right HP volume */
 107	{ 0x3b, 0x00 }, /* 3B left REC volume */
 108	{ 0x3c, 0x00 }, /* 3C right REC volume */
 109	{ 0x3d, 0x00 }, /* 3D left SPK volume */
 110	{ 0x3e, 0x00 }, /* 3E right SPK volume */
 111	{ 0x3f, 0x00 }, /* 3F MIC config */
 112
 113	{ 0x40, 0x00 }, /* 40 MIC threshold */
 114	{ 0x41, 0x00 }, /* 41 excursion limiter filter */
 115	{ 0x42, 0x00 }, /* 42 excursion limiter threshold */
 116	{ 0x43, 0x00 }, /* 43 ALC */
 117	{ 0x44, 0x00 }, /* 44 power limiter threshold */
 118	{ 0x45, 0x00 }, /* 45 power limiter config */
 119	{ 0x46, 0x00 }, /* 46 distortion limiter config */
 120	{ 0x47, 0x00 }, /* 47 audio input */
 121        { 0x48, 0x00 }, /* 48 microphone */
 122	{ 0x49, 0x00 }, /* 49 level control */
 123	{ 0x4a, 0x00 }, /* 4A bypass switches */
 124	{ 0x4b, 0x00 }, /* 4B jack detect */
 125	{ 0x4c, 0x00 }, /* 4C input enable */
 126	{ 0x4d, 0x00 }, /* 4D output enable */
 127	{ 0x4e, 0xF0 }, /* 4E bias control */
 128	{ 0x4f, 0x00 }, /* 4F DAC power */
 129
 130	{ 0x50, 0x0F }, /* 50 DAC power */
 131	{ 0x51, 0x00 }, /* 51 system */
 132	{ 0x52, 0x00 }, /* 52 DAI1 EQ1 */
 133	{ 0x53, 0x00 }, /* 53 DAI1 EQ1 */
 134	{ 0x54, 0x00 }, /* 54 DAI1 EQ1 */
 135	{ 0x55, 0x00 }, /* 55 DAI1 EQ1 */
 136	{ 0x56, 0x00 }, /* 56 DAI1 EQ1 */
 137	{ 0x57, 0x00 }, /* 57 DAI1 EQ1 */
 138	{ 0x58, 0x00 }, /* 58 DAI1 EQ1 */
 139	{ 0x59, 0x00 }, /* 59 DAI1 EQ1 */
 140	{ 0x5a, 0x00 }, /* 5A DAI1 EQ1 */
 141	{ 0x5b, 0x00 }, /* 5B DAI1 EQ1 */
 142	{ 0x5c, 0x00 }, /* 5C DAI1 EQ2 */
 143	{ 0x5d, 0x00 }, /* 5D DAI1 EQ2 */
 144	{ 0x5e, 0x00 }, /* 5E DAI1 EQ2 */
 145	{ 0x5f, 0x00 }, /* 5F DAI1 EQ2 */
 146
 147	{ 0x60, 0x00 }, /* 60 DAI1 EQ2 */
 148	{ 0x61, 0x00 }, /* 61 DAI1 EQ2 */
 149	{ 0x62, 0x00 }, /* 62 DAI1 EQ2 */
 150	{ 0x63, 0x00 }, /* 63 DAI1 EQ2 */
 151	{ 0x64, 0x00 }, /* 64 DAI1 EQ2 */
 152	{ 0x65, 0x00 }, /* 65 DAI1 EQ2 */
 153	{ 0x66, 0x00 }, /* 66 DAI1 EQ3 */
 154	{ 0x67, 0x00 }, /* 67 DAI1 EQ3 */
 155	{ 0x68, 0x00 }, /* 68 DAI1 EQ3 */
 156	{ 0x69, 0x00 }, /* 69 DAI1 EQ3 */
 157	{ 0x6a, 0x00 }, /* 6A DAI1 EQ3 */
 158	{ 0x6b, 0x00 }, /* 6B DAI1 EQ3 */
 159	{ 0x6c, 0x00 }, /* 6C DAI1 EQ3 */
 160	{ 0x6d, 0x00 }, /* 6D DAI1 EQ3 */
 161	{ 0x6e, 0x00 }, /* 6E DAI1 EQ3 */
 162	{ 0x6f, 0x00 }, /* 6F DAI1 EQ3 */
 163
 164	{ 0x70, 0x00 }, /* 70 DAI1 EQ4 */
 165	{ 0x71, 0x00 }, /* 71 DAI1 EQ4 */
 166	{ 0x72, 0x00 }, /* 72 DAI1 EQ4 */
 167	{ 0x73, 0x00 }, /* 73 DAI1 EQ4 */
 168	{ 0x74, 0x00 }, /* 74 DAI1 EQ4 */
 169	{ 0x75, 0x00 }, /* 75 DAI1 EQ4 */
 170	{ 0x76, 0x00 }, /* 76 DAI1 EQ4 */
 171	{ 0x77, 0x00 }, /* 77 DAI1 EQ4 */
 172	{ 0x78, 0x00 }, /* 78 DAI1 EQ4 */
 173	{ 0x79, 0x00 }, /* 79 DAI1 EQ4 */
 174	{ 0x7a, 0x00 }, /* 7A DAI1 EQ5 */
 175	{ 0x7b, 0x00 }, /* 7B DAI1 EQ5 */
 176	{ 0x7c, 0x00 }, /* 7C DAI1 EQ5 */
 177	{ 0x7d, 0x00 }, /* 7D DAI1 EQ5 */
 178	{ 0x7e, 0x00 }, /* 7E DAI1 EQ5 */
 179	{ 0x7f, 0x00 }, /* 7F DAI1 EQ5 */
 180
 181	{ 0x80, 0x00 }, /* 80 DAI1 EQ5 */
 182	{ 0x81, 0x00 }, /* 81 DAI1 EQ5 */
 183	{ 0x82, 0x00 }, /* 82 DAI1 EQ5 */
 184	{ 0x83, 0x00 }, /* 83 DAI1 EQ5 */
 185	{ 0x84, 0x00 }, /* 84 DAI2 EQ1 */
 186	{ 0x85, 0x00 }, /* 85 DAI2 EQ1 */
 187	{ 0x86, 0x00 }, /* 86 DAI2 EQ1 */
 188	{ 0x87, 0x00 }, /* 87 DAI2 EQ1 */
 189	{ 0x88, 0x00 }, /* 88 DAI2 EQ1 */
 190	{ 0x89, 0x00 }, /* 89 DAI2 EQ1 */
 191	{ 0x8a, 0x00 }, /* 8A DAI2 EQ1 */
 192	{ 0x8b, 0x00 }, /* 8B DAI2 EQ1 */
 193	{ 0x8c, 0x00 }, /* 8C DAI2 EQ1 */
 194	{ 0x8d, 0x00 }, /* 8D DAI2 EQ1 */
 195	{ 0x8e, 0x00 }, /* 8E DAI2 EQ2 */
 196	{ 0x8f, 0x00 }, /* 8F DAI2 EQ2 */
 197
 198	{ 0x90, 0x00 }, /* 90 DAI2 EQ2 */
 199	{ 0x91, 0x00 }, /* 91 DAI2 EQ2 */
 200	{ 0x92, 0x00 }, /* 92 DAI2 EQ2 */
 201	{ 0x93, 0x00 }, /* 93 DAI2 EQ2 */
 202	{ 0x94, 0x00 }, /* 94 DAI2 EQ2 */
 203	{ 0x95, 0x00 }, /* 95 DAI2 EQ2 */
 204	{ 0x96, 0x00 }, /* 96 DAI2 EQ2 */
 205	{ 0x97, 0x00 }, /* 97 DAI2 EQ2 */
 206	{ 0x98, 0x00 }, /* 98 DAI2 EQ3 */
 207	{ 0x99, 0x00 }, /* 99 DAI2 EQ3 */
 208	{ 0x9a, 0x00 }, /* 9A DAI2 EQ3 */
 209        { 0x9b, 0x00 }, /* 9B DAI2 EQ3 */
 210	{ 0x9c, 0x00 }, /* 9C DAI2 EQ3 */
 211	{ 0x9d, 0x00 }, /* 9D DAI2 EQ3 */
 212	{ 0x9e, 0x00 }, /* 9E DAI2 EQ3 */
 213	{ 0x9f, 0x00 }, /* 9F DAI2 EQ3 */
 214
 215	{ 0xa0, 0x00 }, /* A0 DAI2 EQ3 */
 216	{ 0xa1, 0x00 }, /* A1 DAI2 EQ3 */
 217	{ 0xa2, 0x00 }, /* A2 DAI2 EQ4 */
 218	{ 0xa3, 0x00 }, /* A3 DAI2 EQ4 */
 219	{ 0xa4, 0x00 }, /* A4 DAI2 EQ4 */
 220	{ 0xa5, 0x00 }, /* A5 DAI2 EQ4 */
 221	{ 0xa6, 0x00 }, /* A6 DAI2 EQ4 */
 222	{ 0xa7, 0x00 }, /* A7 DAI2 EQ4 */
 223	{ 0xa8, 0x00 }, /* A8 DAI2 EQ4 */
 224	{ 0xa9, 0x00 }, /* A9 DAI2 EQ4 */
 225	{ 0xaa, 0x00 }, /* AA DAI2 EQ4 */
 226	{ 0xab, 0x00 }, /* AB DAI2 EQ4 */
 227	{ 0xac, 0x00 }, /* AC DAI2 EQ5 */
 228	{ 0xad, 0x00 }, /* AD DAI2 EQ5 */
 229	{ 0xae, 0x00 }, /* AE DAI2 EQ5 */
 230	{ 0xaf, 0x00 }, /* AF DAI2 EQ5 */
 231
 232	{ 0xb0, 0x00 }, /* B0 DAI2 EQ5 */
 233	{ 0xb1, 0x00 }, /* B1 DAI2 EQ5 */
 234	{ 0xb2, 0x00 }, /* B2 DAI2 EQ5 */
 235	{ 0xb3, 0x00 }, /* B3 DAI2 EQ5 */
 236	{ 0xb4, 0x00 }, /* B4 DAI2 EQ5 */
 237	{ 0xb5, 0x00 }, /* B5 DAI2 EQ5 */
 238	{ 0xb6, 0x00 }, /* B6 DAI1 biquad */
 239	{ 0xb7, 0x00 }, /* B7 DAI1 biquad */
 240	{ 0xb8 ,0x00 }, /* B8 DAI1 biquad */
 241	{ 0xb9, 0x00 }, /* B9 DAI1 biquad */
 242	{ 0xba, 0x00 }, /* BA DAI1 biquad */
 243	{ 0xbb, 0x00 }, /* BB DAI1 biquad */
 244	{ 0xbc, 0x00 }, /* BC DAI1 biquad */
 245	{ 0xbd, 0x00 }, /* BD DAI1 biquad */
 246	{ 0xbe, 0x00 }, /* BE DAI1 biquad */
 247        { 0xbf, 0x00 }, /* BF DAI1 biquad */
 248
 249	{ 0xc0, 0x00 }, /* C0 DAI2 biquad */
 250	{ 0xc1, 0x00 }, /* C1 DAI2 biquad */
 251	{ 0xc2, 0x00 }, /* C2 DAI2 biquad */
 252	{ 0xc3, 0x00 }, /* C3 DAI2 biquad */
 253	{ 0xc4, 0x00 }, /* C4 DAI2 biquad */
 254	{ 0xc5, 0x00 }, /* C5 DAI2 biquad */
 255	{ 0xc6, 0x00 }, /* C6 DAI2 biquad */
 256	{ 0xc7, 0x00 }, /* C7 DAI2 biquad */
 257	{ 0xc8, 0x00 }, /* C8 DAI2 biquad */
 258	{ 0xc9, 0x00 }, /* C9 DAI2 biquad */
 259};
 260
 261static bool max98088_readable_register(struct device *dev, unsigned int reg)
 262{
 263	switch (reg) {
 264	case M98088_REG_00_IRQ_STATUS ... 0xC9:
 265	case M98088_REG_FF_REV_ID:
 266		return true;
 267	default:
 268		return false;
 269	}
 270}
 271
 272static bool max98088_writeable_register(struct device *dev, unsigned int reg)
 273{
 274	switch (reg) {
 275	case M98088_REG_03_BATTERY_VOLTAGE ... 0xC9:
 276		return true;
 277	default:
 278		return false;
 279	}
 280}
 281
 282static bool max98088_volatile_register(struct device *dev, unsigned int reg)
 283{
 284	switch (reg) {
 285	case M98088_REG_00_IRQ_STATUS ... M98088_REG_03_BATTERY_VOLTAGE:
 286	case M98088_REG_FF_REV_ID:
 287		return true;
 288	default:
 289		return false;
 290	}
 291}
 292
 293static const struct regmap_config max98088_regmap = {
 294	.reg_bits = 8,
 295	.val_bits = 8,
 296
 297	.readable_reg = max98088_readable_register,
 298	.writeable_reg = max98088_writeable_register,
 299	.volatile_reg = max98088_volatile_register,
 300	.max_register = 0xff,
 301
 302	.reg_defaults = max98088_reg,
 303	.num_reg_defaults = ARRAY_SIZE(max98088_reg),
 304	.cache_type = REGCACHE_RBTREE,
 305};
 306
 307/*
 308 * Load equalizer DSP coefficient configurations registers
 309 */
 310static void m98088_eq_band(struct snd_soc_component *component, unsigned int dai,
 311                   unsigned int band, u16 *coefs)
 312{
 313	unsigned int eq_reg;
 314	unsigned int i;
 315
 316	if (WARN_ON(band > 4) ||
 317	    WARN_ON(dai > 1))
 318		return;
 319
 320	/* Load the base register address */
 321	eq_reg = dai ? M98088_REG_84_DAI2_EQ_BASE : M98088_REG_52_DAI1_EQ_BASE;
 322
 323	/* Add the band address offset, note adjustment for word address */
 324	eq_reg += band * (M98088_COEFS_PER_BAND << 1);
 325
 326	/* Step through the registers and coefs */
 327	for (i = 0; i < M98088_COEFS_PER_BAND; i++) {
 328		snd_soc_component_write(component, eq_reg++, M98088_BYTE1(coefs[i]));
 329		snd_soc_component_write(component, eq_reg++, M98088_BYTE0(coefs[i]));
 330	}
 331}
 332
 333/*
 334 * Excursion limiter modes
 335 */
 336static const char *max98088_exmode_texts[] = {
 337       "Off", "100Hz", "400Hz", "600Hz", "800Hz", "1000Hz", "200-400Hz",
 338       "400-600Hz", "400-800Hz",
 339};
 340
 341static const unsigned int max98088_exmode_values[] = {
 342       0x00, 0x43, 0x10, 0x20, 0x30, 0x40, 0x11, 0x22, 0x32
 343};
 344
 345static SOC_VALUE_ENUM_SINGLE_DECL(max98088_exmode_enum,
 346				  M98088_REG_41_SPKDHP, 0, 127,
 347				  max98088_exmode_texts,
 348				  max98088_exmode_values);
 349
 350static const char *max98088_ex_thresh[] = { /* volts PP */
 351       "0.6", "1.2", "1.8", "2.4", "3.0", "3.6", "4.2", "4.8"};
 352static SOC_ENUM_SINGLE_DECL(max98088_ex_thresh_enum,
 353			    M98088_REG_42_SPKDHP_THRESH, 0,
 354			    max98088_ex_thresh);
 355
 356static const char *max98088_fltr_mode[] = {"Voice", "Music" };
 357static SOC_ENUM_SINGLE_DECL(max98088_filter_mode_enum,
 358			    M98088_REG_18_DAI1_FILTERS, 7,
 359			    max98088_fltr_mode);
 360
 361static const char *max98088_extmic_text[] = { "None", "MIC1", "MIC2" };
 362
 363static SOC_ENUM_SINGLE_DECL(max98088_extmic_enum,
 364			    M98088_REG_48_CFG_MIC, 0,
 365			    max98088_extmic_text);
 366
 367static const struct snd_kcontrol_new max98088_extmic_mux =
 368       SOC_DAPM_ENUM("External MIC Mux", max98088_extmic_enum);
 369
 370static const char *max98088_dai1_fltr[] = {
 371       "Off", "fc=258/fs=16k", "fc=500/fs=16k",
 372       "fc=258/fs=8k", "fc=500/fs=8k", "fc=200"};
 373static SOC_ENUM_SINGLE_DECL(max98088_dai1_dac_filter_enum,
 374			    M98088_REG_18_DAI1_FILTERS, 0,
 375			    max98088_dai1_fltr);
 376static SOC_ENUM_SINGLE_DECL(max98088_dai1_adc_filter_enum,
 377			    M98088_REG_18_DAI1_FILTERS, 4,
 378			    max98088_dai1_fltr);
 379
 380static int max98088_mic1pre_set(struct snd_kcontrol *kcontrol,
 381                               struct snd_ctl_elem_value *ucontrol)
 382{
 383       struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
 384       struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
 385       unsigned int sel = ucontrol->value.integer.value[0];
 386
 387       max98088->mic1pre = sel;
 388       snd_soc_component_update_bits(component, M98088_REG_35_LVL_MIC1, M98088_MICPRE_MASK,
 389               (1+sel)<<M98088_MICPRE_SHIFT);
 390
 391       return 0;
 392}
 393
 394static int max98088_mic1pre_get(struct snd_kcontrol *kcontrol,
 395                               struct snd_ctl_elem_value *ucontrol)
 396{
 397       struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
 398       struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
 399
 400       ucontrol->value.integer.value[0] = max98088->mic1pre;
 401       return 0;
 402}
 403
 404static int max98088_mic2pre_set(struct snd_kcontrol *kcontrol,
 405                               struct snd_ctl_elem_value *ucontrol)
 406{
 407       struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
 408       struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
 409       unsigned int sel = ucontrol->value.integer.value[0];
 410
 411       max98088->mic2pre = sel;
 412       snd_soc_component_update_bits(component, M98088_REG_36_LVL_MIC2, M98088_MICPRE_MASK,
 413               (1+sel)<<M98088_MICPRE_SHIFT);
 414
 415       return 0;
 416}
 417
 418static int max98088_mic2pre_get(struct snd_kcontrol *kcontrol,
 419                               struct snd_ctl_elem_value *ucontrol)
 420{
 421       struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
 422       struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
 423
 424       ucontrol->value.integer.value[0] = max98088->mic2pre;
 425       return 0;
 426}
 427
 428static const DECLARE_TLV_DB_RANGE(max98088_micboost_tlv,
 429	0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0),
 430	2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0)
 431);
 432
 433static const DECLARE_TLV_DB_RANGE(max98088_hp_tlv,
 434	0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0),
 435	7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0),
 436	15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0),
 437	22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0),
 438	28, 31, TLV_DB_SCALE_ITEM(150, 50, 0)
 439);
 440
 441static const DECLARE_TLV_DB_RANGE(max98088_spk_tlv,
 442	0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0),
 443	7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0),
 444	15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0),
 445	22, 27, TLV_DB_SCALE_ITEM(100, 100, 0),
 446	28, 31, TLV_DB_SCALE_ITEM(650, 50, 0)
 447);
 448
 449static const struct snd_kcontrol_new max98088_snd_controls[] = {
 450
 451	SOC_DOUBLE_R_TLV("Headphone Volume", M98088_REG_39_LVL_HP_L,
 452			 M98088_REG_3A_LVL_HP_R, 0, 31, 0, max98088_hp_tlv),
 453	SOC_DOUBLE_R_TLV("Speaker Volume", M98088_REG_3D_LVL_SPK_L,
 454			 M98088_REG_3E_LVL_SPK_R, 0, 31, 0, max98088_spk_tlv),
 455	SOC_DOUBLE_R_TLV("Receiver Volume", M98088_REG_3B_LVL_REC_L,
 456			 M98088_REG_3C_LVL_REC_R, 0, 31, 0, max98088_spk_tlv),
 457
 458       SOC_DOUBLE_R("Headphone Switch", M98088_REG_39_LVL_HP_L,
 459               M98088_REG_3A_LVL_HP_R, 7, 1, 1),
 460       SOC_DOUBLE_R("Speaker Switch", M98088_REG_3D_LVL_SPK_L,
 461               M98088_REG_3E_LVL_SPK_R, 7, 1, 1),
 462       SOC_DOUBLE_R("Receiver Switch", M98088_REG_3B_LVL_REC_L,
 463               M98088_REG_3C_LVL_REC_R, 7, 1, 1),
 464
 465       SOC_SINGLE("MIC1 Volume", M98088_REG_35_LVL_MIC1, 0, 31, 1),
 466       SOC_SINGLE("MIC2 Volume", M98088_REG_36_LVL_MIC2, 0, 31, 1),
 467
 468       SOC_SINGLE_EXT_TLV("MIC1 Boost Volume",
 469                       M98088_REG_35_LVL_MIC1, 5, 2, 0,
 470                       max98088_mic1pre_get, max98088_mic1pre_set,
 471                       max98088_micboost_tlv),
 472       SOC_SINGLE_EXT_TLV("MIC2 Boost Volume",
 473                       M98088_REG_36_LVL_MIC2, 5, 2, 0,
 474                       max98088_mic2pre_get, max98088_mic2pre_set,
 475                       max98088_micboost_tlv),
 476
 477        SOC_SINGLE("Noise Gate Threshold", M98088_REG_40_MICAGC_THRESH,
 478               4, 15, 0),
 479
 480       SOC_SINGLE("INA Volume", M98088_REG_37_LVL_INA, 0, 7, 1),
 481       SOC_SINGLE("INB Volume", M98088_REG_38_LVL_INB, 0, 7, 1),
 482
 483       SOC_SINGLE("DACL Volume", M98088_REG_2F_LVL_DAI1_PLAY, 0, 15, 1),
 484       SOC_SINGLE("DACR Volume", M98088_REG_31_LVL_DAI2_PLAY, 0, 15, 1),
 485
 486       SOC_SINGLE("ADCL Volume", M98088_REG_33_LVL_ADC_L, 0, 15, 0),
 487       SOC_SINGLE("ADCR Volume", M98088_REG_34_LVL_ADC_R, 0, 15, 0),
 488
 489       SOC_SINGLE("ADCL Boost Volume", M98088_REG_33_LVL_ADC_L, 4, 3, 0),
 490       SOC_SINGLE("ADCR Boost Volume", M98088_REG_34_LVL_ADC_R, 4, 3, 0),
 491
 492       SOC_SINGLE("Left HP Output Mixer Switch", M98088_REG_27_MIX_HP_CNTL, 4, 1, 0),
 493       SOC_SINGLE("Right HP Output Mixer Switch", M98088_REG_27_MIX_HP_CNTL, 5, 1, 0),
 494
 495       SOC_SINGLE("EQ1 Switch", M98088_REG_49_CFG_LEVEL, 0, 1, 0),
 496       SOC_SINGLE("EQ2 Switch", M98088_REG_49_CFG_LEVEL, 1, 1, 0),
 497
 498       SOC_ENUM("EX Limiter Mode", max98088_exmode_enum),
 499       SOC_ENUM("EX Limiter Threshold", max98088_ex_thresh_enum),
 500
 501       SOC_ENUM("DAI1 Filter Mode", max98088_filter_mode_enum),
 502       SOC_ENUM("DAI1 DAC Filter", max98088_dai1_dac_filter_enum),
 503       SOC_ENUM("DAI1 ADC Filter", max98088_dai1_adc_filter_enum),
 504       SOC_SINGLE("DAI2 DC Block Switch", M98088_REG_20_DAI2_FILTERS,
 505               0, 1, 0),
 506
 507       SOC_SINGLE("ALC Switch", M98088_REG_43_SPKALC_COMP, 7, 1, 0),
 508       SOC_SINGLE("ALC Threshold", M98088_REG_43_SPKALC_COMP, 0, 7, 0),
 509       SOC_SINGLE("ALC Multiband", M98088_REG_43_SPKALC_COMP, 3, 1, 0),
 510       SOC_SINGLE("ALC Release Time", M98088_REG_43_SPKALC_COMP, 4, 7, 0),
 511
 512       SOC_SINGLE("PWR Limiter Threshold", M98088_REG_44_PWRLMT_CFG,
 513               4, 15, 0),
 514       SOC_SINGLE("PWR Limiter Weight", M98088_REG_44_PWRLMT_CFG, 0, 7, 0),
 515       SOC_SINGLE("PWR Limiter Time1", M98088_REG_45_PWRLMT_TIME, 0, 15, 0),
 516       SOC_SINGLE("PWR Limiter Time2", M98088_REG_45_PWRLMT_TIME, 4, 15, 0),
 517
 518       SOC_SINGLE("THD Limiter Threshold", M98088_REG_46_THDLMT_CFG, 4, 15, 0),
 519       SOC_SINGLE("THD Limiter Time", M98088_REG_46_THDLMT_CFG, 0, 7, 0),
 520};
 521
 522/* Left speaker mixer switch */
 523static const struct snd_kcontrol_new max98088_left_speaker_mixer_controls[] = {
 524       SOC_DAPM_SINGLE("Left DAC Switch", M98088_REG_2B_MIX_SPK_LEFT, 0, 1, 0),
 525       SOC_DAPM_SINGLE("Right DAC Switch", M98088_REG_2B_MIX_SPK_LEFT, 7, 1, 0),
 
 
 526       SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 5, 1, 0),
 527       SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 6, 1, 0),
 528       SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 1, 1, 0),
 529       SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 2, 1, 0),
 530       SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 3, 1, 0),
 531       SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 4, 1, 0),
 532};
 533
 534/* Right speaker mixer switch */
 535static const struct snd_kcontrol_new max98088_right_speaker_mixer_controls[] = {
 536       SOC_DAPM_SINGLE("Left DAC Switch", M98088_REG_2C_MIX_SPK_RIGHT, 7, 1, 0),
 537       SOC_DAPM_SINGLE("Right DAC Switch", M98088_REG_2C_MIX_SPK_RIGHT, 0, 1, 0),
 
 
 538       SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 5, 1, 0),
 539       SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 6, 1, 0),
 540       SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 1, 1, 0),
 541       SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 2, 1, 0),
 542       SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 3, 1, 0),
 543       SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 4, 1, 0),
 544};
 545
 546/* Left headphone mixer switch */
 547static const struct snd_kcontrol_new max98088_left_hp_mixer_controls[] = {
 548       SOC_DAPM_SINGLE("Left DAC Switch", M98088_REG_25_MIX_HP_LEFT, 0, 1, 0),
 549       SOC_DAPM_SINGLE("Right DAC Switch", M98088_REG_25_MIX_HP_LEFT, 7, 1, 0),
 
 
 550       SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_25_MIX_HP_LEFT, 5, 1, 0),
 551       SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_25_MIX_HP_LEFT, 6, 1, 0),
 552       SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_25_MIX_HP_LEFT, 1, 1, 0),
 553       SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_25_MIX_HP_LEFT, 2, 1, 0),
 554       SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_25_MIX_HP_LEFT, 3, 1, 0),
 555       SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_25_MIX_HP_LEFT, 4, 1, 0),
 556};
 557
 558/* Right headphone mixer switch */
 559static const struct snd_kcontrol_new max98088_right_hp_mixer_controls[] = {
 560       SOC_DAPM_SINGLE("Left DAC Switch", M98088_REG_26_MIX_HP_RIGHT, 7, 1, 0),
 561       SOC_DAPM_SINGLE("Right DAC Switch", M98088_REG_26_MIX_HP_RIGHT, 0, 1, 0),
 
 
 562       SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_26_MIX_HP_RIGHT, 5, 1, 0),
 563       SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_26_MIX_HP_RIGHT, 6, 1, 0),
 564       SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_26_MIX_HP_RIGHT, 1, 1, 0),
 565       SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_26_MIX_HP_RIGHT, 2, 1, 0),
 566       SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_26_MIX_HP_RIGHT, 3, 1, 0),
 567       SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_26_MIX_HP_RIGHT, 4, 1, 0),
 568};
 569
 570/* Left earpiece/receiver mixer switch */
 571static const struct snd_kcontrol_new max98088_left_rec_mixer_controls[] = {
 572       SOC_DAPM_SINGLE("Left DAC Switch", M98088_REG_28_MIX_REC_LEFT, 0, 1, 0),
 573       SOC_DAPM_SINGLE("Right DAC Switch", M98088_REG_28_MIX_REC_LEFT, 7, 1, 0),
 
 
 574       SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_28_MIX_REC_LEFT, 5, 1, 0),
 575       SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_28_MIX_REC_LEFT, 6, 1, 0),
 576       SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_28_MIX_REC_LEFT, 1, 1, 0),
 577       SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_28_MIX_REC_LEFT, 2, 1, 0),
 578       SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_28_MIX_REC_LEFT, 3, 1, 0),
 579       SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_28_MIX_REC_LEFT, 4, 1, 0),
 580};
 581
 582/* Right earpiece/receiver mixer switch */
 583static const struct snd_kcontrol_new max98088_right_rec_mixer_controls[] = {
 584       SOC_DAPM_SINGLE("Left DAC Switch", M98088_REG_29_MIX_REC_RIGHT, 7, 1, 0),
 585       SOC_DAPM_SINGLE("Right DAC Switch", M98088_REG_29_MIX_REC_RIGHT, 0, 1, 0),
 
 
 586       SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_29_MIX_REC_RIGHT, 5, 1, 0),
 587       SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_29_MIX_REC_RIGHT, 6, 1, 0),
 588       SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_29_MIX_REC_RIGHT, 1, 1, 0),
 589       SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_29_MIX_REC_RIGHT, 2, 1, 0),
 590       SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_29_MIX_REC_RIGHT, 3, 1, 0),
 591       SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_29_MIX_REC_RIGHT, 4, 1, 0),
 592};
 593
 594/* Left ADC mixer switch */
 595static const struct snd_kcontrol_new max98088_left_ADC_mixer_controls[] = {
 596       SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_23_MIX_ADC_LEFT, 7, 1, 0),
 597       SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_23_MIX_ADC_LEFT, 6, 1, 0),
 598       SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_23_MIX_ADC_LEFT, 3, 1, 0),
 599       SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_23_MIX_ADC_LEFT, 2, 1, 0),
 600       SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_23_MIX_ADC_LEFT, 1, 1, 0),
 601       SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_23_MIX_ADC_LEFT, 0, 1, 0),
 602};
 603
 604/* Right ADC mixer switch */
 605static const struct snd_kcontrol_new max98088_right_ADC_mixer_controls[] = {
 606       SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 7, 1, 0),
 607       SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 6, 1, 0),
 608       SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 3, 1, 0),
 609       SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 2, 1, 0),
 610       SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 1, 1, 0),
 611       SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 0, 1, 0),
 612};
 613
 614static int max98088_mic_event(struct snd_soc_dapm_widget *w,
 615                            struct snd_kcontrol *kcontrol, int event)
 616{
 617       struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 618       struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
 619
 620       switch (event) {
 621       case SND_SOC_DAPM_POST_PMU:
 622               if (w->reg == M98088_REG_35_LVL_MIC1) {
 623                       snd_soc_component_update_bits(component, w->reg, M98088_MICPRE_MASK,
 624                               (1+max98088->mic1pre)<<M98088_MICPRE_SHIFT);
 625               } else {
 626                       snd_soc_component_update_bits(component, w->reg, M98088_MICPRE_MASK,
 627                               (1+max98088->mic2pre)<<M98088_MICPRE_SHIFT);
 628               }
 629               break;
 630       case SND_SOC_DAPM_POST_PMD:
 631               snd_soc_component_update_bits(component, w->reg, M98088_MICPRE_MASK, 0);
 632               break;
 633       default:
 634               return -EINVAL;
 635       }
 636
 637       return 0;
 638}
 639
 640/*
 641 * The line inputs are 2-channel stereo inputs with the left
 642 * and right channels sharing a common PGA power control signal.
 643 */
 644static int max98088_line_pga(struct snd_soc_dapm_widget *w,
 645                            int event, int line, u8 channel)
 646{
 647       struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 648       struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
 649       u8 *state;
 650
 651	if (WARN_ON(!(channel == 1 || channel == 2)))
 652		return -EINVAL;
 653
 654       switch (line) {
 655       case LINE_INA:
 656               state = &max98088->ina_state;
 657               break;
 658       case LINE_INB:
 659               state = &max98088->inb_state;
 660               break;
 661       default:
 662               return -EINVAL;
 663       }
 664
 665       switch (event) {
 666       case SND_SOC_DAPM_POST_PMU:
 667               *state |= channel;
 668               snd_soc_component_update_bits(component, w->reg,
 669                       (1 << w->shift), (1 << w->shift));
 670               break;
 671       case SND_SOC_DAPM_POST_PMD:
 672               *state &= ~channel;
 673               if (*state == 0) {
 674                       snd_soc_component_update_bits(component, w->reg,
 675                               (1 << w->shift), 0);
 676               }
 677               break;
 678       default:
 679               return -EINVAL;
 680       }
 681
 682       return 0;
 683}
 684
 685static int max98088_pga_ina1_event(struct snd_soc_dapm_widget *w,
 686                                  struct snd_kcontrol *k, int event)
 687{
 688       return max98088_line_pga(w, event, LINE_INA, 1);
 689}
 690
 691static int max98088_pga_ina2_event(struct snd_soc_dapm_widget *w,
 692                                  struct snd_kcontrol *k, int event)
 693{
 694       return max98088_line_pga(w, event, LINE_INA, 2);
 695}
 696
 697static int max98088_pga_inb1_event(struct snd_soc_dapm_widget *w,
 698                                  struct snd_kcontrol *k, int event)
 699{
 700       return max98088_line_pga(w, event, LINE_INB, 1);
 701}
 702
 703static int max98088_pga_inb2_event(struct snd_soc_dapm_widget *w,
 704                                  struct snd_kcontrol *k, int event)
 705{
 706       return max98088_line_pga(w, event, LINE_INB, 2);
 707}
 708
 709static const struct snd_soc_dapm_widget max98088_dapm_widgets[] = {
 710
 711       SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", M98088_REG_4C_PWR_EN_IN, 1, 0),
 712       SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", M98088_REG_4C_PWR_EN_IN, 0, 0),
 713
 714       SND_SOC_DAPM_DAC("DACL", "HiFi Playback",
 
 
 
 
 715               M98088_REG_4D_PWR_EN_OUT, 1, 0),
 716       SND_SOC_DAPM_DAC("DACR", "HiFi Playback",
 717               M98088_REG_4D_PWR_EN_OUT, 0, 0),
 718
 719       SND_SOC_DAPM_PGA("HP Left Out", M98088_REG_4D_PWR_EN_OUT,
 720               7, 0, NULL, 0),
 721       SND_SOC_DAPM_PGA("HP Right Out", M98088_REG_4D_PWR_EN_OUT,
 722               6, 0, NULL, 0),
 723
 724       SND_SOC_DAPM_PGA("SPK Left Out", M98088_REG_4D_PWR_EN_OUT,
 725               5, 0, NULL, 0),
 726       SND_SOC_DAPM_PGA("SPK Right Out", M98088_REG_4D_PWR_EN_OUT,
 727               4, 0, NULL, 0),
 728
 729       SND_SOC_DAPM_PGA("REC Left Out", M98088_REG_4D_PWR_EN_OUT,
 730               3, 0, NULL, 0),
 731       SND_SOC_DAPM_PGA("REC Right Out", M98088_REG_4D_PWR_EN_OUT,
 732               2, 0, NULL, 0),
 733
 734       SND_SOC_DAPM_MUX("External MIC", SND_SOC_NOPM, 0, 0,
 735               &max98088_extmic_mux),
 736
 737       SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
 738               &max98088_left_hp_mixer_controls[0],
 739               ARRAY_SIZE(max98088_left_hp_mixer_controls)),
 740
 741       SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
 742               &max98088_right_hp_mixer_controls[0],
 743               ARRAY_SIZE(max98088_right_hp_mixer_controls)),
 744
 745       SND_SOC_DAPM_MIXER("Left SPK Mixer", SND_SOC_NOPM, 0, 0,
 746               &max98088_left_speaker_mixer_controls[0],
 747               ARRAY_SIZE(max98088_left_speaker_mixer_controls)),
 748
 749       SND_SOC_DAPM_MIXER("Right SPK Mixer", SND_SOC_NOPM, 0, 0,
 750               &max98088_right_speaker_mixer_controls[0],
 751               ARRAY_SIZE(max98088_right_speaker_mixer_controls)),
 752
 753       SND_SOC_DAPM_MIXER("Left REC Mixer", SND_SOC_NOPM, 0, 0,
 754         &max98088_left_rec_mixer_controls[0],
 755               ARRAY_SIZE(max98088_left_rec_mixer_controls)),
 756
 757       SND_SOC_DAPM_MIXER("Right REC Mixer", SND_SOC_NOPM, 0, 0,
 758         &max98088_right_rec_mixer_controls[0],
 759               ARRAY_SIZE(max98088_right_rec_mixer_controls)),
 760
 761       SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
 762               &max98088_left_ADC_mixer_controls[0],
 763               ARRAY_SIZE(max98088_left_ADC_mixer_controls)),
 764
 765       SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
 766               &max98088_right_ADC_mixer_controls[0],
 767               ARRAY_SIZE(max98088_right_ADC_mixer_controls)),
 768
 769       SND_SOC_DAPM_PGA_E("MIC1 Input", M98088_REG_35_LVL_MIC1,
 770               5, 0, NULL, 0, max98088_mic_event,
 771               SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
 772
 773       SND_SOC_DAPM_PGA_E("MIC2 Input", M98088_REG_36_LVL_MIC2,
 774               5, 0, NULL, 0, max98088_mic_event,
 775               SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
 776
 777       SND_SOC_DAPM_PGA_E("INA1 Input", M98088_REG_4C_PWR_EN_IN,
 778               7, 0, NULL, 0, max98088_pga_ina1_event,
 779               SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
 780
 781       SND_SOC_DAPM_PGA_E("INA2 Input", M98088_REG_4C_PWR_EN_IN,
 782               7, 0, NULL, 0, max98088_pga_ina2_event,
 783               SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
 784
 785       SND_SOC_DAPM_PGA_E("INB1 Input", M98088_REG_4C_PWR_EN_IN,
 786               6, 0, NULL, 0, max98088_pga_inb1_event,
 787               SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
 788
 789       SND_SOC_DAPM_PGA_E("INB2 Input", M98088_REG_4C_PWR_EN_IN,
 790               6, 0, NULL, 0, max98088_pga_inb2_event,
 791               SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
 792
 793       SND_SOC_DAPM_MICBIAS("MICBIAS", M98088_REG_4C_PWR_EN_IN, 3, 0),
 794
 795       SND_SOC_DAPM_OUTPUT("HPL"),
 796       SND_SOC_DAPM_OUTPUT("HPR"),
 797       SND_SOC_DAPM_OUTPUT("SPKL"),
 798       SND_SOC_DAPM_OUTPUT("SPKR"),
 799       SND_SOC_DAPM_OUTPUT("RECL"),
 800       SND_SOC_DAPM_OUTPUT("RECR"),
 801
 802       SND_SOC_DAPM_INPUT("MIC1"),
 803       SND_SOC_DAPM_INPUT("MIC2"),
 804       SND_SOC_DAPM_INPUT("INA1"),
 805       SND_SOC_DAPM_INPUT("INA2"),
 806       SND_SOC_DAPM_INPUT("INB1"),
 807       SND_SOC_DAPM_INPUT("INB2"),
 808};
 809
 810static const struct snd_soc_dapm_route max98088_audio_map[] = {
 811       /* Left headphone output mixer */
 812       {"Left HP Mixer", "Left DAC Switch", "DACL"},
 813       {"Left HP Mixer", "Right DAC Switch", "DACR"},
 
 
 814       {"Left HP Mixer", "MIC1 Switch", "MIC1 Input"},
 815       {"Left HP Mixer", "MIC2 Switch", "MIC2 Input"},
 816       {"Left HP Mixer", "INA1 Switch", "INA1 Input"},
 817       {"Left HP Mixer", "INA2 Switch", "INA2 Input"},
 818       {"Left HP Mixer", "INB1 Switch", "INB1 Input"},
 819       {"Left HP Mixer", "INB2 Switch", "INB2 Input"},
 820
 821       /* Right headphone output mixer */
 822       {"Right HP Mixer", "Left DAC Switch", "DACL"},
 823       {"Right HP Mixer", "Right DAC Switch", "DACR"},
 
 
 824       {"Right HP Mixer", "MIC1 Switch", "MIC1 Input"},
 825       {"Right HP Mixer", "MIC2 Switch", "MIC2 Input"},
 826       {"Right HP Mixer", "INA1 Switch", "INA1 Input"},
 827       {"Right HP Mixer", "INA2 Switch", "INA2 Input"},
 828       {"Right HP Mixer", "INB1 Switch", "INB1 Input"},
 829       {"Right HP Mixer", "INB2 Switch", "INB2 Input"},
 830
 831       /* Left speaker output mixer */
 832       {"Left SPK Mixer", "Left DAC Switch", "DACL"},
 833       {"Left SPK Mixer", "Right DAC Switch", "DACR"},
 
 
 834       {"Left SPK Mixer", "MIC1 Switch", "MIC1 Input"},
 835       {"Left SPK Mixer", "MIC2 Switch", "MIC2 Input"},
 836       {"Left SPK Mixer", "INA1 Switch", "INA1 Input"},
 837       {"Left SPK Mixer", "INA2 Switch", "INA2 Input"},
 838       {"Left SPK Mixer", "INB1 Switch", "INB1 Input"},
 839       {"Left SPK Mixer", "INB2 Switch", "INB2 Input"},
 840
 841       /* Right speaker output mixer */
 842       {"Right SPK Mixer", "Left DAC Switch", "DACL"},
 843       {"Right SPK Mixer", "Right DAC Switch", "DACR"},
 
 
 844       {"Right SPK Mixer", "MIC1 Switch", "MIC1 Input"},
 845       {"Right SPK Mixer", "MIC2 Switch", "MIC2 Input"},
 846       {"Right SPK Mixer", "INA1 Switch", "INA1 Input"},
 847       {"Right SPK Mixer", "INA2 Switch", "INA2 Input"},
 848       {"Right SPK Mixer", "INB1 Switch", "INB1 Input"},
 849       {"Right SPK Mixer", "INB2 Switch", "INB2 Input"},
 850
 851       /* Earpiece/Receiver output mixer */
 852       {"Left REC Mixer", "Left DAC Switch", "DACL"},
 853       {"Left REC Mixer", "Right DAC Switch", "DACR"},
 
 
 854       {"Left REC Mixer", "MIC1 Switch", "MIC1 Input"},
 855       {"Left REC Mixer", "MIC2 Switch", "MIC2 Input"},
 856       {"Left REC Mixer", "INA1 Switch", "INA1 Input"},
 857       {"Left REC Mixer", "INA2 Switch", "INA2 Input"},
 858       {"Left REC Mixer", "INB1 Switch", "INB1 Input"},
 859       {"Left REC Mixer", "INB2 Switch", "INB2 Input"},
 860
 861       /* Earpiece/Receiver output mixer */
 862       {"Right REC Mixer", "Left DAC Switch", "DACL"},
 863       {"Right REC Mixer", "Right DAC Switch", "DACR"},
 
 
 864       {"Right REC Mixer", "MIC1 Switch", "MIC1 Input"},
 865       {"Right REC Mixer", "MIC2 Switch", "MIC2 Input"},
 866       {"Right REC Mixer", "INA1 Switch", "INA1 Input"},
 867       {"Right REC Mixer", "INA2 Switch", "INA2 Input"},
 868       {"Right REC Mixer", "INB1 Switch", "INB1 Input"},
 869       {"Right REC Mixer", "INB2 Switch", "INB2 Input"},
 870
 871       {"HP Left Out", NULL, "Left HP Mixer"},
 872       {"HP Right Out", NULL, "Right HP Mixer"},
 873       {"SPK Left Out", NULL, "Left SPK Mixer"},
 874       {"SPK Right Out", NULL, "Right SPK Mixer"},
 875       {"REC Left Out", NULL, "Left REC Mixer"},
 876       {"REC Right Out", NULL, "Right REC Mixer"},
 877
 878       {"HPL", NULL, "HP Left Out"},
 879       {"HPR", NULL, "HP Right Out"},
 880       {"SPKL", NULL, "SPK Left Out"},
 881       {"SPKR", NULL, "SPK Right Out"},
 882       {"RECL", NULL, "REC Left Out"},
 883       {"RECR", NULL, "REC Right Out"},
 884
 885       /* Left ADC input mixer */
 886       {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"},
 887       {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"},
 888       {"Left ADC Mixer", "INA1 Switch", "INA1 Input"},
 889       {"Left ADC Mixer", "INA2 Switch", "INA2 Input"},
 890       {"Left ADC Mixer", "INB1 Switch", "INB1 Input"},
 891       {"Left ADC Mixer", "INB2 Switch", "INB2 Input"},
 892
 893       /* Right ADC input mixer */
 894       {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"},
 895       {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"},
 896       {"Right ADC Mixer", "INA1 Switch", "INA1 Input"},
 897       {"Right ADC Mixer", "INA2 Switch", "INA2 Input"},
 898       {"Right ADC Mixer", "INB1 Switch", "INB1 Input"},
 899       {"Right ADC Mixer", "INB2 Switch", "INB2 Input"},
 900
 901       /* Inputs */
 902       {"ADCL", NULL, "Left ADC Mixer"},
 903       {"ADCR", NULL, "Right ADC Mixer"},
 904       {"INA1 Input", NULL, "INA1"},
 905       {"INA2 Input", NULL, "INA2"},
 906       {"INB1 Input", NULL, "INB1"},
 907       {"INB2 Input", NULL, "INB2"},
 908       {"MIC1 Input", NULL, "MIC1"},
 909       {"MIC2 Input", NULL, "MIC2"},
 910};
 911
 912/* codec mclk clock divider coefficients */
 913static const struct {
 914       u32 rate;
 915       u8  sr;
 916} rate_table[] = {
 917       {8000,  0x10},
 918       {11025, 0x20},
 919       {16000, 0x30},
 920       {22050, 0x40},
 921       {24000, 0x50},
 922       {32000, 0x60},
 923       {44100, 0x70},
 924       {48000, 0x80},
 925       {88200, 0x90},
 926       {96000, 0xA0},
 927};
 928
 929static inline int rate_value(int rate, u8 *value)
 930{
 931       int i;
 932
 933       for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
 934               if (rate_table[i].rate >= rate) {
 935                       *value = rate_table[i].sr;
 936                       return 0;
 937               }
 938       }
 939       *value = rate_table[0].sr;
 940       return -EINVAL;
 941}
 942
 943static int max98088_dai1_hw_params(struct snd_pcm_substream *substream,
 944                                  struct snd_pcm_hw_params *params,
 945                                  struct snd_soc_dai *dai)
 946{
 947       struct snd_soc_component *component = dai->component;
 948       struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
 949       struct max98088_cdata *cdata;
 950       unsigned long long ni;
 951       unsigned int rate;
 952       u8 regval;
 953
 954       cdata = &max98088->dai[0];
 955
 956       rate = params_rate(params);
 957
 958       switch (params_width(params)) {
 959       case 16:
 960               snd_soc_component_update_bits(component, M98088_REG_14_DAI1_FORMAT,
 961                       M98088_DAI_WS, 0);
 962               break;
 963       case 24:
 964               snd_soc_component_update_bits(component, M98088_REG_14_DAI1_FORMAT,
 965                       M98088_DAI_WS, M98088_DAI_WS);
 966               break;
 967       default:
 968               return -EINVAL;
 969       }
 970
 971       snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 0);
 972
 973       if (rate_value(rate, &regval))
 974               return -EINVAL;
 975
 976       snd_soc_component_update_bits(component, M98088_REG_11_DAI1_CLKMODE,
 977               M98088_CLKMODE_MASK, regval);
 978       cdata->rate = rate;
 979
 980       /* Configure NI when operating as master */
 981       if (snd_soc_component_read(component, M98088_REG_14_DAI1_FORMAT)
 982               & M98088_DAI_MAS) {
 983               unsigned long pclk;
 984
 985               if (max98088->sysclk == 0) {
 986                       dev_err(component->dev, "Invalid system clock frequency\n");
 987                       return -EINVAL;
 988               }
 989               ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
 990                               * (unsigned long long int)rate;
 991               pclk = DIV_ROUND_CLOSEST(max98088->sysclk, max98088->mclk_prescaler);
 992               ni = DIV_ROUND_CLOSEST_ULL(ni, pclk);
 993               snd_soc_component_write(component, M98088_REG_12_DAI1_CLKCFG_HI,
 994                       (ni >> 8) & 0x7F);
 995               snd_soc_component_write(component, M98088_REG_13_DAI1_CLKCFG_LO,
 996                       ni & 0xFF);
 997       }
 998
 999       /* Update sample rate mode */
1000       if (rate < 50000)
1001               snd_soc_component_update_bits(component, M98088_REG_18_DAI1_FILTERS,
1002                       M98088_DAI_DHF, 0);
1003       else
1004               snd_soc_component_update_bits(component, M98088_REG_18_DAI1_FILTERS,
1005                       M98088_DAI_DHF, M98088_DAI_DHF);
1006
1007       snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS, M98088_SHDNRUN,
1008               M98088_SHDNRUN);
1009
1010       return 0;
1011}
1012
1013static int max98088_dai2_hw_params(struct snd_pcm_substream *substream,
1014                                  struct snd_pcm_hw_params *params,
1015                                  struct snd_soc_dai *dai)
1016{
1017       struct snd_soc_component *component = dai->component;
1018       struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
1019       struct max98088_cdata *cdata;
1020       unsigned long long ni;
1021       unsigned int rate;
1022       u8 regval;
1023
1024       cdata = &max98088->dai[1];
1025
1026       rate = params_rate(params);
1027
1028       switch (params_width(params)) {
1029       case 16:
1030               snd_soc_component_update_bits(component, M98088_REG_1C_DAI2_FORMAT,
1031                       M98088_DAI_WS, 0);
1032               break;
1033       case 24:
1034               snd_soc_component_update_bits(component, M98088_REG_1C_DAI2_FORMAT,
1035                       M98088_DAI_WS, M98088_DAI_WS);
1036               break;
1037       default:
1038               return -EINVAL;
1039       }
1040
1041       snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 0);
1042
1043       if (rate_value(rate, &regval))
1044               return -EINVAL;
1045
1046       snd_soc_component_update_bits(component, M98088_REG_19_DAI2_CLKMODE,
1047               M98088_CLKMODE_MASK, regval);
1048       cdata->rate = rate;
1049
1050       /* Configure NI when operating as master */
1051       if (snd_soc_component_read(component, M98088_REG_1C_DAI2_FORMAT)
1052               & M98088_DAI_MAS) {
1053               unsigned long pclk;
1054
1055               if (max98088->sysclk == 0) {
1056                       dev_err(component->dev, "Invalid system clock frequency\n");
1057                       return -EINVAL;
1058               }
1059               ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL)
1060                               * (unsigned long long int)rate;
1061               pclk = DIV_ROUND_CLOSEST(max98088->sysclk, max98088->mclk_prescaler);
1062               ni = DIV_ROUND_CLOSEST_ULL(ni, pclk);
1063               snd_soc_component_write(component, M98088_REG_1A_DAI2_CLKCFG_HI,
1064                       (ni >> 8) & 0x7F);
1065               snd_soc_component_write(component, M98088_REG_1B_DAI2_CLKCFG_LO,
1066                       ni & 0xFF);
1067       }
1068
1069       /* Update sample rate mode */
1070       if (rate < 50000)
1071               snd_soc_component_update_bits(component, M98088_REG_20_DAI2_FILTERS,
1072                       M98088_DAI_DHF, 0);
1073       else
1074               snd_soc_component_update_bits(component, M98088_REG_20_DAI2_FILTERS,
1075                       M98088_DAI_DHF, M98088_DAI_DHF);
1076
1077       snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS, M98088_SHDNRUN,
1078               M98088_SHDNRUN);
1079
1080       return 0;
1081}
1082
1083static int max98088_dai_set_sysclk(struct snd_soc_dai *dai,
1084                                  int clk_id, unsigned int freq, int dir)
1085{
1086       struct snd_soc_component *component = dai->component;
1087       struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
1088
1089       /* Requested clock frequency is already setup */
1090       if (freq == max98088->sysclk)
1091               return 0;
1092
1093	if (!IS_ERR(max98088->mclk)) {
1094		freq = clk_round_rate(max98088->mclk, freq);
1095		clk_set_rate(max98088->mclk, freq);
1096	}
1097
1098       /* Setup clocks for slave mode, and using the PLL
1099        * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
1100        *         0x02 (when master clk is 20MHz to 30MHz)..
1101        */
1102       if ((freq >= 10000000) && (freq < 20000000)) {
1103               snd_soc_component_write(component, M98088_REG_10_SYS_CLK, 0x10);
1104               max98088->mclk_prescaler = 1;
1105       } else if ((freq >= 20000000) && (freq < 30000000)) {
1106               snd_soc_component_write(component, M98088_REG_10_SYS_CLK, 0x20);
1107               max98088->mclk_prescaler = 2;
1108       } else {
1109               dev_err(component->dev, "Invalid master clock frequency\n");
1110               return -EINVAL;
1111       }
1112
1113       if (snd_soc_component_read(component, M98088_REG_51_PWR_SYS)  & M98088_SHDNRUN) {
1114               snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS,
1115                       M98088_SHDNRUN, 0);
1116               snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS,
1117                       M98088_SHDNRUN, M98088_SHDNRUN);
1118       }
1119
1120       dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq);
1121
1122       max98088->sysclk = freq;
1123       return 0;
1124}
1125
1126static int max98088_dai1_set_fmt(struct snd_soc_dai *codec_dai,
1127                                unsigned int fmt)
1128{
1129       struct snd_soc_component *component = codec_dai->component;
1130       struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
1131       struct max98088_cdata *cdata;
1132       u8 reg15val;
1133       u8 reg14val = 0;
1134
1135       cdata = &max98088->dai[0];
1136
1137       if (fmt != cdata->fmt) {
1138               cdata->fmt = fmt;
1139
1140               switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
1141               case SND_SOC_DAIFMT_CBC_CFC:
1142                       /* Consumer mode PLL */
1143                       snd_soc_component_write(component, M98088_REG_12_DAI1_CLKCFG_HI,
1144                               0x80);
1145                       snd_soc_component_write(component, M98088_REG_13_DAI1_CLKCFG_LO,
1146                               0x00);
1147                       break;
1148               case SND_SOC_DAIFMT_CBP_CFP:
1149                       /* Set to provider mode */
1150                       reg14val |= M98088_DAI_MAS;
1151                       break;
 
 
1152               default:
1153                       dev_err(component->dev, "Clock mode unsupported");
1154                       return -EINVAL;
1155               }
1156
1157               switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1158               case SND_SOC_DAIFMT_I2S:
1159                       reg14val |= M98088_DAI_DLY;
1160                       break;
1161               case SND_SOC_DAIFMT_LEFT_J:
1162                       break;
1163               default:
1164                       return -EINVAL;
1165               }
1166
1167               switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1168               case SND_SOC_DAIFMT_NB_NF:
1169                       break;
1170               case SND_SOC_DAIFMT_NB_IF:
1171                       reg14val |= M98088_DAI_WCI;
1172                       break;
1173               case SND_SOC_DAIFMT_IB_NF:
1174                       reg14val |= M98088_DAI_BCI;
1175                       break;
1176               case SND_SOC_DAIFMT_IB_IF:
1177                       reg14val |= M98088_DAI_BCI|M98088_DAI_WCI;
1178                       break;
1179               default:
1180                       return -EINVAL;
1181               }
1182
1183               snd_soc_component_update_bits(component, M98088_REG_14_DAI1_FORMAT,
1184                       M98088_DAI_MAS | M98088_DAI_DLY | M98088_DAI_BCI |
1185                       M98088_DAI_WCI, reg14val);
1186
1187               reg15val = M98088_DAI_BSEL64;
1188               if (max98088->digmic)
1189                       reg15val |= M98088_DAI_OSR64;
1190               snd_soc_component_write(component, M98088_REG_15_DAI1_CLOCK, reg15val);
1191       }
1192
1193       return 0;
1194}
1195
1196static int max98088_dai2_set_fmt(struct snd_soc_dai *codec_dai,
1197                                unsigned int fmt)
1198{
1199       struct snd_soc_component *component = codec_dai->component;
1200       struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
1201       struct max98088_cdata *cdata;
1202       u8 reg1Cval = 0;
1203
1204       cdata = &max98088->dai[1];
1205
1206       if (fmt != cdata->fmt) {
1207               cdata->fmt = fmt;
1208
1209               switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
1210               case SND_SOC_DAIFMT_CBC_CFC:
1211                       /* Consumer mode PLL */
1212                       snd_soc_component_write(component, M98088_REG_1A_DAI2_CLKCFG_HI,
1213                               0x80);
1214                       snd_soc_component_write(component, M98088_REG_1B_DAI2_CLKCFG_LO,
1215                               0x00);
1216                       break;
1217               case SND_SOC_DAIFMT_CBP_CFP:
1218                       /* Set to provider mode */
1219                       reg1Cval |= M98088_DAI_MAS;
1220                       break;
 
 
1221               default:
1222                       dev_err(component->dev, "Clock mode unsupported");
1223                       return -EINVAL;
1224               }
1225
1226               switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1227               case SND_SOC_DAIFMT_I2S:
1228                       reg1Cval |= M98088_DAI_DLY;
1229                       break;
1230               case SND_SOC_DAIFMT_LEFT_J:
1231                       break;
1232               default:
1233                       return -EINVAL;
1234               }
1235
1236               switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1237               case SND_SOC_DAIFMT_NB_NF:
1238                       break;
1239               case SND_SOC_DAIFMT_NB_IF:
1240                       reg1Cval |= M98088_DAI_WCI;
1241                       break;
1242               case SND_SOC_DAIFMT_IB_NF:
1243                       reg1Cval |= M98088_DAI_BCI;
1244                       break;
1245               case SND_SOC_DAIFMT_IB_IF:
1246                       reg1Cval |= M98088_DAI_BCI|M98088_DAI_WCI;
1247                       break;
1248               default:
1249                       return -EINVAL;
1250               }
1251
1252               snd_soc_component_update_bits(component, M98088_REG_1C_DAI2_FORMAT,
1253                       M98088_DAI_MAS | M98088_DAI_DLY | M98088_DAI_BCI |
1254                       M98088_DAI_WCI, reg1Cval);
1255
1256               snd_soc_component_write(component, M98088_REG_1D_DAI2_CLOCK,
1257                       M98088_DAI_BSEL64);
1258       }
1259
1260       return 0;
1261}
1262
1263static int max98088_dai1_mute(struct snd_soc_dai *codec_dai, int mute,
1264			      int direction)
1265{
1266       struct snd_soc_component *component = codec_dai->component;
1267       int reg;
1268
1269       if (mute)
1270               reg = M98088_DAI_MUTE;
1271       else
1272               reg = 0;
1273
1274       snd_soc_component_update_bits(component, M98088_REG_2F_LVL_DAI1_PLAY,
1275                           M98088_DAI_MUTE_MASK, reg);
1276       return 0;
1277}
1278
1279static int max98088_dai2_mute(struct snd_soc_dai *codec_dai, int mute,
1280			      int direction)
1281{
1282       struct snd_soc_component *component = codec_dai->component;
1283       int reg;
1284
1285       if (mute)
1286               reg = M98088_DAI_MUTE;
1287       else
1288               reg = 0;
1289
1290       snd_soc_component_update_bits(component, M98088_REG_31_LVL_DAI2_PLAY,
1291                           M98088_DAI_MUTE_MASK, reg);
1292       return 0;
1293}
1294
1295static int max98088_set_bias_level(struct snd_soc_component *component,
1296                                  enum snd_soc_bias_level level)
1297{
1298	struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
1299	int ret;
1300
1301	switch (level) {
1302	case SND_SOC_BIAS_ON:
1303		break;
1304
1305	case SND_SOC_BIAS_PREPARE:
1306		/*
1307		 * SND_SOC_BIAS_PREPARE is called while preparing for a
1308		 * transition to ON or away from ON. If current bias_level
1309		 * is SND_SOC_BIAS_ON, then it is preparing for a transition
1310		 * away from ON. Disable the clock in that case, otherwise
1311		 * enable it.
1312		 */
1313		if (!IS_ERR(max98088->mclk)) {
1314			if (snd_soc_component_get_bias_level(component) ==
1315			    SND_SOC_BIAS_ON) {
1316				clk_disable_unprepare(max98088->mclk);
1317			} else {
1318				ret = clk_prepare_enable(max98088->mclk);
1319				if (ret)
1320					return ret;
1321			}
1322		}
1323		break;
1324
1325	case SND_SOC_BIAS_STANDBY:
1326		if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
1327			regcache_sync(max98088->regmap);
1328
1329		snd_soc_component_update_bits(component, M98088_REG_4C_PWR_EN_IN,
1330				   M98088_MBEN, M98088_MBEN);
1331		break;
1332
1333	case SND_SOC_BIAS_OFF:
1334		snd_soc_component_update_bits(component, M98088_REG_4C_PWR_EN_IN,
1335				    M98088_MBEN, 0);
1336		regcache_mark_dirty(max98088->regmap);
1337		break;
1338	}
1339	return 0;
1340}
1341
1342#define MAX98088_RATES SNDRV_PCM_RATE_8000_96000
1343#define MAX98088_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
1344
1345static const struct snd_soc_dai_ops max98088_dai1_ops = {
1346       .set_sysclk = max98088_dai_set_sysclk,
1347       .set_fmt = max98088_dai1_set_fmt,
1348       .hw_params = max98088_dai1_hw_params,
1349       .mute_stream = max98088_dai1_mute,
1350       .no_capture_mute = 1,
1351};
1352
1353static const struct snd_soc_dai_ops max98088_dai2_ops = {
1354       .set_sysclk = max98088_dai_set_sysclk,
1355       .set_fmt = max98088_dai2_set_fmt,
1356       .hw_params = max98088_dai2_hw_params,
1357       .mute_stream = max98088_dai2_mute,
1358       .no_capture_mute = 1,
1359};
1360
1361static struct snd_soc_dai_driver max98088_dai[] = {
1362{
1363       .name = "HiFi",
1364       .playback = {
1365               .stream_name = "HiFi Playback",
1366               .channels_min = 1,
1367               .channels_max = 2,
1368               .rates = MAX98088_RATES,
1369               .formats = MAX98088_FORMATS,
1370       },
1371       .capture = {
1372               .stream_name = "HiFi Capture",
1373               .channels_min = 1,
1374               .channels_max = 2,
1375               .rates = MAX98088_RATES,
1376               .formats = MAX98088_FORMATS,
1377       },
1378        .ops = &max98088_dai1_ops,
1379},
1380{
1381       .name = "Aux",
1382       .playback = {
1383               .stream_name = "Aux Playback",
1384               .channels_min = 1,
1385               .channels_max = 2,
1386               .rates = MAX98088_RATES,
1387               .formats = MAX98088_FORMATS,
1388       },
1389       .ops = &max98088_dai2_ops,
1390}
1391};
1392
1393static const char *eq_mode_name[] = {"EQ1 Mode", "EQ2 Mode"};
1394
1395static int max98088_get_channel(struct snd_soc_component *component, const char *name)
1396{
1397	int ret;
1398
1399	ret = match_string(eq_mode_name, ARRAY_SIZE(eq_mode_name), name);
1400	if (ret < 0)
1401		dev_err(component->dev, "Bad EQ channel name '%s'\n", name);
1402	return ret;
1403}
1404
1405static void max98088_setup_eq1(struct snd_soc_component *component)
1406{
1407       struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
1408       struct max98088_pdata *pdata = max98088->pdata;
1409       struct max98088_eq_cfg *coef_set;
1410       int best, best_val, save, i, sel, fs;
1411       struct max98088_cdata *cdata;
1412
1413       cdata = &max98088->dai[0];
1414
1415       if (!pdata || !max98088->eq_textcnt)
1416               return;
1417
1418       /* Find the selected configuration with nearest sample rate */
1419       fs = cdata->rate;
1420       sel = cdata->eq_sel;
1421
1422       best = 0;
1423       best_val = INT_MAX;
1424       for (i = 0; i < pdata->eq_cfgcnt; i++) {
1425               if (strcmp(pdata->eq_cfg[i].name, max98088->eq_texts[sel]) == 0 &&
1426                   abs(pdata->eq_cfg[i].rate - fs) < best_val) {
1427                       best = i;
1428                       best_val = abs(pdata->eq_cfg[i].rate - fs);
1429               }
1430       }
1431
1432       dev_dbg(component->dev, "Selected %s/%dHz for %dHz sample rate\n",
1433               pdata->eq_cfg[best].name,
1434               pdata->eq_cfg[best].rate, fs);
1435
1436       /* Disable EQ while configuring, and save current on/off state */
1437       save = snd_soc_component_read(component, M98088_REG_49_CFG_LEVEL);
1438       snd_soc_component_update_bits(component, M98088_REG_49_CFG_LEVEL, M98088_EQ1EN, 0);
1439
1440       coef_set = &pdata->eq_cfg[sel];
1441
1442       m98088_eq_band(component, 0, 0, coef_set->band1);
1443       m98088_eq_band(component, 0, 1, coef_set->band2);
1444       m98088_eq_band(component, 0, 2, coef_set->band3);
1445       m98088_eq_band(component, 0, 3, coef_set->band4);
1446       m98088_eq_band(component, 0, 4, coef_set->band5);
1447
1448       /* Restore the original on/off state */
1449       snd_soc_component_update_bits(component, M98088_REG_49_CFG_LEVEL, M98088_EQ1EN, save);
1450}
1451
1452static void max98088_setup_eq2(struct snd_soc_component *component)
1453{
1454       struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
1455       struct max98088_pdata *pdata = max98088->pdata;
1456       struct max98088_eq_cfg *coef_set;
1457       int best, best_val, save, i, sel, fs;
1458       struct max98088_cdata *cdata;
1459
1460       cdata = &max98088->dai[1];
1461
1462       if (!pdata || !max98088->eq_textcnt)
1463               return;
1464
1465       /* Find the selected configuration with nearest sample rate */
1466       fs = cdata->rate;
1467
1468       sel = cdata->eq_sel;
1469       best = 0;
1470       best_val = INT_MAX;
1471       for (i = 0; i < pdata->eq_cfgcnt; i++) {
1472               if (strcmp(pdata->eq_cfg[i].name, max98088->eq_texts[sel]) == 0 &&
1473                   abs(pdata->eq_cfg[i].rate - fs) < best_val) {
1474                       best = i;
1475                       best_val = abs(pdata->eq_cfg[i].rate - fs);
1476               }
1477       }
1478
1479       dev_dbg(component->dev, "Selected %s/%dHz for %dHz sample rate\n",
1480               pdata->eq_cfg[best].name,
1481               pdata->eq_cfg[best].rate, fs);
1482
1483       /* Disable EQ while configuring, and save current on/off state */
1484       save = snd_soc_component_read(component, M98088_REG_49_CFG_LEVEL);
1485       snd_soc_component_update_bits(component, M98088_REG_49_CFG_LEVEL, M98088_EQ2EN, 0);
1486
1487       coef_set = &pdata->eq_cfg[sel];
1488
1489       m98088_eq_band(component, 1, 0, coef_set->band1);
1490       m98088_eq_band(component, 1, 1, coef_set->band2);
1491       m98088_eq_band(component, 1, 2, coef_set->band3);
1492       m98088_eq_band(component, 1, 3, coef_set->band4);
1493       m98088_eq_band(component, 1, 4, coef_set->band5);
1494
1495       /* Restore the original on/off state */
1496       snd_soc_component_update_bits(component, M98088_REG_49_CFG_LEVEL, M98088_EQ2EN,
1497               save);
1498}
1499
1500static int max98088_put_eq_enum(struct snd_kcontrol *kcontrol,
1501                                struct snd_ctl_elem_value *ucontrol)
1502{
1503       struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1504       struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
1505       struct max98088_pdata *pdata = max98088->pdata;
1506       int channel = max98088_get_channel(component, kcontrol->id.name);
1507       struct max98088_cdata *cdata;
1508	int sel = ucontrol->value.enumerated.item[0];
1509
1510       if (channel < 0)
1511	       return channel;
1512
1513       cdata = &max98088->dai[channel];
1514
1515       if (sel >= pdata->eq_cfgcnt)
1516               return -EINVAL;
1517
1518       cdata->eq_sel = sel;
1519
1520       switch (channel) {
1521       case 0:
1522               max98088_setup_eq1(component);
1523               break;
1524       case 1:
1525               max98088_setup_eq2(component);
1526               break;
1527       }
1528
1529       return 0;
1530}
1531
1532static int max98088_get_eq_enum(struct snd_kcontrol *kcontrol,
1533                                struct snd_ctl_elem_value *ucontrol)
1534{
1535       struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1536       struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
1537       int channel = max98088_get_channel(component, kcontrol->id.name);
1538       struct max98088_cdata *cdata;
1539
1540       if (channel < 0)
1541	       return channel;
1542
1543       cdata = &max98088->dai[channel];
1544       ucontrol->value.enumerated.item[0] = cdata->eq_sel;
1545       return 0;
1546}
1547
1548static void max98088_handle_eq_pdata(struct snd_soc_component *component)
1549{
1550       struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
1551       struct max98088_pdata *pdata = max98088->pdata;
1552       struct max98088_eq_cfg *cfg;
1553       unsigned int cfgcnt;
1554       int i, j;
1555       const char **t;
1556       int ret;
1557       struct snd_kcontrol_new controls[] = {
1558               SOC_ENUM_EXT((char *)eq_mode_name[0],
1559                       max98088->eq_enum,
1560                       max98088_get_eq_enum,
1561                       max98088_put_eq_enum),
1562               SOC_ENUM_EXT((char *)eq_mode_name[1],
1563                       max98088->eq_enum,
1564                       max98088_get_eq_enum,
1565                       max98088_put_eq_enum),
1566       };
1567       BUILD_BUG_ON(ARRAY_SIZE(controls) != ARRAY_SIZE(eq_mode_name));
1568
1569       cfg = pdata->eq_cfg;
1570       cfgcnt = pdata->eq_cfgcnt;
1571
1572       /* Setup an array of texts for the equalizer enum.
1573        * This is based on Mark Brown's equalizer driver code.
1574        */
1575       max98088->eq_textcnt = 0;
1576       max98088->eq_texts = NULL;
1577       for (i = 0; i < cfgcnt; i++) {
1578               for (j = 0; j < max98088->eq_textcnt; j++) {
1579                       if (strcmp(cfg[i].name, max98088->eq_texts[j]) == 0)
1580                               break;
1581               }
1582
1583               if (j != max98088->eq_textcnt)
1584                       continue;
1585
1586               /* Expand the array */
1587               t = krealloc(max98088->eq_texts,
1588                            sizeof(char *) * (max98088->eq_textcnt + 1),
1589                            GFP_KERNEL);
1590               if (t == NULL)
1591                       continue;
1592
1593               /* Store the new entry */
1594               t[max98088->eq_textcnt] = cfg[i].name;
1595               max98088->eq_textcnt++;
1596               max98088->eq_texts = t;
1597       }
1598
1599       /* Now point the soc_enum to .texts array items */
1600       max98088->eq_enum.texts = max98088->eq_texts;
1601       max98088->eq_enum.items = max98088->eq_textcnt;
1602
1603       ret = snd_soc_add_component_controls(component, controls, ARRAY_SIZE(controls));
1604       if (ret != 0)
1605               dev_err(component->dev, "Failed to add EQ control: %d\n", ret);
1606}
1607
1608static void max98088_handle_pdata(struct snd_soc_component *component)
1609{
1610       struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
1611       struct max98088_pdata *pdata = max98088->pdata;
1612       u8 regval = 0;
1613
1614       if (!pdata) {
1615               dev_dbg(component->dev, "No platform data\n");
1616               return;
1617       }
1618
1619       /* Configure mic for analog/digital mic mode */
1620       if (pdata->digmic_left_mode)
1621               regval |= M98088_DIGMIC_L;
1622
1623       if (pdata->digmic_right_mode)
1624               regval |= M98088_DIGMIC_R;
1625
1626       max98088->digmic = (regval ? 1 : 0);
1627
1628       snd_soc_component_write(component, M98088_REG_48_CFG_MIC, regval);
1629
1630       /* Configure receiver output */
1631       regval = ((pdata->receiver_mode) ? M98088_REC_LINEMODE : 0);
1632       snd_soc_component_update_bits(component, M98088_REG_2A_MIC_REC_CNTL,
1633               M98088_REC_LINEMODE_MASK, regval);
1634
1635       /* Configure equalizers */
1636       if (pdata->eq_cfgcnt)
1637               max98088_handle_eq_pdata(component);
1638}
1639
1640static int max98088_probe(struct snd_soc_component *component)
1641{
1642       struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
1643       struct max98088_cdata *cdata;
1644       int ret = 0;
1645
1646       regcache_mark_dirty(max98088->regmap);
1647
1648       /* initialize private data */
1649
1650       max98088->sysclk = (unsigned)-1;
1651       max98088->eq_textcnt = 0;
1652
1653       cdata = &max98088->dai[0];
1654       cdata->rate = (unsigned)-1;
1655       cdata->fmt  = (unsigned)-1;
1656       cdata->eq_sel = 0;
1657
1658       cdata = &max98088->dai[1];
1659       cdata->rate = (unsigned)-1;
1660       cdata->fmt  = (unsigned)-1;
1661       cdata->eq_sel = 0;
1662
1663       max98088->ina_state = 0;
1664       max98088->inb_state = 0;
1665       max98088->ex_mode = 0;
1666       max98088->digmic = 0;
1667       max98088->mic1pre = 0;
1668       max98088->mic2pre = 0;
1669
1670       ret = snd_soc_component_read(component, M98088_REG_FF_REV_ID);
1671       if (ret < 0) {
1672               dev_err(component->dev, "Failed to read device revision: %d\n",
1673                       ret);
1674               goto err_access;
1675       }
1676       dev_info(component->dev, "revision %c\n", ret - 0x40 + 'A');
1677
1678       snd_soc_component_write(component, M98088_REG_51_PWR_SYS, M98088_PWRSV);
1679
1680       snd_soc_component_write(component, M98088_REG_0F_IRQ_ENABLE, 0x00);
1681
1682       snd_soc_component_write(component, M98088_REG_22_MIX_DAC,
1683               M98088_DAI1L_TO_DACL|M98088_DAI2L_TO_DACL|
1684               M98088_DAI1R_TO_DACR|M98088_DAI2R_TO_DACR);
1685
1686       snd_soc_component_write(component, M98088_REG_4E_BIAS_CNTL, 0xF0);
1687       snd_soc_component_write(component, M98088_REG_50_DAC_BIAS2, 0x0F);
1688
1689       snd_soc_component_write(component, M98088_REG_16_DAI1_IOCFG,
1690               M98088_S1NORMAL|M98088_SDATA);
1691
1692       snd_soc_component_write(component, M98088_REG_1E_DAI2_IOCFG,
1693               M98088_S2NORMAL|M98088_SDATA);
1694
1695       max98088_handle_pdata(component);
1696
1697err_access:
1698       return ret;
1699}
1700
1701static void max98088_remove(struct snd_soc_component *component)
1702{
1703       struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component);
1704
1705       kfree(max98088->eq_texts);
1706}
1707
1708static const struct snd_soc_component_driver soc_component_dev_max98088 = {
1709	.probe			= max98088_probe,
1710	.remove			= max98088_remove,
1711	.set_bias_level		= max98088_set_bias_level,
1712	.controls		= max98088_snd_controls,
1713	.num_controls		= ARRAY_SIZE(max98088_snd_controls),
1714	.dapm_widgets		= max98088_dapm_widgets,
1715	.num_dapm_widgets	= ARRAY_SIZE(max98088_dapm_widgets),
1716	.dapm_routes		= max98088_audio_map,
1717	.num_dapm_routes	= ARRAY_SIZE(max98088_audio_map),
1718	.suspend_bias_off	= 1,
1719	.idle_bias_on		= 1,
1720	.use_pmdown_time	= 1,
1721	.endianness		= 1,
 
1722};
1723
1724static const struct i2c_device_id max98088_i2c_id[] = {
1725       { "max98088", MAX98088 },
1726       { "max98089", MAX98089 },
1727       { }
1728};
1729MODULE_DEVICE_TABLE(i2c, max98088_i2c_id);
1730
1731static int max98088_i2c_probe(struct i2c_client *i2c)
1732{
1733	struct max98088_priv *max98088;
1734	const struct i2c_device_id *id;
1735
1736	max98088 = devm_kzalloc(&i2c->dev, sizeof(struct max98088_priv),
1737				GFP_KERNEL);
1738	if (max98088 == NULL)
1739		return -ENOMEM;
1740
1741	max98088->regmap = devm_regmap_init_i2c(i2c, &max98088_regmap);
1742	if (IS_ERR(max98088->regmap))
1743		return PTR_ERR(max98088->regmap);
1744
1745	max98088->mclk = devm_clk_get(&i2c->dev, "mclk");
1746	if (IS_ERR(max98088->mclk))
1747		if (PTR_ERR(max98088->mclk) == -EPROBE_DEFER)
1748			return PTR_ERR(max98088->mclk);
1749
1750	id = i2c_match_id(max98088_i2c_id, i2c);
1751	max98088->devtype = id->driver_data;
1752
1753	i2c_set_clientdata(i2c, max98088);
1754	max98088->pdata = i2c->dev.platform_data;
1755
1756	return devm_snd_soc_register_component(&i2c->dev, &soc_component_dev_max98088,
1757					      &max98088_dai[0], 2);
 
1758}
1759
 
 
 
 
 
 
 
1760#if defined(CONFIG_OF)
1761static const struct of_device_id max98088_of_match[] = {
1762	{ .compatible = "maxim,max98088" },
1763	{ .compatible = "maxim,max98089" },
1764	{ }
1765};
1766MODULE_DEVICE_TABLE(of, max98088_of_match);
1767#endif
1768
1769static struct i2c_driver max98088_i2c_driver = {
1770	.driver = {
1771		.name = "max98088",
1772		.of_match_table = of_match_ptr(max98088_of_match),
1773	},
1774	.probe = max98088_i2c_probe,
1775	.id_table = max98088_i2c_id,
1776};
1777
1778module_i2c_driver(max98088_i2c_driver);
1779
1780MODULE_DESCRIPTION("ALSA SoC MAX98088 driver");
1781MODULE_AUTHOR("Peter Hsiang, Jesse Marroquin");
1782MODULE_LICENSE("GPL");