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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (C) 2012 - 2014 Allwinner Tech
4 * Pan Nan <pannan@allwinnertech.com>
5 *
6 * Copyright (C) 2014 Maxime Ripard
7 * Maxime Ripard <maxime.ripard@free-electrons.com>
8 */
9
10#include <linux/bitfield.h>
11#include <linux/clk.h>
12#include <linux/delay.h>
13#include <linux/device.h>
14#include <linux/interrupt.h>
15#include <linux/io.h>
16#include <linux/module.h>
17#include <linux/of.h>
18#include <linux/platform_device.h>
19#include <linux/pm_runtime.h>
20#include <linux/reset.h>
21#include <linux/dmaengine.h>
22
23#include <linux/spi/spi.h>
24
25#define SUN6I_AUTOSUSPEND_TIMEOUT 2000
26
27#define SUN6I_FIFO_DEPTH 128
28#define SUN8I_FIFO_DEPTH 64
29
30#define SUN6I_GBL_CTL_REG 0x04
31#define SUN6I_GBL_CTL_BUS_ENABLE BIT(0)
32#define SUN6I_GBL_CTL_MASTER BIT(1)
33#define SUN6I_GBL_CTL_TP BIT(7)
34#define SUN6I_GBL_CTL_RST BIT(31)
35
36#define SUN6I_TFR_CTL_REG 0x08
37#define SUN6I_TFR_CTL_CPHA BIT(0)
38#define SUN6I_TFR_CTL_CPOL BIT(1)
39#define SUN6I_TFR_CTL_SPOL BIT(2)
40#define SUN6I_TFR_CTL_CS_MASK 0x30
41#define SUN6I_TFR_CTL_CS(cs) (((cs) << 4) & SUN6I_TFR_CTL_CS_MASK)
42#define SUN6I_TFR_CTL_CS_MANUAL BIT(6)
43#define SUN6I_TFR_CTL_CS_LEVEL BIT(7)
44#define SUN6I_TFR_CTL_DHB BIT(8)
45#define SUN6I_TFR_CTL_SDC BIT(11)
46#define SUN6I_TFR_CTL_FBS BIT(12)
47#define SUN6I_TFR_CTL_SDM BIT(13)
48#define SUN6I_TFR_CTL_XCH BIT(31)
49
50#define SUN6I_INT_CTL_REG 0x10
51#define SUN6I_INT_CTL_RF_RDY BIT(0)
52#define SUN6I_INT_CTL_TF_ERQ BIT(4)
53#define SUN6I_INT_CTL_RF_OVF BIT(8)
54#define SUN6I_INT_CTL_TC BIT(12)
55
56#define SUN6I_INT_STA_REG 0x14
57
58#define SUN6I_FIFO_CTL_REG 0x18
59#define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_MASK 0xff
60#define SUN6I_FIFO_CTL_RF_DRQ_EN BIT(8)
61#define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS 0
62#define SUN6I_FIFO_CTL_RF_RST BIT(15)
63#define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_MASK 0xff
64#define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS 16
65#define SUN6I_FIFO_CTL_TF_DRQ_EN BIT(24)
66#define SUN6I_FIFO_CTL_TF_RST BIT(31)
67
68#define SUN6I_FIFO_STA_REG 0x1c
69#define SUN6I_FIFO_STA_RF_CNT_MASK GENMASK(7, 0)
70#define SUN6I_FIFO_STA_TF_CNT_MASK GENMASK(23, 16)
71
72#define SUN6I_CLK_CTL_REG 0x24
73#define SUN6I_CLK_CTL_CDR2_MASK 0xff
74#define SUN6I_CLK_CTL_CDR2(div) (((div) & SUN6I_CLK_CTL_CDR2_MASK) << 0)
75#define SUN6I_CLK_CTL_CDR1_MASK 0xf
76#define SUN6I_CLK_CTL_CDR1(div) (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8)
77#define SUN6I_CLK_CTL_DRS BIT(12)
78
79#define SUN6I_MAX_XFER_SIZE 0xffffff
80
81#define SUN6I_BURST_CNT_REG 0x30
82
83#define SUN6I_XMIT_CNT_REG 0x34
84
85#define SUN6I_BURST_CTL_CNT_REG 0x38
86#define SUN6I_BURST_CTL_CNT_STC_MASK GENMASK(23, 0)
87#define SUN6I_BURST_CTL_CNT_DRM BIT(28)
88#define SUN6I_BURST_CTL_CNT_QUAD_EN BIT(29)
89
90#define SUN6I_TXDATA_REG 0x200
91#define SUN6I_RXDATA_REG 0x300
92
93struct sun6i_spi_cfg {
94 unsigned long fifo_depth;
95 bool has_clk_ctl;
96 u32 mode_bits;
97};
98
99struct sun6i_spi {
100 struct spi_controller *host;
101 void __iomem *base_addr;
102 dma_addr_t dma_addr_rx;
103 dma_addr_t dma_addr_tx;
104 struct clk *hclk;
105 struct clk *mclk;
106 struct reset_control *rstc;
107
108 struct completion done;
109 struct completion dma_rx_done;
110
111 const u8 *tx_buf;
112 u8 *rx_buf;
113 int len;
114 const struct sun6i_spi_cfg *cfg;
115};
116
117static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg)
118{
119 return readl(sspi->base_addr + reg);
120}
121
122static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value)
123{
124 writel(value, sspi->base_addr + reg);
125}
126
127static inline u32 sun6i_spi_get_rx_fifo_count(struct sun6i_spi *sspi)
128{
129 u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
130
131 return FIELD_GET(SUN6I_FIFO_STA_RF_CNT_MASK, reg);
132}
133
134static inline u32 sun6i_spi_get_tx_fifo_count(struct sun6i_spi *sspi)
135{
136 u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
137
138 return FIELD_GET(SUN6I_FIFO_STA_TF_CNT_MASK, reg);
139}
140
141static inline void sun6i_spi_disable_interrupt(struct sun6i_spi *sspi, u32 mask)
142{
143 u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG);
144
145 reg &= ~mask;
146 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
147}
148
149static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi)
150{
151 u32 len;
152 u8 byte;
153
154 /* See how much data is available */
155 len = sun6i_spi_get_rx_fifo_count(sspi);
156
157 while (len--) {
158 byte = readb(sspi->base_addr + SUN6I_RXDATA_REG);
159 if (sspi->rx_buf)
160 *sspi->rx_buf++ = byte;
161 }
162}
163
164static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi)
165{
166 u32 cnt;
167 int len;
168 u8 byte;
169
170 /* See how much data we can fit */
171 cnt = sspi->cfg->fifo_depth - sun6i_spi_get_tx_fifo_count(sspi);
172
173 len = min((int)cnt, sspi->len);
174
175 while (len--) {
176 byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
177 writeb(byte, sspi->base_addr + SUN6I_TXDATA_REG);
178 sspi->len--;
179 }
180}
181
182static void sun6i_spi_set_cs(struct spi_device *spi, bool enable)
183{
184 struct sun6i_spi *sspi = spi_controller_get_devdata(spi->controller);
185 u32 reg;
186
187 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
188 reg &= ~SUN6I_TFR_CTL_CS_MASK;
189 reg |= SUN6I_TFR_CTL_CS(spi_get_chipselect(spi, 0));
190
191 if (enable)
192 reg |= SUN6I_TFR_CTL_CS_LEVEL;
193 else
194 reg &= ~SUN6I_TFR_CTL_CS_LEVEL;
195
196 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
197}
198
199static size_t sun6i_spi_max_transfer_size(struct spi_device *spi)
200{
201 return SUN6I_MAX_XFER_SIZE - 1;
202}
203
204static void sun6i_spi_dma_rx_cb(void *param)
205{
206 struct sun6i_spi *sspi = param;
207
208 complete(&sspi->dma_rx_done);
209}
210
211static int sun6i_spi_prepare_dma(struct sun6i_spi *sspi,
212 struct spi_transfer *tfr)
213{
214 struct dma_async_tx_descriptor *rxdesc, *txdesc;
215 struct spi_controller *host = sspi->host;
216
217 rxdesc = NULL;
218 if (tfr->rx_buf) {
219 struct dma_slave_config rxconf = {
220 .direction = DMA_DEV_TO_MEM,
221 .src_addr = sspi->dma_addr_rx,
222 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
223 .src_maxburst = 8,
224 };
225
226 dmaengine_slave_config(host->dma_rx, &rxconf);
227
228 rxdesc = dmaengine_prep_slave_sg(host->dma_rx,
229 tfr->rx_sg.sgl,
230 tfr->rx_sg.nents,
231 DMA_DEV_TO_MEM,
232 DMA_PREP_INTERRUPT);
233 if (!rxdesc)
234 return -EINVAL;
235 rxdesc->callback_param = sspi;
236 rxdesc->callback = sun6i_spi_dma_rx_cb;
237 }
238
239 txdesc = NULL;
240 if (tfr->tx_buf) {
241 struct dma_slave_config txconf = {
242 .direction = DMA_MEM_TO_DEV,
243 .dst_addr = sspi->dma_addr_tx,
244 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
245 .dst_maxburst = 8,
246 };
247
248 dmaengine_slave_config(host->dma_tx, &txconf);
249
250 txdesc = dmaengine_prep_slave_sg(host->dma_tx,
251 tfr->tx_sg.sgl,
252 tfr->tx_sg.nents,
253 DMA_MEM_TO_DEV,
254 DMA_PREP_INTERRUPT);
255 if (!txdesc) {
256 if (rxdesc)
257 dmaengine_terminate_sync(host->dma_rx);
258 return -EINVAL;
259 }
260 }
261
262 if (tfr->rx_buf) {
263 dmaengine_submit(rxdesc);
264 dma_async_issue_pending(host->dma_rx);
265 }
266
267 if (tfr->tx_buf) {
268 dmaengine_submit(txdesc);
269 dma_async_issue_pending(host->dma_tx);
270 }
271
272 return 0;
273}
274
275static int sun6i_spi_transfer_one(struct spi_controller *host,
276 struct spi_device *spi,
277 struct spi_transfer *tfr)
278{
279 struct sun6i_spi *sspi = spi_controller_get_devdata(host);
280 unsigned int div, div_cdr1, div_cdr2;
281 unsigned long time_left;
282 unsigned int start, end, tx_time;
283 unsigned int trig_level;
284 unsigned int tx_len = 0, rx_len = 0, nbits = 0;
285 bool use_dma;
286 int ret = 0;
287 u32 reg;
288
289 if (tfr->len > SUN6I_MAX_XFER_SIZE)
290 return -EINVAL;
291
292 reinit_completion(&sspi->done);
293 reinit_completion(&sspi->dma_rx_done);
294 sspi->tx_buf = tfr->tx_buf;
295 sspi->rx_buf = tfr->rx_buf;
296 sspi->len = tfr->len;
297 use_dma = host->can_dma ? host->can_dma(host, spi, tfr) : false;
298
299 /* Clear pending interrupts */
300 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, ~0);
301
302 /* Reset FIFO */
303 sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG,
304 SUN6I_FIFO_CTL_RF_RST | SUN6I_FIFO_CTL_TF_RST);
305
306 reg = 0;
307
308 if (!use_dma) {
309 /*
310 * Setup FIFO interrupt trigger level
311 * Here we choose 3/4 of the full fifo depth, as it's
312 * the hardcoded value used in old generation of Allwinner
313 * SPI controller. (See spi-sun4i.c)
314 */
315 trig_level = sspi->cfg->fifo_depth / 4 * 3;
316 } else {
317 /*
318 * Setup FIFO DMA request trigger level
319 * We choose 1/2 of the full fifo depth, that value will
320 * be used as DMA burst length.
321 */
322 trig_level = sspi->cfg->fifo_depth / 2;
323
324 if (tfr->tx_buf)
325 reg |= SUN6I_FIFO_CTL_TF_DRQ_EN;
326 if (tfr->rx_buf)
327 reg |= SUN6I_FIFO_CTL_RF_DRQ_EN;
328 }
329
330 reg |= (trig_level << SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS) |
331 (trig_level << SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS);
332
333 sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG, reg);
334
335 /*
336 * Setup the transfer control register: Chip Select,
337 * polarities, etc.
338 */
339 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
340
341 if (spi->mode & SPI_CPOL)
342 reg |= SUN6I_TFR_CTL_CPOL;
343 else
344 reg &= ~SUN6I_TFR_CTL_CPOL;
345
346 if (spi->mode & SPI_CPHA)
347 reg |= SUN6I_TFR_CTL_CPHA;
348 else
349 reg &= ~SUN6I_TFR_CTL_CPHA;
350
351 if (spi->mode & SPI_LSB_FIRST)
352 reg |= SUN6I_TFR_CTL_FBS;
353 else
354 reg &= ~SUN6I_TFR_CTL_FBS;
355
356 /*
357 * If it's a TX only transfer, we don't want to fill the RX
358 * FIFO with bogus data
359 */
360 if (sspi->rx_buf) {
361 reg &= ~SUN6I_TFR_CTL_DHB;
362 rx_len = tfr->len;
363 } else {
364 reg |= SUN6I_TFR_CTL_DHB;
365 }
366
367 /* We want to control the chip select manually */
368 reg |= SUN6I_TFR_CTL_CS_MANUAL;
369
370 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
371
372 if (sspi->cfg->has_clk_ctl) {
373 unsigned int mclk_rate = clk_get_rate(sspi->mclk);
374
375 /* Ensure that we have a parent clock fast enough */
376 if (mclk_rate < (2 * tfr->speed_hz)) {
377 clk_set_rate(sspi->mclk, 2 * tfr->speed_hz);
378 mclk_rate = clk_get_rate(sspi->mclk);
379 }
380
381 /*
382 * Setup clock divider.
383 *
384 * We have two choices there. Either we can use the clock
385 * divide rate 1, which is calculated thanks to this formula:
386 * SPI_CLK = MOD_CLK / (2 ^ cdr)
387 * Or we can use CDR2, which is calculated with the formula:
388 * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
389 * Wether we use the former or the latter is set through the
390 * DRS bit.
391 *
392 * First try CDR2, and if we can't reach the expected
393 * frequency, fall back to CDR1.
394 */
395 div_cdr1 = DIV_ROUND_UP(mclk_rate, tfr->speed_hz);
396 div_cdr2 = DIV_ROUND_UP(div_cdr1, 2);
397 if (div_cdr2 <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) {
398 reg = SUN6I_CLK_CTL_CDR2(div_cdr2 - 1) | SUN6I_CLK_CTL_DRS;
399 tfr->effective_speed_hz = mclk_rate / (2 * div_cdr2);
400 } else {
401 div = min(SUN6I_CLK_CTL_CDR1_MASK, order_base_2(div_cdr1));
402 reg = SUN6I_CLK_CTL_CDR1(div);
403 tfr->effective_speed_hz = mclk_rate / (1 << div);
404 }
405
406 sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg);
407 } else {
408 clk_set_rate(sspi->mclk, tfr->speed_hz);
409 tfr->effective_speed_hz = clk_get_rate(sspi->mclk);
410
411 /*
412 * Configure work mode.
413 *
414 * There are three work modes depending on the controller clock
415 * frequency:
416 * - normal sample mode : CLK <= 24MHz SDM=1 SDC=0
417 * - delay half-cycle sample mode : CLK <= 40MHz SDM=0 SDC=0
418 * - delay one-cycle sample mode : CLK >= 80MHz SDM=0 SDC=1
419 */
420 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
421 reg &= ~(SUN6I_TFR_CTL_SDM | SUN6I_TFR_CTL_SDC);
422
423 if (tfr->effective_speed_hz <= 24000000)
424 reg |= SUN6I_TFR_CTL_SDM;
425 else if (tfr->effective_speed_hz >= 80000000)
426 reg |= SUN6I_TFR_CTL_SDC;
427
428 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
429 }
430
431 /* Finally enable the bus - doing so before might raise SCK to HIGH */
432 reg = sun6i_spi_read(sspi, SUN6I_GBL_CTL_REG);
433 reg |= SUN6I_GBL_CTL_BUS_ENABLE;
434 sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG, reg);
435
436 /* Setup the transfer now... */
437 if (sspi->tx_buf) {
438 tx_len = tfr->len;
439 nbits = tfr->tx_nbits;
440 } else if (tfr->rx_buf) {
441 nbits = tfr->rx_nbits;
442 }
443
444 switch (nbits) {
445 case SPI_NBITS_DUAL:
446 reg = SUN6I_BURST_CTL_CNT_DRM;
447 break;
448 case SPI_NBITS_QUAD:
449 reg = SUN6I_BURST_CTL_CNT_QUAD_EN;
450 break;
451 case SPI_NBITS_SINGLE:
452 default:
453 reg = FIELD_PREP(SUN6I_BURST_CTL_CNT_STC_MASK, tx_len);
454 }
455
456 /* Setup the counters */
457 sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG, reg);
458 sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, tfr->len);
459 sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, tx_len);
460
461 if (!use_dma) {
462 /* Fill the TX FIFO */
463 sun6i_spi_fill_fifo(sspi);
464 } else {
465 ret = sun6i_spi_prepare_dma(sspi, tfr);
466 if (ret) {
467 dev_warn(&host->dev,
468 "%s: prepare DMA failed, ret=%d",
469 dev_name(&spi->dev), ret);
470 return ret;
471 }
472 }
473
474 /* Enable the interrupts */
475 reg = SUN6I_INT_CTL_TC;
476
477 if (!use_dma) {
478 if (rx_len > sspi->cfg->fifo_depth)
479 reg |= SUN6I_INT_CTL_RF_RDY;
480 if (tx_len > sspi->cfg->fifo_depth)
481 reg |= SUN6I_INT_CTL_TF_ERQ;
482 }
483
484 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
485
486 /* Start the transfer */
487 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
488 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg | SUN6I_TFR_CTL_XCH);
489
490 tx_time = spi_controller_xfer_timeout(host, tfr);
491 start = jiffies;
492 time_left = wait_for_completion_timeout(&sspi->done,
493 msecs_to_jiffies(tx_time));
494
495 if (!use_dma) {
496 sun6i_spi_drain_fifo(sspi);
497 } else {
498 if (time_left && rx_len) {
499 /*
500 * Even though RX on the peripheral side has finished
501 * RX DMA might still be in flight
502 */
503 time_left = wait_for_completion_timeout(&sspi->dma_rx_done,
504 time_left);
505 if (!time_left)
506 dev_warn(&host->dev, "RX DMA timeout\n");
507 }
508 }
509
510 end = jiffies;
511 if (!time_left) {
512 dev_warn(&host->dev,
513 "%s: timeout transferring %u bytes@%iHz for %i(%i)ms",
514 dev_name(&spi->dev), tfr->len, tfr->speed_hz,
515 jiffies_to_msecs(end - start), tx_time);
516 ret = -ETIMEDOUT;
517 }
518
519 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0);
520
521 if (ret && use_dma) {
522 dmaengine_terminate_sync(host->dma_rx);
523 dmaengine_terminate_sync(host->dma_tx);
524 }
525
526 return ret;
527}
528
529static irqreturn_t sun6i_spi_handler(int irq, void *dev_id)
530{
531 struct sun6i_spi *sspi = dev_id;
532 u32 status = sun6i_spi_read(sspi, SUN6I_INT_STA_REG);
533
534 /* Transfer complete */
535 if (status & SUN6I_INT_CTL_TC) {
536 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC);
537 complete(&sspi->done);
538 return IRQ_HANDLED;
539 }
540
541 /* Receive FIFO 3/4 full */
542 if (status & SUN6I_INT_CTL_RF_RDY) {
543 sun6i_spi_drain_fifo(sspi);
544 /* Only clear the interrupt _after_ draining the FIFO */
545 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_RF_RDY);
546 return IRQ_HANDLED;
547 }
548
549 /* Transmit FIFO 3/4 empty */
550 if (status & SUN6I_INT_CTL_TF_ERQ) {
551 sun6i_spi_fill_fifo(sspi);
552
553 if (!sspi->len)
554 /* nothing left to transmit */
555 sun6i_spi_disable_interrupt(sspi, SUN6I_INT_CTL_TF_ERQ);
556
557 /* Only clear the interrupt _after_ re-seeding the FIFO */
558 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TF_ERQ);
559
560 return IRQ_HANDLED;
561 }
562
563 return IRQ_NONE;
564}
565
566static int sun6i_spi_runtime_resume(struct device *dev)
567{
568 struct spi_controller *host = dev_get_drvdata(dev);
569 struct sun6i_spi *sspi = spi_controller_get_devdata(host);
570 int ret;
571
572 ret = clk_prepare_enable(sspi->hclk);
573 if (ret) {
574 dev_err(dev, "Couldn't enable AHB clock\n");
575 goto out;
576 }
577
578 ret = clk_prepare_enable(sspi->mclk);
579 if (ret) {
580 dev_err(dev, "Couldn't enable module clock\n");
581 goto err;
582 }
583
584 ret = reset_control_deassert(sspi->rstc);
585 if (ret) {
586 dev_err(dev, "Couldn't deassert the device from reset\n");
587 goto err2;
588 }
589
590 sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG,
591 SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP);
592
593 return 0;
594
595err2:
596 clk_disable_unprepare(sspi->mclk);
597err:
598 clk_disable_unprepare(sspi->hclk);
599out:
600 return ret;
601}
602
603static int sun6i_spi_runtime_suspend(struct device *dev)
604{
605 struct spi_controller *host = dev_get_drvdata(dev);
606 struct sun6i_spi *sspi = spi_controller_get_devdata(host);
607
608 reset_control_assert(sspi->rstc);
609 clk_disable_unprepare(sspi->mclk);
610 clk_disable_unprepare(sspi->hclk);
611
612 return 0;
613}
614
615static bool sun6i_spi_can_dma(struct spi_controller *host,
616 struct spi_device *spi,
617 struct spi_transfer *xfer)
618{
619 struct sun6i_spi *sspi = spi_controller_get_devdata(host);
620
621 /*
622 * If the number of spi words to transfer is less or equal than
623 * the fifo length we can just fill the fifo and wait for a single
624 * irq, so don't bother setting up dma
625 */
626 return xfer->len > sspi->cfg->fifo_depth;
627}
628
629static int sun6i_spi_probe(struct platform_device *pdev)
630{
631 struct spi_controller *host;
632 struct sun6i_spi *sspi;
633 struct resource *mem;
634 int ret = 0, irq;
635
636 host = spi_alloc_host(&pdev->dev, sizeof(struct sun6i_spi));
637 if (!host) {
638 dev_err(&pdev->dev, "Unable to allocate SPI Host\n");
639 return -ENOMEM;
640 }
641
642 platform_set_drvdata(pdev, host);
643 sspi = spi_controller_get_devdata(host);
644
645 sspi->base_addr = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
646 if (IS_ERR(sspi->base_addr)) {
647 ret = PTR_ERR(sspi->base_addr);
648 goto err_free_host;
649 }
650
651 irq = platform_get_irq(pdev, 0);
652 if (irq < 0) {
653 ret = -ENXIO;
654 goto err_free_host;
655 }
656
657 ret = devm_request_irq(&pdev->dev, irq, sun6i_spi_handler,
658 0, "sun6i-spi", sspi);
659 if (ret) {
660 dev_err(&pdev->dev, "Cannot request IRQ\n");
661 goto err_free_host;
662 }
663
664 sspi->host = host;
665 sspi->cfg = of_device_get_match_data(&pdev->dev);
666
667 host->max_speed_hz = 100 * 1000 * 1000;
668 host->min_speed_hz = 3 * 1000;
669 host->use_gpio_descriptors = true;
670 host->set_cs = sun6i_spi_set_cs;
671 host->transfer_one = sun6i_spi_transfer_one;
672 host->num_chipselect = 4;
673 host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST |
674 sspi->cfg->mode_bits;
675 host->bits_per_word_mask = SPI_BPW_MASK(8);
676 host->dev.of_node = pdev->dev.of_node;
677 host->auto_runtime_pm = true;
678 host->max_transfer_size = sun6i_spi_max_transfer_size;
679
680 sspi->hclk = devm_clk_get(&pdev->dev, "ahb");
681 if (IS_ERR(sspi->hclk)) {
682 dev_err(&pdev->dev, "Unable to acquire AHB clock\n");
683 ret = PTR_ERR(sspi->hclk);
684 goto err_free_host;
685 }
686
687 sspi->mclk = devm_clk_get(&pdev->dev, "mod");
688 if (IS_ERR(sspi->mclk)) {
689 dev_err(&pdev->dev, "Unable to acquire module clock\n");
690 ret = PTR_ERR(sspi->mclk);
691 goto err_free_host;
692 }
693
694 init_completion(&sspi->done);
695 init_completion(&sspi->dma_rx_done);
696
697 sspi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
698 if (IS_ERR(sspi->rstc)) {
699 dev_err(&pdev->dev, "Couldn't get reset controller\n");
700 ret = PTR_ERR(sspi->rstc);
701 goto err_free_host;
702 }
703
704 host->dma_tx = dma_request_chan(&pdev->dev, "tx");
705 if (IS_ERR(host->dma_tx)) {
706 /* Check tx to see if we need defer probing driver */
707 if (PTR_ERR(host->dma_tx) == -EPROBE_DEFER) {
708 ret = -EPROBE_DEFER;
709 goto err_free_host;
710 }
711 dev_warn(&pdev->dev, "Failed to request TX DMA channel\n");
712 host->dma_tx = NULL;
713 }
714
715 host->dma_rx = dma_request_chan(&pdev->dev, "rx");
716 if (IS_ERR(host->dma_rx)) {
717 if (PTR_ERR(host->dma_rx) == -EPROBE_DEFER) {
718 ret = -EPROBE_DEFER;
719 goto err_free_dma_tx;
720 }
721 dev_warn(&pdev->dev, "Failed to request RX DMA channel\n");
722 host->dma_rx = NULL;
723 }
724
725 if (host->dma_tx && host->dma_rx) {
726 sspi->dma_addr_tx = mem->start + SUN6I_TXDATA_REG;
727 sspi->dma_addr_rx = mem->start + SUN6I_RXDATA_REG;
728 host->can_dma = sun6i_spi_can_dma;
729 }
730
731 /*
732 * This wake-up/shutdown pattern is to be able to have the
733 * device woken up, even if runtime_pm is disabled
734 */
735 ret = sun6i_spi_runtime_resume(&pdev->dev);
736 if (ret) {
737 dev_err(&pdev->dev, "Couldn't resume the device\n");
738 goto err_free_dma_rx;
739 }
740
741 pm_runtime_set_autosuspend_delay(&pdev->dev, SUN6I_AUTOSUSPEND_TIMEOUT);
742 pm_runtime_use_autosuspend(&pdev->dev);
743 pm_runtime_set_active(&pdev->dev);
744 pm_runtime_enable(&pdev->dev);
745
746 ret = devm_spi_register_controller(&pdev->dev, host);
747 if (ret) {
748 dev_err(&pdev->dev, "cannot register SPI host\n");
749 goto err_pm_disable;
750 }
751
752 return 0;
753
754err_pm_disable:
755 pm_runtime_disable(&pdev->dev);
756 sun6i_spi_runtime_suspend(&pdev->dev);
757err_free_dma_rx:
758 if (host->dma_rx)
759 dma_release_channel(host->dma_rx);
760err_free_dma_tx:
761 if (host->dma_tx)
762 dma_release_channel(host->dma_tx);
763err_free_host:
764 spi_controller_put(host);
765 return ret;
766}
767
768static void sun6i_spi_remove(struct platform_device *pdev)
769{
770 struct spi_controller *host = platform_get_drvdata(pdev);
771
772 pm_runtime_force_suspend(&pdev->dev);
773
774 if (host->dma_tx)
775 dma_release_channel(host->dma_tx);
776 if (host->dma_rx)
777 dma_release_channel(host->dma_rx);
778}
779
780static const struct sun6i_spi_cfg sun6i_a31_spi_cfg = {
781 .fifo_depth = SUN6I_FIFO_DEPTH,
782 .has_clk_ctl = true,
783};
784
785static const struct sun6i_spi_cfg sun8i_h3_spi_cfg = {
786 .fifo_depth = SUN8I_FIFO_DEPTH,
787 .has_clk_ctl = true,
788};
789
790static const struct sun6i_spi_cfg sun50i_r329_spi_cfg = {
791 .fifo_depth = SUN8I_FIFO_DEPTH,
792 .mode_bits = SPI_RX_DUAL | SPI_TX_DUAL | SPI_RX_QUAD | SPI_TX_QUAD,
793};
794
795static const struct of_device_id sun6i_spi_match[] = {
796 { .compatible = "allwinner,sun6i-a31-spi", .data = &sun6i_a31_spi_cfg },
797 { .compatible = "allwinner,sun8i-h3-spi", .data = &sun8i_h3_spi_cfg },
798 {
799 .compatible = "allwinner,sun50i-r329-spi",
800 .data = &sun50i_r329_spi_cfg
801 },
802 {}
803};
804MODULE_DEVICE_TABLE(of, sun6i_spi_match);
805
806static const struct dev_pm_ops sun6i_spi_pm_ops = {
807 .runtime_resume = sun6i_spi_runtime_resume,
808 .runtime_suspend = sun6i_spi_runtime_suspend,
809};
810
811static struct platform_driver sun6i_spi_driver = {
812 .probe = sun6i_spi_probe,
813 .remove = sun6i_spi_remove,
814 .driver = {
815 .name = "sun6i-spi",
816 .of_match_table = sun6i_spi_match,
817 .pm = &sun6i_spi_pm_ops,
818 },
819};
820module_platform_driver(sun6i_spi_driver);
821
822MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>");
823MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
824MODULE_DESCRIPTION("Allwinner A31 SPI controller driver");
825MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (C) 2012 - 2014 Allwinner Tech
4 * Pan Nan <pannan@allwinnertech.com>
5 *
6 * Copyright (C) 2014 Maxime Ripard
7 * Maxime Ripard <maxime.ripard@free-electrons.com>
8 */
9
10#include <linux/bitfield.h>
11#include <linux/clk.h>
12#include <linux/delay.h>
13#include <linux/device.h>
14#include <linux/interrupt.h>
15#include <linux/io.h>
16#include <linux/module.h>
17#include <linux/of_device.h>
18#include <linux/platform_device.h>
19#include <linux/pm_runtime.h>
20#include <linux/reset.h>
21
22#include <linux/spi/spi.h>
23
24#define SUN6I_FIFO_DEPTH 128
25#define SUN8I_FIFO_DEPTH 64
26
27#define SUN6I_GBL_CTL_REG 0x04
28#define SUN6I_GBL_CTL_BUS_ENABLE BIT(0)
29#define SUN6I_GBL_CTL_MASTER BIT(1)
30#define SUN6I_GBL_CTL_TP BIT(7)
31#define SUN6I_GBL_CTL_RST BIT(31)
32
33#define SUN6I_TFR_CTL_REG 0x08
34#define SUN6I_TFR_CTL_CPHA BIT(0)
35#define SUN6I_TFR_CTL_CPOL BIT(1)
36#define SUN6I_TFR_CTL_SPOL BIT(2)
37#define SUN6I_TFR_CTL_CS_MASK 0x30
38#define SUN6I_TFR_CTL_CS(cs) (((cs) << 4) & SUN6I_TFR_CTL_CS_MASK)
39#define SUN6I_TFR_CTL_CS_MANUAL BIT(6)
40#define SUN6I_TFR_CTL_CS_LEVEL BIT(7)
41#define SUN6I_TFR_CTL_DHB BIT(8)
42#define SUN6I_TFR_CTL_FBS BIT(12)
43#define SUN6I_TFR_CTL_XCH BIT(31)
44
45#define SUN6I_INT_CTL_REG 0x10
46#define SUN6I_INT_CTL_RF_RDY BIT(0)
47#define SUN6I_INT_CTL_TF_ERQ BIT(4)
48#define SUN6I_INT_CTL_RF_OVF BIT(8)
49#define SUN6I_INT_CTL_TC BIT(12)
50
51#define SUN6I_INT_STA_REG 0x14
52
53#define SUN6I_FIFO_CTL_REG 0x18
54#define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_MASK 0xff
55#define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS 0
56#define SUN6I_FIFO_CTL_RF_RST BIT(15)
57#define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_MASK 0xff
58#define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS 16
59#define SUN6I_FIFO_CTL_TF_RST BIT(31)
60
61#define SUN6I_FIFO_STA_REG 0x1c
62#define SUN6I_FIFO_STA_RF_CNT_MASK GENMASK(7, 0)
63#define SUN6I_FIFO_STA_TF_CNT_MASK GENMASK(23, 16)
64
65#define SUN6I_CLK_CTL_REG 0x24
66#define SUN6I_CLK_CTL_CDR2_MASK 0xff
67#define SUN6I_CLK_CTL_CDR2(div) (((div) & SUN6I_CLK_CTL_CDR2_MASK) << 0)
68#define SUN6I_CLK_CTL_CDR1_MASK 0xf
69#define SUN6I_CLK_CTL_CDR1(div) (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8)
70#define SUN6I_CLK_CTL_DRS BIT(12)
71
72#define SUN6I_MAX_XFER_SIZE 0xffffff
73
74#define SUN6I_BURST_CNT_REG 0x30
75
76#define SUN6I_XMIT_CNT_REG 0x34
77
78#define SUN6I_BURST_CTL_CNT_REG 0x38
79
80#define SUN6I_TXDATA_REG 0x200
81#define SUN6I_RXDATA_REG 0x300
82
83struct sun6i_spi {
84 struct spi_master *master;
85 void __iomem *base_addr;
86 struct clk *hclk;
87 struct clk *mclk;
88 struct reset_control *rstc;
89
90 struct completion done;
91
92 const u8 *tx_buf;
93 u8 *rx_buf;
94 int len;
95 unsigned long fifo_depth;
96};
97
98static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg)
99{
100 return readl(sspi->base_addr + reg);
101}
102
103static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value)
104{
105 writel(value, sspi->base_addr + reg);
106}
107
108static inline u32 sun6i_spi_get_rx_fifo_count(struct sun6i_spi *sspi)
109{
110 u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
111
112 return FIELD_GET(SUN6I_FIFO_STA_RF_CNT_MASK, reg);
113}
114
115static inline u32 sun6i_spi_get_tx_fifo_count(struct sun6i_spi *sspi)
116{
117 u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
118
119 return FIELD_GET(SUN6I_FIFO_STA_TF_CNT_MASK, reg);
120}
121
122static inline void sun6i_spi_disable_interrupt(struct sun6i_spi *sspi, u32 mask)
123{
124 u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG);
125
126 reg &= ~mask;
127 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
128}
129
130static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi)
131{
132 u32 len;
133 u8 byte;
134
135 /* See how much data is available */
136 len = sun6i_spi_get_rx_fifo_count(sspi);
137
138 while (len--) {
139 byte = readb(sspi->base_addr + SUN6I_RXDATA_REG);
140 if (sspi->rx_buf)
141 *sspi->rx_buf++ = byte;
142 }
143}
144
145static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi)
146{
147 u32 cnt;
148 int len;
149 u8 byte;
150
151 /* See how much data we can fit */
152 cnt = sspi->fifo_depth - sun6i_spi_get_tx_fifo_count(sspi);
153
154 len = min((int)cnt, sspi->len);
155
156 while (len--) {
157 byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
158 writeb(byte, sspi->base_addr + SUN6I_TXDATA_REG);
159 sspi->len--;
160 }
161}
162
163static void sun6i_spi_set_cs(struct spi_device *spi, bool enable)
164{
165 struct sun6i_spi *sspi = spi_master_get_devdata(spi->master);
166 u32 reg;
167
168 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
169 reg &= ~SUN6I_TFR_CTL_CS_MASK;
170 reg |= SUN6I_TFR_CTL_CS(spi->chip_select);
171
172 if (enable)
173 reg |= SUN6I_TFR_CTL_CS_LEVEL;
174 else
175 reg &= ~SUN6I_TFR_CTL_CS_LEVEL;
176
177 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
178}
179
180static size_t sun6i_spi_max_transfer_size(struct spi_device *spi)
181{
182 return SUN6I_MAX_XFER_SIZE - 1;
183}
184
185static int sun6i_spi_transfer_one(struct spi_master *master,
186 struct spi_device *spi,
187 struct spi_transfer *tfr)
188{
189 struct sun6i_spi *sspi = spi_master_get_devdata(master);
190 unsigned int mclk_rate, div, div_cdr1, div_cdr2, timeout;
191 unsigned int start, end, tx_time;
192 unsigned int trig_level;
193 unsigned int tx_len = 0, rx_len = 0;
194 int ret = 0;
195 u32 reg;
196
197 if (tfr->len > SUN6I_MAX_XFER_SIZE)
198 return -EINVAL;
199
200 reinit_completion(&sspi->done);
201 sspi->tx_buf = tfr->tx_buf;
202 sspi->rx_buf = tfr->rx_buf;
203 sspi->len = tfr->len;
204
205 /* Clear pending interrupts */
206 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, ~0);
207
208 /* Reset FIFO */
209 sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG,
210 SUN6I_FIFO_CTL_RF_RST | SUN6I_FIFO_CTL_TF_RST);
211
212 /*
213 * Setup FIFO interrupt trigger level
214 * Here we choose 3/4 of the full fifo depth, as it's the hardcoded
215 * value used in old generation of Allwinner SPI controller.
216 * (See spi-sun4i.c)
217 */
218 trig_level = sspi->fifo_depth / 4 * 3;
219 sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG,
220 (trig_level << SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS) |
221 (trig_level << SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS));
222
223 /*
224 * Setup the transfer control register: Chip Select,
225 * polarities, etc.
226 */
227 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
228
229 if (spi->mode & SPI_CPOL)
230 reg |= SUN6I_TFR_CTL_CPOL;
231 else
232 reg &= ~SUN6I_TFR_CTL_CPOL;
233
234 if (spi->mode & SPI_CPHA)
235 reg |= SUN6I_TFR_CTL_CPHA;
236 else
237 reg &= ~SUN6I_TFR_CTL_CPHA;
238
239 if (spi->mode & SPI_LSB_FIRST)
240 reg |= SUN6I_TFR_CTL_FBS;
241 else
242 reg &= ~SUN6I_TFR_CTL_FBS;
243
244 /*
245 * If it's a TX only transfer, we don't want to fill the RX
246 * FIFO with bogus data
247 */
248 if (sspi->rx_buf) {
249 reg &= ~SUN6I_TFR_CTL_DHB;
250 rx_len = tfr->len;
251 } else {
252 reg |= SUN6I_TFR_CTL_DHB;
253 }
254
255 /* We want to control the chip select manually */
256 reg |= SUN6I_TFR_CTL_CS_MANUAL;
257
258 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
259
260 /* Ensure that we have a parent clock fast enough */
261 mclk_rate = clk_get_rate(sspi->mclk);
262 if (mclk_rate < (2 * tfr->speed_hz)) {
263 clk_set_rate(sspi->mclk, 2 * tfr->speed_hz);
264 mclk_rate = clk_get_rate(sspi->mclk);
265 }
266
267 /*
268 * Setup clock divider.
269 *
270 * We have two choices there. Either we can use the clock
271 * divide rate 1, which is calculated thanks to this formula:
272 * SPI_CLK = MOD_CLK / (2 ^ cdr)
273 * Or we can use CDR2, which is calculated with the formula:
274 * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
275 * Wether we use the former or the latter is set through the
276 * DRS bit.
277 *
278 * First try CDR2, and if we can't reach the expected
279 * frequency, fall back to CDR1.
280 */
281 div_cdr1 = DIV_ROUND_UP(mclk_rate, tfr->speed_hz);
282 div_cdr2 = DIV_ROUND_UP(div_cdr1, 2);
283 if (div_cdr2 <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) {
284 reg = SUN6I_CLK_CTL_CDR2(div_cdr2 - 1) | SUN6I_CLK_CTL_DRS;
285 tfr->effective_speed_hz = mclk_rate / (2 * div_cdr2);
286 } else {
287 div = min(SUN6I_CLK_CTL_CDR1_MASK, order_base_2(div_cdr1));
288 reg = SUN6I_CLK_CTL_CDR1(div);
289 tfr->effective_speed_hz = mclk_rate / (1 << div);
290 }
291
292 sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg);
293
294 /* Setup the transfer now... */
295 if (sspi->tx_buf)
296 tx_len = tfr->len;
297
298 /* Setup the counters */
299 sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, tfr->len);
300 sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, tx_len);
301 sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG, tx_len);
302
303 /* Fill the TX FIFO */
304 sun6i_spi_fill_fifo(sspi);
305
306 /* Enable the interrupts */
307 reg = SUN6I_INT_CTL_TC;
308
309 if (rx_len > sspi->fifo_depth)
310 reg |= SUN6I_INT_CTL_RF_RDY;
311 if (tx_len > sspi->fifo_depth)
312 reg |= SUN6I_INT_CTL_TF_ERQ;
313
314 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
315
316 /* Start the transfer */
317 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
318 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg | SUN6I_TFR_CTL_XCH);
319
320 tx_time = max(tfr->len * 8 * 2 / (tfr->speed_hz / 1000), 100U);
321 start = jiffies;
322 timeout = wait_for_completion_timeout(&sspi->done,
323 msecs_to_jiffies(tx_time));
324 end = jiffies;
325 if (!timeout) {
326 dev_warn(&master->dev,
327 "%s: timeout transferring %u bytes@%iHz for %i(%i)ms",
328 dev_name(&spi->dev), tfr->len, tfr->speed_hz,
329 jiffies_to_msecs(end - start), tx_time);
330 ret = -ETIMEDOUT;
331 }
332
333 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0);
334
335 return ret;
336}
337
338static irqreturn_t sun6i_spi_handler(int irq, void *dev_id)
339{
340 struct sun6i_spi *sspi = dev_id;
341 u32 status = sun6i_spi_read(sspi, SUN6I_INT_STA_REG);
342
343 /* Transfer complete */
344 if (status & SUN6I_INT_CTL_TC) {
345 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC);
346 sun6i_spi_drain_fifo(sspi);
347 complete(&sspi->done);
348 return IRQ_HANDLED;
349 }
350
351 /* Receive FIFO 3/4 full */
352 if (status & SUN6I_INT_CTL_RF_RDY) {
353 sun6i_spi_drain_fifo(sspi);
354 /* Only clear the interrupt _after_ draining the FIFO */
355 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_RF_RDY);
356 return IRQ_HANDLED;
357 }
358
359 /* Transmit FIFO 3/4 empty */
360 if (status & SUN6I_INT_CTL_TF_ERQ) {
361 sun6i_spi_fill_fifo(sspi);
362
363 if (!sspi->len)
364 /* nothing left to transmit */
365 sun6i_spi_disable_interrupt(sspi, SUN6I_INT_CTL_TF_ERQ);
366
367 /* Only clear the interrupt _after_ re-seeding the FIFO */
368 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TF_ERQ);
369
370 return IRQ_HANDLED;
371 }
372
373 return IRQ_NONE;
374}
375
376static int sun6i_spi_runtime_resume(struct device *dev)
377{
378 struct spi_master *master = dev_get_drvdata(dev);
379 struct sun6i_spi *sspi = spi_master_get_devdata(master);
380 int ret;
381
382 ret = clk_prepare_enable(sspi->hclk);
383 if (ret) {
384 dev_err(dev, "Couldn't enable AHB clock\n");
385 goto out;
386 }
387
388 ret = clk_prepare_enable(sspi->mclk);
389 if (ret) {
390 dev_err(dev, "Couldn't enable module clock\n");
391 goto err;
392 }
393
394 ret = reset_control_deassert(sspi->rstc);
395 if (ret) {
396 dev_err(dev, "Couldn't deassert the device from reset\n");
397 goto err2;
398 }
399
400 sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG,
401 SUN6I_GBL_CTL_BUS_ENABLE | SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP);
402
403 return 0;
404
405err2:
406 clk_disable_unprepare(sspi->mclk);
407err:
408 clk_disable_unprepare(sspi->hclk);
409out:
410 return ret;
411}
412
413static int sun6i_spi_runtime_suspend(struct device *dev)
414{
415 struct spi_master *master = dev_get_drvdata(dev);
416 struct sun6i_spi *sspi = spi_master_get_devdata(master);
417
418 reset_control_assert(sspi->rstc);
419 clk_disable_unprepare(sspi->mclk);
420 clk_disable_unprepare(sspi->hclk);
421
422 return 0;
423}
424
425static int sun6i_spi_probe(struct platform_device *pdev)
426{
427 struct spi_master *master;
428 struct sun6i_spi *sspi;
429 int ret = 0, irq;
430
431 master = spi_alloc_master(&pdev->dev, sizeof(struct sun6i_spi));
432 if (!master) {
433 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
434 return -ENOMEM;
435 }
436
437 platform_set_drvdata(pdev, master);
438 sspi = spi_master_get_devdata(master);
439
440 sspi->base_addr = devm_platform_ioremap_resource(pdev, 0);
441 if (IS_ERR(sspi->base_addr)) {
442 ret = PTR_ERR(sspi->base_addr);
443 goto err_free_master;
444 }
445
446 irq = platform_get_irq(pdev, 0);
447 if (irq < 0) {
448 ret = -ENXIO;
449 goto err_free_master;
450 }
451
452 ret = devm_request_irq(&pdev->dev, irq, sun6i_spi_handler,
453 0, "sun6i-spi", sspi);
454 if (ret) {
455 dev_err(&pdev->dev, "Cannot request IRQ\n");
456 goto err_free_master;
457 }
458
459 sspi->master = master;
460 sspi->fifo_depth = (unsigned long)of_device_get_match_data(&pdev->dev);
461
462 master->max_speed_hz = 100 * 1000 * 1000;
463 master->min_speed_hz = 3 * 1000;
464 master->use_gpio_descriptors = true;
465 master->set_cs = sun6i_spi_set_cs;
466 master->transfer_one = sun6i_spi_transfer_one;
467 master->num_chipselect = 4;
468 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
469 master->bits_per_word_mask = SPI_BPW_MASK(8);
470 master->dev.of_node = pdev->dev.of_node;
471 master->auto_runtime_pm = true;
472 master->max_transfer_size = sun6i_spi_max_transfer_size;
473
474 sspi->hclk = devm_clk_get(&pdev->dev, "ahb");
475 if (IS_ERR(sspi->hclk)) {
476 dev_err(&pdev->dev, "Unable to acquire AHB clock\n");
477 ret = PTR_ERR(sspi->hclk);
478 goto err_free_master;
479 }
480
481 sspi->mclk = devm_clk_get(&pdev->dev, "mod");
482 if (IS_ERR(sspi->mclk)) {
483 dev_err(&pdev->dev, "Unable to acquire module clock\n");
484 ret = PTR_ERR(sspi->mclk);
485 goto err_free_master;
486 }
487
488 init_completion(&sspi->done);
489
490 sspi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
491 if (IS_ERR(sspi->rstc)) {
492 dev_err(&pdev->dev, "Couldn't get reset controller\n");
493 ret = PTR_ERR(sspi->rstc);
494 goto err_free_master;
495 }
496
497 /*
498 * This wake-up/shutdown pattern is to be able to have the
499 * device woken up, even if runtime_pm is disabled
500 */
501 ret = sun6i_spi_runtime_resume(&pdev->dev);
502 if (ret) {
503 dev_err(&pdev->dev, "Couldn't resume the device\n");
504 goto err_free_master;
505 }
506
507 pm_runtime_set_active(&pdev->dev);
508 pm_runtime_enable(&pdev->dev);
509 pm_runtime_idle(&pdev->dev);
510
511 ret = devm_spi_register_master(&pdev->dev, master);
512 if (ret) {
513 dev_err(&pdev->dev, "cannot register SPI master\n");
514 goto err_pm_disable;
515 }
516
517 return 0;
518
519err_pm_disable:
520 pm_runtime_disable(&pdev->dev);
521 sun6i_spi_runtime_suspend(&pdev->dev);
522err_free_master:
523 spi_master_put(master);
524 return ret;
525}
526
527static int sun6i_spi_remove(struct platform_device *pdev)
528{
529 pm_runtime_force_suspend(&pdev->dev);
530
531 return 0;
532}
533
534static const struct of_device_id sun6i_spi_match[] = {
535 { .compatible = "allwinner,sun6i-a31-spi", .data = (void *)SUN6I_FIFO_DEPTH },
536 { .compatible = "allwinner,sun8i-h3-spi", .data = (void *)SUN8I_FIFO_DEPTH },
537 {}
538};
539MODULE_DEVICE_TABLE(of, sun6i_spi_match);
540
541static const struct dev_pm_ops sun6i_spi_pm_ops = {
542 .runtime_resume = sun6i_spi_runtime_resume,
543 .runtime_suspend = sun6i_spi_runtime_suspend,
544};
545
546static struct platform_driver sun6i_spi_driver = {
547 .probe = sun6i_spi_probe,
548 .remove = sun6i_spi_remove,
549 .driver = {
550 .name = "sun6i-spi",
551 .of_match_table = sun6i_spi_match,
552 .pm = &sun6i_spi_pm_ops,
553 },
554};
555module_platform_driver(sun6i_spi_driver);
556
557MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>");
558MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
559MODULE_DESCRIPTION("Allwinner A31 SPI controller driver");
560MODULE_LICENSE("GPL");