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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * DWMAC4 Header file.
4 *
5 * Copyright (C) 2015 STMicroelectronics Ltd
6 *
7 * Author: Alexandre Torgue <alexandre.torgue@st.com>
8 */
9
10#ifndef __DWMAC4_H__
11#define __DWMAC4_H__
12
13#include "common.h"
14
15/* MAC registers */
16#define GMAC_CONFIG 0x00000000
17#define GMAC_EXT_CONFIG 0x00000004
18#define GMAC_PACKET_FILTER 0x00000008
19#define GMAC_HASH_TAB(x) (0x10 + (x) * 4)
20#define GMAC_VLAN_TAG 0x00000050
21#define GMAC_VLAN_TAG_DATA 0x00000054
22#define GMAC_VLAN_HASH_TABLE 0x00000058
23#define GMAC_RX_FLOW_CTRL 0x00000090
24#define GMAC_VLAN_INCL 0x00000060
25#define GMAC_QX_TX_FLOW_CTRL(x) (0x70 + x * 4)
26#define GMAC_TXQ_PRTY_MAP0 0x98
27#define GMAC_TXQ_PRTY_MAP1 0x9C
28#define GMAC_RXQ_CTRL0 0x000000a0
29#define GMAC_RXQ_CTRL1 0x000000a4
30#define GMAC_RXQ_CTRL2 0x000000a8
31#define GMAC_RXQ_CTRL3 0x000000ac
32#define GMAC_INT_STATUS 0x000000b0
33#define GMAC_INT_EN 0x000000b4
34#define GMAC_1US_TIC_COUNTER 0x000000dc
35#define GMAC_PCS_BASE 0x000000e0
36#define GMAC_PHYIF_CONTROL_STATUS 0x000000f8
37#define GMAC_PMT 0x000000c0
38#define GMAC_DEBUG 0x00000114
39#define GMAC_HW_FEATURE0 0x0000011c
40#define GMAC_HW_FEATURE1 0x00000120
41#define GMAC_HW_FEATURE2 0x00000124
42#define GMAC_HW_FEATURE3 0x00000128
43#define GMAC_MDIO_ADDR 0x00000200
44#define GMAC_MDIO_DATA 0x00000204
45#define GMAC_GPIO_STATUS 0x0000020C
46#define GMAC_ARP_ADDR 0x00000210
47#define GMAC_EXT_CFG1 0x00000238
48#define GMAC_ADDR_HIGH(reg) (0x300 + reg * 8)
49#define GMAC_ADDR_LOW(reg) (0x304 + reg * 8)
50#define GMAC_L3L4_CTRL(reg) (0x900 + (reg) * 0x30)
51#define GMAC_L4_ADDR(reg) (0x904 + (reg) * 0x30)
52#define GMAC_L3_ADDR0(reg) (0x910 + (reg) * 0x30)
53#define GMAC_L3_ADDR1(reg) (0x914 + (reg) * 0x30)
54#define GMAC_TIMESTAMP_STATUS 0x00000b20
55
56/* RX Queues Routing */
57#define GMAC_RXQCTRL_AVCPQ_MASK GENMASK(2, 0)
58#define GMAC_RXQCTRL_AVCPQ_SHIFT 0
59#define GMAC_RXQCTRL_PTPQ_MASK GENMASK(6, 4)
60#define GMAC_RXQCTRL_PTPQ_SHIFT 4
61#define GMAC_RXQCTRL_DCBCPQ_MASK GENMASK(10, 8)
62#define GMAC_RXQCTRL_DCBCPQ_SHIFT 8
63#define GMAC_RXQCTRL_UPQ_MASK GENMASK(14, 12)
64#define GMAC_RXQCTRL_UPQ_SHIFT 12
65#define GMAC_RXQCTRL_MCBCQ_MASK GENMASK(18, 16)
66#define GMAC_RXQCTRL_MCBCQ_SHIFT 16
67#define GMAC_RXQCTRL_MCBCQEN BIT(20)
68#define GMAC_RXQCTRL_MCBCQEN_SHIFT 20
69#define GMAC_RXQCTRL_TACPQE BIT(21)
70#define GMAC_RXQCTRL_TACPQE_SHIFT 21
71#define GMAC_RXQCTRL_FPRQ GENMASK(26, 24)
72
73/* MAC Packet Filtering */
74#define GMAC_PACKET_FILTER_PR BIT(0)
75#define GMAC_PACKET_FILTER_HMC BIT(2)
76#define GMAC_PACKET_FILTER_PM BIT(4)
77#define GMAC_PACKET_FILTER_PCF BIT(7)
78#define GMAC_PACKET_FILTER_HPF BIT(10)
79#define GMAC_PACKET_FILTER_VTFE BIT(16)
80#define GMAC_PACKET_FILTER_IPFE BIT(20)
81#define GMAC_PACKET_FILTER_RA BIT(31)
82
83#define GMAC_MAX_PERFECT_ADDRESSES 128
84
85/* MAC VLAN */
86#define GMAC_VLAN_EDVLP BIT(26)
87#define GMAC_VLAN_VTHM BIT(25)
88#define GMAC_VLAN_DOVLTC BIT(20)
89#define GMAC_VLAN_ESVL BIT(18)
90#define GMAC_VLAN_ETV BIT(16)
91#define GMAC_VLAN_VID GENMASK(15, 0)
92#define GMAC_VLAN_VLTI BIT(20)
93#define GMAC_VLAN_CSVL BIT(19)
94#define GMAC_VLAN_VLC GENMASK(17, 16)
95#define GMAC_VLAN_VLC_SHIFT 16
96#define GMAC_VLAN_VLHT GENMASK(15, 0)
97
98/* MAC VLAN Tag */
99#define GMAC_VLAN_TAG_VID GENMASK(15, 0)
100#define GMAC_VLAN_TAG_ETV BIT(16)
101
102/* MAC VLAN Tag Control */
103#define GMAC_VLAN_TAG_CTRL_OB BIT(0)
104#define GMAC_VLAN_TAG_CTRL_CT BIT(1)
105#define GMAC_VLAN_TAG_CTRL_OFS_MASK GENMASK(6, 2)
106#define GMAC_VLAN_TAG_CTRL_OFS_SHIFT 2
107#define GMAC_VLAN_TAG_CTRL_EVLS_MASK GENMASK(22, 21)
108#define GMAC_VLAN_TAG_CTRL_EVLS_SHIFT 21
109#define GMAC_VLAN_TAG_CTRL_EVLRXS BIT(24)
110
111#define GMAC_VLAN_TAG_STRIP_NONE (0x0 << GMAC_VLAN_TAG_CTRL_EVLS_SHIFT)
112#define GMAC_VLAN_TAG_STRIP_PASS (0x1 << GMAC_VLAN_TAG_CTRL_EVLS_SHIFT)
113#define GMAC_VLAN_TAG_STRIP_FAIL (0x2 << GMAC_VLAN_TAG_CTRL_EVLS_SHIFT)
114#define GMAC_VLAN_TAG_STRIP_ALL (0x3 << GMAC_VLAN_TAG_CTRL_EVLS_SHIFT)
115
116/* MAC VLAN Tag Data/Filter */
117#define GMAC_VLAN_TAG_DATA_VID GENMASK(15, 0)
118#define GMAC_VLAN_TAG_DATA_VEN BIT(16)
119#define GMAC_VLAN_TAG_DATA_ETV BIT(17)
120
121/* MAC RX Queue Enable */
122#define GMAC_RX_QUEUE_CLEAR(queue) ~(GENMASK(1, 0) << ((queue) * 2))
123#define GMAC_RX_AV_QUEUE_ENABLE(queue) BIT((queue) * 2)
124#define GMAC_RX_DCB_QUEUE_ENABLE(queue) BIT(((queue) * 2) + 1)
125
126/* MAC Flow Control RX */
127#define GMAC_RX_FLOW_CTRL_RFE BIT(0)
128
129/* RX Queues Priorities */
130#define GMAC_RXQCTRL_PSRQX_MASK(x) GENMASK(7 + ((x) * 8), 0 + ((x) * 8))
131#define GMAC_RXQCTRL_PSRQX_SHIFT(x) ((x) * 8)
132
133/* TX Queues Priorities */
134#define GMAC_TXQCTRL_PSTQX_MASK(x) GENMASK(7 + ((x) * 8), 0 + ((x) * 8))
135#define GMAC_TXQCTRL_PSTQX_SHIFT(x) ((x) * 8)
136
137/* MAC Flow Control TX */
138#define GMAC_TX_FLOW_CTRL_TFE BIT(1)
139#define GMAC_TX_FLOW_CTRL_PT_SHIFT 16
140
141/* MAC Interrupt bitmap*/
142#define GMAC_INT_RGSMIIS BIT(0)
143#define GMAC_INT_PCS_LINK BIT(1)
144#define GMAC_INT_PCS_ANE BIT(2)
145#define GMAC_INT_PCS_PHYIS BIT(3)
146#define GMAC_INT_PMT_EN BIT(4)
147#define GMAC_INT_LPI_EN BIT(5)
148#define GMAC_INT_TSIE BIT(12)
149
150#define GMAC_PCS_IRQ_DEFAULT (GMAC_INT_RGSMIIS | GMAC_INT_PCS_LINK | \
151 GMAC_INT_PCS_ANE)
152
153#define GMAC_INT_DEFAULT_ENABLE (GMAC_INT_PMT_EN | GMAC_INT_LPI_EN | \
154 GMAC_INT_TSIE)
155
156enum dwmac4_irq_status {
157 time_stamp_irq = 0x00001000,
158 mmc_rx_csum_offload_irq = 0x00000800,
159 mmc_tx_irq = 0x00000400,
160 mmc_rx_irq = 0x00000200,
161 mmc_irq = 0x00000100,
162 lpi_irq = 0x00000020,
163 pmt_irq = 0x00000010,
164};
165
166/* MAC PMT bitmap */
167enum power_event {
168 pointer_reset = 0x80000000,
169 global_unicast = 0x00000200,
170 wake_up_rx_frame = 0x00000040,
171 magic_frame = 0x00000020,
172 wake_up_frame_en = 0x00000004,
173 magic_pkt_en = 0x00000002,
174 power_down = 0x00000001,
175};
176
177/* Energy Efficient Ethernet (EEE) for GMAC4
178 *
179 * LPI status, timer and control register offset
180 */
181#define GMAC4_LPI_CTRL_STATUS 0xd0
182#define GMAC4_LPI_TIMER_CTRL 0xd4
183#define GMAC4_LPI_ENTRY_TIMER 0xd8
184#define GMAC4_MAC_ONEUS_TIC_COUNTER 0xdc
185
186/* LPI control and status defines */
187#define GMAC4_LPI_CTRL_STATUS_LPITCSE BIT(21) /* LPI Tx Clock Stop Enable */
188#define GMAC4_LPI_CTRL_STATUS_LPIATE BIT(20) /* LPI Timer Enable */
189#define GMAC4_LPI_CTRL_STATUS_LPITXA BIT(19) /* Enable LPI TX Automate */
190#define GMAC4_LPI_CTRL_STATUS_PLS BIT(17) /* PHY Link Status */
191#define GMAC4_LPI_CTRL_STATUS_LPIEN BIT(16) /* LPI Enable */
192#define GMAC4_LPI_CTRL_STATUS_RLPIEX BIT(3) /* Receive LPI Exit */
193#define GMAC4_LPI_CTRL_STATUS_RLPIEN BIT(2) /* Receive LPI Entry */
194#define GMAC4_LPI_CTRL_STATUS_TLPIEX BIT(1) /* Transmit LPI Exit */
195#define GMAC4_LPI_CTRL_STATUS_TLPIEN BIT(0) /* Transmit LPI Entry */
196
197/* MAC Debug bitmap */
198#define GMAC_DEBUG_TFCSTS_MASK GENMASK(18, 17)
199#define GMAC_DEBUG_TFCSTS_SHIFT 17
200#define GMAC_DEBUG_TFCSTS_IDLE 0
201#define GMAC_DEBUG_TFCSTS_WAIT 1
202#define GMAC_DEBUG_TFCSTS_GEN_PAUSE 2
203#define GMAC_DEBUG_TFCSTS_XFER 3
204#define GMAC_DEBUG_TPESTS BIT(16)
205#define GMAC_DEBUG_RFCFCSTS_MASK GENMASK(2, 1)
206#define GMAC_DEBUG_RFCFCSTS_SHIFT 1
207#define GMAC_DEBUG_RPESTS BIT(0)
208
209/* MAC config */
210#define GMAC_CONFIG_ARPEN BIT(31)
211#define GMAC_CONFIG_SARC GENMASK(30, 28)
212#define GMAC_CONFIG_SARC_SHIFT 28
213#define GMAC_CONFIG_IPC BIT(27)
214#define GMAC_CONFIG_IPG GENMASK(26, 24)
215#define GMAC_CONFIG_IPG_SHIFT 24
216#define GMAC_CONFIG_2K BIT(22)
217#define GMAC_CONFIG_ACS BIT(20)
218#define GMAC_CONFIG_BE BIT(18)
219#define GMAC_CONFIG_JD BIT(17)
220#define GMAC_CONFIG_JE BIT(16)
221#define GMAC_CONFIG_PS BIT(15)
222#define GMAC_CONFIG_FES BIT(14)
223#define GMAC_CONFIG_FES_SHIFT 14
224#define GMAC_CONFIG_DM BIT(13)
225#define GMAC_CONFIG_LM BIT(12)
226#define GMAC_CONFIG_DCRS BIT(9)
227#define GMAC_CONFIG_TE BIT(1)
228#define GMAC_CONFIG_RE BIT(0)
229
230/* MAC extended config */
231#define GMAC_CONFIG_EIPG GENMASK(29, 25)
232#define GMAC_CONFIG_EIPG_SHIFT 25
233#define GMAC_CONFIG_EIPG_EN BIT(24)
234#define GMAC_CONFIG_HDSMS GENMASK(22, 20)
235#define GMAC_CONFIG_HDSMS_SHIFT 20
236#define GMAC_CONFIG_HDSMS_256 (0x2 << GMAC_CONFIG_HDSMS_SHIFT)
237
238/* MAC HW features0 bitmap */
239#define GMAC_HW_FEAT_SAVLANINS BIT(27)
240#define GMAC_HW_FEAT_ADDMAC BIT(18)
241#define GMAC_HW_FEAT_RXCOESEL BIT(16)
242#define GMAC_HW_FEAT_TXCOSEL BIT(14)
243#define GMAC_HW_FEAT_EEESEL BIT(13)
244#define GMAC_HW_FEAT_TSSEL BIT(12)
245#define GMAC_HW_FEAT_ARPOFFSEL BIT(9)
246#define GMAC_HW_FEAT_MMCSEL BIT(8)
247#define GMAC_HW_FEAT_MGKSEL BIT(7)
248#define GMAC_HW_FEAT_RWKSEL BIT(6)
249#define GMAC_HW_FEAT_SMASEL BIT(5)
250#define GMAC_HW_FEAT_VLHASH BIT(4)
251#define GMAC_HW_FEAT_PCSSEL BIT(3)
252#define GMAC_HW_FEAT_HDSEL BIT(2)
253#define GMAC_HW_FEAT_GMIISEL BIT(1)
254#define GMAC_HW_FEAT_MIISEL BIT(0)
255
256/* MAC HW features1 bitmap */
257#define GMAC_HW_FEAT_L3L4FNUM GENMASK(30, 27)
258#define GMAC_HW_HASH_TB_SZ GENMASK(25, 24)
259#define GMAC_HW_FEAT_AVSEL BIT(20)
260#define GMAC_HW_TSOEN BIT(18)
261#define GMAC_HW_FEAT_SPHEN BIT(17)
262#define GMAC_HW_ADDR64 GENMASK(15, 14)
263#define GMAC_HW_TXFIFOSIZE GENMASK(10, 6)
264#define GMAC_HW_RXFIFOSIZE GENMASK(4, 0)
265
266/* MAC HW features2 bitmap */
267#define GMAC_HW_FEAT_AUXSNAPNUM GENMASK(30, 28)
268#define GMAC_HW_FEAT_PPSOUTNUM GENMASK(26, 24)
269#define GMAC_HW_FEAT_TXCHCNT GENMASK(21, 18)
270#define GMAC_HW_FEAT_RXCHCNT GENMASK(15, 12)
271#define GMAC_HW_FEAT_TXQCNT GENMASK(9, 6)
272#define GMAC_HW_FEAT_RXQCNT GENMASK(3, 0)
273
274/* MAC HW features3 bitmap */
275#define GMAC_HW_FEAT_ASP GENMASK(29, 28)
276#define GMAC_HW_FEAT_TBSSEL BIT(27)
277#define GMAC_HW_FEAT_FPESEL BIT(26)
278#define GMAC_HW_FEAT_ESTWID GENMASK(21, 20)
279#define GMAC_HW_FEAT_ESTDEP GENMASK(19, 17)
280#define GMAC_HW_FEAT_ESTSEL BIT(16)
281#define GMAC_HW_FEAT_FRPES GENMASK(14, 13)
282#define GMAC_HW_FEAT_FRPBS GENMASK(12, 11)
283#define GMAC_HW_FEAT_FRPSEL BIT(10)
284#define GMAC_HW_FEAT_DVLAN BIT(5)
285#define GMAC_HW_FEAT_NRVF GENMASK(2, 0)
286
287/* MAC extended config 1 */
288#define GMAC_CONFIG1_SAVE_EN BIT(24)
289#define GMAC_CONFIG1_SPLM(v) FIELD_PREP(GENMASK(9, 8), v)
290
291/* GMAC GPIO Status reg */
292#define GMAC_GPO0 BIT(16)
293#define GMAC_GPO1 BIT(17)
294#define GMAC_GPO2 BIT(18)
295#define GMAC_GPO3 BIT(19)
296
297/* MAC HW ADDR regs */
298#define GMAC_HI_DCS GENMASK(18, 16)
299#define GMAC_HI_DCS_SHIFT 16
300#define GMAC_HI_REG_AE BIT(31)
301
302/* L3/L4 Filters regs */
303#define GMAC_L4DPIM0 BIT(21)
304#define GMAC_L4DPM0 BIT(20)
305#define GMAC_L4SPIM0 BIT(19)
306#define GMAC_L4SPM0 BIT(18)
307#define GMAC_L4PEN0 BIT(16)
308#define GMAC_L3DAIM0 BIT(5)
309#define GMAC_L3DAM0 BIT(4)
310#define GMAC_L3SAIM0 BIT(3)
311#define GMAC_L3SAM0 BIT(2)
312#define GMAC_L3PEN0 BIT(0)
313#define GMAC_L4DP0 GENMASK(31, 16)
314#define GMAC_L4DP0_SHIFT 16
315#define GMAC_L4SP0 GENMASK(15, 0)
316
317/* MAC Timestamp Status */
318#define GMAC_TIMESTAMP_AUXTSTRIG BIT(2)
319#define GMAC_TIMESTAMP_ATSNS_MASK GENMASK(29, 25)
320#define GMAC_TIMESTAMP_ATSNS_SHIFT 25
321
322/* MTL registers */
323#define MTL_OPERATION_MODE 0x00000c00
324#define MTL_FRPE BIT(15)
325#define MTL_OPERATION_SCHALG_MASK GENMASK(6, 5)
326#define MTL_OPERATION_SCHALG_WRR (0x0 << 5)
327#define MTL_OPERATION_SCHALG_WFQ (0x1 << 5)
328#define MTL_OPERATION_SCHALG_DWRR (0x2 << 5)
329#define MTL_OPERATION_SCHALG_SP (0x3 << 5)
330#define MTL_OPERATION_RAA BIT(2)
331#define MTL_OPERATION_RAA_SP (0x0 << 2)
332#define MTL_OPERATION_RAA_WSP (0x1 << 2)
333
334#define MTL_INT_STATUS 0x00000c20
335#define MTL_INT_QX(x) BIT(x)
336
337#define MTL_RXQ_DMA_MAP0 0x00000c30 /* queue 0 to 3 */
338#define MTL_RXQ_DMA_MAP1 0x00000c34 /* queue 4 to 7 */
339#define MTL_RXQ_DMA_QXMDMACH_MASK(x) (0xf << 8 * (x))
340#define MTL_RXQ_DMA_QXMDMACH(chan, q) ((chan) << (8 * (q)))
341
342#define MTL_CHAN_BASE_ADDR 0x00000d00
343#define MTL_CHAN_BASE_OFFSET 0x40
344
345static inline u32 mtl_chanx_base_addr(const struct dwmac4_addrs *addrs,
346 const u32 x)
347{
348 u32 addr;
349
350 if (addrs)
351 addr = addrs->mtl_chan + (x * addrs->mtl_chan_offset);
352 else
353 addr = MTL_CHAN_BASE_ADDR + (x * MTL_CHAN_BASE_OFFSET);
354
355 return addr;
356}
357
358#define MTL_CHAN_TX_OP_MODE(addrs, x) mtl_chanx_base_addr(addrs, x)
359#define MTL_CHAN_TX_DEBUG(addrs, x) (mtl_chanx_base_addr(addrs, x) + 0x8)
360#define MTL_CHAN_INT_CTRL(addrs, x) (mtl_chanx_base_addr(addrs, x) + 0x2c)
361#define MTL_CHAN_RX_OP_MODE(addrs, x) (mtl_chanx_base_addr(addrs, x) + 0x30)
362#define MTL_CHAN_RX_DEBUG(addrs, x) (mtl_chanx_base_addr(addrs, x) + 0x38)
363
364#define MTL_OP_MODE_RSF BIT(5)
365#define MTL_OP_MODE_TXQEN_MASK GENMASK(3, 2)
366#define MTL_OP_MODE_TXQEN_AV BIT(2)
367#define MTL_OP_MODE_TXQEN BIT(3)
368#define MTL_OP_MODE_TSF BIT(1)
369
370#define MTL_OP_MODE_TQS_MASK GENMASK(24, 16)
371#define MTL_OP_MODE_TQS_SHIFT 16
372
373#define MTL_OP_MODE_TTC_MASK 0x70
374#define MTL_OP_MODE_TTC_SHIFT 4
375
376#define MTL_OP_MODE_TTC_32 0
377#define MTL_OP_MODE_TTC_64 (1 << MTL_OP_MODE_TTC_SHIFT)
378#define MTL_OP_MODE_TTC_96 (2 << MTL_OP_MODE_TTC_SHIFT)
379#define MTL_OP_MODE_TTC_128 (3 << MTL_OP_MODE_TTC_SHIFT)
380#define MTL_OP_MODE_TTC_192 (4 << MTL_OP_MODE_TTC_SHIFT)
381#define MTL_OP_MODE_TTC_256 (5 << MTL_OP_MODE_TTC_SHIFT)
382#define MTL_OP_MODE_TTC_384 (6 << MTL_OP_MODE_TTC_SHIFT)
383#define MTL_OP_MODE_TTC_512 (7 << MTL_OP_MODE_TTC_SHIFT)
384
385#define MTL_OP_MODE_RQS_MASK GENMASK(29, 20)
386#define MTL_OP_MODE_RQS_SHIFT 20
387
388#define MTL_OP_MODE_RFD_MASK GENMASK(19, 14)
389#define MTL_OP_MODE_RFD_SHIFT 14
390
391#define MTL_OP_MODE_RFA_MASK GENMASK(13, 8)
392#define MTL_OP_MODE_RFA_SHIFT 8
393
394#define MTL_OP_MODE_EHFC BIT(7)
395
396#define MTL_OP_MODE_RTC_MASK GENMASK(1, 0)
397#define MTL_OP_MODE_RTC_SHIFT 0
398
399#define MTL_OP_MODE_RTC_32 (1 << MTL_OP_MODE_RTC_SHIFT)
400#define MTL_OP_MODE_RTC_64 0
401#define MTL_OP_MODE_RTC_96 (2 << MTL_OP_MODE_RTC_SHIFT)
402#define MTL_OP_MODE_RTC_128 (3 << MTL_OP_MODE_RTC_SHIFT)
403
404/* MTL ETS Control register */
405#define MTL_ETS_CTRL_BASE_ADDR 0x00000d10
406#define MTL_ETS_CTRL_BASE_OFFSET 0x40
407
408static inline u32 mtl_etsx_ctrl_base_addr(const struct dwmac4_addrs *addrs,
409 const u32 x)
410{
411 u32 addr;
412
413 if (addrs)
414 addr = addrs->mtl_ets_ctrl + (x * addrs->mtl_ets_ctrl_offset);
415 else
416 addr = MTL_ETS_CTRL_BASE_ADDR + (x * MTL_ETS_CTRL_BASE_OFFSET);
417
418 return addr;
419}
420
421#define MTL_ETS_CTRL_CC BIT(3)
422#define MTL_ETS_CTRL_AVALG BIT(2)
423
424/* MTL Queue Quantum Weight */
425#define MTL_TXQ_WEIGHT_BASE_ADDR 0x00000d18
426#define MTL_TXQ_WEIGHT_BASE_OFFSET 0x40
427
428static inline u32 mtl_txqx_weight_base_addr(const struct dwmac4_addrs *addrs,
429 const u32 x)
430{
431 u32 addr;
432
433 if (addrs)
434 addr = addrs->mtl_txq_weight + (x * addrs->mtl_txq_weight_offset);
435 else
436 addr = MTL_TXQ_WEIGHT_BASE_ADDR + (x * MTL_TXQ_WEIGHT_BASE_OFFSET);
437
438 return addr;
439}
440
441#define MTL_TXQ_WEIGHT_ISCQW_MASK GENMASK(20, 0)
442
443/* MTL sendSlopeCredit register */
444#define MTL_SEND_SLP_CRED_BASE_ADDR 0x00000d1c
445#define MTL_SEND_SLP_CRED_OFFSET 0x40
446
447static inline u32 mtl_send_slp_credx_base_addr(const struct dwmac4_addrs *addrs,
448 const u32 x)
449{
450 u32 addr;
451
452 if (addrs)
453 addr = addrs->mtl_send_slp_cred + (x * addrs->mtl_send_slp_cred_offset);
454 else
455 addr = MTL_SEND_SLP_CRED_BASE_ADDR + (x * MTL_SEND_SLP_CRED_OFFSET);
456
457 return addr;
458}
459
460#define MTL_SEND_SLP_CRED_SSC_MASK GENMASK(13, 0)
461
462/* MTL hiCredit register */
463#define MTL_HIGH_CRED_BASE_ADDR 0x00000d20
464#define MTL_HIGH_CRED_OFFSET 0x40
465
466static inline u32 mtl_high_credx_base_addr(const struct dwmac4_addrs *addrs,
467 const u32 x)
468{
469 u32 addr;
470
471 if (addrs)
472 addr = addrs->mtl_high_cred + (x * addrs->mtl_high_cred_offset);
473 else
474 addr = MTL_HIGH_CRED_BASE_ADDR + (x * MTL_HIGH_CRED_OFFSET);
475
476 return addr;
477}
478
479#define MTL_HIGH_CRED_HC_MASK GENMASK(28, 0)
480
481/* MTL loCredit register */
482#define MTL_LOW_CRED_BASE_ADDR 0x00000d24
483#define MTL_LOW_CRED_OFFSET 0x40
484
485static inline u32 mtl_low_credx_base_addr(const struct dwmac4_addrs *addrs,
486 const u32 x)
487{
488 u32 addr;
489
490 if (addrs)
491 addr = addrs->mtl_low_cred + (x * addrs->mtl_low_cred_offset);
492 else
493 addr = MTL_LOW_CRED_BASE_ADDR + (x * MTL_LOW_CRED_OFFSET);
494
495 return addr;
496}
497
498#define MTL_HIGH_CRED_LC_MASK GENMASK(28, 0)
499
500/* MTL debug */
501#define MTL_DEBUG_TXSTSFSTS BIT(5)
502#define MTL_DEBUG_TXFSTS BIT(4)
503#define MTL_DEBUG_TWCSTS BIT(3)
504
505/* MTL debug: Tx FIFO Read Controller Status */
506#define MTL_DEBUG_TRCSTS_MASK GENMASK(2, 1)
507#define MTL_DEBUG_TRCSTS_SHIFT 1
508#define MTL_DEBUG_TRCSTS_IDLE 0
509#define MTL_DEBUG_TRCSTS_READ 1
510#define MTL_DEBUG_TRCSTS_TXW 2
511#define MTL_DEBUG_TRCSTS_WRITE 3
512#define MTL_DEBUG_TXPAUSED BIT(0)
513
514/* MAC debug: GMII or MII Transmit Protocol Engine Status */
515#define MTL_DEBUG_RXFSTS_MASK GENMASK(5, 4)
516#define MTL_DEBUG_RXFSTS_SHIFT 4
517#define MTL_DEBUG_RXFSTS_EMPTY 0
518#define MTL_DEBUG_RXFSTS_BT 1
519#define MTL_DEBUG_RXFSTS_AT 2
520#define MTL_DEBUG_RXFSTS_FULL 3
521#define MTL_DEBUG_RRCSTS_MASK GENMASK(2, 1)
522#define MTL_DEBUG_RRCSTS_SHIFT 1
523#define MTL_DEBUG_RRCSTS_IDLE 0
524#define MTL_DEBUG_RRCSTS_RDATA 1
525#define MTL_DEBUG_RRCSTS_RSTAT 2
526#define MTL_DEBUG_RRCSTS_FLUSH 3
527#define MTL_DEBUG_RWCSTS BIT(0)
528
529/* MTL interrupt */
530#define MTL_RX_OVERFLOW_INT_EN BIT(24)
531#define MTL_RX_OVERFLOW_INT BIT(16)
532
533/* Default operating mode of the MAC */
534#define GMAC_CORE_INIT (GMAC_CONFIG_JD | GMAC_CONFIG_PS | \
535 GMAC_CONFIG_BE | GMAC_CONFIG_DCRS | \
536 GMAC_CONFIG_JE)
537
538/* To dump the core regs excluding the Address Registers */
539#define GMAC_REG_NUM 132
540
541/* MTL debug */
542#define MTL_DEBUG_TXSTSFSTS BIT(5)
543#define MTL_DEBUG_TXFSTS BIT(4)
544#define MTL_DEBUG_TWCSTS BIT(3)
545
546/* MTL debug: Tx FIFO Read Controller Status */
547#define MTL_DEBUG_TRCSTS_MASK GENMASK(2, 1)
548#define MTL_DEBUG_TRCSTS_SHIFT 1
549#define MTL_DEBUG_TRCSTS_IDLE 0
550#define MTL_DEBUG_TRCSTS_READ 1
551#define MTL_DEBUG_TRCSTS_TXW 2
552#define MTL_DEBUG_TRCSTS_WRITE 3
553#define MTL_DEBUG_TXPAUSED BIT(0)
554
555/* MAC debug: GMII or MII Transmit Protocol Engine Status */
556#define MTL_DEBUG_RXFSTS_MASK GENMASK(5, 4)
557#define MTL_DEBUG_RXFSTS_SHIFT 4
558#define MTL_DEBUG_RXFSTS_EMPTY 0
559#define MTL_DEBUG_RXFSTS_BT 1
560#define MTL_DEBUG_RXFSTS_AT 2
561#define MTL_DEBUG_RXFSTS_FULL 3
562#define MTL_DEBUG_RRCSTS_MASK GENMASK(2, 1)
563#define MTL_DEBUG_RRCSTS_SHIFT 1
564#define MTL_DEBUG_RRCSTS_IDLE 0
565#define MTL_DEBUG_RRCSTS_RDATA 1
566#define MTL_DEBUG_RRCSTS_RSTAT 2
567#define MTL_DEBUG_RRCSTS_FLUSH 3
568#define MTL_DEBUG_RWCSTS BIT(0)
569
570/* SGMII/RGMII status register */
571#define GMAC_PHYIF_CTRLSTATUS_TC BIT(0)
572#define GMAC_PHYIF_CTRLSTATUS_LUD BIT(1)
573#define GMAC_PHYIF_CTRLSTATUS_SMIDRXS BIT(4)
574#define GMAC_PHYIF_CTRLSTATUS_LNKMOD BIT(16)
575#define GMAC_PHYIF_CTRLSTATUS_SPEED GENMASK(18, 17)
576#define GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT 17
577#define GMAC_PHYIF_CTRLSTATUS_LNKSTS BIT(19)
578#define GMAC_PHYIF_CTRLSTATUS_JABTO BIT(20)
579#define GMAC_PHYIF_CTRLSTATUS_FALSECARDET BIT(21)
580/* LNKSPEED */
581#define GMAC_PHYIF_CTRLSTATUS_SPEED_125 0x2
582#define GMAC_PHYIF_CTRLSTATUS_SPEED_25 0x1
583#define GMAC_PHYIF_CTRLSTATUS_SPEED_2_5 0x0
584
585extern const struct stmmac_dma_ops dwmac4_dma_ops;
586extern const struct stmmac_dma_ops dwmac410_dma_ops;
587#endif /* __DWMAC4_H__ */
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * DWMAC4 Header file.
4 *
5 * Copyright (C) 2015 STMicroelectronics Ltd
6 *
7 * Author: Alexandre Torgue <alexandre.torgue@st.com>
8 */
9
10#ifndef __DWMAC4_H__
11#define __DWMAC4_H__
12
13#include "common.h"
14
15/* MAC registers */
16#define GMAC_CONFIG 0x00000000
17#define GMAC_EXT_CONFIG 0x00000004
18#define GMAC_PACKET_FILTER 0x00000008
19#define GMAC_HASH_TAB(x) (0x10 + (x) * 4)
20#define GMAC_VLAN_TAG 0x00000050
21#define GMAC_VLAN_TAG_DATA 0x00000054
22#define GMAC_VLAN_HASH_TABLE 0x00000058
23#define GMAC_RX_FLOW_CTRL 0x00000090
24#define GMAC_VLAN_INCL 0x00000060
25#define GMAC_QX_TX_FLOW_CTRL(x) (0x70 + x * 4)
26#define GMAC_TXQ_PRTY_MAP0 0x98
27#define GMAC_TXQ_PRTY_MAP1 0x9C
28#define GMAC_RXQ_CTRL0 0x000000a0
29#define GMAC_RXQ_CTRL1 0x000000a4
30#define GMAC_RXQ_CTRL2 0x000000a8
31#define GMAC_RXQ_CTRL3 0x000000ac
32#define GMAC_INT_STATUS 0x000000b0
33#define GMAC_INT_EN 0x000000b4
34#define GMAC_1US_TIC_COUNTER 0x000000dc
35#define GMAC_PCS_BASE 0x000000e0
36#define GMAC_PHYIF_CONTROL_STATUS 0x000000f8
37#define GMAC_PMT 0x000000c0
38#define GMAC_DEBUG 0x00000114
39#define GMAC_HW_FEATURE0 0x0000011c
40#define GMAC_HW_FEATURE1 0x00000120
41#define GMAC_HW_FEATURE2 0x00000124
42#define GMAC_HW_FEATURE3 0x00000128
43#define GMAC_MDIO_ADDR 0x00000200
44#define GMAC_MDIO_DATA 0x00000204
45#define GMAC_ARP_ADDR 0x00000210
46#define GMAC_ADDR_HIGH(reg) (0x300 + reg * 8)
47#define GMAC_ADDR_LOW(reg) (0x304 + reg * 8)
48#define GMAC_L3L4_CTRL(reg) (0x900 + (reg) * 0x30)
49#define GMAC_L4_ADDR(reg) (0x904 + (reg) * 0x30)
50#define GMAC_L3_ADDR0(reg) (0x910 + (reg) * 0x30)
51#define GMAC_L3_ADDR1(reg) (0x914 + (reg) * 0x30)
52
53/* RX Queues Routing */
54#define GMAC_RXQCTRL_AVCPQ_MASK GENMASK(2, 0)
55#define GMAC_RXQCTRL_AVCPQ_SHIFT 0
56#define GMAC_RXQCTRL_PTPQ_MASK GENMASK(6, 4)
57#define GMAC_RXQCTRL_PTPQ_SHIFT 4
58#define GMAC_RXQCTRL_DCBCPQ_MASK GENMASK(10, 8)
59#define GMAC_RXQCTRL_DCBCPQ_SHIFT 8
60#define GMAC_RXQCTRL_UPQ_MASK GENMASK(14, 12)
61#define GMAC_RXQCTRL_UPQ_SHIFT 12
62#define GMAC_RXQCTRL_MCBCQ_MASK GENMASK(18, 16)
63#define GMAC_RXQCTRL_MCBCQ_SHIFT 16
64#define GMAC_RXQCTRL_MCBCQEN BIT(20)
65#define GMAC_RXQCTRL_MCBCQEN_SHIFT 20
66#define GMAC_RXQCTRL_TACPQE BIT(21)
67#define GMAC_RXQCTRL_TACPQE_SHIFT 21
68#define GMAC_RXQCTRL_FPRQ GENMASK(26, 24)
69#define GMAC_RXQCTRL_FPRQ_SHIFT 24
70
71/* MAC Packet Filtering */
72#define GMAC_PACKET_FILTER_PR BIT(0)
73#define GMAC_PACKET_FILTER_HMC BIT(2)
74#define GMAC_PACKET_FILTER_PM BIT(4)
75#define GMAC_PACKET_FILTER_PCF BIT(7)
76#define GMAC_PACKET_FILTER_HPF BIT(10)
77#define GMAC_PACKET_FILTER_VTFE BIT(16)
78#define GMAC_PACKET_FILTER_IPFE BIT(20)
79
80#define GMAC_MAX_PERFECT_ADDRESSES 128
81
82/* MAC VLAN */
83#define GMAC_VLAN_EDVLP BIT(26)
84#define GMAC_VLAN_VTHM BIT(25)
85#define GMAC_VLAN_DOVLTC BIT(20)
86#define GMAC_VLAN_ESVL BIT(18)
87#define GMAC_VLAN_ETV BIT(16)
88#define GMAC_VLAN_VID GENMASK(15, 0)
89#define GMAC_VLAN_VLTI BIT(20)
90#define GMAC_VLAN_CSVL BIT(19)
91#define GMAC_VLAN_VLC GENMASK(17, 16)
92#define GMAC_VLAN_VLC_SHIFT 16
93#define GMAC_VLAN_VLHT GENMASK(15, 0)
94
95/* MAC VLAN Tag */
96#define GMAC_VLAN_TAG_VID GENMASK(15, 0)
97#define GMAC_VLAN_TAG_ETV BIT(16)
98
99/* MAC VLAN Tag Control */
100#define GMAC_VLAN_TAG_CTRL_OB BIT(0)
101#define GMAC_VLAN_TAG_CTRL_CT BIT(1)
102#define GMAC_VLAN_TAG_CTRL_OFS_MASK GENMASK(6, 2)
103#define GMAC_VLAN_TAG_CTRL_OFS_SHIFT 2
104#define GMAC_VLAN_TAG_CTRL_EVLS_MASK GENMASK(22, 21)
105#define GMAC_VLAN_TAG_CTRL_EVLS_SHIFT 21
106#define GMAC_VLAN_TAG_CTRL_EVLRXS BIT(24)
107
108#define GMAC_VLAN_TAG_STRIP_NONE (0x0 << GMAC_VLAN_TAG_CTRL_EVLS_SHIFT)
109#define GMAC_VLAN_TAG_STRIP_PASS (0x1 << GMAC_VLAN_TAG_CTRL_EVLS_SHIFT)
110#define GMAC_VLAN_TAG_STRIP_FAIL (0x2 << GMAC_VLAN_TAG_CTRL_EVLS_SHIFT)
111#define GMAC_VLAN_TAG_STRIP_ALL (0x3 << GMAC_VLAN_TAG_CTRL_EVLS_SHIFT)
112
113/* MAC VLAN Tag Data/Filter */
114#define GMAC_VLAN_TAG_DATA_VID GENMASK(15, 0)
115#define GMAC_VLAN_TAG_DATA_VEN BIT(16)
116#define GMAC_VLAN_TAG_DATA_ETV BIT(17)
117
118/* MAC RX Queue Enable */
119#define GMAC_RX_QUEUE_CLEAR(queue) ~(GENMASK(1, 0) << ((queue) * 2))
120#define GMAC_RX_AV_QUEUE_ENABLE(queue) BIT((queue) * 2)
121#define GMAC_RX_DCB_QUEUE_ENABLE(queue) BIT(((queue) * 2) + 1)
122
123/* MAC Flow Control RX */
124#define GMAC_RX_FLOW_CTRL_RFE BIT(0)
125
126/* RX Queues Priorities */
127#define GMAC_RXQCTRL_PSRQX_MASK(x) GENMASK(7 + ((x) * 8), 0 + ((x) * 8))
128#define GMAC_RXQCTRL_PSRQX_SHIFT(x) ((x) * 8)
129
130/* TX Queues Priorities */
131#define GMAC_TXQCTRL_PSTQX_MASK(x) GENMASK(7 + ((x) * 8), 0 + ((x) * 8))
132#define GMAC_TXQCTRL_PSTQX_SHIFT(x) ((x) * 8)
133
134/* MAC Flow Control TX */
135#define GMAC_TX_FLOW_CTRL_TFE BIT(1)
136#define GMAC_TX_FLOW_CTRL_PT_SHIFT 16
137
138/* MAC Interrupt bitmap*/
139#define GMAC_INT_RGSMIIS BIT(0)
140#define GMAC_INT_PCS_LINK BIT(1)
141#define GMAC_INT_PCS_ANE BIT(2)
142#define GMAC_INT_PCS_PHYIS BIT(3)
143#define GMAC_INT_PMT_EN BIT(4)
144#define GMAC_INT_LPI_EN BIT(5)
145
146#define GMAC_PCS_IRQ_DEFAULT (GMAC_INT_RGSMIIS | GMAC_INT_PCS_LINK | \
147 GMAC_INT_PCS_ANE)
148
149#define GMAC_INT_DEFAULT_ENABLE (GMAC_INT_PMT_EN | GMAC_INT_LPI_EN)
150
151enum dwmac4_irq_status {
152 time_stamp_irq = 0x00001000,
153 mmc_rx_csum_offload_irq = 0x00000800,
154 mmc_tx_irq = 0x00000400,
155 mmc_rx_irq = 0x00000200,
156 mmc_irq = 0x00000100,
157 lpi_irq = 0x00000020,
158 pmt_irq = 0x00000010,
159};
160
161/* MAC PMT bitmap */
162enum power_event {
163 pointer_reset = 0x80000000,
164 global_unicast = 0x00000200,
165 wake_up_rx_frame = 0x00000040,
166 magic_frame = 0x00000020,
167 wake_up_frame_en = 0x00000004,
168 magic_pkt_en = 0x00000002,
169 power_down = 0x00000001,
170};
171
172/* Energy Efficient Ethernet (EEE) for GMAC4
173 *
174 * LPI status, timer and control register offset
175 */
176#define GMAC4_LPI_CTRL_STATUS 0xd0
177#define GMAC4_LPI_TIMER_CTRL 0xd4
178
179/* LPI control and status defines */
180#define GMAC4_LPI_CTRL_STATUS_LPITCSE BIT(21) /* LPI Tx Clock Stop Enable */
181#define GMAC4_LPI_CTRL_STATUS_LPITXA BIT(19) /* Enable LPI TX Automate */
182#define GMAC4_LPI_CTRL_STATUS_PLS BIT(17) /* PHY Link Status */
183#define GMAC4_LPI_CTRL_STATUS_LPIEN BIT(16) /* LPI Enable */
184#define GMAC4_LPI_CTRL_STATUS_RLPIEX BIT(3) /* Receive LPI Exit */
185#define GMAC4_LPI_CTRL_STATUS_RLPIEN BIT(2) /* Receive LPI Entry */
186#define GMAC4_LPI_CTRL_STATUS_TLPIEX BIT(1) /* Transmit LPI Exit */
187#define GMAC4_LPI_CTRL_STATUS_TLPIEN BIT(0) /* Transmit LPI Entry */
188
189/* MAC Debug bitmap */
190#define GMAC_DEBUG_TFCSTS_MASK GENMASK(18, 17)
191#define GMAC_DEBUG_TFCSTS_SHIFT 17
192#define GMAC_DEBUG_TFCSTS_IDLE 0
193#define GMAC_DEBUG_TFCSTS_WAIT 1
194#define GMAC_DEBUG_TFCSTS_GEN_PAUSE 2
195#define GMAC_DEBUG_TFCSTS_XFER 3
196#define GMAC_DEBUG_TPESTS BIT(16)
197#define GMAC_DEBUG_RFCFCSTS_MASK GENMASK(2, 1)
198#define GMAC_DEBUG_RFCFCSTS_SHIFT 1
199#define GMAC_DEBUG_RPESTS BIT(0)
200
201/* MAC config */
202#define GMAC_CONFIG_ARPEN BIT(31)
203#define GMAC_CONFIG_SARC GENMASK(30, 28)
204#define GMAC_CONFIG_SARC_SHIFT 28
205#define GMAC_CONFIG_IPC BIT(27)
206#define GMAC_CONFIG_IPG GENMASK(26, 24)
207#define GMAC_CONFIG_IPG_SHIFT 24
208#define GMAC_CONFIG_2K BIT(22)
209#define GMAC_CONFIG_ACS BIT(20)
210#define GMAC_CONFIG_BE BIT(18)
211#define GMAC_CONFIG_JD BIT(17)
212#define GMAC_CONFIG_JE BIT(16)
213#define GMAC_CONFIG_PS BIT(15)
214#define GMAC_CONFIG_FES BIT(14)
215#define GMAC_CONFIG_FES_SHIFT 14
216#define GMAC_CONFIG_DM BIT(13)
217#define GMAC_CONFIG_LM BIT(12)
218#define GMAC_CONFIG_DCRS BIT(9)
219#define GMAC_CONFIG_TE BIT(1)
220#define GMAC_CONFIG_RE BIT(0)
221
222/* MAC extended config */
223#define GMAC_CONFIG_EIPG GENMASK(29, 25)
224#define GMAC_CONFIG_EIPG_SHIFT 25
225#define GMAC_CONFIG_EIPG_EN BIT(24)
226#define GMAC_CONFIG_HDSMS GENMASK(22, 20)
227#define GMAC_CONFIG_HDSMS_SHIFT 20
228#define GMAC_CONFIG_HDSMS_256 (0x2 << GMAC_CONFIG_HDSMS_SHIFT)
229
230/* MAC HW features0 bitmap */
231#define GMAC_HW_FEAT_SAVLANINS BIT(27)
232#define GMAC_HW_FEAT_ADDMAC BIT(18)
233#define GMAC_HW_FEAT_RXCOESEL BIT(16)
234#define GMAC_HW_FEAT_TXCOSEL BIT(14)
235#define GMAC_HW_FEAT_EEESEL BIT(13)
236#define GMAC_HW_FEAT_TSSEL BIT(12)
237#define GMAC_HW_FEAT_ARPOFFSEL BIT(9)
238#define GMAC_HW_FEAT_MMCSEL BIT(8)
239#define GMAC_HW_FEAT_MGKSEL BIT(7)
240#define GMAC_HW_FEAT_RWKSEL BIT(6)
241#define GMAC_HW_FEAT_SMASEL BIT(5)
242#define GMAC_HW_FEAT_VLHASH BIT(4)
243#define GMAC_HW_FEAT_PCSSEL BIT(3)
244#define GMAC_HW_FEAT_HDSEL BIT(2)
245#define GMAC_HW_FEAT_GMIISEL BIT(1)
246#define GMAC_HW_FEAT_MIISEL BIT(0)
247
248/* MAC HW features1 bitmap */
249#define GMAC_HW_FEAT_L3L4FNUM GENMASK(30, 27)
250#define GMAC_HW_HASH_TB_SZ GENMASK(25, 24)
251#define GMAC_HW_FEAT_AVSEL BIT(20)
252#define GMAC_HW_TSOEN BIT(18)
253#define GMAC_HW_FEAT_SPHEN BIT(17)
254#define GMAC_HW_ADDR64 GENMASK(15, 14)
255#define GMAC_HW_TXFIFOSIZE GENMASK(10, 6)
256#define GMAC_HW_RXFIFOSIZE GENMASK(4, 0)
257
258/* MAC HW features2 bitmap */
259#define GMAC_HW_FEAT_PPSOUTNUM GENMASK(26, 24)
260#define GMAC_HW_FEAT_TXCHCNT GENMASK(21, 18)
261#define GMAC_HW_FEAT_RXCHCNT GENMASK(15, 12)
262#define GMAC_HW_FEAT_TXQCNT GENMASK(9, 6)
263#define GMAC_HW_FEAT_RXQCNT GENMASK(3, 0)
264
265/* MAC HW features3 bitmap */
266#define GMAC_HW_FEAT_ASP GENMASK(29, 28)
267#define GMAC_HW_FEAT_TBSSEL BIT(27)
268#define GMAC_HW_FEAT_FPESEL BIT(26)
269#define GMAC_HW_FEAT_ESTWID GENMASK(21, 20)
270#define GMAC_HW_FEAT_ESTDEP GENMASK(19, 17)
271#define GMAC_HW_FEAT_ESTSEL BIT(16)
272#define GMAC_HW_FEAT_FRPES GENMASK(14, 13)
273#define GMAC_HW_FEAT_FRPBS GENMASK(12, 11)
274#define GMAC_HW_FEAT_FRPSEL BIT(10)
275#define GMAC_HW_FEAT_DVLAN BIT(5)
276#define GMAC_HW_FEAT_NRVF GENMASK(2, 0)
277
278/* MAC HW ADDR regs */
279#define GMAC_HI_DCS GENMASK(18, 16)
280#define GMAC_HI_DCS_SHIFT 16
281#define GMAC_HI_REG_AE BIT(31)
282
283/* L3/L4 Filters regs */
284#define GMAC_L4DPIM0 BIT(21)
285#define GMAC_L4DPM0 BIT(20)
286#define GMAC_L4SPIM0 BIT(19)
287#define GMAC_L4SPM0 BIT(18)
288#define GMAC_L4PEN0 BIT(16)
289#define GMAC_L3DAIM0 BIT(5)
290#define GMAC_L3DAM0 BIT(4)
291#define GMAC_L3SAIM0 BIT(3)
292#define GMAC_L3SAM0 BIT(2)
293#define GMAC_L3PEN0 BIT(0)
294#define GMAC_L4DP0 GENMASK(31, 16)
295#define GMAC_L4DP0_SHIFT 16
296#define GMAC_L4SP0 GENMASK(15, 0)
297
298/* MTL registers */
299#define MTL_OPERATION_MODE 0x00000c00
300#define MTL_FRPE BIT(15)
301#define MTL_OPERATION_SCHALG_MASK GENMASK(6, 5)
302#define MTL_OPERATION_SCHALG_WRR (0x0 << 5)
303#define MTL_OPERATION_SCHALG_WFQ (0x1 << 5)
304#define MTL_OPERATION_SCHALG_DWRR (0x2 << 5)
305#define MTL_OPERATION_SCHALG_SP (0x3 << 5)
306#define MTL_OPERATION_RAA BIT(2)
307#define MTL_OPERATION_RAA_SP (0x0 << 2)
308#define MTL_OPERATION_RAA_WSP (0x1 << 2)
309
310#define MTL_INT_STATUS 0x00000c20
311#define MTL_INT_QX(x) BIT(x)
312
313#define MTL_RXQ_DMA_MAP0 0x00000c30 /* queue 0 to 3 */
314#define MTL_RXQ_DMA_MAP1 0x00000c34 /* queue 4 to 7 */
315#define MTL_RXQ_DMA_Q04MDMACH_MASK GENMASK(3, 0)
316#define MTL_RXQ_DMA_Q04MDMACH(x) ((x) << 0)
317#define MTL_RXQ_DMA_QXMDMACH_MASK(x) GENMASK(11 + (8 * ((x) - 1)), 8 * (x))
318#define MTL_RXQ_DMA_QXMDMACH(chan, q) ((chan) << (8 * (q)))
319
320#define MTL_CHAN_BASE_ADDR 0x00000d00
321#define MTL_CHAN_BASE_OFFSET 0x40
322#define MTL_CHANX_BASE_ADDR(x) (MTL_CHAN_BASE_ADDR + \
323 (x * MTL_CHAN_BASE_OFFSET))
324
325#define MTL_CHAN_TX_OP_MODE(x) MTL_CHANX_BASE_ADDR(x)
326#define MTL_CHAN_TX_DEBUG(x) (MTL_CHANX_BASE_ADDR(x) + 0x8)
327#define MTL_CHAN_INT_CTRL(x) (MTL_CHANX_BASE_ADDR(x) + 0x2c)
328#define MTL_CHAN_RX_OP_MODE(x) (MTL_CHANX_BASE_ADDR(x) + 0x30)
329#define MTL_CHAN_RX_DEBUG(x) (MTL_CHANX_BASE_ADDR(x) + 0x38)
330
331#define MTL_OP_MODE_RSF BIT(5)
332#define MTL_OP_MODE_TXQEN_MASK GENMASK(3, 2)
333#define MTL_OP_MODE_TXQEN_AV BIT(2)
334#define MTL_OP_MODE_TXQEN BIT(3)
335#define MTL_OP_MODE_TSF BIT(1)
336
337#define MTL_OP_MODE_TQS_MASK GENMASK(24, 16)
338#define MTL_OP_MODE_TQS_SHIFT 16
339
340#define MTL_OP_MODE_TTC_MASK 0x70
341#define MTL_OP_MODE_TTC_SHIFT 4
342
343#define MTL_OP_MODE_TTC_32 0
344#define MTL_OP_MODE_TTC_64 (1 << MTL_OP_MODE_TTC_SHIFT)
345#define MTL_OP_MODE_TTC_96 (2 << MTL_OP_MODE_TTC_SHIFT)
346#define MTL_OP_MODE_TTC_128 (3 << MTL_OP_MODE_TTC_SHIFT)
347#define MTL_OP_MODE_TTC_192 (4 << MTL_OP_MODE_TTC_SHIFT)
348#define MTL_OP_MODE_TTC_256 (5 << MTL_OP_MODE_TTC_SHIFT)
349#define MTL_OP_MODE_TTC_384 (6 << MTL_OP_MODE_TTC_SHIFT)
350#define MTL_OP_MODE_TTC_512 (7 << MTL_OP_MODE_TTC_SHIFT)
351
352#define MTL_OP_MODE_RQS_MASK GENMASK(29, 20)
353#define MTL_OP_MODE_RQS_SHIFT 20
354
355#define MTL_OP_MODE_RFD_MASK GENMASK(19, 14)
356#define MTL_OP_MODE_RFD_SHIFT 14
357
358#define MTL_OP_MODE_RFA_MASK GENMASK(13, 8)
359#define MTL_OP_MODE_RFA_SHIFT 8
360
361#define MTL_OP_MODE_EHFC BIT(7)
362
363#define MTL_OP_MODE_RTC_MASK 0x18
364#define MTL_OP_MODE_RTC_SHIFT 3
365
366#define MTL_OP_MODE_RTC_32 (1 << MTL_OP_MODE_RTC_SHIFT)
367#define MTL_OP_MODE_RTC_64 0
368#define MTL_OP_MODE_RTC_96 (2 << MTL_OP_MODE_RTC_SHIFT)
369#define MTL_OP_MODE_RTC_128 (3 << MTL_OP_MODE_RTC_SHIFT)
370
371/* MTL ETS Control register */
372#define MTL_ETS_CTRL_BASE_ADDR 0x00000d10
373#define MTL_ETS_CTRL_BASE_OFFSET 0x40
374#define MTL_ETSX_CTRL_BASE_ADDR(x) (MTL_ETS_CTRL_BASE_ADDR + \
375 ((x) * MTL_ETS_CTRL_BASE_OFFSET))
376
377#define MTL_ETS_CTRL_CC BIT(3)
378#define MTL_ETS_CTRL_AVALG BIT(2)
379
380/* MTL Queue Quantum Weight */
381#define MTL_TXQ_WEIGHT_BASE_ADDR 0x00000d18
382#define MTL_TXQ_WEIGHT_BASE_OFFSET 0x40
383#define MTL_TXQX_WEIGHT_BASE_ADDR(x) (MTL_TXQ_WEIGHT_BASE_ADDR + \
384 ((x) * MTL_TXQ_WEIGHT_BASE_OFFSET))
385#define MTL_TXQ_WEIGHT_ISCQW_MASK GENMASK(20, 0)
386
387/* MTL sendSlopeCredit register */
388#define MTL_SEND_SLP_CRED_BASE_ADDR 0x00000d1c
389#define MTL_SEND_SLP_CRED_OFFSET 0x40
390#define MTL_SEND_SLP_CREDX_BASE_ADDR(x) (MTL_SEND_SLP_CRED_BASE_ADDR + \
391 ((x) * MTL_SEND_SLP_CRED_OFFSET))
392
393#define MTL_SEND_SLP_CRED_SSC_MASK GENMASK(13, 0)
394
395/* MTL hiCredit register */
396#define MTL_HIGH_CRED_BASE_ADDR 0x00000d20
397#define MTL_HIGH_CRED_OFFSET 0x40
398#define MTL_HIGH_CREDX_BASE_ADDR(x) (MTL_HIGH_CRED_BASE_ADDR + \
399 ((x) * MTL_HIGH_CRED_OFFSET))
400
401#define MTL_HIGH_CRED_HC_MASK GENMASK(28, 0)
402
403/* MTL loCredit register */
404#define MTL_LOW_CRED_BASE_ADDR 0x00000d24
405#define MTL_LOW_CRED_OFFSET 0x40
406#define MTL_LOW_CREDX_BASE_ADDR(x) (MTL_LOW_CRED_BASE_ADDR + \
407 ((x) * MTL_LOW_CRED_OFFSET))
408
409#define MTL_HIGH_CRED_LC_MASK GENMASK(28, 0)
410
411/* MTL debug */
412#define MTL_DEBUG_TXSTSFSTS BIT(5)
413#define MTL_DEBUG_TXFSTS BIT(4)
414#define MTL_DEBUG_TWCSTS BIT(3)
415
416/* MTL debug: Tx FIFO Read Controller Status */
417#define MTL_DEBUG_TRCSTS_MASK GENMASK(2, 1)
418#define MTL_DEBUG_TRCSTS_SHIFT 1
419#define MTL_DEBUG_TRCSTS_IDLE 0
420#define MTL_DEBUG_TRCSTS_READ 1
421#define MTL_DEBUG_TRCSTS_TXW 2
422#define MTL_DEBUG_TRCSTS_WRITE 3
423#define MTL_DEBUG_TXPAUSED BIT(0)
424
425/* MAC debug: GMII or MII Transmit Protocol Engine Status */
426#define MTL_DEBUG_RXFSTS_MASK GENMASK(5, 4)
427#define MTL_DEBUG_RXFSTS_SHIFT 4
428#define MTL_DEBUG_RXFSTS_EMPTY 0
429#define MTL_DEBUG_RXFSTS_BT 1
430#define MTL_DEBUG_RXFSTS_AT 2
431#define MTL_DEBUG_RXFSTS_FULL 3
432#define MTL_DEBUG_RRCSTS_MASK GENMASK(2, 1)
433#define MTL_DEBUG_RRCSTS_SHIFT 1
434#define MTL_DEBUG_RRCSTS_IDLE 0
435#define MTL_DEBUG_RRCSTS_RDATA 1
436#define MTL_DEBUG_RRCSTS_RSTAT 2
437#define MTL_DEBUG_RRCSTS_FLUSH 3
438#define MTL_DEBUG_RWCSTS BIT(0)
439
440/* MTL interrupt */
441#define MTL_RX_OVERFLOW_INT_EN BIT(24)
442#define MTL_RX_OVERFLOW_INT BIT(16)
443
444/* Default operating mode of the MAC */
445#define GMAC_CORE_INIT (GMAC_CONFIG_JD | GMAC_CONFIG_PS | \
446 GMAC_CONFIG_BE | GMAC_CONFIG_DCRS | \
447 GMAC_CONFIG_JE)
448
449/* To dump the core regs excluding the Address Registers */
450#define GMAC_REG_NUM 132
451
452/* MTL debug */
453#define MTL_DEBUG_TXSTSFSTS BIT(5)
454#define MTL_DEBUG_TXFSTS BIT(4)
455#define MTL_DEBUG_TWCSTS BIT(3)
456
457/* MTL debug: Tx FIFO Read Controller Status */
458#define MTL_DEBUG_TRCSTS_MASK GENMASK(2, 1)
459#define MTL_DEBUG_TRCSTS_SHIFT 1
460#define MTL_DEBUG_TRCSTS_IDLE 0
461#define MTL_DEBUG_TRCSTS_READ 1
462#define MTL_DEBUG_TRCSTS_TXW 2
463#define MTL_DEBUG_TRCSTS_WRITE 3
464#define MTL_DEBUG_TXPAUSED BIT(0)
465
466/* MAC debug: GMII or MII Transmit Protocol Engine Status */
467#define MTL_DEBUG_RXFSTS_MASK GENMASK(5, 4)
468#define MTL_DEBUG_RXFSTS_SHIFT 4
469#define MTL_DEBUG_RXFSTS_EMPTY 0
470#define MTL_DEBUG_RXFSTS_BT 1
471#define MTL_DEBUG_RXFSTS_AT 2
472#define MTL_DEBUG_RXFSTS_FULL 3
473#define MTL_DEBUG_RRCSTS_MASK GENMASK(2, 1)
474#define MTL_DEBUG_RRCSTS_SHIFT 1
475#define MTL_DEBUG_RRCSTS_IDLE 0
476#define MTL_DEBUG_RRCSTS_RDATA 1
477#define MTL_DEBUG_RRCSTS_RSTAT 2
478#define MTL_DEBUG_RRCSTS_FLUSH 3
479#define MTL_DEBUG_RWCSTS BIT(0)
480
481/* SGMII/RGMII status register */
482#define GMAC_PHYIF_CTRLSTATUS_TC BIT(0)
483#define GMAC_PHYIF_CTRLSTATUS_LUD BIT(1)
484#define GMAC_PHYIF_CTRLSTATUS_SMIDRXS BIT(4)
485#define GMAC_PHYIF_CTRLSTATUS_LNKMOD BIT(16)
486#define GMAC_PHYIF_CTRLSTATUS_SPEED GENMASK(18, 17)
487#define GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT 17
488#define GMAC_PHYIF_CTRLSTATUS_LNKSTS BIT(19)
489#define GMAC_PHYIF_CTRLSTATUS_JABTO BIT(20)
490#define GMAC_PHYIF_CTRLSTATUS_FALSECARDET BIT(21)
491/* LNKMOD */
492#define GMAC_PHYIF_CTRLSTATUS_LNKMOD_MASK 0x1
493/* LNKSPEED */
494#define GMAC_PHYIF_CTRLSTATUS_SPEED_125 0x2
495#define GMAC_PHYIF_CTRLSTATUS_SPEED_25 0x1
496#define GMAC_PHYIF_CTRLSTATUS_SPEED_2_5 0x0
497
498extern const struct stmmac_dma_ops dwmac4_dma_ops;
499extern const struct stmmac_dma_ops dwmac410_dma_ops;
500#endif /* __DWMAC4_H__ */