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1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Marvell 88E6xxx Ethernet switch single-chip definition
4 *
5 * Copyright (c) 2008 Marvell Semiconductor
6 */
7
8#ifndef _MV88E6XXX_CHIP_H
9#define _MV88E6XXX_CHIP_H
10
11#include <linux/idr.h>
12#include <linux/if_vlan.h>
13#include <linux/irq.h>
14#include <linux/gpio/consumer.h>
15#include <linux/kthread.h>
16#include <linux/leds.h>
17#include <linux/phy.h>
18#include <linux/property.h>
19#include <linux/ptp_clock_kernel.h>
20#include <linux/timecounter.h>
21#include <net/dsa.h>
22
23#define EDSA_HLEN 8
24#define MV88E6XXX_N_FID 4096
25#define MV88E6XXX_N_SID 64
26
27#define MV88E6XXX_FID_STANDALONE 0
28#define MV88E6XXX_FID_BRIDGED 1
29
30/* PVT limits for 4-bit port and 5-bit switch */
31#define MV88E6XXX_MAX_PVT_SWITCHES 32
32#define MV88E6XXX_MAX_PVT_PORTS 16
33#define MV88E6XXX_MAX_PVT_ENTRIES \
34 (MV88E6XXX_MAX_PVT_SWITCHES * MV88E6XXX_MAX_PVT_PORTS)
35
36#define MV88E6XXX_MAX_GPIO 16
37
38enum mv88e6xxx_egress_mode {
39 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
40 MV88E6XXX_EGRESS_MODE_UNTAGGED,
41 MV88E6XXX_EGRESS_MODE_TAGGED,
42 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
43};
44
45enum mv88e6xxx_egress_direction {
46 MV88E6XXX_EGRESS_DIR_INGRESS,
47 MV88E6XXX_EGRESS_DIR_EGRESS,
48};
49
50enum mv88e6xxx_frame_mode {
51 MV88E6XXX_FRAME_MODE_NORMAL,
52 MV88E6XXX_FRAME_MODE_DSA,
53 MV88E6XXX_FRAME_MODE_PROVIDER,
54 MV88E6XXX_FRAME_MODE_ETHERTYPE,
55};
56
57/* List of supported models */
58enum mv88e6xxx_model {
59 MV88E6020,
60 MV88E6071,
61 MV88E6085,
62 MV88E6095,
63 MV88E6097,
64 MV88E6123,
65 MV88E6131,
66 MV88E6141,
67 MV88E6161,
68 MV88E6165,
69 MV88E6171,
70 MV88E6172,
71 MV88E6175,
72 MV88E6176,
73 MV88E6185,
74 MV88E6190,
75 MV88E6190X,
76 MV88E6191,
77 MV88E6191X,
78 MV88E6193X,
79 MV88E6220,
80 MV88E6240,
81 MV88E6250,
82 MV88E6290,
83 MV88E6320,
84 MV88E6321,
85 MV88E6341,
86 MV88E6350,
87 MV88E6351,
88 MV88E6352,
89 MV88E6361,
90 MV88E6390,
91 MV88E6390X,
92 MV88E6393X,
93};
94
95enum mv88e6xxx_family {
96 MV88E6XXX_FAMILY_NONE,
97 MV88E6XXX_FAMILY_6065, /* 6031 6035 6061 6065 */
98 MV88E6XXX_FAMILY_6095, /* 6092 6095 */
99 MV88E6XXX_FAMILY_6097, /* 6046 6085 6096 6097 */
100 MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */
101 MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */
102 MV88E6XXX_FAMILY_6250, /* 6220 6250 6020 6071 */
103 MV88E6XXX_FAMILY_6320, /* 6320 6321 */
104 MV88E6XXX_FAMILY_6341, /* 6141 6341 */
105 MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */
106 MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */
107 MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */
108 MV88E6XXX_FAMILY_6393, /* 6191X 6193X 6361 6393X */
109};
110
111/**
112 * enum mv88e6xxx_edsa_support - Ethertype DSA tag support level
113 * @MV88E6XXX_EDSA_UNSUPPORTED: Device has no support for EDSA tags
114 * @MV88E6XXX_EDSA_UNDOCUMENTED: Documentation indicates that
115 * egressing FORWARD frames with an EDSA
116 * tag is reserved for future use, but
117 * empirical data shows that this mode
118 * is supported.
119 * @MV88E6XXX_EDSA_SUPPORTED: EDSA tags are fully supported.
120 */
121enum mv88e6xxx_edsa_support {
122 MV88E6XXX_EDSA_UNSUPPORTED = 0,
123 MV88E6XXX_EDSA_UNDOCUMENTED,
124 MV88E6XXX_EDSA_SUPPORTED,
125};
126
127struct mv88e6xxx_ops;
128
129struct mv88e6xxx_info {
130 enum mv88e6xxx_family family;
131 u16 prod_num;
132 const char *name;
133 unsigned int num_databases;
134 unsigned int num_macs;
135 unsigned int num_ports;
136 unsigned int num_internal_phys;
137 unsigned int num_gpio;
138 unsigned int max_vid;
139 unsigned int max_sid;
140 unsigned int port_base_addr;
141 unsigned int phy_base_addr;
142 unsigned int global1_addr;
143 unsigned int global2_addr;
144 unsigned int age_time_coeff;
145 unsigned int g1_irqs;
146 unsigned int g2_irqs;
147 bool pvt;
148
149 /* Mark certain ports as invalid. This is required for example for the
150 * MV88E6220 (which is in general a MV88E6250 with 7 ports) but the
151 * ports 2-4 are not routet to pins.
152 */
153 unsigned int invalid_port_mask;
154 /* Multi-chip Addressing Mode.
155 * Some chips respond to only 2 registers of its own SMI device address
156 * when it is non-zero, and use indirect access to internal registers.
157 */
158 bool multi_chip;
159 /* Dual-chip Addressing Mode
160 * Some chips respond to only half of the 32 SMI addresses,
161 * allowing two to coexist on the same SMI interface.
162 */
163 bool dual_chip;
164
165 enum mv88e6xxx_edsa_support edsa_support;
166
167 /* Mask for FromPort and ToPort value of PortVec used in ATU Move
168 * operation. 0 means that the ATU Move operation is not supported.
169 */
170 u8 atu_move_port_mask;
171 const struct mv88e6xxx_ops *ops;
172
173 /* Supports PTP */
174 bool ptp_support;
175
176 /* Internal PHY start index. 0 means that internal PHYs range starts at
177 * port 0, 1 means internal PHYs range starts at port 1, etc
178 */
179 unsigned int internal_phys_offset;
180};
181
182struct mv88e6xxx_atu_entry {
183 u8 state;
184 bool trunk;
185 u16 portvec;
186 u8 mac[ETH_ALEN];
187};
188
189struct mv88e6xxx_vtu_entry {
190 u16 vid;
191 u16 fid;
192 u8 sid;
193 bool valid;
194 bool policy;
195 u8 member[DSA_MAX_PORTS];
196 u8 state[DSA_MAX_PORTS]; /* Older silicon has no STU */
197};
198
199struct mv88e6xxx_stu_entry {
200 u8 sid;
201 bool valid;
202 u8 state[DSA_MAX_PORTS];
203};
204
205struct mv88e6xxx_bus_ops;
206struct mv88e6xxx_irq_ops;
207struct mv88e6xxx_gpio_ops;
208struct mv88e6xxx_avb_ops;
209struct mv88e6xxx_ptp_ops;
210struct mv88e6xxx_pcs_ops;
211struct mv88e6xxx_cc_coeffs;
212
213struct mv88e6xxx_irq {
214 u16 masked;
215 struct irq_chip chip;
216 struct irq_domain *domain;
217 int nirqs;
218};
219
220/* state flags for mv88e6xxx_port_hwtstamp::state */
221enum {
222 MV88E6XXX_HWTSTAMP_ENABLED,
223 MV88E6XXX_HWTSTAMP_TX_IN_PROGRESS,
224};
225
226struct mv88e6xxx_port_hwtstamp {
227 /* Port index */
228 int port_id;
229
230 /* Timestamping state */
231 unsigned long state;
232
233 /* Resources for receive timestamping */
234 struct sk_buff_head rx_queue;
235 struct sk_buff_head rx_queue2;
236
237 /* Resources for transmit timestamping */
238 unsigned long tx_tstamp_start;
239 struct sk_buff *tx_skb;
240 u16 tx_seq_id;
241
242 /* Current timestamp configuration */
243 struct hwtstamp_config tstamp_config;
244};
245
246enum mv88e6xxx_policy_mapping {
247 MV88E6XXX_POLICY_MAPPING_DA,
248 MV88E6XXX_POLICY_MAPPING_SA,
249 MV88E6XXX_POLICY_MAPPING_VTU,
250 MV88E6XXX_POLICY_MAPPING_ETYPE,
251 MV88E6XXX_POLICY_MAPPING_PPPOE,
252 MV88E6XXX_POLICY_MAPPING_VBAS,
253 MV88E6XXX_POLICY_MAPPING_OPT82,
254 MV88E6XXX_POLICY_MAPPING_UDP,
255};
256
257enum mv88e6xxx_policy_action {
258 MV88E6XXX_POLICY_ACTION_NORMAL,
259 MV88E6XXX_POLICY_ACTION_MIRROR,
260 MV88E6XXX_POLICY_ACTION_TRAP,
261 MV88E6XXX_POLICY_ACTION_DISCARD,
262};
263
264struct mv88e6xxx_policy {
265 enum mv88e6xxx_policy_mapping mapping;
266 enum mv88e6xxx_policy_action action;
267 struct ethtool_rx_flow_spec fs;
268 u8 addr[ETH_ALEN];
269 int port;
270 u16 vid;
271};
272
273struct mv88e6xxx_vlan {
274 u16 vid;
275 bool valid;
276};
277
278struct mv88e6xxx_port {
279 struct mv88e6xxx_chip *chip;
280 int port;
281 struct fwnode_handle *fwnode;
282 struct mv88e6xxx_vlan bridge_pvid;
283 u64 serdes_stats[2];
284 u64 atu_member_violation;
285 u64 atu_miss_violation;
286 u64 atu_full_violation;
287 u64 vtu_member_violation;
288 u64 vtu_miss_violation;
289 phy_interface_t interface;
290 u8 cmode;
291 bool mirror_ingress;
292 bool mirror_egress;
293 struct devlink_region *region;
294 void *pcs_private;
295
296 /* LED related information */
297 bool fiber;
298 struct led_classdev led0;
299 struct led_classdev led1;
300
301 /* MacAuth Bypass control flag */
302 bool mab;
303};
304
305enum mv88e6xxx_region_id {
306 MV88E6XXX_REGION_GLOBAL1 = 0,
307 MV88E6XXX_REGION_GLOBAL2,
308 MV88E6XXX_REGION_ATU,
309 MV88E6XXX_REGION_VTU,
310 MV88E6XXX_REGION_STU,
311 MV88E6XXX_REGION_PVT,
312
313 _MV88E6XXX_REGION_MAX,
314};
315
316struct mv88e6xxx_region_priv {
317 enum mv88e6xxx_region_id id;
318};
319
320struct mv88e6xxx_mst {
321 struct list_head node;
322
323 refcount_t refcnt;
324 struct net_device *br;
325 u16 msti;
326
327 struct mv88e6xxx_stu_entry stu;
328};
329
330#define STATS_TYPE_PORT BIT(0)
331#define STATS_TYPE_BANK0 BIT(1)
332#define STATS_TYPE_BANK1 BIT(2)
333
334struct mv88e6xxx_hw_stat {
335 char string[ETH_GSTRING_LEN];
336 size_t size;
337 int reg;
338 int type;
339};
340
341struct mv88e6xxx_chip {
342 const struct mv88e6xxx_info *info;
343
344 /* Currently configured tagging protocol */
345 enum dsa_tag_protocol tag_protocol;
346
347 /* The dsa_switch this private structure is related to */
348 struct dsa_switch *ds;
349
350 /* The device this structure is associated to */
351 struct device *dev;
352
353 /* This mutex protects the access to the switch registers */
354 struct mutex reg_lock;
355
356 /* The MII bus and the address on the bus that is used to
357 * communication with the switch
358 */
359 const struct mv88e6xxx_bus_ops *smi_ops;
360 struct mii_bus *bus;
361 int sw_addr;
362
363 /* Handles automatic disabling and re-enabling of the PHY
364 * polling unit.
365 */
366 const struct mv88e6xxx_bus_ops *phy_ops;
367 struct mutex ppu_mutex;
368 int ppu_disabled;
369 struct work_struct ppu_work;
370 struct timer_list ppu_timer;
371
372 /* This mutex serialises access to the statistics unit.
373 * Hold this mutex over snapshot + dump sequences.
374 */
375 struct mutex stats_mutex;
376
377 /* A switch may have a GPIO line tied to its reset pin. Parse
378 * this from the device tree, and use it before performing
379 * switch soft reset.
380 */
381 struct gpio_desc *reset;
382
383 /* set to size of eeprom if supported by the switch */
384 u32 eeprom_len;
385
386 /* List of mdio busses */
387 struct list_head mdios;
388
389 /* Policy Control List IDs and rules */
390 struct idr policies;
391
392 /* There can be two interrupt controllers, which are chained
393 * off a GPIO as interrupt source
394 */
395 struct mv88e6xxx_irq g1_irq;
396 struct mv88e6xxx_irq g2_irq;
397 int irq;
398 char irq_name[64];
399 int device_irq;
400 char device_irq_name[64];
401 int watchdog_irq;
402 char watchdog_irq_name[64];
403
404 int atu_prob_irq;
405 char atu_prob_irq_name[64];
406 int vtu_prob_irq;
407 char vtu_prob_irq_name[64];
408 struct kthread_worker *kworker;
409 struct kthread_delayed_work irq_poll_work;
410
411 /* GPIO resources */
412 u8 gpio_data[2];
413
414 /* This cyclecounter abstracts the switch PTP time.
415 * reg_lock must be held for any operation that read()s.
416 */
417 struct cyclecounter tstamp_cc;
418 struct timecounter tstamp_tc;
419 struct delayed_work overflow_work;
420 const struct mv88e6xxx_cc_coeffs *cc_coeffs;
421
422 struct ptp_clock *ptp_clock;
423 struct ptp_clock_info ptp_clock_info;
424 struct delayed_work tai_event_work;
425 struct ptp_pin_desc pin_config[MV88E6XXX_MAX_GPIO];
426 u16 trig_config;
427 u16 evcap_config;
428 u16 enable_count;
429
430 /* Current ingress and egress monitor ports */
431 int egress_dest_port;
432 int ingress_dest_port;
433
434 /* Per-port timestamping resources. */
435 struct mv88e6xxx_port_hwtstamp port_hwtstamp[DSA_MAX_PORTS];
436
437 /* Array of port structures. */
438 struct mv88e6xxx_port ports[DSA_MAX_PORTS];
439
440 /* devlink regions */
441 struct devlink_region *regions[_MV88E6XXX_REGION_MAX];
442
443 /* Bridge MST to SID mappings */
444 struct list_head msts;
445
446 /* FID map */
447 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
448};
449
450struct mv88e6xxx_bus_ops {
451 int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
452 int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
453 int (*init)(struct mv88e6xxx_chip *chip);
454};
455
456struct mv88e6xxx_mdio_bus {
457 struct mii_bus *bus;
458 struct mv88e6xxx_chip *chip;
459 struct list_head list;
460 bool external;
461};
462
463struct mv88e6xxx_ops {
464 /* Switch Setup Errata, called early in the switch setup to
465 * allow any errata actions to be performed
466 */
467 int (*setup_errata)(struct mv88e6xxx_chip *chip);
468
469 int (*ieee_pri_map)(struct mv88e6xxx_chip *chip);
470 int (*ip_pri_map)(struct mv88e6xxx_chip *chip);
471
472 /* Ingress Rate Limit unit (IRL) operations */
473 int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port);
474
475 int (*get_eeprom)(struct mv88e6xxx_chip *chip,
476 struct ethtool_eeprom *eeprom, u8 *data);
477 int (*set_eeprom)(struct mv88e6xxx_chip *chip,
478 struct ethtool_eeprom *eeprom, u8 *data);
479
480 int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr);
481
482 int (*phy_read)(struct mv88e6xxx_chip *chip,
483 struct mii_bus *bus,
484 int addr, int reg, u16 *val);
485 int (*phy_write)(struct mv88e6xxx_chip *chip,
486 struct mii_bus *bus,
487 int addr, int reg, u16 val);
488
489 int (*phy_read_c45)(struct mv88e6xxx_chip *chip,
490 struct mii_bus *bus,
491 int addr, int devad, int reg, u16 *val);
492 int (*phy_write_c45)(struct mv88e6xxx_chip *chip,
493 struct mii_bus *bus,
494 int addr, int devad, int reg, u16 val);
495
496 /* Priority Override Table operations */
497 int (*pot_clear)(struct mv88e6xxx_chip *chip);
498
499 /* PHY Polling Unit (PPU) operations */
500 int (*ppu_enable)(struct mv88e6xxx_chip *chip);
501 int (*ppu_disable)(struct mv88e6xxx_chip *chip);
502
503 /* Additional handlers to run before and after hard reset, to make sure
504 * that the switch and EEPROM are in a good state.
505 */
506 int (*hardware_reset_pre)(struct mv88e6xxx_chip *chip);
507 int (*hardware_reset_post)(struct mv88e6xxx_chip *chip);
508
509 /* Switch Software Reset */
510 int (*reset)(struct mv88e6xxx_chip *chip);
511
512 /* RGMII Receive/Transmit Timing Control
513 * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise.
514 */
515 int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port,
516 phy_interface_t mode);
517
518#define LINK_FORCED_DOWN 0
519#define LINK_FORCED_UP 1
520#define LINK_UNFORCED -2
521
522 /* Port's MAC link state
523 * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down,
524 * or LINK_UNFORCED for normal link detection.
525 */
526 int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link);
527
528 /* Synchronise the port link state with that of the SERDES
529 */
530 int (*port_sync_link)(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup);
531
532#define PAUSE_ON 1
533#define PAUSE_OFF 0
534
535 /* Enable/disable sending Pause */
536 int (*port_set_pause)(struct mv88e6xxx_chip *chip, int port,
537 int pause);
538
539#define SPEED_UNFORCED -2
540#define DUPLEX_UNFORCED -2
541
542 /* Port's MAC speed (in Mbps) and MAC duplex mode
543 *
544 * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid.
545 * Use SPEED_UNFORCED for normal detection.
546 *
547 * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex,
548 * or DUPLEX_UNFORCED for normal duplex detection.
549 */
550 int (*port_set_speed_duplex)(struct mv88e6xxx_chip *chip, int port,
551 int speed, int duplex);
552
553 /* What interface mode should be used for maximum speed? */
554 phy_interface_t (*port_max_speed_mode)(struct mv88e6xxx_chip *chip,
555 int port);
556
557 int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port);
558
559 int (*port_set_policy)(struct mv88e6xxx_chip *chip, int port,
560 enum mv88e6xxx_policy_mapping mapping,
561 enum mv88e6xxx_policy_action action);
562
563 int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port,
564 enum mv88e6xxx_frame_mode mode);
565 int (*port_set_ucast_flood)(struct mv88e6xxx_chip *chip, int port,
566 bool unicast);
567 int (*port_set_mcast_flood)(struct mv88e6xxx_chip *chip, int port,
568 bool multicast);
569 int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port,
570 u16 etype);
571 int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port,
572 size_t size);
573
574 int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port);
575 int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in,
576 u8 out);
577 int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port);
578 int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port);
579 int (*port_setup_message_port)(struct mv88e6xxx_chip *chip, int port);
580
581 /* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc.
582 * Some chips allow this to be configured on specific ports.
583 */
584 int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port,
585 phy_interface_t mode);
586 int (*port_get_cmode)(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
587
588 /* LED control */
589 int (*port_setup_leds)(struct mv88e6xxx_chip *chip, int port);
590
591 /* Some devices have a per port register indicating what is
592 * the upstream port this port should forward to.
593 */
594 int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port,
595 int upstream_port);
596
597 /* Snapshot the statistics for a port. The statistics can then
598 * be read back a leisure but still with a consistent view.
599 */
600 int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port);
601
602 /* Set the histogram mode for statistics, when the control registers
603 * are separated out of the STATS_OP register.
604 */
605 int (*stats_set_histogram)(struct mv88e6xxx_chip *chip);
606
607 /* Return the number of strings describing statistics */
608 int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip);
609 void (*stats_get_strings)(struct mv88e6xxx_chip *chip, uint8_t **data);
610 size_t (*stats_get_stat)(struct mv88e6xxx_chip *chip, int port,
611 const struct mv88e6xxx_hw_stat *stat,
612 uint64_t *data);
613 int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port);
614 int (*set_egress_port)(struct mv88e6xxx_chip *chip,
615 enum mv88e6xxx_egress_direction direction,
616 int port);
617
618#define MV88E6XXX_CASCADE_PORT_NONE 0xe
619#define MV88E6XXX_CASCADE_PORT_MULTIPLE 0xf
620
621 int (*set_cascade_port)(struct mv88e6xxx_chip *chip, int port);
622
623 const struct mv88e6xxx_irq_ops *watchdog_ops;
624
625 int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip);
626
627 /* SERDES lane mapping */
628 int (*serdes_get_lane)(struct mv88e6xxx_chip *chip, int port);
629
630 /* SERDES interrupt handling */
631 unsigned int (*serdes_irq_mapping)(struct mv88e6xxx_chip *chip,
632 int port);
633
634 /* Statistics from the SERDES interface */
635 int (*serdes_get_sset_count)(struct mv88e6xxx_chip *chip, int port);
636 int (*serdes_get_strings)(struct mv88e6xxx_chip *chip, int port,
637 uint8_t **data);
638 size_t (*serdes_get_stats)(struct mv88e6xxx_chip *chip, int port,
639 uint64_t *data);
640
641 /* SERDES registers for ethtool */
642 int (*serdes_get_regs_len)(struct mv88e6xxx_chip *chip, int port);
643 void (*serdes_get_regs)(struct mv88e6xxx_chip *chip, int port,
644 void *_p);
645
646 /* SERDES SGMII/Fiber Output Amplitude */
647 int (*serdes_set_tx_amplitude)(struct mv88e6xxx_chip *chip, int port,
648 int val);
649
650 /* Address Translation Unit operations */
651 int (*atu_get_hash)(struct mv88e6xxx_chip *chip, u8 *hash);
652 int (*atu_set_hash)(struct mv88e6xxx_chip *chip, u8 hash);
653
654 /* VLAN Translation Unit operations */
655 int (*vtu_getnext)(struct mv88e6xxx_chip *chip,
656 struct mv88e6xxx_vtu_entry *entry);
657 int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip,
658 struct mv88e6xxx_vtu_entry *entry);
659
660 /* Spanning Tree Unit operations */
661 int (*stu_getnext)(struct mv88e6xxx_chip *chip,
662 struct mv88e6xxx_stu_entry *entry);
663 int (*stu_loadpurge)(struct mv88e6xxx_chip *chip,
664 struct mv88e6xxx_stu_entry *entry);
665
666 /* GPIO operations */
667 const struct mv88e6xxx_gpio_ops *gpio_ops;
668
669 /* Interface to the AVB/PTP registers */
670 const struct mv88e6xxx_avb_ops *avb_ops;
671
672 /* Remote Management Unit operations */
673 int (*rmu_disable)(struct mv88e6xxx_chip *chip);
674
675 /* Precision Time Protocol operations */
676 const struct mv88e6xxx_ptp_ops *ptp_ops;
677
678 /* Phylink */
679 void (*phylink_get_caps)(struct mv88e6xxx_chip *chip, int port,
680 struct phylink_config *config);
681
682 const struct mv88e6xxx_pcs_ops *pcs_ops;
683
684 /* Max Frame Size */
685 int (*set_max_frame_size)(struct mv88e6xxx_chip *chip, int mtu);
686};
687
688struct mv88e6xxx_irq_ops {
689 /* Action to be performed when the interrupt happens */
690 int (*irq_action)(struct mv88e6xxx_chip *chip, int irq);
691 /* Setup the hardware to generate the interrupt */
692 int (*irq_setup)(struct mv88e6xxx_chip *chip);
693 /* Reset the hardware to stop generating the interrupt */
694 void (*irq_free)(struct mv88e6xxx_chip *chip);
695};
696
697struct mv88e6xxx_gpio_ops {
698 /* Get/set data on GPIO pin */
699 int (*get_data)(struct mv88e6xxx_chip *chip, unsigned int pin);
700 int (*set_data)(struct mv88e6xxx_chip *chip, unsigned int pin,
701 int value);
702
703 /* get/set GPIO direction */
704 int (*get_dir)(struct mv88e6xxx_chip *chip, unsigned int pin);
705 int (*set_dir)(struct mv88e6xxx_chip *chip, unsigned int pin,
706 bool input);
707
708 /* get/set GPIO pin control */
709 int (*get_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin,
710 int *func);
711 int (*set_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin,
712 int func);
713};
714
715struct mv88e6xxx_avb_ops {
716 /* Access port-scoped Precision Time Protocol registers */
717 int (*port_ptp_read)(struct mv88e6xxx_chip *chip, int port, int addr,
718 u16 *data, int len);
719 int (*port_ptp_write)(struct mv88e6xxx_chip *chip, int port, int addr,
720 u16 data);
721
722 /* Access global Precision Time Protocol registers */
723 int (*ptp_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data,
724 int len);
725 int (*ptp_write)(struct mv88e6xxx_chip *chip, int addr, u16 data);
726
727 /* Access global Time Application Interface registers */
728 int (*tai_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data,
729 int len);
730 int (*tai_write)(struct mv88e6xxx_chip *chip, int addr, u16 data);
731};
732
733struct mv88e6xxx_ptp_ops {
734 u64 (*clock_read)(const struct cyclecounter *cc);
735 int (*ptp_enable)(struct ptp_clock_info *ptp,
736 struct ptp_clock_request *rq, int on);
737 int (*ptp_verify)(struct ptp_clock_info *ptp, unsigned int pin,
738 enum ptp_pin_function func, unsigned int chan);
739 void (*event_work)(struct work_struct *ugly);
740 int (*port_enable)(struct mv88e6xxx_chip *chip, int port);
741 int (*port_disable)(struct mv88e6xxx_chip *chip, int port);
742 int (*global_enable)(struct mv88e6xxx_chip *chip);
743 int (*global_disable)(struct mv88e6xxx_chip *chip);
744 int (*set_ptp_cpu_port)(struct mv88e6xxx_chip *chip, int port);
745 int n_ext_ts;
746 int arr0_sts_reg;
747 int arr1_sts_reg;
748 int dep_sts_reg;
749 u32 rx_filters;
750};
751
752struct mv88e6xxx_pcs_ops {
753 int (*pcs_init)(struct mv88e6xxx_chip *chip, int port);
754 void (*pcs_teardown)(struct mv88e6xxx_chip *chip, int port);
755 struct phylink_pcs *(*pcs_select)(struct mv88e6xxx_chip *chip, int port,
756 phy_interface_t mode);
757
758};
759
760static inline bool mv88e6xxx_has_stu(struct mv88e6xxx_chip *chip)
761{
762 return chip->info->max_sid > 0 &&
763 chip->info->ops->stu_loadpurge &&
764 chip->info->ops->stu_getnext;
765}
766
767static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip)
768{
769 return chip->info->pvt;
770}
771
772static inline bool mv88e6xxx_has_lag(struct mv88e6xxx_chip *chip)
773{
774 return !!chip->info->global2_addr;
775}
776
777static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip)
778{
779 return chip->info->num_databases;
780}
781
782static inline unsigned int mv88e6xxx_num_macs(struct mv88e6xxx_chip *chip)
783{
784 return chip->info->num_macs;
785}
786
787static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip)
788{
789 return chip->info->num_ports;
790}
791
792static inline unsigned int mv88e6xxx_max_vid(struct mv88e6xxx_chip *chip)
793{
794 return chip->info->max_vid;
795}
796
797static inline unsigned int mv88e6xxx_max_sid(struct mv88e6xxx_chip *chip)
798{
799 return chip->info->max_sid;
800}
801
802static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip)
803{
804 return GENMASK((s32)mv88e6xxx_num_ports(chip) - 1, 0);
805}
806
807static inline unsigned int mv88e6xxx_num_gpio(struct mv88e6xxx_chip *chip)
808{
809 return chip->info->num_gpio;
810}
811
812static inline bool mv88e6xxx_is_invalid_port(struct mv88e6xxx_chip *chip, int port)
813{
814 return (chip->info->invalid_port_mask & BIT(port)) != 0;
815}
816
817static inline void mv88e6xxx_port_set_mab(struct mv88e6xxx_chip *chip,
818 int port, bool mab)
819{
820 chip->ports[port].mab = mab;
821}
822
823int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
824int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
825int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
826 u16 mask, u16 val);
827int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
828 int bit, int val);
829struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip);
830
831static inline void mv88e6xxx_reg_lock(struct mv88e6xxx_chip *chip)
832{
833 mutex_lock(&chip->reg_lock);
834}
835
836static inline void mv88e6xxx_reg_unlock(struct mv88e6xxx_chip *chip)
837{
838 mutex_unlock(&chip->reg_lock);
839}
840
841int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip,
842 int (*cb)(struct mv88e6xxx_chip *chip,
843 const struct mv88e6xxx_vtu_entry *entry,
844 void *priv),
845 void *priv);
846
847#endif /* _MV88E6XXX_CHIP_H */
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Marvell 88E6xxx Ethernet switch single-chip definition
4 *
5 * Copyright (c) 2008 Marvell Semiconductor
6 */
7
8#ifndef _MV88E6XXX_CHIP_H
9#define _MV88E6XXX_CHIP_H
10
11#include <linux/idr.h>
12#include <linux/if_vlan.h>
13#include <linux/irq.h>
14#include <linux/gpio/consumer.h>
15#include <linux/kthread.h>
16#include <linux/phy.h>
17#include <linux/ptp_clock_kernel.h>
18#include <linux/timecounter.h>
19#include <net/dsa.h>
20
21#define MV88E6XXX_N_FID 4096
22
23/* PVT limits for 4-bit port and 5-bit switch */
24#define MV88E6XXX_MAX_PVT_SWITCHES 32
25#define MV88E6XXX_MAX_PVT_PORTS 16
26
27#define MV88E6XXX_MAX_GPIO 16
28
29enum mv88e6xxx_egress_mode {
30 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
31 MV88E6XXX_EGRESS_MODE_UNTAGGED,
32 MV88E6XXX_EGRESS_MODE_TAGGED,
33 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
34};
35
36enum mv88e6xxx_egress_direction {
37 MV88E6XXX_EGRESS_DIR_INGRESS,
38 MV88E6XXX_EGRESS_DIR_EGRESS,
39};
40
41enum mv88e6xxx_frame_mode {
42 MV88E6XXX_FRAME_MODE_NORMAL,
43 MV88E6XXX_FRAME_MODE_DSA,
44 MV88E6XXX_FRAME_MODE_PROVIDER,
45 MV88E6XXX_FRAME_MODE_ETHERTYPE,
46};
47
48/* List of supported models */
49enum mv88e6xxx_model {
50 MV88E6085,
51 MV88E6095,
52 MV88E6097,
53 MV88E6123,
54 MV88E6131,
55 MV88E6141,
56 MV88E6161,
57 MV88E6165,
58 MV88E6171,
59 MV88E6172,
60 MV88E6175,
61 MV88E6176,
62 MV88E6185,
63 MV88E6190,
64 MV88E6190X,
65 MV88E6191,
66 MV88E6220,
67 MV88E6240,
68 MV88E6250,
69 MV88E6290,
70 MV88E6320,
71 MV88E6321,
72 MV88E6341,
73 MV88E6350,
74 MV88E6351,
75 MV88E6352,
76 MV88E6390,
77 MV88E6390X,
78};
79
80enum mv88e6xxx_family {
81 MV88E6XXX_FAMILY_NONE,
82 MV88E6XXX_FAMILY_6065, /* 6031 6035 6061 6065 */
83 MV88E6XXX_FAMILY_6095, /* 6092 6095 */
84 MV88E6XXX_FAMILY_6097, /* 6046 6085 6096 6097 */
85 MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */
86 MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */
87 MV88E6XXX_FAMILY_6250, /* 6220 6250 */
88 MV88E6XXX_FAMILY_6320, /* 6320 6321 */
89 MV88E6XXX_FAMILY_6341, /* 6141 6341 */
90 MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */
91 MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */
92 MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */
93};
94
95struct mv88e6xxx_ops;
96
97struct mv88e6xxx_info {
98 enum mv88e6xxx_family family;
99 u16 prod_num;
100 const char *name;
101 unsigned int num_databases;
102 unsigned int num_macs;
103 unsigned int num_ports;
104 unsigned int num_internal_phys;
105 unsigned int num_gpio;
106 unsigned int max_vid;
107 unsigned int port_base_addr;
108 unsigned int phy_base_addr;
109 unsigned int global1_addr;
110 unsigned int global2_addr;
111 unsigned int age_time_coeff;
112 unsigned int g1_irqs;
113 unsigned int g2_irqs;
114 bool pvt;
115
116 /* Mark certain ports as invalid. This is required for example for the
117 * MV88E6220 (which is in general a MV88E6250 with 7 ports) but the
118 * ports 2-4 are not routet to pins.
119 */
120 unsigned int invalid_port_mask;
121 /* Multi-chip Addressing Mode.
122 * Some chips respond to only 2 registers of its own SMI device address
123 * when it is non-zero, and use indirect access to internal registers.
124 */
125 bool multi_chip;
126 /* Dual-chip Addressing Mode
127 * Some chips respond to only half of the 32 SMI addresses,
128 * allowing two to coexist on the same SMI interface.
129 */
130 bool dual_chip;
131
132 enum dsa_tag_protocol tag_protocol;
133
134 /* Mask for FromPort and ToPort value of PortVec used in ATU Move
135 * operation. 0 means that the ATU Move operation is not supported.
136 */
137 u8 atu_move_port_mask;
138 const struct mv88e6xxx_ops *ops;
139
140 /* Supports PTP */
141 bool ptp_support;
142};
143
144struct mv88e6xxx_atu_entry {
145 u8 state;
146 bool trunk;
147 u16 portvec;
148 u8 mac[ETH_ALEN];
149};
150
151struct mv88e6xxx_vtu_entry {
152 u16 vid;
153 u16 fid;
154 u8 sid;
155 bool valid;
156 u8 member[DSA_MAX_PORTS];
157 u8 state[DSA_MAX_PORTS];
158};
159
160struct mv88e6xxx_bus_ops;
161struct mv88e6xxx_irq_ops;
162struct mv88e6xxx_gpio_ops;
163struct mv88e6xxx_avb_ops;
164struct mv88e6xxx_ptp_ops;
165
166struct mv88e6xxx_irq {
167 u16 masked;
168 struct irq_chip chip;
169 struct irq_domain *domain;
170 int nirqs;
171};
172
173/* state flags for mv88e6xxx_port_hwtstamp::state */
174enum {
175 MV88E6XXX_HWTSTAMP_ENABLED,
176 MV88E6XXX_HWTSTAMP_TX_IN_PROGRESS,
177};
178
179struct mv88e6xxx_port_hwtstamp {
180 /* Port index */
181 int port_id;
182
183 /* Timestamping state */
184 unsigned long state;
185
186 /* Resources for receive timestamping */
187 struct sk_buff_head rx_queue;
188 struct sk_buff_head rx_queue2;
189
190 /* Resources for transmit timestamping */
191 unsigned long tx_tstamp_start;
192 struct sk_buff *tx_skb;
193 u16 tx_seq_id;
194
195 /* Current timestamp configuration */
196 struct hwtstamp_config tstamp_config;
197};
198
199enum mv88e6xxx_policy_mapping {
200 MV88E6XXX_POLICY_MAPPING_DA,
201 MV88E6XXX_POLICY_MAPPING_SA,
202 MV88E6XXX_POLICY_MAPPING_VTU,
203 MV88E6XXX_POLICY_MAPPING_ETYPE,
204 MV88E6XXX_POLICY_MAPPING_PPPOE,
205 MV88E6XXX_POLICY_MAPPING_VBAS,
206 MV88E6XXX_POLICY_MAPPING_OPT82,
207 MV88E6XXX_POLICY_MAPPING_UDP,
208};
209
210enum mv88e6xxx_policy_action {
211 MV88E6XXX_POLICY_ACTION_NORMAL,
212 MV88E6XXX_POLICY_ACTION_MIRROR,
213 MV88E6XXX_POLICY_ACTION_TRAP,
214 MV88E6XXX_POLICY_ACTION_DISCARD,
215};
216
217struct mv88e6xxx_policy {
218 enum mv88e6xxx_policy_mapping mapping;
219 enum mv88e6xxx_policy_action action;
220 struct ethtool_rx_flow_spec fs;
221 u8 addr[ETH_ALEN];
222 int port;
223 u16 vid;
224};
225
226struct mv88e6xxx_port {
227 struct mv88e6xxx_chip *chip;
228 int port;
229 u64 serdes_stats[2];
230 u64 atu_member_violation;
231 u64 atu_miss_violation;
232 u64 atu_full_violation;
233 u64 vtu_member_violation;
234 u64 vtu_miss_violation;
235 phy_interface_t interface;
236 u8 cmode;
237 bool mirror_ingress;
238 bool mirror_egress;
239 unsigned int serdes_irq;
240 char serdes_irq_name[64];
241};
242
243struct mv88e6xxx_chip {
244 const struct mv88e6xxx_info *info;
245
246 /* The dsa_switch this private structure is related to */
247 struct dsa_switch *ds;
248
249 /* The device this structure is associated to */
250 struct device *dev;
251
252 /* This mutex protects the access to the switch registers */
253 struct mutex reg_lock;
254
255 /* The MII bus and the address on the bus that is used to
256 * communication with the switch
257 */
258 const struct mv88e6xxx_bus_ops *smi_ops;
259 struct mii_bus *bus;
260 int sw_addr;
261
262 /* Handles automatic disabling and re-enabling of the PHY
263 * polling unit.
264 */
265 const struct mv88e6xxx_bus_ops *phy_ops;
266 struct mutex ppu_mutex;
267 int ppu_disabled;
268 struct work_struct ppu_work;
269 struct timer_list ppu_timer;
270
271 /* This mutex serialises access to the statistics unit.
272 * Hold this mutex over snapshot + dump sequences.
273 */
274 struct mutex stats_mutex;
275
276 /* A switch may have a GPIO line tied to its reset pin. Parse
277 * this from the device tree, and use it before performing
278 * switch soft reset.
279 */
280 struct gpio_desc *reset;
281
282 /* set to size of eeprom if supported by the switch */
283 u32 eeprom_len;
284
285 /* List of mdio busses */
286 struct list_head mdios;
287
288 /* Policy Control List IDs and rules */
289 struct idr policies;
290
291 /* There can be two interrupt controllers, which are chained
292 * off a GPIO as interrupt source
293 */
294 struct mv88e6xxx_irq g1_irq;
295 struct mv88e6xxx_irq g2_irq;
296 int irq;
297 char irq_name[64];
298 int device_irq;
299 char device_irq_name[64];
300 int watchdog_irq;
301 char watchdog_irq_name[64];
302
303 int atu_prob_irq;
304 char atu_prob_irq_name[64];
305 int vtu_prob_irq;
306 char vtu_prob_irq_name[64];
307 struct kthread_worker *kworker;
308 struct kthread_delayed_work irq_poll_work;
309
310 /* GPIO resources */
311 u8 gpio_data[2];
312
313 /* This cyclecounter abstracts the switch PTP time.
314 * reg_lock must be held for any operation that read()s.
315 */
316 struct cyclecounter tstamp_cc;
317 struct timecounter tstamp_tc;
318 struct delayed_work overflow_work;
319
320 struct ptp_clock *ptp_clock;
321 struct ptp_clock_info ptp_clock_info;
322 struct delayed_work tai_event_work;
323 struct ptp_pin_desc pin_config[MV88E6XXX_MAX_GPIO];
324 u16 trig_config;
325 u16 evcap_config;
326 u16 enable_count;
327
328 /* Current ingress and egress monitor ports */
329 int egress_dest_port;
330 int ingress_dest_port;
331
332 /* Per-port timestamping resources. */
333 struct mv88e6xxx_port_hwtstamp port_hwtstamp[DSA_MAX_PORTS];
334
335 /* Array of port structures. */
336 struct mv88e6xxx_port ports[DSA_MAX_PORTS];
337};
338
339struct mv88e6xxx_bus_ops {
340 int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
341 int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
342};
343
344struct mv88e6xxx_mdio_bus {
345 struct mii_bus *bus;
346 struct mv88e6xxx_chip *chip;
347 struct list_head list;
348 bool external;
349};
350
351struct mv88e6xxx_ops {
352 /* Switch Setup Errata, called early in the switch setup to
353 * allow any errata actions to be performed
354 */
355 int (*setup_errata)(struct mv88e6xxx_chip *chip);
356
357 int (*ieee_pri_map)(struct mv88e6xxx_chip *chip);
358 int (*ip_pri_map)(struct mv88e6xxx_chip *chip);
359
360 /* Ingress Rate Limit unit (IRL) operations */
361 int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port);
362
363 int (*get_eeprom)(struct mv88e6xxx_chip *chip,
364 struct ethtool_eeprom *eeprom, u8 *data);
365 int (*set_eeprom)(struct mv88e6xxx_chip *chip,
366 struct ethtool_eeprom *eeprom, u8 *data);
367
368 int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr);
369
370 int (*phy_read)(struct mv88e6xxx_chip *chip,
371 struct mii_bus *bus,
372 int addr, int reg, u16 *val);
373 int (*phy_write)(struct mv88e6xxx_chip *chip,
374 struct mii_bus *bus,
375 int addr, int reg, u16 val);
376
377 /* Priority Override Table operations */
378 int (*pot_clear)(struct mv88e6xxx_chip *chip);
379
380 /* PHY Polling Unit (PPU) operations */
381 int (*ppu_enable)(struct mv88e6xxx_chip *chip);
382 int (*ppu_disable)(struct mv88e6xxx_chip *chip);
383
384 /* Switch Software Reset */
385 int (*reset)(struct mv88e6xxx_chip *chip);
386
387 /* RGMII Receive/Transmit Timing Control
388 * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise.
389 */
390 int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port,
391 phy_interface_t mode);
392
393#define LINK_FORCED_DOWN 0
394#define LINK_FORCED_UP 1
395#define LINK_UNFORCED -2
396
397 /* Port's MAC link state
398 * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down,
399 * or LINK_UNFORCED for normal link detection.
400 */
401 int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link);
402
403#define PAUSE_ON 1
404#define PAUSE_OFF 0
405
406 /* Enable/disable sending Pause */
407 int (*port_set_pause)(struct mv88e6xxx_chip *chip, int port,
408 int pause);
409
410#define SPEED_MAX INT_MAX
411#define SPEED_UNFORCED -2
412#define DUPLEX_UNFORCED -2
413
414 /* Port's MAC speed (in Mbps) and MAC duplex mode
415 *
416 * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid.
417 * Use SPEED_UNFORCED for normal detection, SPEED_MAX for max value.
418 *
419 * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex,
420 * or DUPLEX_UNFORCED for normal duplex detection.
421 */
422 int (*port_set_speed_duplex)(struct mv88e6xxx_chip *chip, int port,
423 int speed, int duplex);
424
425 /* What interface mode should be used for maximum speed? */
426 phy_interface_t (*port_max_speed_mode)(int port);
427
428 int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port);
429
430 int (*port_set_policy)(struct mv88e6xxx_chip *chip, int port,
431 enum mv88e6xxx_policy_mapping mapping,
432 enum mv88e6xxx_policy_action action);
433
434 int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port,
435 enum mv88e6xxx_frame_mode mode);
436 int (*port_set_egress_floods)(struct mv88e6xxx_chip *chip, int port,
437 bool unicast, bool multicast);
438 int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port,
439 u16 etype);
440 int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port,
441 size_t size);
442
443 int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port);
444 int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in,
445 u8 out);
446 int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port);
447 int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port);
448 int (*port_setup_message_port)(struct mv88e6xxx_chip *chip, int port);
449
450 /* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc.
451 * Some chips allow this to be configured on specific ports.
452 */
453 int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port,
454 phy_interface_t mode);
455 int (*port_get_cmode)(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
456
457 /* Some devices have a per port register indicating what is
458 * the upstream port this port should forward to.
459 */
460 int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port,
461 int upstream_port);
462
463 /* Snapshot the statistics for a port. The statistics can then
464 * be read back a leisure but still with a consistent view.
465 */
466 int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port);
467
468 /* Set the histogram mode for statistics, when the control registers
469 * are separated out of the STATS_OP register.
470 */
471 int (*stats_set_histogram)(struct mv88e6xxx_chip *chip);
472
473 /* Return the number of strings describing statistics */
474 int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip);
475 int (*stats_get_strings)(struct mv88e6xxx_chip *chip, uint8_t *data);
476 int (*stats_get_stats)(struct mv88e6xxx_chip *chip, int port,
477 uint64_t *data);
478 int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port);
479 int (*set_egress_port)(struct mv88e6xxx_chip *chip,
480 enum mv88e6xxx_egress_direction direction,
481 int port);
482
483#define MV88E6XXX_CASCADE_PORT_NONE 0xe
484#define MV88E6XXX_CASCADE_PORT_MULTIPLE 0xf
485
486 int (*set_cascade_port)(struct mv88e6xxx_chip *chip, int port);
487
488 const struct mv88e6xxx_irq_ops *watchdog_ops;
489
490 int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip);
491
492 /* Power on/off a SERDES interface */
493 int (*serdes_power)(struct mv88e6xxx_chip *chip, int port, u8 lane,
494 bool up);
495
496 /* SERDES lane mapping */
497 u8 (*serdes_get_lane)(struct mv88e6xxx_chip *chip, int port);
498
499 int (*serdes_pcs_get_state)(struct mv88e6xxx_chip *chip, int port,
500 u8 lane, struct phylink_link_state *state);
501 int (*serdes_pcs_config)(struct mv88e6xxx_chip *chip, int port,
502 u8 lane, unsigned int mode,
503 phy_interface_t interface,
504 const unsigned long *advertise);
505 int (*serdes_pcs_an_restart)(struct mv88e6xxx_chip *chip, int port,
506 u8 lane);
507 int (*serdes_pcs_link_up)(struct mv88e6xxx_chip *chip, int port,
508 u8 lane, int speed, int duplex);
509
510 /* SERDES interrupt handling */
511 unsigned int (*serdes_irq_mapping)(struct mv88e6xxx_chip *chip,
512 int port);
513 int (*serdes_irq_enable)(struct mv88e6xxx_chip *chip, int port, u8 lane,
514 bool enable);
515 irqreturn_t (*serdes_irq_status)(struct mv88e6xxx_chip *chip, int port,
516 u8 lane);
517
518 /* Statistics from the SERDES interface */
519 int (*serdes_get_sset_count)(struct mv88e6xxx_chip *chip, int port);
520 int (*serdes_get_strings)(struct mv88e6xxx_chip *chip, int port,
521 uint8_t *data);
522 int (*serdes_get_stats)(struct mv88e6xxx_chip *chip, int port,
523 uint64_t *data);
524
525 /* SERDES registers for ethtool */
526 int (*serdes_get_regs_len)(struct mv88e6xxx_chip *chip, int port);
527 void (*serdes_get_regs)(struct mv88e6xxx_chip *chip, int port,
528 void *_p);
529
530 /* Address Translation Unit operations */
531 int (*atu_get_hash)(struct mv88e6xxx_chip *chip, u8 *hash);
532 int (*atu_set_hash)(struct mv88e6xxx_chip *chip, u8 hash);
533
534 /* VLAN Translation Unit operations */
535 int (*vtu_getnext)(struct mv88e6xxx_chip *chip,
536 struct mv88e6xxx_vtu_entry *entry);
537 int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip,
538 struct mv88e6xxx_vtu_entry *entry);
539
540 /* GPIO operations */
541 const struct mv88e6xxx_gpio_ops *gpio_ops;
542
543 /* Interface to the AVB/PTP registers */
544 const struct mv88e6xxx_avb_ops *avb_ops;
545
546 /* Remote Management Unit operations */
547 int (*rmu_disable)(struct mv88e6xxx_chip *chip);
548
549 /* Precision Time Protocol operations */
550 const struct mv88e6xxx_ptp_ops *ptp_ops;
551
552 /* Phylink */
553 void (*phylink_validate)(struct mv88e6xxx_chip *chip, int port,
554 unsigned long *mask,
555 struct phylink_link_state *state);
556
557 /* Max Frame Size */
558 int (*set_max_frame_size)(struct mv88e6xxx_chip *chip, int mtu);
559};
560
561struct mv88e6xxx_irq_ops {
562 /* Action to be performed when the interrupt happens */
563 int (*irq_action)(struct mv88e6xxx_chip *chip, int irq);
564 /* Setup the hardware to generate the interrupt */
565 int (*irq_setup)(struct mv88e6xxx_chip *chip);
566 /* Reset the hardware to stop generating the interrupt */
567 void (*irq_free)(struct mv88e6xxx_chip *chip);
568};
569
570struct mv88e6xxx_gpio_ops {
571 /* Get/set data on GPIO pin */
572 int (*get_data)(struct mv88e6xxx_chip *chip, unsigned int pin);
573 int (*set_data)(struct mv88e6xxx_chip *chip, unsigned int pin,
574 int value);
575
576 /* get/set GPIO direction */
577 int (*get_dir)(struct mv88e6xxx_chip *chip, unsigned int pin);
578 int (*set_dir)(struct mv88e6xxx_chip *chip, unsigned int pin,
579 bool input);
580
581 /* get/set GPIO pin control */
582 int (*get_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin,
583 int *func);
584 int (*set_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin,
585 int func);
586};
587
588struct mv88e6xxx_avb_ops {
589 /* Access port-scoped Precision Time Protocol registers */
590 int (*port_ptp_read)(struct mv88e6xxx_chip *chip, int port, int addr,
591 u16 *data, int len);
592 int (*port_ptp_write)(struct mv88e6xxx_chip *chip, int port, int addr,
593 u16 data);
594
595 /* Access global Precision Time Protocol registers */
596 int (*ptp_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data,
597 int len);
598 int (*ptp_write)(struct mv88e6xxx_chip *chip, int addr, u16 data);
599
600 /* Access global Time Application Interface registers */
601 int (*tai_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data,
602 int len);
603 int (*tai_write)(struct mv88e6xxx_chip *chip, int addr, u16 data);
604};
605
606struct mv88e6xxx_ptp_ops {
607 u64 (*clock_read)(const struct cyclecounter *cc);
608 int (*ptp_enable)(struct ptp_clock_info *ptp,
609 struct ptp_clock_request *rq, int on);
610 int (*ptp_verify)(struct ptp_clock_info *ptp, unsigned int pin,
611 enum ptp_pin_function func, unsigned int chan);
612 void (*event_work)(struct work_struct *ugly);
613 int (*port_enable)(struct mv88e6xxx_chip *chip, int port);
614 int (*port_disable)(struct mv88e6xxx_chip *chip, int port);
615 int (*global_enable)(struct mv88e6xxx_chip *chip);
616 int (*global_disable)(struct mv88e6xxx_chip *chip);
617 int n_ext_ts;
618 int arr0_sts_reg;
619 int arr1_sts_reg;
620 int dep_sts_reg;
621 u32 rx_filters;
622 u32 cc_shift;
623 u32 cc_mult;
624 u32 cc_mult_num;
625 u32 cc_mult_dem;
626};
627
628#define STATS_TYPE_PORT BIT(0)
629#define STATS_TYPE_BANK0 BIT(1)
630#define STATS_TYPE_BANK1 BIT(2)
631
632struct mv88e6xxx_hw_stat {
633 char string[ETH_GSTRING_LEN];
634 size_t size;
635 int reg;
636 int type;
637};
638
639static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip)
640{
641 return chip->info->pvt;
642}
643
644static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip)
645{
646 return chip->info->num_databases;
647}
648
649static inline unsigned int mv88e6xxx_num_macs(struct mv88e6xxx_chip *chip)
650{
651 return chip->info->num_macs;
652}
653
654static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip)
655{
656 return chip->info->num_ports;
657}
658
659static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip)
660{
661 return GENMASK((s32)mv88e6xxx_num_ports(chip) - 1, 0);
662}
663
664static inline unsigned int mv88e6xxx_num_gpio(struct mv88e6xxx_chip *chip)
665{
666 return chip->info->num_gpio;
667}
668
669static inline bool mv88e6xxx_is_invalid_port(struct mv88e6xxx_chip *chip, int port)
670{
671 return (chip->info->invalid_port_mask & BIT(port)) != 0;
672}
673
674int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
675int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
676int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
677 u16 mask, u16 val);
678int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
679 int bit, int val);
680struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip);
681
682static inline void mv88e6xxx_reg_lock(struct mv88e6xxx_chip *chip)
683{
684 mutex_lock(&chip->reg_lock);
685}
686
687static inline void mv88e6xxx_reg_unlock(struct mv88e6xxx_chip *chip)
688{
689 mutex_unlock(&chip->reg_lock);
690}
691
692#endif /* _MV88E6XXX_CHIP_H */