Loading...
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * GPIO driver for the ACCES 104-DIO-48E series
4 * Copyright (C) 2016 William Breathitt Gray
5 *
6 * This driver supports the following ACCES devices: 104-DIO-48E and
7 * 104-DIO-24E.
8 */
9#include <linux/bits.h>
10#include <linux/device.h>
11#include <linux/err.h>
12#include <linux/i8254.h>
13#include <linux/ioport.h>
14#include <linux/irq.h>
15#include <linux/isa.h>
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/moduleparam.h>
19#include <linux/regmap.h>
20#include <linux/spinlock.h>
21#include <linux/types.h>
22
23#include "gpio-i8255.h"
24
25MODULE_IMPORT_NS("I8255");
26
27#define DIO48E_EXTENT 16
28#define MAX_NUM_DIO48E max_num_isa_dev(DIO48E_EXTENT)
29
30static unsigned int base[MAX_NUM_DIO48E];
31static unsigned int num_dio48e;
32module_param_hw_array(base, uint, ioport, &num_dio48e, 0);
33MODULE_PARM_DESC(base, "ACCES 104-DIO-48E base addresses");
34
35static unsigned int irq[MAX_NUM_DIO48E];
36static unsigned int num_irq;
37module_param_hw_array(irq, uint, irq, &num_irq, 0);
38MODULE_PARM_DESC(irq, "ACCES 104-DIO-48E interrupt line numbers");
39
40#define DIO48E_ENABLE_INTERRUPT 0xB
41#define DIO48E_DISABLE_INTERRUPT DIO48E_ENABLE_INTERRUPT
42#define DIO48E_ENABLE_COUNTER_TIMER_ADDRESSING 0xD
43#define DIO48E_DISABLE_COUNTER_TIMER_ADDRESSING DIO48E_ENABLE_COUNTER_TIMER_ADDRESSING
44#define DIO48E_CLEAR_INTERRUPT 0xF
45
46#define DIO48E_NUM_PPI 2
47
48static const struct regmap_range dio48e_wr_ranges[] = {
49 regmap_reg_range(0x0, 0x9), regmap_reg_range(0xB, 0xB),
50 regmap_reg_range(0xD, 0xD), regmap_reg_range(0xF, 0xF),
51};
52static const struct regmap_range dio48e_rd_ranges[] = {
53 regmap_reg_range(0x0, 0x2), regmap_reg_range(0x4, 0x6),
54 regmap_reg_range(0xB, 0xB), regmap_reg_range(0xD, 0xD),
55 regmap_reg_range(0xF, 0xF),
56};
57static const struct regmap_range dio48e_volatile_ranges[] = {
58 i8255_volatile_regmap_range(0x0), i8255_volatile_regmap_range(0x4),
59 regmap_reg_range(0xB, 0xB), regmap_reg_range(0xD, 0xD),
60 regmap_reg_range(0xF, 0xF),
61};
62static const struct regmap_range dio48e_precious_ranges[] = {
63 regmap_reg_range(0xB, 0xB), regmap_reg_range(0xD, 0xD),
64 regmap_reg_range(0xF, 0xF),
65};
66static const struct regmap_access_table dio48e_wr_table = {
67 .yes_ranges = dio48e_wr_ranges,
68 .n_yes_ranges = ARRAY_SIZE(dio48e_wr_ranges),
69};
70static const struct regmap_access_table dio48e_rd_table = {
71 .yes_ranges = dio48e_rd_ranges,
72 .n_yes_ranges = ARRAY_SIZE(dio48e_rd_ranges),
73};
74static const struct regmap_access_table dio48e_volatile_table = {
75 .yes_ranges = dio48e_volatile_ranges,
76 .n_yes_ranges = ARRAY_SIZE(dio48e_volatile_ranges),
77};
78static const struct regmap_access_table dio48e_precious_table = {
79 .yes_ranges = dio48e_precious_ranges,
80 .n_yes_ranges = ARRAY_SIZE(dio48e_precious_ranges),
81};
82
83static const struct regmap_range pit_wr_ranges[] = {
84 regmap_reg_range(0x0, 0x3),
85};
86static const struct regmap_range pit_rd_ranges[] = {
87 regmap_reg_range(0x0, 0x2),
88};
89static const struct regmap_access_table pit_wr_table = {
90 .yes_ranges = pit_wr_ranges,
91 .n_yes_ranges = ARRAY_SIZE(pit_wr_ranges),
92};
93static const struct regmap_access_table pit_rd_table = {
94 .yes_ranges = pit_rd_ranges,
95 .n_yes_ranges = ARRAY_SIZE(pit_rd_ranges),
96};
97
98/* only bit 3 on each respective Port C supports interrupts */
99#define DIO48E_REGMAP_IRQ(_ppi) \
100 [19 + (_ppi) * 24] = { \
101 .mask = BIT(_ppi), \
102 .type = { .types_supported = IRQ_TYPE_EDGE_RISING }, \
103 }
104
105static const struct regmap_irq dio48e_regmap_irqs[] = {
106 DIO48E_REGMAP_IRQ(0), DIO48E_REGMAP_IRQ(1),
107};
108
109/**
110 * struct dio48e_gpio - GPIO device private data structure
111 * @lock: synchronization lock to prevent I/O race conditions
112 * @map: Regmap for the device
113 * @regs: virtual mapping for device registers
114 * @flags: IRQ flags saved during locking
115 * @irq_mask: Current IRQ mask state on the device
116 */
117struct dio48e_gpio {
118 raw_spinlock_t lock;
119 struct regmap *map;
120 void __iomem *regs;
121 unsigned long flags;
122 unsigned int irq_mask;
123};
124
125static void dio48e_regmap_lock(void *lock_arg) __acquires(&dio48egpio->lock)
126{
127 struct dio48e_gpio *const dio48egpio = lock_arg;
128 unsigned long flags;
129
130 raw_spin_lock_irqsave(&dio48egpio->lock, flags);
131 dio48egpio->flags = flags;
132}
133
134static void dio48e_regmap_unlock(void *lock_arg) __releases(&dio48egpio->lock)
135{
136 struct dio48e_gpio *const dio48egpio = lock_arg;
137
138 raw_spin_unlock_irqrestore(&dio48egpio->lock, dio48egpio->flags);
139}
140
141static void pit_regmap_lock(void *lock_arg) __acquires(&dio48egpio->lock)
142{
143 struct dio48e_gpio *const dio48egpio = lock_arg;
144 unsigned long flags;
145
146 raw_spin_lock_irqsave(&dio48egpio->lock, flags);
147 dio48egpio->flags = flags;
148
149 iowrite8(0x00, dio48egpio->regs + DIO48E_ENABLE_COUNTER_TIMER_ADDRESSING);
150}
151
152static void pit_regmap_unlock(void *lock_arg) __releases(&dio48egpio->lock)
153{
154 struct dio48e_gpio *const dio48egpio = lock_arg;
155
156 ioread8(dio48egpio->regs + DIO48E_DISABLE_COUNTER_TIMER_ADDRESSING);
157
158 raw_spin_unlock_irqrestore(&dio48egpio->lock, dio48egpio->flags);
159}
160
161static int dio48e_handle_mask_sync(const int index,
162 const unsigned int mask_buf_def,
163 const unsigned int mask_buf,
164 void *const irq_drv_data)
165{
166 struct dio48e_gpio *const dio48egpio = irq_drv_data;
167 const unsigned int prev_mask = dio48egpio->irq_mask;
168 int err;
169 unsigned int val;
170
171 /* exit early if no change since the previous mask */
172 if (mask_buf == prev_mask)
173 return 0;
174
175 /* remember the current mask for the next mask sync */
176 dio48egpio->irq_mask = mask_buf;
177
178 /* if all previously masked, enable interrupts when unmasking */
179 if (prev_mask == mask_buf_def) {
180 err = regmap_write(dio48egpio->map, DIO48E_CLEAR_INTERRUPT, 0x00);
181 if (err)
182 return err;
183 return regmap_write(dio48egpio->map, DIO48E_ENABLE_INTERRUPT, 0x00);
184 }
185
186 /* if all are currently masked, disable interrupts */
187 if (mask_buf == mask_buf_def)
188 return regmap_read(dio48egpio->map, DIO48E_DISABLE_INTERRUPT, &val);
189
190 return 0;
191}
192
193#define DIO48E_NGPIO 48
194static const char *dio48e_names[DIO48E_NGPIO] = {
195 "PPI Group 0 Port A 0", "PPI Group 0 Port A 1", "PPI Group 0 Port A 2",
196 "PPI Group 0 Port A 3", "PPI Group 0 Port A 4", "PPI Group 0 Port A 5",
197 "PPI Group 0 Port A 6", "PPI Group 0 Port A 7", "PPI Group 0 Port B 0",
198 "PPI Group 0 Port B 1", "PPI Group 0 Port B 2", "PPI Group 0 Port B 3",
199 "PPI Group 0 Port B 4", "PPI Group 0 Port B 5", "PPI Group 0 Port B 6",
200 "PPI Group 0 Port B 7", "PPI Group 0 Port C 0", "PPI Group 0 Port C 1",
201 "PPI Group 0 Port C 2", "PPI Group 0 Port C 3", "PPI Group 0 Port C 4",
202 "PPI Group 0 Port C 5", "PPI Group 0 Port C 6", "PPI Group 0 Port C 7",
203 "PPI Group 1 Port A 0", "PPI Group 1 Port A 1", "PPI Group 1 Port A 2",
204 "PPI Group 1 Port A 3", "PPI Group 1 Port A 4", "PPI Group 1 Port A 5",
205 "PPI Group 1 Port A 6", "PPI Group 1 Port A 7", "PPI Group 1 Port B 0",
206 "PPI Group 1 Port B 1", "PPI Group 1 Port B 2", "PPI Group 1 Port B 3",
207 "PPI Group 1 Port B 4", "PPI Group 1 Port B 5", "PPI Group 1 Port B 6",
208 "PPI Group 1 Port B 7", "PPI Group 1 Port C 0", "PPI Group 1 Port C 1",
209 "PPI Group 1 Port C 2", "PPI Group 1 Port C 3", "PPI Group 1 Port C 4",
210 "PPI Group 1 Port C 5", "PPI Group 1 Port C 6", "PPI Group 1 Port C 7"
211};
212
213static int dio48e_irq_init_hw(struct regmap *const map)
214{
215 unsigned int val;
216
217 /* Disable IRQ by default */
218 return regmap_read(map, DIO48E_DISABLE_INTERRUPT, &val);
219}
220
221static int dio48e_probe(struct device *dev, unsigned int id)
222{
223 const char *const name = dev_name(dev);
224 struct i8255_regmap_config config = {};
225 void __iomem *regs;
226 struct regmap *map;
227 struct regmap_config dio48e_regmap_config;
228 struct regmap_config pit_regmap_config;
229 struct i8254_regmap_config pit_config;
230 int err;
231 struct regmap_irq_chip *chip;
232 struct dio48e_gpio *dio48egpio;
233 struct regmap_irq_chip_data *chip_data;
234
235 if (!devm_request_region(dev, base[id], DIO48E_EXTENT, name)) {
236 dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
237 base[id], base[id] + DIO48E_EXTENT);
238 return -EBUSY;
239 }
240
241 dio48egpio = devm_kzalloc(dev, sizeof(*dio48egpio), GFP_KERNEL);
242 if (!dio48egpio)
243 return -ENOMEM;
244
245 regs = devm_ioport_map(dev, base[id], DIO48E_EXTENT);
246 if (!regs)
247 return -ENOMEM;
248
249 dio48egpio->regs = regs;
250
251 raw_spin_lock_init(&dio48egpio->lock);
252
253 dio48e_regmap_config = (struct regmap_config) {
254 .reg_bits = 8,
255 .reg_stride = 1,
256 .val_bits = 8,
257 .lock = dio48e_regmap_lock,
258 .unlock = dio48e_regmap_unlock,
259 .lock_arg = dio48egpio,
260 .io_port = true,
261 .wr_table = &dio48e_wr_table,
262 .rd_table = &dio48e_rd_table,
263 .volatile_table = &dio48e_volatile_table,
264 .precious_table = &dio48e_precious_table,
265 .cache_type = REGCACHE_FLAT,
266 };
267
268 map = devm_regmap_init_mmio(dev, regs, &dio48e_regmap_config);
269 if (IS_ERR(map))
270 return dev_err_probe(dev, PTR_ERR(map),
271 "Unable to initialize register map\n");
272
273 dio48egpio->map = map;
274
275 pit_regmap_config = (struct regmap_config) {
276 .name = "i8254",
277 .reg_bits = 8,
278 .reg_stride = 1,
279 .val_bits = 8,
280 .lock = pit_regmap_lock,
281 .unlock = pit_regmap_unlock,
282 .lock_arg = dio48egpio,
283 .io_port = true,
284 .wr_table = &pit_wr_table,
285 .rd_table = &pit_rd_table,
286 };
287
288 pit_config.map = devm_regmap_init_mmio(dev, regs, &pit_regmap_config);
289 if (IS_ERR(pit_config.map))
290 return dev_err_probe(dev, PTR_ERR(pit_config.map),
291 "Unable to initialize i8254 register map\n");
292
293 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
294 if (!chip)
295 return -ENOMEM;
296
297 chip->name = name;
298 chip->mask_base = DIO48E_ENABLE_INTERRUPT;
299 chip->ack_base = DIO48E_CLEAR_INTERRUPT;
300 chip->no_status = true;
301 chip->num_regs = 1;
302 chip->irqs = dio48e_regmap_irqs;
303 chip->num_irqs = ARRAY_SIZE(dio48e_regmap_irqs);
304 chip->handle_mask_sync = dio48e_handle_mask_sync;
305 chip->irq_drv_data = dio48egpio;
306
307 /* Initialize to prevent spurious interrupts before we're ready */
308 err = dio48e_irq_init_hw(map);
309 if (err)
310 return err;
311
312 err = devm_regmap_add_irq_chip(dev, map, irq[id], 0, 0, chip, &chip_data);
313 if (err)
314 return dev_err_probe(dev, err, "IRQ registration failed\n");
315
316 pit_config.parent = dev;
317
318 err = devm_i8254_regmap_register(dev, &pit_config);
319 if (err)
320 return err;
321
322 config.parent = dev;
323 config.map = map;
324 config.num_ppi = DIO48E_NUM_PPI;
325 config.names = dio48e_names;
326 config.domain = regmap_irq_get_domain(chip_data);
327
328 return devm_i8255_regmap_register(dev, &config);
329}
330
331static struct isa_driver dio48e_driver = {
332 .probe = dio48e_probe,
333 .driver = {
334 .name = "104-dio-48e"
335 },
336};
337module_isa_driver_with_irq(dio48e_driver, num_dio48e, num_irq);
338
339MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
340MODULE_DESCRIPTION("ACCES 104-DIO-48E GPIO driver");
341MODULE_LICENSE("GPL v2");
342MODULE_IMPORT_NS("I8254");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * GPIO driver for the ACCES 104-DIO-48E series
4 * Copyright (C) 2016 William Breathitt Gray
5 *
6 * This driver supports the following ACCES devices: 104-DIO-48E and
7 * 104-DIO-24E.
8 */
9#include <linux/bitmap.h>
10#include <linux/bitops.h>
11#include <linux/device.h>
12#include <linux/errno.h>
13#include <linux/gpio/driver.h>
14#include <linux/io.h>
15#include <linux/ioport.h>
16#include <linux/interrupt.h>
17#include <linux/irqdesc.h>
18#include <linux/isa.h>
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/moduleparam.h>
22#include <linux/spinlock.h>
23
24#define DIO48E_EXTENT 16
25#define MAX_NUM_DIO48E max_num_isa_dev(DIO48E_EXTENT)
26
27static unsigned int base[MAX_NUM_DIO48E];
28static unsigned int num_dio48e;
29module_param_hw_array(base, uint, ioport, &num_dio48e, 0);
30MODULE_PARM_DESC(base, "ACCES 104-DIO-48E base addresses");
31
32static unsigned int irq[MAX_NUM_DIO48E];
33module_param_hw_array(irq, uint, irq, NULL, 0);
34MODULE_PARM_DESC(irq, "ACCES 104-DIO-48E interrupt line numbers");
35
36/**
37 * struct dio48e_gpio - GPIO device private data structure
38 * @chip: instance of the gpio_chip
39 * @io_state: bit I/O state (whether bit is set to input or output)
40 * @out_state: output bits state
41 * @control: Control registers state
42 * @lock: synchronization lock to prevent I/O race conditions
43 * @base: base port address of the GPIO device
44 * @irq_mask: I/O bits affected by interrupts
45 */
46struct dio48e_gpio {
47 struct gpio_chip chip;
48 unsigned char io_state[6];
49 unsigned char out_state[6];
50 unsigned char control[2];
51 raw_spinlock_t lock;
52 unsigned base;
53 unsigned char irq_mask;
54};
55
56static int dio48e_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
57{
58 struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
59 const unsigned port = offset / 8;
60 const unsigned mask = BIT(offset % 8);
61
62 if (dio48egpio->io_state[port] & mask)
63 return GPIO_LINE_DIRECTION_IN;
64
65 return GPIO_LINE_DIRECTION_OUT;
66}
67
68static int dio48e_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
69{
70 struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
71 const unsigned io_port = offset / 8;
72 const unsigned int control_port = io_port / 3;
73 const unsigned control_addr = dio48egpio->base + 3 + control_port*4;
74 unsigned long flags;
75 unsigned control;
76
77 raw_spin_lock_irqsave(&dio48egpio->lock, flags);
78
79 /* Check if configuring Port C */
80 if (io_port == 2 || io_port == 5) {
81 /* Port C can be configured by nibble */
82 if (offset % 8 > 3) {
83 dio48egpio->io_state[io_port] |= 0xF0;
84 dio48egpio->control[control_port] |= BIT(3);
85 } else {
86 dio48egpio->io_state[io_port] |= 0x0F;
87 dio48egpio->control[control_port] |= BIT(0);
88 }
89 } else {
90 dio48egpio->io_state[io_port] |= 0xFF;
91 if (io_port == 0 || io_port == 3)
92 dio48egpio->control[control_port] |= BIT(4);
93 else
94 dio48egpio->control[control_port] |= BIT(1);
95 }
96
97 control = BIT(7) | dio48egpio->control[control_port];
98 outb(control, control_addr);
99 control &= ~BIT(7);
100 outb(control, control_addr);
101
102 raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
103
104 return 0;
105}
106
107static int dio48e_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
108 int value)
109{
110 struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
111 const unsigned io_port = offset / 8;
112 const unsigned int control_port = io_port / 3;
113 const unsigned mask = BIT(offset % 8);
114 const unsigned control_addr = dio48egpio->base + 3 + control_port*4;
115 const unsigned out_port = (io_port > 2) ? io_port + 1 : io_port;
116 unsigned long flags;
117 unsigned control;
118
119 raw_spin_lock_irqsave(&dio48egpio->lock, flags);
120
121 /* Check if configuring Port C */
122 if (io_port == 2 || io_port == 5) {
123 /* Port C can be configured by nibble */
124 if (offset % 8 > 3) {
125 dio48egpio->io_state[io_port] &= 0x0F;
126 dio48egpio->control[control_port] &= ~BIT(3);
127 } else {
128 dio48egpio->io_state[io_port] &= 0xF0;
129 dio48egpio->control[control_port] &= ~BIT(0);
130 }
131 } else {
132 dio48egpio->io_state[io_port] &= 0x00;
133 if (io_port == 0 || io_port == 3)
134 dio48egpio->control[control_port] &= ~BIT(4);
135 else
136 dio48egpio->control[control_port] &= ~BIT(1);
137 }
138
139 if (value)
140 dio48egpio->out_state[io_port] |= mask;
141 else
142 dio48egpio->out_state[io_port] &= ~mask;
143
144 control = BIT(7) | dio48egpio->control[control_port];
145 outb(control, control_addr);
146
147 outb(dio48egpio->out_state[io_port], dio48egpio->base + out_port);
148
149 control &= ~BIT(7);
150 outb(control, control_addr);
151
152 raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
153
154 return 0;
155}
156
157static int dio48e_gpio_get(struct gpio_chip *chip, unsigned offset)
158{
159 struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
160 const unsigned port = offset / 8;
161 const unsigned mask = BIT(offset % 8);
162 const unsigned in_port = (port > 2) ? port + 1 : port;
163 unsigned long flags;
164 unsigned port_state;
165
166 raw_spin_lock_irqsave(&dio48egpio->lock, flags);
167
168 /* ensure that GPIO is set for input */
169 if (!(dio48egpio->io_state[port] & mask)) {
170 raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
171 return -EINVAL;
172 }
173
174 port_state = inb(dio48egpio->base + in_port);
175
176 raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
177
178 return !!(port_state & mask);
179}
180
181static const size_t ports[] = { 0, 1, 2, 4, 5, 6 };
182
183static int dio48e_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
184 unsigned long *bits)
185{
186 struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
187 unsigned long offset;
188 unsigned long gpio_mask;
189 unsigned int port_addr;
190 unsigned long port_state;
191
192 /* clear bits array to a clean slate */
193 bitmap_zero(bits, chip->ngpio);
194
195 for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) {
196 port_addr = dio48egpio->base + ports[offset / 8];
197 port_state = inb(port_addr) & gpio_mask;
198
199 bitmap_set_value8(bits, port_state, offset);
200 }
201
202 return 0;
203}
204
205static void dio48e_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
206{
207 struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
208 const unsigned port = offset / 8;
209 const unsigned mask = BIT(offset % 8);
210 const unsigned out_port = (port > 2) ? port + 1 : port;
211 unsigned long flags;
212
213 raw_spin_lock_irqsave(&dio48egpio->lock, flags);
214
215 if (value)
216 dio48egpio->out_state[port] |= mask;
217 else
218 dio48egpio->out_state[port] &= ~mask;
219
220 outb(dio48egpio->out_state[port], dio48egpio->base + out_port);
221
222 raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
223}
224
225static void dio48e_gpio_set_multiple(struct gpio_chip *chip,
226 unsigned long *mask, unsigned long *bits)
227{
228 struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
229 unsigned long offset;
230 unsigned long gpio_mask;
231 size_t index;
232 unsigned int port_addr;
233 unsigned long bitmask;
234 unsigned long flags;
235
236 for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) {
237 index = offset / 8;
238 port_addr = dio48egpio->base + ports[index];
239
240 bitmask = bitmap_get_value8(bits, offset) & gpio_mask;
241
242 raw_spin_lock_irqsave(&dio48egpio->lock, flags);
243
244 /* update output state data and set device gpio register */
245 dio48egpio->out_state[index] &= ~gpio_mask;
246 dio48egpio->out_state[index] |= bitmask;
247 outb(dio48egpio->out_state[index], port_addr);
248
249 raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
250 }
251}
252
253static void dio48e_irq_ack(struct irq_data *data)
254{
255}
256
257static void dio48e_irq_mask(struct irq_data *data)
258{
259 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
260 struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
261 const unsigned long offset = irqd_to_hwirq(data);
262 unsigned long flags;
263
264 /* only bit 3 on each respective Port C supports interrupts */
265 if (offset != 19 && offset != 43)
266 return;
267
268 raw_spin_lock_irqsave(&dio48egpio->lock, flags);
269
270 if (offset == 19)
271 dio48egpio->irq_mask &= ~BIT(0);
272 else
273 dio48egpio->irq_mask &= ~BIT(1);
274
275 if (!dio48egpio->irq_mask)
276 /* disable interrupts */
277 inb(dio48egpio->base + 0xB);
278
279 raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
280}
281
282static void dio48e_irq_unmask(struct irq_data *data)
283{
284 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
285 struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
286 const unsigned long offset = irqd_to_hwirq(data);
287 unsigned long flags;
288
289 /* only bit 3 on each respective Port C supports interrupts */
290 if (offset != 19 && offset != 43)
291 return;
292
293 raw_spin_lock_irqsave(&dio48egpio->lock, flags);
294
295 if (!dio48egpio->irq_mask) {
296 /* enable interrupts */
297 outb(0x00, dio48egpio->base + 0xF);
298 outb(0x00, dio48egpio->base + 0xB);
299 }
300
301 if (offset == 19)
302 dio48egpio->irq_mask |= BIT(0);
303 else
304 dio48egpio->irq_mask |= BIT(1);
305
306 raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
307}
308
309static int dio48e_irq_set_type(struct irq_data *data, unsigned flow_type)
310{
311 const unsigned long offset = irqd_to_hwirq(data);
312
313 /* only bit 3 on each respective Port C supports interrupts */
314 if (offset != 19 && offset != 43)
315 return -EINVAL;
316
317 if (flow_type != IRQ_TYPE_NONE && flow_type != IRQ_TYPE_EDGE_RISING)
318 return -EINVAL;
319
320 return 0;
321}
322
323static struct irq_chip dio48e_irqchip = {
324 .name = "104-dio-48e",
325 .irq_ack = dio48e_irq_ack,
326 .irq_mask = dio48e_irq_mask,
327 .irq_unmask = dio48e_irq_unmask,
328 .irq_set_type = dio48e_irq_set_type
329};
330
331static irqreturn_t dio48e_irq_handler(int irq, void *dev_id)
332{
333 struct dio48e_gpio *const dio48egpio = dev_id;
334 struct gpio_chip *const chip = &dio48egpio->chip;
335 const unsigned long irq_mask = dio48egpio->irq_mask;
336 unsigned long gpio;
337
338 for_each_set_bit(gpio, &irq_mask, 2)
339 generic_handle_irq(irq_find_mapping(chip->irq.domain,
340 19 + gpio*24));
341
342 raw_spin_lock(&dio48egpio->lock);
343
344 outb(0x00, dio48egpio->base + 0xF);
345
346 raw_spin_unlock(&dio48egpio->lock);
347
348 return IRQ_HANDLED;
349}
350
351#define DIO48E_NGPIO 48
352static const char *dio48e_names[DIO48E_NGPIO] = {
353 "PPI Group 0 Port A 0", "PPI Group 0 Port A 1", "PPI Group 0 Port A 2",
354 "PPI Group 0 Port A 3", "PPI Group 0 Port A 4", "PPI Group 0 Port A 5",
355 "PPI Group 0 Port A 6", "PPI Group 0 Port A 7", "PPI Group 0 Port B 0",
356 "PPI Group 0 Port B 1", "PPI Group 0 Port B 2", "PPI Group 0 Port B 3",
357 "PPI Group 0 Port B 4", "PPI Group 0 Port B 5", "PPI Group 0 Port B 6",
358 "PPI Group 0 Port B 7", "PPI Group 0 Port C 0", "PPI Group 0 Port C 1",
359 "PPI Group 0 Port C 2", "PPI Group 0 Port C 3", "PPI Group 0 Port C 4",
360 "PPI Group 0 Port C 5", "PPI Group 0 Port C 6", "PPI Group 0 Port C 7",
361 "PPI Group 1 Port A 0", "PPI Group 1 Port A 1", "PPI Group 1 Port A 2",
362 "PPI Group 1 Port A 3", "PPI Group 1 Port A 4", "PPI Group 1 Port A 5",
363 "PPI Group 1 Port A 6", "PPI Group 1 Port A 7", "PPI Group 1 Port B 0",
364 "PPI Group 1 Port B 1", "PPI Group 1 Port B 2", "PPI Group 1 Port B 3",
365 "PPI Group 1 Port B 4", "PPI Group 1 Port B 5", "PPI Group 1 Port B 6",
366 "PPI Group 1 Port B 7", "PPI Group 1 Port C 0", "PPI Group 1 Port C 1",
367 "PPI Group 1 Port C 2", "PPI Group 1 Port C 3", "PPI Group 1 Port C 4",
368 "PPI Group 1 Port C 5", "PPI Group 1 Port C 6", "PPI Group 1 Port C 7"
369};
370
371static int dio48e_irq_init_hw(struct gpio_chip *gc)
372{
373 struct dio48e_gpio *const dio48egpio = gpiochip_get_data(gc);
374
375 /* Disable IRQ by default */
376 inb(dio48egpio->base + 0xB);
377
378 return 0;
379}
380
381static int dio48e_probe(struct device *dev, unsigned int id)
382{
383 struct dio48e_gpio *dio48egpio;
384 const char *const name = dev_name(dev);
385 struct gpio_irq_chip *girq;
386 int err;
387
388 dio48egpio = devm_kzalloc(dev, sizeof(*dio48egpio), GFP_KERNEL);
389 if (!dio48egpio)
390 return -ENOMEM;
391
392 if (!devm_request_region(dev, base[id], DIO48E_EXTENT, name)) {
393 dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
394 base[id], base[id] + DIO48E_EXTENT);
395 return -EBUSY;
396 }
397
398 dio48egpio->chip.label = name;
399 dio48egpio->chip.parent = dev;
400 dio48egpio->chip.owner = THIS_MODULE;
401 dio48egpio->chip.base = -1;
402 dio48egpio->chip.ngpio = DIO48E_NGPIO;
403 dio48egpio->chip.names = dio48e_names;
404 dio48egpio->chip.get_direction = dio48e_gpio_get_direction;
405 dio48egpio->chip.direction_input = dio48e_gpio_direction_input;
406 dio48egpio->chip.direction_output = dio48e_gpio_direction_output;
407 dio48egpio->chip.get = dio48e_gpio_get;
408 dio48egpio->chip.get_multiple = dio48e_gpio_get_multiple;
409 dio48egpio->chip.set = dio48e_gpio_set;
410 dio48egpio->chip.set_multiple = dio48e_gpio_set_multiple;
411 dio48egpio->base = base[id];
412
413 girq = &dio48egpio->chip.irq;
414 girq->chip = &dio48e_irqchip;
415 /* This will let us handle the parent IRQ in the driver */
416 girq->parent_handler = NULL;
417 girq->num_parents = 0;
418 girq->parents = NULL;
419 girq->default_type = IRQ_TYPE_NONE;
420 girq->handler = handle_edge_irq;
421 girq->init_hw = dio48e_irq_init_hw;
422
423 raw_spin_lock_init(&dio48egpio->lock);
424
425 /* initialize all GPIO as output */
426 outb(0x80, base[id] + 3);
427 outb(0x00, base[id]);
428 outb(0x00, base[id] + 1);
429 outb(0x00, base[id] + 2);
430 outb(0x00, base[id] + 3);
431 outb(0x80, base[id] + 7);
432 outb(0x00, base[id] + 4);
433 outb(0x00, base[id] + 5);
434 outb(0x00, base[id] + 6);
435 outb(0x00, base[id] + 7);
436
437 err = devm_gpiochip_add_data(dev, &dio48egpio->chip, dio48egpio);
438 if (err) {
439 dev_err(dev, "GPIO registering failed (%d)\n", err);
440 return err;
441 }
442
443 err = devm_request_irq(dev, irq[id], dio48e_irq_handler, 0, name,
444 dio48egpio);
445 if (err) {
446 dev_err(dev, "IRQ handler registering failed (%d)\n", err);
447 return err;
448 }
449
450 return 0;
451}
452
453static struct isa_driver dio48e_driver = {
454 .probe = dio48e_probe,
455 .driver = {
456 .name = "104-dio-48e"
457 },
458};
459module_isa_driver(dio48e_driver, num_dio48e);
460
461MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
462MODULE_DESCRIPTION("ACCES 104-DIO-48E GPIO driver");
463MODULE_LICENSE("GPL v2");