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1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2//
3// Copyright 2015 Freescale Semiconductor, Inc.
4// Copyright 2016 Toradex AG
5
6#include "imx7s.dtsi"
7#include <dt-bindings/reset/imx7-reset.h>
8
9/ {
10 cpus {
11 cpu0: cpu@0 {
12 clock-frequency = <996000000>;
13 operating-points-v2 = <&cpu0_opp_table>;
14 #cooling-cells = <2>;
15 nvmem-cells = <&fuse_grade>;
16 nvmem-cell-names = "speed_grade";
17 };
18
19 cpu1: cpu@1 {
20 compatible = "arm,cortex-a7";
21 device_type = "cpu";
22 reg = <1>;
23 clock-frequency = <996000000>;
24 operating-points-v2 = <&cpu0_opp_table>;
25 #cooling-cells = <2>;
26 cpu-idle-states = <&cpu_sleep_wait>;
27 };
28 };
29
30 timer {
31 compatible = "arm,armv7-timer";
32 interrupt-parent = <&intc>;
33 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
34 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
35 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
36 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
37 };
38
39 cpu0_opp_table: opp-table {
40 compatible = "operating-points-v2";
41 opp-shared;
42
43 opp-792000000 {
44 opp-hz = /bits/ 64 <792000000>;
45 opp-microvolt = <1000000>;
46 clock-latency-ns = <150000>;
47 opp-supported-hw = <0xd>, <0x7>;
48 opp-suspend;
49 };
50
51 opp-996000000 {
52 opp-hz = /bits/ 64 <996000000>;
53 opp-microvolt = <1100000>;
54 clock-latency-ns = <150000>;
55 opp-supported-hw = <0xc>, <0x7>;
56 opp-suspend;
57 };
58
59 opp-1200000000 {
60 opp-hz = /bits/ 64 <1200000000>;
61 opp-microvolt = <1225000>;
62 clock-latency-ns = <150000>;
63 opp-supported-hw = <0x8>, <0x3>;
64 opp-suspend;
65 };
66 };
67
68 usbphynop2: usbphynop2 {
69 compatible = "usb-nop-xceiv";
70 clocks = <&clks IMX7D_USB_PHY2_CLK>;
71 clock-names = "main_clk";
72 #phy-cells = <0>;
73 };
74
75 soc {
76 etm@3007d000 {
77 compatible = "arm,coresight-etm3x", "arm,primecell";
78 reg = <0x3007d000 0x1000>;
79
80 /*
81 * System will hang if added nosmp in kernel command line
82 * without arm,primecell-periphid because amba bus try to
83 * read id and core1 power off at this time.
84 */
85 arm,primecell-periphid = <0xbb956>;
86 cpu = <&cpu1>;
87 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
88 clock-names = "apb_pclk";
89
90 out-ports {
91 port {
92 etm1_out_port: endpoint {
93 remote-endpoint = <&ca_funnel_in_port1>;
94 };
95 };
96 };
97 };
98
99 intc: interrupt-controller@31001000 {
100 compatible = "arm,cortex-a7-gic";
101 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
102 #interrupt-cells = <3>;
103 interrupt-controller;
104 interrupt-parent = <&intc>;
105 reg = <0x31001000 0x1000>,
106 <0x31002000 0x2000>,
107 <0x31004000 0x2000>,
108 <0x31006000 0x2000>;
109 };
110 };
111};
112
113&aips2 {
114 pcie_phy: pcie-phy@306d0000 {
115 compatible = "fsl,imx7d-pcie-phy";
116 reg = <0x306d0000 0x10000>;
117 status = "disabled";
118 };
119};
120
121&aips3 {
122 usbotg2: usb@30b20000 {
123 compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
124 reg = <0x30b20000 0x200>;
125 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
126 clocks = <&clks IMX7D_USB_CTRL_CLK>;
127 fsl,usbphy = <&usbphynop2>;
128 fsl,usbmisc = <&usbmisc2 0>;
129 phy-clkgate-delay-us = <400>;
130 status = "disabled";
131 };
132
133 usbmisc2: usbmisc@30b20200 {
134 #index-cells = <1>;
135 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
136 reg = <0x30b20200 0x200>;
137 };
138
139 fec2: ethernet@30bf0000 {
140 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
141 reg = <0x30bf0000 0x10000>;
142 interrupt-names = "int0", "int1", "int2", "pps";
143 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
144 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
145 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
146 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
147 clocks = <&clks IMX7D_ENET2_IPG_ROOT_CLK>,
148 <&clks IMX7D_ENET_AXI_ROOT_CLK>,
149 <&clks IMX7D_ENET2_TIME_ROOT_CLK>,
150 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
151 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
152 clock-names = "ipg", "ahb", "ptp",
153 "enet_clk_ref", "enet_out";
154 fsl,num-tx-queues = <3>;
155 fsl,num-rx-queues = <3>;
156 fsl,stop-mode = <&gpr 0x10 4>;
157 status = "disabled";
158 };
159
160 pcie: pcie@33800000 {
161 compatible = "fsl,imx7d-pcie", "snps,dw-pcie";
162 reg = <0x33800000 0x4000>,
163 <0x4ff00000 0x80000>;
164 reg-names = "dbi", "config";
165 #address-cells = <3>;
166 #size-cells = <2>;
167 device_type = "pci";
168 bus-range = <0x00 0xff>;
169 ranges = <0x81000000 0 0 0x4ff80000 0 0x00010000 /* downstream I/O */
170 0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */
171 num-lanes = <1>;
172 num-viewport = <4>;
173 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
174 interrupt-names = "msi";
175 #interrupt-cells = <1>;
176 interrupt-map-mask = <0 0 0 0x7>;
177 /*
178 * Reference manual lists pci irqs incorrectly
179 * Real hardware ordering is same as imx6: D+MSI, C, B, A
180 */
181 interrupt-map = <0 0 0 1 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
182 <0 0 0 2 &intc GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
183 <0 0 0 3 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
184 <0 0 0 4 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
185 clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>,
186 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>,
187 <&clks IMX7D_PCIE_PHY_ROOT_CLK>;
188 clock-names = "pcie", "pcie_bus", "pcie_phy";
189 assigned-clocks = <&clks IMX7D_PCIE_CTRL_ROOT_SRC>,
190 <&clks IMX7D_PCIE_PHY_ROOT_SRC>;
191 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>,
192 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
193
194 fsl,max-link-speed = <2>;
195 power-domains = <&pgc_pcie_phy>;
196 resets = <&src IMX7_RESET_PCIEPHY>,
197 <&src IMX7_RESET_PCIE_CTRL_APPS_EN>,
198 <&src IMX7_RESET_PCIE_CTRL_APPS_TURNOFF>;
199 reset-names = "pciephy", "apps", "turnoff";
200 fsl,imx7d-pcie-phy = <&pcie_phy>;
201 status = "disabled";
202 };
203};
204
205&ca_funnel_in_ports {
206 #address-cells = <1>;
207 #size-cells = <0>;
208
209 port@1 {
210 reg = <1>;
211 ca_funnel_in_port1: endpoint {
212 remote-endpoint = <&etm1_out_port>;
213 };
214 };
215};