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1// SPDX-License-Identifier: GPL-2.0
2//
3// Copyright 2015 Freescale Semiconductor, Inc.
4
5#include <dt-bindings/clock/imx6ul-clock.h>
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/input/input.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include "imx6ul-pinfunc.h"
10
11/ {
12 #address-cells = <1>;
13 #size-cells = <1>;
14 /*
15 * The decompressor and also some bootloaders rely on a
16 * pre-existing /chosen node to be available to insert the
17 * command line and merge other ATAGS info.
18 */
19 chosen {};
20
21 aliases {
22 ethernet0 = &fec1;
23 ethernet1 = &fec2;
24 gpio0 = &gpio1;
25 gpio1 = &gpio2;
26 gpio2 = &gpio3;
27 gpio3 = &gpio4;
28 gpio4 = &gpio5;
29 i2c0 = &i2c1;
30 i2c1 = &i2c2;
31 i2c2 = &i2c3;
32 i2c3 = &i2c4;
33 mmc0 = &usdhc1;
34 mmc1 = &usdhc2;
35 serial0 = &uart1;
36 serial1 = &uart2;
37 serial2 = &uart3;
38 serial3 = &uart4;
39 serial4 = &uart5;
40 serial5 = &uart6;
41 serial6 = &uart7;
42 serial7 = &uart8;
43 sai1 = &sai1;
44 sai2 = &sai2;
45 sai3 = &sai3;
46 spi0 = &ecspi1;
47 spi1 = &ecspi2;
48 spi2 = &ecspi3;
49 spi3 = &ecspi4;
50 usbphy0 = &usbphy1;
51 usbphy1 = &usbphy2;
52 };
53
54 cpus {
55 #address-cells = <1>;
56 #size-cells = <0>;
57
58 cpu0: cpu@0 {
59 compatible = "arm,cortex-a7";
60 device_type = "cpu";
61 reg = <0>;
62 clock-frequency = <696000000>;
63 clock-latency = <61036>; /* two CLK32 periods */
64 #cooling-cells = <2>;
65 operating-points = <
66 /* kHz uV */
67 696000 1275000
68 528000 1175000
69 396000 1025000
70 198000 950000
71 >;
72 fsl,soc-operating-points = <
73 /* KHz uV */
74 696000 1275000
75 528000 1175000
76 396000 1175000
77 198000 1175000
78 >;
79 clocks = <&clks IMX6UL_CLK_ARM>,
80 <&clks IMX6UL_CLK_PLL2_BUS>,
81 <&clks IMX6UL_CLK_PLL2_PFD2>,
82 <&clks IMX6UL_CA7_SECONDARY_SEL>,
83 <&clks IMX6UL_CLK_STEP>,
84 <&clks IMX6UL_CLK_PLL1_SW>,
85 <&clks IMX6UL_CLK_PLL1_SYS>;
86 clock-names = "arm", "pll2_bus", "pll2_pfd2_396m",
87 "secondary_sel", "step", "pll1_sw",
88 "pll1_sys";
89 arm-supply = <®_arm>;
90 soc-supply = <®_soc>;
91 nvmem-cells = <&cpu_speed_grade>;
92 nvmem-cell-names = "speed_grade";
93 };
94 };
95
96 timer {
97 compatible = "arm,armv7-timer";
98 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
99 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
100 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
101 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
102 interrupt-parent = <&intc>;
103 status = "disabled";
104 };
105
106 ckil: clock-cli {
107 compatible = "fixed-clock";
108 #clock-cells = <0>;
109 clock-frequency = <32768>;
110 clock-output-names = "ckil";
111 };
112
113 osc: clock-osc {
114 compatible = "fixed-clock";
115 #clock-cells = <0>;
116 clock-frequency = <24000000>;
117 clock-output-names = "osc";
118 };
119
120 ipp_di0: clock-di0 {
121 compatible = "fixed-clock";
122 #clock-cells = <0>;
123 clock-frequency = <0>;
124 clock-output-names = "ipp_di0";
125 };
126
127 ipp_di1: clock-di1 {
128 compatible = "fixed-clock";
129 #clock-cells = <0>;
130 clock-frequency = <0>;
131 clock-output-names = "ipp_di1";
132 };
133
134 pmu {
135 compatible = "arm,cortex-a7-pmu";
136 interrupt-parent = <&gpc>;
137 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
138 };
139
140 soc {
141 #address-cells = <1>;
142 #size-cells = <1>;
143 compatible = "simple-bus";
144 interrupt-parent = <&gpc>;
145 ranges;
146
147 ocram: sram@900000 {
148 compatible = "mmio-sram";
149 reg = <0x00900000 0x20000>;
150 };
151
152 intc: interrupt-controller@a01000 {
153 compatible = "arm,gic-400", "arm,cortex-a7-gic";
154 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
155 #interrupt-cells = <3>;
156 interrupt-controller;
157 interrupt-parent = <&intc>;
158 reg = <0x00a01000 0x1000>,
159 <0x00a02000 0x2000>,
160 <0x00a04000 0x2000>,
161 <0x00a06000 0x2000>;
162 };
163
164 dma_apbh: dma-apbh@1804000 {
165 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
166 reg = <0x01804000 0x2000>;
167 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
168 <0 13 IRQ_TYPE_LEVEL_HIGH>,
169 <0 13 IRQ_TYPE_LEVEL_HIGH>,
170 <0 13 IRQ_TYPE_LEVEL_HIGH>;
171 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
172 #dma-cells = <1>;
173 dma-channels = <4>;
174 clocks = <&clks IMX6UL_CLK_APBHDMA>;
175 };
176
177 gpmi: gpmi-nand@1806000 {
178 compatible = "fsl,imx6q-gpmi-nand";
179 #address-cells = <1>;
180 #size-cells = <1>;
181 reg = <0x01806000 0x2000>, <0x01808000 0x2000>;
182 reg-names = "gpmi-nand", "bch";
183 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
184 interrupt-names = "bch";
185 clocks = <&clks IMX6UL_CLK_GPMI_IO>,
186 <&clks IMX6UL_CLK_GPMI_APB>,
187 <&clks IMX6UL_CLK_GPMI_BCH>,
188 <&clks IMX6UL_CLK_GPMI_BCH_APB>,
189 <&clks IMX6UL_CLK_PER_BCH>;
190 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
191 "gpmi_bch_apb", "per1_bch";
192 dmas = <&dma_apbh 0>;
193 dma-names = "rx-tx";
194 status = "disabled";
195 };
196
197 aips1: bus@2000000 {
198 compatible = "fsl,aips-bus", "simple-bus";
199 #address-cells = <1>;
200 #size-cells = <1>;
201 reg = <0x02000000 0x100000>;
202 ranges;
203
204 spba-bus@2000000 {
205 compatible = "fsl,spba-bus", "simple-bus";
206 #address-cells = <1>;
207 #size-cells = <1>;
208 reg = <0x02000000 0x40000>;
209 ranges;
210
211 ecspi1: spi@2008000 {
212 #address-cells = <1>;
213 #size-cells = <0>;
214 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
215 reg = <0x02008000 0x4000>;
216 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
217 clocks = <&clks IMX6UL_CLK_ECSPI1>,
218 <&clks IMX6UL_CLK_ECSPI1>;
219 clock-names = "ipg", "per";
220 dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
221 dma-names = "rx", "tx";
222 status = "disabled";
223 };
224
225 ecspi2: spi@200c000 {
226 #address-cells = <1>;
227 #size-cells = <0>;
228 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
229 reg = <0x0200c000 0x4000>;
230 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
231 clocks = <&clks IMX6UL_CLK_ECSPI2>,
232 <&clks IMX6UL_CLK_ECSPI2>;
233 clock-names = "ipg", "per";
234 dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
235 dma-names = "rx", "tx";
236 status = "disabled";
237 };
238
239 ecspi3: spi@2010000 {
240 #address-cells = <1>;
241 #size-cells = <0>;
242 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
243 reg = <0x02010000 0x4000>;
244 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
245 clocks = <&clks IMX6UL_CLK_ECSPI3>,
246 <&clks IMX6UL_CLK_ECSPI3>;
247 clock-names = "ipg", "per";
248 dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
249 dma-names = "rx", "tx";
250 status = "disabled";
251 };
252
253 ecspi4: spi@2014000 {
254 #address-cells = <1>;
255 #size-cells = <0>;
256 compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
257 reg = <0x02014000 0x4000>;
258 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
259 clocks = <&clks IMX6UL_CLK_ECSPI4>,
260 <&clks IMX6UL_CLK_ECSPI4>;
261 clock-names = "ipg", "per";
262 dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
263 dma-names = "rx", "tx";
264 status = "disabled";
265 };
266
267 uart7: serial@2018000 {
268 compatible = "fsl,imx6ul-uart",
269 "fsl,imx6q-uart";
270 reg = <0x02018000 0x4000>;
271 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
272 clocks = <&clks IMX6UL_CLK_UART7_IPG>,
273 <&clks IMX6UL_CLK_UART7_SERIAL>;
274 clock-names = "ipg", "per";
275 status = "disabled";
276 };
277
278 uart1: serial@2020000 {
279 compatible = "fsl,imx6ul-uart",
280 "fsl,imx6q-uart";
281 reg = <0x02020000 0x4000>;
282 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
283 clocks = <&clks IMX6UL_CLK_UART1_IPG>,
284 <&clks IMX6UL_CLK_UART1_SERIAL>;
285 clock-names = "ipg", "per";
286 status = "disabled";
287 };
288
289 uart8: serial@2024000 {
290 compatible = "fsl,imx6ul-uart",
291 "fsl,imx6q-uart";
292 reg = <0x02024000 0x4000>;
293 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
294 clocks = <&clks IMX6UL_CLK_UART8_IPG>,
295 <&clks IMX6UL_CLK_UART8_SERIAL>;
296 clock-names = "ipg", "per";
297 status = "disabled";
298 };
299
300 sai1: sai@2028000 {
301 #sound-dai-cells = <0>;
302 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
303 reg = <0x02028000 0x4000>;
304 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
305 clocks = <&clks IMX6UL_CLK_SAI1_IPG>,
306 <&clks IMX6UL_CLK_SAI1>,
307 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
308 clock-names = "bus", "mclk1", "mclk2", "mclk3";
309 dmas = <&sdma 35 24 0>,
310 <&sdma 36 24 0>;
311 dma-names = "rx", "tx";
312 status = "disabled";
313 };
314
315 sai2: sai@202c000 {
316 #sound-dai-cells = <0>;
317 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
318 reg = <0x0202c000 0x4000>;
319 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
320 clocks = <&clks IMX6UL_CLK_SAI2_IPG>,
321 <&clks IMX6UL_CLK_SAI2>,
322 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
323 clock-names = "bus", "mclk1", "mclk2", "mclk3";
324 dmas = <&sdma 37 24 0>,
325 <&sdma 38 24 0>;
326 dma-names = "rx", "tx";
327 status = "disabled";
328 };
329
330 sai3: sai@2030000 {
331 #sound-dai-cells = <0>;
332 compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
333 reg = <0x02030000 0x4000>;
334 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
335 clocks = <&clks IMX6UL_CLK_SAI3_IPG>,
336 <&clks IMX6UL_CLK_SAI3>,
337 <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
338 clock-names = "bus", "mclk1", "mclk2", "mclk3";
339 dmas = <&sdma 39 24 0>,
340 <&sdma 40 24 0>;
341 dma-names = "rx", "tx";
342 status = "disabled";
343 };
344
345 asrc: asrc@2034000 {
346 compatible = "fsl,imx6ul-asrc", "fsl,imx53-asrc";
347 reg = <0x2034000 0x4000>;
348 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
349 clocks = <&clks IMX6UL_CLK_ASRC_IPG>,
350 <&clks IMX6UL_CLK_ASRC_MEM>, <&clks 0>,
351 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
352 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
353 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
354 <&clks IMX6UL_CLK_SPDIF>, <&clks 0>, <&clks 0>,
355 <&clks IMX6UL_CLK_SPBA>;
356 clock-names = "mem", "ipg", "asrck_0",
357 "asrck_1", "asrck_2", "asrck_3", "asrck_4",
358 "asrck_5", "asrck_6", "asrck_7", "asrck_8",
359 "asrck_9", "asrck_a", "asrck_b", "asrck_c",
360 "asrck_d", "asrck_e", "asrck_f", "spba";
361 dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
362 <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
363 dma-names = "rxa", "rxb", "rxc",
364 "txa", "txb", "txc";
365 fsl,asrc-rate = <48000>;
366 fsl,asrc-width = <16>;
367 status = "okay";
368 };
369 };
370
371 tsc: tsc@2040000 {
372 compatible = "fsl,imx6ul-tsc";
373 reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
374 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
375 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
376 clocks = <&clks IMX6UL_CLK_IPG>,
377 <&clks IMX6UL_CLK_ADC2>;
378 clock-names = "tsc", "adc";
379 status = "disabled";
380 };
381
382 pwm1: pwm@2080000 {
383 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
384 reg = <0x02080000 0x4000>;
385 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
386 clocks = <&clks IMX6UL_CLK_PWM1>,
387 <&clks IMX6UL_CLK_PWM1>;
388 clock-names = "ipg", "per";
389 #pwm-cells = <3>;
390 status = "disabled";
391 };
392
393 pwm2: pwm@2084000 {
394 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
395 reg = <0x02084000 0x4000>;
396 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
397 clocks = <&clks IMX6UL_CLK_PWM2>,
398 <&clks IMX6UL_CLK_PWM2>;
399 clock-names = "ipg", "per";
400 #pwm-cells = <3>;
401 status = "disabled";
402 };
403
404 pwm3: pwm@2088000 {
405 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
406 reg = <0x02088000 0x4000>;
407 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
408 clocks = <&clks IMX6UL_CLK_PWM3>,
409 <&clks IMX6UL_CLK_PWM3>;
410 clock-names = "ipg", "per";
411 #pwm-cells = <3>;
412 status = "disabled";
413 };
414
415 pwm4: pwm@208c000 {
416 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
417 reg = <0x0208c000 0x4000>;
418 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
419 clocks = <&clks IMX6UL_CLK_PWM4>,
420 <&clks IMX6UL_CLK_PWM4>;
421 clock-names = "ipg", "per";
422 #pwm-cells = <3>;
423 status = "disabled";
424 };
425
426 can1: flexcan@2090000 {
427 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
428 reg = <0x02090000 0x4000>;
429 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
430 clocks = <&clks IMX6UL_CLK_CAN1_IPG>,
431 <&clks IMX6UL_CLK_CAN1_SERIAL>;
432 clock-names = "ipg", "per";
433 fsl,stop-mode = <&gpr 0x10 1 0x10 17>;
434 status = "disabled";
435 };
436
437 can2: flexcan@2094000 {
438 compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
439 reg = <0x02094000 0x4000>;
440 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
441 clocks = <&clks IMX6UL_CLK_CAN2_IPG>,
442 <&clks IMX6UL_CLK_CAN2_SERIAL>;
443 clock-names = "ipg", "per";
444 fsl,stop-mode = <&gpr 0x10 2 0x10 18>;
445 status = "disabled";
446 };
447
448 gpt1: timer@2098000 {
449 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
450 reg = <0x02098000 0x4000>;
451 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
452 clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
453 <&clks IMX6UL_CLK_GPT1_SERIAL>;
454 clock-names = "ipg", "per";
455 };
456
457 gpio1: gpio@209c000 {
458 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
459 reg = <0x0209c000 0x4000>;
460 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
461 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
462 clocks = <&clks IMX6UL_CLK_GPIO1>;
463 gpio-controller;
464 #gpio-cells = <2>;
465 interrupt-controller;
466 #interrupt-cells = <2>;
467 gpio-ranges = <&iomuxc 0 23 10>, <&iomuxc 10 17 6>,
468 <&iomuxc 16 33 16>;
469 };
470
471 gpio2: gpio@20a0000 {
472 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
473 reg = <0x020a0000 0x4000>;
474 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
475 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
476 clocks = <&clks IMX6UL_CLK_GPIO2>;
477 gpio-controller;
478 #gpio-cells = <2>;
479 interrupt-controller;
480 #interrupt-cells = <2>;
481 gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>;
482 };
483
484 gpio3: gpio@20a4000 {
485 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
486 reg = <0x020a4000 0x4000>;
487 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
488 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
489 clocks = <&clks IMX6UL_CLK_GPIO3>;
490 gpio-controller;
491 #gpio-cells = <2>;
492 interrupt-controller;
493 #interrupt-cells = <2>;
494 gpio-ranges = <&iomuxc 0 65 29>;
495 };
496
497 gpio4: gpio@20a8000 {
498 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
499 reg = <0x020a8000 0x4000>;
500 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
501 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
502 clocks = <&clks IMX6UL_CLK_GPIO4>;
503 gpio-controller;
504 #gpio-cells = <2>;
505 interrupt-controller;
506 #interrupt-cells = <2>;
507 gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>;
508 };
509
510 gpio5: gpio@20ac000 {
511 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
512 reg = <0x020ac000 0x4000>;
513 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
514 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
515 clocks = <&clks IMX6UL_CLK_GPIO5>;
516 gpio-controller;
517 #gpio-cells = <2>;
518 interrupt-controller;
519 #interrupt-cells = <2>;
520 gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>;
521 };
522
523 fec2: ethernet@20b4000 {
524 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
525 reg = <0x020b4000 0x4000>;
526 interrupt-names = "int0", "pps";
527 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
528 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
529 clocks = <&clks IMX6UL_CLK_ENET>,
530 <&clks IMX6UL_CLK_ENET_AHB>,
531 <&clks IMX6UL_CLK_ENET_PTP>,
532 <&clks IMX6UL_CLK_ENET2_REF_125M>,
533 <&clks IMX6UL_CLK_ENET2_REF_125M>;
534 clock-names = "ipg", "ahb", "ptp",
535 "enet_clk_ref", "enet_out";
536 fsl,num-tx-queues = <1>;
537 fsl,num-rx-queues = <1>;
538 fsl,stop-mode = <&gpr 0x10 4>;
539 status = "disabled";
540 };
541
542 kpp: keypad@20b8000 {
543 compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp";
544 reg = <0x020b8000 0x4000>;
545 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
546 clocks = <&clks IMX6UL_CLK_KPP>;
547 status = "disabled";
548 };
549
550 wdog1: watchdog@20bc000 {
551 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
552 reg = <0x020bc000 0x4000>;
553 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
554 clocks = <&clks IMX6UL_CLK_WDOG1>;
555 };
556
557 wdog2: watchdog@20c0000 {
558 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
559 reg = <0x020c0000 0x4000>;
560 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
561 clocks = <&clks IMX6UL_CLK_WDOG2>;
562 status = "disabled";
563 };
564
565 clks: clock-controller@20c4000 {
566 compatible = "fsl,imx6ul-ccm";
567 reg = <0x020c4000 0x4000>;
568 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
569 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
570 #clock-cells = <1>;
571 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
572 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
573 };
574
575 anatop: anatop@20c8000 {
576 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
577 "syscon", "simple-mfd";
578 reg = <0x020c8000 0x1000>;
579 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
580 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
581 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
582
583 reg_3p0: regulator-3p0 {
584 compatible = "fsl,anatop-regulator";
585 regulator-name = "vdd3p0";
586 regulator-min-microvolt = <2625000>;
587 regulator-max-microvolt = <3400000>;
588 anatop-reg-offset = <0x120>;
589 anatop-vol-bit-shift = <8>;
590 anatop-vol-bit-width = <5>;
591 anatop-min-bit-val = <0>;
592 anatop-min-voltage = <2625000>;
593 anatop-max-voltage = <3400000>;
594 anatop-enable-bit = <0>;
595 };
596
597 reg_arm: regulator-vddcore {
598 compatible = "fsl,anatop-regulator";
599 regulator-name = "cpu";
600 regulator-min-microvolt = <725000>;
601 regulator-max-microvolt = <1450000>;
602 regulator-always-on;
603 anatop-reg-offset = <0x140>;
604 anatop-vol-bit-shift = <0>;
605 anatop-vol-bit-width = <5>;
606 anatop-delay-reg-offset = <0x170>;
607 anatop-delay-bit-shift = <24>;
608 anatop-delay-bit-width = <2>;
609 anatop-min-bit-val = <1>;
610 anatop-min-voltage = <725000>;
611 anatop-max-voltage = <1450000>;
612 };
613
614 reg_soc: regulator-vddsoc {
615 compatible = "fsl,anatop-regulator";
616 regulator-name = "vddsoc";
617 regulator-min-microvolt = <725000>;
618 regulator-max-microvolt = <1450000>;
619 regulator-always-on;
620 anatop-reg-offset = <0x140>;
621 anatop-vol-bit-shift = <18>;
622 anatop-vol-bit-width = <5>;
623 anatop-delay-reg-offset = <0x170>;
624 anatop-delay-bit-shift = <28>;
625 anatop-delay-bit-width = <2>;
626 anatop-min-bit-val = <1>;
627 anatop-min-voltage = <725000>;
628 anatop-max-voltage = <1450000>;
629 };
630
631 tempmon: tempmon {
632 compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon";
633 interrupt-parent = <&gpc>;
634 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
635 fsl,tempmon = <&anatop>;
636 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
637 nvmem-cell-names = "calib", "temp_grade";
638 clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;
639 };
640 };
641
642 usbphy1: usbphy@20c9000 {
643 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
644 reg = <0x020c9000 0x1000>;
645 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
646 clocks = <&clks IMX6UL_CLK_USBPHY1>;
647 phy-3p0-supply = <®_3p0>;
648 fsl,anatop = <&anatop>;
649 };
650
651 usbphy2: usbphy@20ca000 {
652 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
653 reg = <0x020ca000 0x1000>;
654 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
655 clocks = <&clks IMX6UL_CLK_USBPHY2>;
656 phy-3p0-supply = <®_3p0>;
657 fsl,anatop = <&anatop>;
658 };
659
660 snvs: snvs@20cc000 {
661 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
662 reg = <0x020cc000 0x4000>;
663
664 snvs_rtc: snvs-rtc-lp {
665 compatible = "fsl,sec-v4.0-mon-rtc-lp";
666 regmap = <&snvs>;
667 offset = <0x34>;
668 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
669 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
670 };
671
672 snvs_poweroff: snvs-poweroff {
673 compatible = "syscon-poweroff";
674 regmap = <&snvs>;
675 offset = <0x38>;
676 value = <0x60>;
677 mask = <0x60>;
678 status = "disabled";
679 };
680
681 snvs_pwrkey: snvs-powerkey {
682 compatible = "fsl,sec-v4.0-pwrkey";
683 regmap = <&snvs>;
684 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
685 linux,keycode = <KEY_POWER>;
686 wakeup-source;
687 status = "disabled";
688 };
689
690 snvs_lpgpr: snvs-lpgpr {
691 compatible = "fsl,imx6ul-snvs-lpgpr";
692 };
693 };
694
695 epit1: epit@20d0000 {
696 reg = <0x020d0000 0x4000>;
697 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
698 };
699
700 epit2: epit@20d4000 {
701 reg = <0x020d4000 0x4000>;
702 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
703 };
704
705 src: reset-controller@20d8000 {
706 compatible = "fsl,imx6ul-src", "fsl,imx51-src";
707 reg = <0x020d8000 0x4000>;
708 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
709 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
710 #reset-cells = <1>;
711 };
712
713 gpc: gpc@20dc000 {
714 compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
715 reg = <0x020dc000 0x4000>;
716 interrupt-controller;
717 #interrupt-cells = <3>;
718 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
719 interrupt-parent = <&intc>;
720 };
721
722 iomuxc: pinctrl@20e0000 {
723 compatible = "fsl,imx6ul-iomuxc";
724 reg = <0x020e0000 0x4000>;
725 };
726
727 gpr: iomuxc-gpr@20e4000 {
728 compatible = "fsl,imx6ul-iomuxc-gpr",
729 "fsl,imx6q-iomuxc-gpr", "syscon";
730 reg = <0x020e4000 0x4000>;
731 };
732
733 gpt2: timer@20e8000 {
734 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
735 reg = <0x020e8000 0x4000>;
736 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
737 clocks = <&clks IMX6UL_CLK_GPT2_BUS>,
738 <&clks IMX6UL_CLK_GPT2_SERIAL>;
739 clock-names = "ipg", "per";
740 status = "disabled";
741 };
742
743 sdma: sdma@20ec000 {
744 compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma",
745 "fsl,imx35-sdma";
746 reg = <0x020ec000 0x4000>;
747 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
748 clocks = <&clks IMX6UL_CLK_IPG>,
749 <&clks IMX6UL_CLK_SDMA>;
750 clock-names = "ipg", "ahb";
751 #dma-cells = <3>;
752 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
753 };
754
755 pwm5: pwm@20f0000 {
756 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
757 reg = <0x020f0000 0x4000>;
758 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
759 clocks = <&clks IMX6UL_CLK_PWM5>,
760 <&clks IMX6UL_CLK_PWM5>;
761 clock-names = "ipg", "per";
762 #pwm-cells = <3>;
763 status = "disabled";
764 };
765
766 pwm6: pwm@20f4000 {
767 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
768 reg = <0x020f4000 0x4000>;
769 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
770 clocks = <&clks IMX6UL_CLK_PWM6>,
771 <&clks IMX6UL_CLK_PWM6>;
772 clock-names = "ipg", "per";
773 #pwm-cells = <3>;
774 status = "disabled";
775 };
776
777 pwm7: pwm@20f8000 {
778 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
779 reg = <0x020f8000 0x4000>;
780 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
781 clocks = <&clks IMX6UL_CLK_PWM7>,
782 <&clks IMX6UL_CLK_PWM7>;
783 clock-names = "ipg", "per";
784 #pwm-cells = <3>;
785 status = "disabled";
786 };
787
788 pwm8: pwm@20fc000 {
789 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
790 reg = <0x020fc000 0x4000>;
791 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
792 clocks = <&clks IMX6UL_CLK_PWM8>,
793 <&clks IMX6UL_CLK_PWM8>;
794 clock-names = "ipg", "per";
795 #pwm-cells = <3>;
796 status = "disabled";
797 };
798 };
799
800 aips2: bus@2100000 {
801 compatible = "fsl,aips-bus", "simple-bus";
802 #address-cells = <1>;
803 #size-cells = <1>;
804 reg = <0x02100000 0x100000>;
805 ranges;
806
807 crypto: crypto@2140000 {
808 compatible = "fsl,imx6ul-caam", "fsl,sec-v4.0";
809 #address-cells = <1>;
810 #size-cells = <1>;
811 reg = <0x2140000 0x3c000>;
812 ranges = <0 0x2140000 0x3c000>;
813 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
814 clocks = <&clks IMX6UL_CLK_CAAM_IPG>, <&clks IMX6UL_CLK_CAAM_ACLK>,
815 <&clks IMX6UL_CLK_CAAM_MEM>;
816 clock-names = "ipg", "aclk", "mem";
817
818 sec_jr0: jr@1000 {
819 compatible = "fsl,sec-v4.0-job-ring";
820 reg = <0x1000 0x1000>;
821 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
822 };
823
824 sec_jr1: jr@2000 {
825 compatible = "fsl,sec-v4.0-job-ring";
826 reg = <0x2000 0x1000>;
827 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
828 };
829
830 sec_jr2: jr@3000 {
831 compatible = "fsl,sec-v4.0-job-ring";
832 reg = <0x3000 0x1000>;
833 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
834 };
835 };
836
837 usbotg1: usb@2184000 {
838 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
839 reg = <0x02184000 0x200>;
840 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
841 clocks = <&clks IMX6UL_CLK_USBOH3>;
842 fsl,usbphy = <&usbphy1>;
843 fsl,usbmisc = <&usbmisc 0>;
844 fsl,anatop = <&anatop>;
845 ahb-burst-config = <0x0>;
846 tx-burst-size-dword = <0x10>;
847 rx-burst-size-dword = <0x10>;
848 status = "disabled";
849 };
850
851 usbotg2: usb@2184200 {
852 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
853 reg = <0x02184200 0x200>;
854 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
855 clocks = <&clks IMX6UL_CLK_USBOH3>;
856 fsl,usbphy = <&usbphy2>;
857 fsl,usbmisc = <&usbmisc 1>;
858 ahb-burst-config = <0x0>;
859 tx-burst-size-dword = <0x10>;
860 rx-burst-size-dword = <0x10>;
861 status = "disabled";
862 };
863
864 usbmisc: usbmisc@2184800 {
865 #index-cells = <1>;
866 compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
867 reg = <0x02184800 0x200>;
868 };
869
870 fec1: ethernet@2188000 {
871 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
872 reg = <0x02188000 0x4000>;
873 interrupt-names = "int0", "pps";
874 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
875 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
876 clocks = <&clks IMX6UL_CLK_ENET>,
877 <&clks IMX6UL_CLK_ENET_AHB>,
878 <&clks IMX6UL_CLK_ENET_PTP>,
879 <&clks IMX6UL_CLK_ENET_REF>,
880 <&clks IMX6UL_CLK_ENET_REF>;
881 clock-names = "ipg", "ahb", "ptp",
882 "enet_clk_ref", "enet_out";
883 fsl,num-tx-queues = <1>;
884 fsl,num-rx-queues = <1>;
885 fsl,stop-mode = <&gpr 0x10 3>;
886 status = "disabled";
887 };
888
889 usdhc1: mmc@2190000 {
890 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
891 reg = <0x02190000 0x4000>;
892 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
893 clocks = <&clks IMX6UL_CLK_USDHC1>,
894 <&clks IMX6UL_CLK_USDHC1>,
895 <&clks IMX6UL_CLK_USDHC1>;
896 clock-names = "ipg", "ahb", "per";
897 fsl,tuning-step = <2>;
898 fsl,tuning-start-tap = <20>;
899 bus-width = <4>;
900 status = "disabled";
901 };
902
903 usdhc2: mmc@2194000 {
904 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
905 reg = <0x02194000 0x4000>;
906 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
907 clocks = <&clks IMX6UL_CLK_USDHC2>,
908 <&clks IMX6UL_CLK_USDHC2>,
909 <&clks IMX6UL_CLK_USDHC2>;
910 clock-names = "ipg", "ahb", "per";
911 bus-width = <4>;
912 fsl,tuning-step = <2>;
913 fsl,tuning-start-tap = <20>;
914 status = "disabled";
915 };
916
917 adc1: adc@2198000 {
918 compatible = "fsl,imx6ul-adc", "fsl,vf610-adc";
919 reg = <0x02198000 0x4000>;
920 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
921 clocks = <&clks IMX6UL_CLK_ADC1>;
922 num-channels = <2>;
923 clock-names = "adc";
924 fsl,adck-max-frequency = <30000000>, <40000000>,
925 <20000000>;
926 status = "disabled";
927 };
928
929 i2c1: i2c@21a0000 {
930 #address-cells = <1>;
931 #size-cells = <0>;
932 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
933 reg = <0x021a0000 0x4000>;
934 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
935 clocks = <&clks IMX6UL_CLK_I2C1>;
936 status = "disabled";
937 };
938
939 i2c2: i2c@21a4000 {
940 #address-cells = <1>;
941 #size-cells = <0>;
942 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
943 reg = <0x021a4000 0x4000>;
944 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
945 clocks = <&clks IMX6UL_CLK_I2C2>;
946 status = "disabled";
947 };
948
949 i2c3: i2c@21a8000 {
950 #address-cells = <1>;
951 #size-cells = <0>;
952 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
953 reg = <0x021a8000 0x4000>;
954 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
955 clocks = <&clks IMX6UL_CLK_I2C3>;
956 status = "disabled";
957 };
958
959 memory-controller@21b0000 {
960 compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
961 reg = <0x021b0000 0x4000>;
962 clocks = <&clks IMX6UL_CLK_MMDC_P0_IPG>;
963 };
964
965 weim: weim@21b8000 {
966 #address-cells = <2>;
967 #size-cells = <1>;
968 compatible = "fsl,imx6ul-weim", "fsl,imx6q-weim";
969 reg = <0x021b8000 0x4000>;
970 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
971 clocks = <&clks IMX6UL_CLK_EIM>;
972 fsl,weim-cs-gpr = <&gpr>;
973 status = "disabled";
974 };
975
976 ocotp: efuse@21bc000 {
977 #address-cells = <1>;
978 #size-cells = <1>;
979 compatible = "fsl,imx6ul-ocotp", "syscon";
980 reg = <0x021bc000 0x4000>;
981 clocks = <&clks IMX6UL_CLK_OCOTP>;
982
983 tempmon_calib: calib@38 {
984 reg = <0x38 4>;
985 };
986
987 tempmon_temp_grade: temp-grade@20 {
988 reg = <0x20 4>;
989 };
990
991 cpu_speed_grade: speed-grade@10 {
992 reg = <0x10 4>;
993 };
994 };
995
996 csi: csi@21c4000 {
997 compatible = "fsl,imx6ul-csi", "fsl,imx7-csi";
998 reg = <0x021c4000 0x4000>;
999 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1000 clocks = <&clks IMX6UL_CLK_CSI>;
1001 clock-names = "mclk";
1002 status = "disabled";
1003 };
1004
1005 lcdif: lcdif@21c8000 {
1006 compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
1007 reg = <0x021c8000 0x4000>;
1008 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1009 clocks = <&clks IMX6UL_CLK_LCDIF_PIX>,
1010 <&clks IMX6UL_CLK_LCDIF_APB>,
1011 <&clks IMX6UL_CLK_DUMMY>;
1012 clock-names = "pix", "axi", "disp_axi";
1013 status = "disabled";
1014 };
1015
1016 pxp: pxp@21cc000 {
1017 compatible = "fsl,imx6ul-pxp";
1018 reg = <0x021cc000 0x4000>;
1019 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1020 clocks = <&clks IMX6UL_CLK_PXP>;
1021 clock-names = "axi";
1022 };
1023
1024 qspi: spi@21e0000 {
1025 #address-cells = <1>;
1026 #size-cells = <0>;
1027 compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
1028 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
1029 reg-names = "QuadSPI", "QuadSPI-memory";
1030 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1031 clocks = <&clks IMX6UL_CLK_QSPI>,
1032 <&clks IMX6UL_CLK_QSPI>;
1033 clock-names = "qspi_en", "qspi";
1034 status = "disabled";
1035 };
1036
1037 wdog3: watchdog@21e4000 {
1038 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
1039 reg = <0x021e4000 0x4000>;
1040 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1041 clocks = <&clks IMX6UL_CLK_WDOG3>;
1042 status = "disabled";
1043 };
1044
1045 uart2: serial@21e8000 {
1046 compatible = "fsl,imx6ul-uart",
1047 "fsl,imx6q-uart";
1048 reg = <0x021e8000 0x4000>;
1049 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1050 clocks = <&clks IMX6UL_CLK_UART2_IPG>,
1051 <&clks IMX6UL_CLK_UART2_SERIAL>;
1052 clock-names = "ipg", "per";
1053 status = "disabled";
1054 };
1055
1056 uart3: serial@21ec000 {
1057 compatible = "fsl,imx6ul-uart",
1058 "fsl,imx6q-uart";
1059 reg = <0x021ec000 0x4000>;
1060 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1061 clocks = <&clks IMX6UL_CLK_UART3_IPG>,
1062 <&clks IMX6UL_CLK_UART3_SERIAL>;
1063 clock-names = "ipg", "per";
1064 status = "disabled";
1065 };
1066
1067 uart4: serial@21f0000 {
1068 compatible = "fsl,imx6ul-uart",
1069 "fsl,imx6q-uart";
1070 reg = <0x021f0000 0x4000>;
1071 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1072 clocks = <&clks IMX6UL_CLK_UART4_IPG>,
1073 <&clks IMX6UL_CLK_UART4_SERIAL>;
1074 clock-names = "ipg", "per";
1075 status = "disabled";
1076 };
1077
1078 uart5: serial@21f4000 {
1079 compatible = "fsl,imx6ul-uart",
1080 "fsl,imx6q-uart";
1081 reg = <0x021f4000 0x4000>;
1082 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1083 clocks = <&clks IMX6UL_CLK_UART5_IPG>,
1084 <&clks IMX6UL_CLK_UART5_SERIAL>;
1085 clock-names = "ipg", "per";
1086 status = "disabled";
1087 };
1088
1089 i2c4: i2c@21f8000 {
1090 #address-cells = <1>;
1091 #size-cells = <0>;
1092 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
1093 reg = <0x021f8000 0x4000>;
1094 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1095 clocks = <&clks IMX6UL_CLK_I2C4>;
1096 status = "disabled";
1097 };
1098
1099 uart6: serial@21fc000 {
1100 compatible = "fsl,imx6ul-uart",
1101 "fsl,imx6q-uart";
1102 reg = <0x021fc000 0x4000>;
1103 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1104 clocks = <&clks IMX6UL_CLK_UART6_IPG>,
1105 <&clks IMX6UL_CLK_UART6_SERIAL>;
1106 clock-names = "ipg", "per";
1107 status = "disabled";
1108 };
1109 };
1110 };
1111};