Loading...
Note: File does not exist in v6.13.7.
1// SPDX-License-Identifier: GPL-2.0
2//
3// Copyright 2013 Freescale Semiconductor, Inc.
4
5#include <dt-bindings/interrupt-controller/irq.h>
6#include "imx6dl-pinfunc.h"
7#include "imx6qdl.dtsi"
8
9/ {
10 aliases {
11 i2c3 = &i2c4;
12 };
13
14 cpus {
15 #address-cells = <1>;
16 #size-cells = <0>;
17
18 cpu0: cpu@0 {
19 compatible = "arm,cortex-a9";
20 device_type = "cpu";
21 reg = <0>;
22 next-level-cache = <&L2>;
23 operating-points = <
24 /* kHz uV */
25 996000 1250000
26 792000 1175000
27 396000 1150000
28 >;
29 fsl,soc-operating-points = <
30 /* ARM kHz SOC-PU uV */
31 996000 1175000
32 792000 1175000
33 396000 1175000
34 >;
35 clock-latency = <61036>; /* two CLK32 periods */
36 #cooling-cells = <2>;
37 clocks = <&clks IMX6QDL_CLK_ARM>,
38 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
39 <&clks IMX6QDL_CLK_STEP>,
40 <&clks IMX6QDL_CLK_PLL1_SW>,
41 <&clks IMX6QDL_CLK_PLL1_SYS>;
42 clock-names = "arm", "pll2_pfd2_396m", "step",
43 "pll1_sw", "pll1_sys";
44 arm-supply = <®_arm>;
45 pu-supply = <®_pu>;
46 soc-supply = <®_soc>;
47 nvmem-cells = <&cpu_speed_grade>;
48 nvmem-cell-names = "speed_grade";
49 };
50
51 cpu@1 {
52 compatible = "arm,cortex-a9";
53 device_type = "cpu";
54 reg = <1>;
55 next-level-cache = <&L2>;
56 operating-points = <
57 /* kHz uV */
58 996000 1250000
59 792000 1175000
60 396000 1150000
61 >;
62 fsl,soc-operating-points = <
63 /* ARM kHz SOC-PU uV */
64 996000 1175000
65 792000 1175000
66 396000 1175000
67 >;
68 clock-latency = <61036>; /* two CLK32 periods */
69 #cooling-cells = <2>;
70 clocks = <&clks IMX6QDL_CLK_ARM>,
71 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
72 <&clks IMX6QDL_CLK_STEP>,
73 <&clks IMX6QDL_CLK_PLL1_SW>,
74 <&clks IMX6QDL_CLK_PLL1_SYS>;
75 clock-names = "arm", "pll2_pfd2_396m", "step",
76 "pll1_sw", "pll1_sys";
77 arm-supply = <®_arm>;
78 pu-supply = <®_pu>;
79 soc-supply = <®_soc>;
80 };
81 };
82
83 soc {
84 ocram: sram@900000 {
85 compatible = "mmio-sram";
86 reg = <0x00900000 0x20000>;
87 clocks = <&clks IMX6QDL_CLK_OCRAM>;
88 };
89
90 aips1: bus@2000000 {
91 iomuxc: pinctrl@20e0000 {
92 compatible = "fsl,imx6dl-iomuxc";
93 };
94
95 pxp: pxp@20f0000 {
96 reg = <0x020f0000 0x4000>;
97 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
98 };
99
100 epdc: epdc@20f4000 {
101 reg = <0x020f4000 0x4000>;
102 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
103 };
104 };
105
106 aips2: bus@2100000 {
107 i2c4: i2c@21f8000 {
108 #address-cells = <1>;
109 #size-cells = <0>;
110 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
111 reg = <0x021f8000 0x4000>;
112 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
113 clocks = <&clks IMX6DL_CLK_I2C4>;
114 status = "disabled";
115 };
116 };
117 };
118
119 capture-subsystem {
120 compatible = "fsl,imx-capture-subsystem";
121 ports = <&ipu1_csi0>, <&ipu1_csi1>;
122 };
123
124 display-subsystem {
125 compatible = "fsl,imx-display-subsystem";
126 ports = <&ipu1_di0>, <&ipu1_di1>;
127 };
128};
129
130&gpio1 {
131 gpio-ranges = <&iomuxc 0 131 2>, <&iomuxc 2 137 8>, <&iomuxc 10 189 2>,
132 <&iomuxc 12 194 1>, <&iomuxc 13 193 1>, <&iomuxc 14 192 1>,
133 <&iomuxc 15 191 1>, <&iomuxc 16 185 2>, <&iomuxc 18 184 1>,
134 <&iomuxc 19 187 1>, <&iomuxc 20 183 1>, <&iomuxc 21 188 1>,
135 <&iomuxc 22 123 3>, <&iomuxc 25 121 1>, <&iomuxc 26 127 1>,
136 <&iomuxc 27 126 1>, <&iomuxc 28 128 1>, <&iomuxc 29 130 1>,
137 <&iomuxc 30 129 1>, <&iomuxc 31 122 1>;
138};
139
140&gpio2 {
141 gpio-ranges = <&iomuxc 0 161 8>, <&iomuxc 8 208 8>, <&iomuxc 16 74 1>,
142 <&iomuxc 17 73 1>, <&iomuxc 18 72 1>, <&iomuxc 19 71 1>,
143 <&iomuxc 20 70 1>, <&iomuxc 21 69 1>, <&iomuxc 22 68 1>,
144 <&iomuxc 23 79 2>, <&iomuxc 25 118 2>, <&iomuxc 27 117 1>,
145 <&iomuxc 28 113 4>;
146};
147
148&gpio3 {
149 gpio-ranges = <&iomuxc 0 97 2>, <&iomuxc 2 105 8>, <&iomuxc 10 99 6>,
150 <&iomuxc 16 81 16>;
151};
152
153&gpio4 {
154 gpio-ranges = <&iomuxc 5 136 1>, <&iomuxc 6 145 1>, <&iomuxc 7 150 1>,
155 <&iomuxc 8 146 1>, <&iomuxc 9 151 1>, <&iomuxc 10 147 1>,
156 <&iomuxc 11 152 1>, <&iomuxc 12 148 1>, <&iomuxc 13 153 1>,
157 <&iomuxc 14 149 1>, <&iomuxc 15 154 1>, <&iomuxc 16 39 7>,
158 <&iomuxc 23 56 1>, <&iomuxc 24 61 7>, <&iomuxc 31 46 1>;
159};
160
161&gpio5 {
162 gpio-ranges = <&iomuxc 0 120 1>, <&iomuxc 2 77 1>, <&iomuxc 4 76 1>,
163 <&iomuxc 5 47 9>, <&iomuxc 14 57 4>, <&iomuxc 18 37 1>,
164 <&iomuxc 19 36 1>, <&iomuxc 20 35 1>, <&iomuxc 21 38 1>,
165 <&iomuxc 22 29 6>, <&iomuxc 28 19 4>;
166};
167
168&gpio6 {
169 gpio-ranges = <&iomuxc 0 23 6>, <&iomuxc 6 75 1>, <&iomuxc 7 156 1>,
170 <&iomuxc 8 155 1>, <&iomuxc 9 170 1>, <&iomuxc 10 169 1>,
171 <&iomuxc 11 157 1>, <&iomuxc 14 158 3>, <&iomuxc 17 204 1>,
172 <&iomuxc 18 203 1>, <&iomuxc 19 182 1>, <&iomuxc 20 177 4>,
173 <&iomuxc 24 175 1>, <&iomuxc 25 171 1>, <&iomuxc 26 181 1>,
174 <&iomuxc 27 172 3>, <&iomuxc 30 176 1>, <&iomuxc 31 78 1>;
175};
176
177&gpio7 {
178 gpio-ranges = <&iomuxc 0 202 1>, <&iomuxc 1 201 1>, <&iomuxc 2 196 1>,
179 <&iomuxc 3 195 1>, <&iomuxc 4 197 4>, <&iomuxc 8 205 1>,
180 <&iomuxc 9 207 1>, <&iomuxc 10 206 1>, <&iomuxc 11 133 3>;
181};
182
183&gpr {
184 ipu1_csi0_mux {
185 compatible = "video-mux";
186 mux-controls = <&mux 0>;
187 #address-cells = <1>;
188 #size-cells = <0>;
189
190 port@0 {
191 reg = <0>;
192
193 ipu1_csi0_mux_from_mipi_vc0: endpoint {
194 remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
195 };
196 };
197
198 port@1 {
199 reg = <1>;
200
201 ipu1_csi0_mux_from_mipi_vc1: endpoint {
202 remote-endpoint = <&mipi_vc1_to_ipu1_csi0_mux>;
203 };
204 };
205
206 port@2 {
207 reg = <2>;
208
209 ipu1_csi0_mux_from_mipi_vc2: endpoint {
210 remote-endpoint = <&mipi_vc2_to_ipu1_csi0_mux>;
211 };
212 };
213
214 port@3 {
215 reg = <3>;
216
217 ipu1_csi0_mux_from_mipi_vc3: endpoint {
218 remote-endpoint = <&mipi_vc3_to_ipu1_csi0_mux>;
219 };
220 };
221
222 port@4 {
223 reg = <4>;
224
225 ipu1_csi0_mux_from_parallel_sensor: endpoint {
226 };
227 };
228
229 port@5 {
230 reg = <5>;
231
232 ipu1_csi0_mux_to_ipu1_csi0: endpoint {
233 remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
234 };
235 };
236 };
237
238 ipu1_csi1_mux {
239 compatible = "video-mux";
240 mux-controls = <&mux 1>;
241 #address-cells = <1>;
242 #size-cells = <0>;
243
244 port@0 {
245 reg = <0>;
246
247 ipu1_csi1_mux_from_mipi_vc0: endpoint {
248 remote-endpoint = <&mipi_vc0_to_ipu1_csi1_mux>;
249 };
250 };
251
252 port@1 {
253 reg = <1>;
254
255 ipu1_csi1_mux_from_mipi_vc1: endpoint {
256 remote-endpoint = <&mipi_vc1_to_ipu1_csi1_mux>;
257 };
258 };
259
260 port@2 {
261 reg = <2>;
262
263 ipu1_csi1_mux_from_mipi_vc2: endpoint {
264 remote-endpoint = <&mipi_vc2_to_ipu1_csi1_mux>;
265 };
266 };
267
268 port@3 {
269 reg = <3>;
270
271 ipu1_csi1_mux_from_mipi_vc3: endpoint {
272 remote-endpoint = <&mipi_vc3_to_ipu1_csi1_mux>;
273 };
274 };
275
276 port@4 {
277 reg = <4>;
278
279 ipu1_csi1_mux_from_parallel_sensor: endpoint {
280 };
281 };
282
283 port@5 {
284 reg = <5>;
285
286 ipu1_csi1_mux_to_ipu1_csi1: endpoint {
287 remote-endpoint = <&ipu1_csi1_from_ipu1_csi1_mux>;
288 };
289 };
290 };
291};
292
293&gpt {
294 compatible = "fsl,imx6dl-gpt";
295};
296
297&hdmi {
298 compatible = "fsl,imx6dl-hdmi";
299};
300
301&ipu1_csi1 {
302 ipu1_csi1_from_ipu1_csi1_mux: endpoint {
303 remote-endpoint = <&ipu1_csi1_mux_to_ipu1_csi1>;
304 };
305};
306
307&ldb {
308 clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
309 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
310 <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
311 clock-names = "di0_pll", "di1_pll",
312 "di0_sel", "di1_sel",
313 "di0", "di1";
314};
315
316&mipi_csi {
317 port@1 {
318 reg = <1>;
319 #address-cells = <1>;
320 #size-cells = <0>;
321
322 mipi_vc0_to_ipu1_csi0_mux: endpoint@0 {
323 reg = <0>;
324 remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
325 };
326
327 mipi_vc0_to_ipu1_csi1_mux: endpoint@1 {
328 reg = <1>;
329 remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc0>;
330 };
331 };
332
333 port@2 {
334 reg = <2>;
335 #address-cells = <1>;
336 #size-cells = <0>;
337
338 mipi_vc1_to_ipu1_csi0_mux: endpoint@0 {
339 reg = <0>;
340 remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc1>;
341 };
342
343 mipi_vc1_to_ipu1_csi1_mux: endpoint@1 {
344 reg = <1>;
345 remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc1>;
346 };
347 };
348
349 port@3 {
350 reg = <3>;
351 #address-cells = <1>;
352 #size-cells = <0>;
353
354 mipi_vc2_to_ipu1_csi0_mux: endpoint@0 {
355 reg = <0>;
356 remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc2>;
357 };
358
359 mipi_vc2_to_ipu1_csi1_mux: endpoint@1 {
360 reg = <1>;
361 remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc2>;
362 };
363 };
364
365 port@4 {
366 reg = <4>;
367 #address-cells = <1>;
368 #size-cells = <0>;
369
370 mipi_vc3_to_ipu1_csi0_mux: endpoint@0 {
371 reg = <0>;
372 remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc3>;
373 };
374
375 mipi_vc3_to_ipu1_csi1_mux: endpoint@1 {
376 reg = <1>;
377 remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc3>;
378 };
379 };
380};
381
382&mux {
383 mux-reg-masks = <0x34 0x00000007>, /* IPU_CSI0_MUX */
384 <0x34 0x00000038>, /* IPU_CSI1_MUX */
385 <0x0c 0x0000000c>, /* HDMI_MUX_CTL */
386 <0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
387 <0x0c 0x00000300>, /* LVDS1_MUX_CTL */
388 <0x28 0x00000003>, /* DCIC1_MUX_CTL */
389 <0x28 0x0000000c>; /* DCIC2_MUX_CTL */
390};
391
392&vpu {
393 compatible = "fsl,imx6dl-vpu", "cnm,coda960";
394};