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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Driver for Cirrus Logic EP93xx SPI controller.
4 *
5 * Copyright (C) 2010-2011 Mika Westerberg
6 *
7 * Explicit FIFO handling code was inspired by amba-pl022 driver.
8 *
9 * Chip select support using other than built-in GPIOs by H. Hartley Sweeten.
10 *
11 * For more information about the SPI controller see documentation on Cirrus
12 * Logic web site:
13 * https://www.cirrus.com/en/pubs/manual/EP93xx_Users_Guide_UM1.pdf
14 */
15
16#include <linux/io.h>
17#include <linux/clk.h>
18#include <linux/err.h>
19#include <linux/delay.h>
20#include <linux/device.h>
21#include <linux/dma-direction.h>
22#include <linux/dma-mapping.h>
23#include <linux/dmaengine.h>
24#include <linux/bitops.h>
25#include <linux/interrupt.h>
26#include <linux/module.h>
27#include <linux/property.h>
28#include <linux/platform_device.h>
29#include <linux/sched.h>
30#include <linux/scatterlist.h>
31#include <linux/spi/spi.h>
32
33#define SSPCR0 0x0000
34#define SSPCR0_SPO BIT(6)
35#define SSPCR0_SPH BIT(7)
36#define SSPCR0_SCR_SHIFT 8
37
38#define SSPCR1 0x0004
39#define SSPCR1_RIE BIT(0)
40#define SSPCR1_TIE BIT(1)
41#define SSPCR1_RORIE BIT(2)
42#define SSPCR1_LBM BIT(3)
43#define SSPCR1_SSE BIT(4)
44#define SSPCR1_MS BIT(5)
45#define SSPCR1_SOD BIT(6)
46
47#define SSPDR 0x0008
48
49#define SSPSR 0x000c
50#define SSPSR_TFE BIT(0)
51#define SSPSR_TNF BIT(1)
52#define SSPSR_RNE BIT(2)
53#define SSPSR_RFF BIT(3)
54#define SSPSR_BSY BIT(4)
55#define SSPCPSR 0x0010
56
57#define SSPIIR 0x0014
58#define SSPIIR_RIS BIT(0)
59#define SSPIIR_TIS BIT(1)
60#define SSPIIR_RORIS BIT(2)
61#define SSPICR SSPIIR
62
63/* timeout in milliseconds */
64#define SPI_TIMEOUT 5
65/* maximum depth of RX/TX FIFO */
66#define SPI_FIFO_SIZE 8
67
68/**
69 * struct ep93xx_spi - EP93xx SPI controller structure
70 * @clk: clock for the controller
71 * @mmio: pointer to ioremap()'d registers
72 * @sspdr_phys: physical address of the SSPDR register
73 * @tx: current byte in transfer to transmit
74 * @rx: current byte in transfer to receive
75 * @fifo_level: how full is FIFO (%0..%SPI_FIFO_SIZE - %1). Receiving one
76 * frame decreases this level and sending one frame increases it.
77 * @dma_rx: RX DMA channel
78 * @dma_tx: TX DMA channel
79 * @rx_sgt: sg table for RX transfers
80 * @tx_sgt: sg table for TX transfers
81 * @zeropage: dummy page used as RX buffer when only TX buffer is passed in by
82 * the client
83 */
84struct ep93xx_spi {
85 struct clk *clk;
86 void __iomem *mmio;
87 unsigned long sspdr_phys;
88 size_t tx;
89 size_t rx;
90 size_t fifo_level;
91 struct dma_chan *dma_rx;
92 struct dma_chan *dma_tx;
93 struct sg_table rx_sgt;
94 struct sg_table tx_sgt;
95 void *zeropage;
96};
97
98/* converts bits per word to CR0.DSS value */
99#define bits_per_word_to_dss(bpw) ((bpw) - 1)
100
101/**
102 * ep93xx_spi_calc_divisors() - calculates SPI clock divisors
103 * @host: SPI host
104 * @rate: desired SPI output clock rate
105 * @div_cpsr: pointer to return the cpsr (pre-scaler) divider
106 * @div_scr: pointer to return the scr divider
107 */
108static int ep93xx_spi_calc_divisors(struct spi_controller *host,
109 u32 rate, u8 *div_cpsr, u8 *div_scr)
110{
111 struct ep93xx_spi *espi = spi_controller_get_devdata(host);
112 unsigned long spi_clk_rate = clk_get_rate(espi->clk);
113 int cpsr, scr;
114
115 /*
116 * Make sure that max value is between values supported by the
117 * controller.
118 */
119 rate = clamp(rate, host->min_speed_hz, host->max_speed_hz);
120
121 /*
122 * Calculate divisors so that we can get speed according the
123 * following formula:
124 * rate = spi_clock_rate / (cpsr * (1 + scr))
125 *
126 * cpsr must be even number and starts from 2, scr can be any number
127 * between 0 and 255.
128 */
129 for (cpsr = 2; cpsr <= 254; cpsr += 2) {
130 for (scr = 0; scr <= 255; scr++) {
131 if ((spi_clk_rate / (cpsr * (scr + 1))) <= rate) {
132 *div_scr = (u8)scr;
133 *div_cpsr = (u8)cpsr;
134 return 0;
135 }
136 }
137 }
138
139 return -EINVAL;
140}
141
142static int ep93xx_spi_chip_setup(struct spi_controller *host,
143 struct spi_device *spi,
144 struct spi_transfer *xfer)
145{
146 struct ep93xx_spi *espi = spi_controller_get_devdata(host);
147 u8 dss = bits_per_word_to_dss(xfer->bits_per_word);
148 u8 div_cpsr = 0;
149 u8 div_scr = 0;
150 u16 cr0;
151 int err;
152
153 err = ep93xx_spi_calc_divisors(host, xfer->speed_hz,
154 &div_cpsr, &div_scr);
155 if (err)
156 return err;
157
158 cr0 = div_scr << SSPCR0_SCR_SHIFT;
159 if (spi->mode & SPI_CPOL)
160 cr0 |= SSPCR0_SPO;
161 if (spi->mode & SPI_CPHA)
162 cr0 |= SSPCR0_SPH;
163 cr0 |= dss;
164
165 dev_dbg(&host->dev, "setup: mode %d, cpsr %d, scr %d, dss %d\n",
166 spi->mode, div_cpsr, div_scr, dss);
167 dev_dbg(&host->dev, "setup: cr0 %#x\n", cr0);
168
169 writel(div_cpsr, espi->mmio + SSPCPSR);
170 writel(cr0, espi->mmio + SSPCR0);
171
172 return 0;
173}
174
175static void ep93xx_do_write(struct spi_controller *host)
176{
177 struct ep93xx_spi *espi = spi_controller_get_devdata(host);
178 struct spi_transfer *xfer = host->cur_msg->state;
179 u32 val = 0;
180
181 if (xfer->bits_per_word > 8) {
182 if (xfer->tx_buf)
183 val = ((u16 *)xfer->tx_buf)[espi->tx];
184 espi->tx += 2;
185 } else {
186 if (xfer->tx_buf)
187 val = ((u8 *)xfer->tx_buf)[espi->tx];
188 espi->tx += 1;
189 }
190 writel(val, espi->mmio + SSPDR);
191}
192
193static void ep93xx_do_read(struct spi_controller *host)
194{
195 struct ep93xx_spi *espi = spi_controller_get_devdata(host);
196 struct spi_transfer *xfer = host->cur_msg->state;
197 u32 val;
198
199 val = readl(espi->mmio + SSPDR);
200 if (xfer->bits_per_word > 8) {
201 if (xfer->rx_buf)
202 ((u16 *)xfer->rx_buf)[espi->rx] = val;
203 espi->rx += 2;
204 } else {
205 if (xfer->rx_buf)
206 ((u8 *)xfer->rx_buf)[espi->rx] = val;
207 espi->rx += 1;
208 }
209}
210
211/**
212 * ep93xx_spi_read_write() - perform next RX/TX transfer
213 * @host: SPI host
214 *
215 * This function transfers next bytes (or half-words) to/from RX/TX FIFOs. If
216 * called several times, the whole transfer will be completed. Returns
217 * %-EINPROGRESS when current transfer was not yet completed otherwise %0.
218 *
219 * When this function is finished, RX FIFO should be empty and TX FIFO should be
220 * full.
221 */
222static int ep93xx_spi_read_write(struct spi_controller *host)
223{
224 struct ep93xx_spi *espi = spi_controller_get_devdata(host);
225 struct spi_transfer *xfer = host->cur_msg->state;
226
227 /* read as long as RX FIFO has frames in it */
228 while ((readl(espi->mmio + SSPSR) & SSPSR_RNE)) {
229 ep93xx_do_read(host);
230 espi->fifo_level--;
231 }
232
233 /* write as long as TX FIFO has room */
234 while (espi->fifo_level < SPI_FIFO_SIZE && espi->tx < xfer->len) {
235 ep93xx_do_write(host);
236 espi->fifo_level++;
237 }
238
239 if (espi->rx == xfer->len)
240 return 0;
241
242 return -EINPROGRESS;
243}
244
245static enum dma_transfer_direction
246ep93xx_dma_data_to_trans_dir(enum dma_data_direction dir)
247{
248 switch (dir) {
249 case DMA_TO_DEVICE:
250 return DMA_MEM_TO_DEV;
251 case DMA_FROM_DEVICE:
252 return DMA_DEV_TO_MEM;
253 default:
254 return DMA_TRANS_NONE;
255 }
256}
257
258/**
259 * ep93xx_spi_dma_prepare() - prepares a DMA transfer
260 * @host: SPI host
261 * @dir: DMA transfer direction
262 *
263 * Function configures the DMA, maps the buffer and prepares the DMA
264 * descriptor. Returns a valid DMA descriptor in case of success and ERR_PTR
265 * in case of failure.
266 */
267static struct dma_async_tx_descriptor *
268ep93xx_spi_dma_prepare(struct spi_controller *host,
269 enum dma_data_direction dir)
270{
271 struct ep93xx_spi *espi = spi_controller_get_devdata(host);
272 struct spi_transfer *xfer = host->cur_msg->state;
273 struct dma_async_tx_descriptor *txd;
274 enum dma_slave_buswidth buswidth;
275 struct dma_slave_config conf;
276 struct scatterlist *sg;
277 struct sg_table *sgt;
278 struct dma_chan *chan;
279 const void *buf, *pbuf;
280 size_t len = xfer->len;
281 int i, ret, nents;
282
283 if (xfer->bits_per_word > 8)
284 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
285 else
286 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
287
288 memset(&conf, 0, sizeof(conf));
289 conf.direction = ep93xx_dma_data_to_trans_dir(dir);
290
291 if (dir == DMA_FROM_DEVICE) {
292 chan = espi->dma_rx;
293 buf = xfer->rx_buf;
294 sgt = &espi->rx_sgt;
295
296 conf.src_addr = espi->sspdr_phys;
297 conf.src_addr_width = buswidth;
298 } else {
299 chan = espi->dma_tx;
300 buf = xfer->tx_buf;
301 sgt = &espi->tx_sgt;
302
303 conf.dst_addr = espi->sspdr_phys;
304 conf.dst_addr_width = buswidth;
305 }
306
307 ret = dmaengine_slave_config(chan, &conf);
308 if (ret)
309 return ERR_PTR(ret);
310
311 /*
312 * We need to split the transfer into PAGE_SIZE'd chunks. This is
313 * because we are using @espi->zeropage to provide a zero RX buffer
314 * for the TX transfers and we have only allocated one page for that.
315 *
316 * For performance reasons we allocate a new sg_table only when
317 * needed. Otherwise we will re-use the current one. Eventually the
318 * last sg_table is released in ep93xx_spi_release_dma().
319 */
320
321 nents = DIV_ROUND_UP(len, PAGE_SIZE);
322 if (nents != sgt->nents) {
323 sg_free_table(sgt);
324
325 ret = sg_alloc_table(sgt, nents, GFP_KERNEL);
326 if (ret)
327 return ERR_PTR(ret);
328 }
329
330 pbuf = buf;
331 for_each_sg(sgt->sgl, sg, sgt->nents, i) {
332 size_t bytes = min_t(size_t, len, PAGE_SIZE);
333
334 if (buf) {
335 sg_set_page(sg, virt_to_page(pbuf), bytes,
336 offset_in_page(pbuf));
337 } else {
338 sg_set_page(sg, virt_to_page(espi->zeropage),
339 bytes, 0);
340 }
341
342 pbuf += bytes;
343 len -= bytes;
344 }
345
346 if (WARN_ON(len)) {
347 dev_warn(&host->dev, "len = %zu expected 0!\n", len);
348 return ERR_PTR(-EINVAL);
349 }
350
351 nents = dma_map_sg(chan->device->dev, sgt->sgl, sgt->nents, dir);
352 if (!nents)
353 return ERR_PTR(-ENOMEM);
354
355 txd = dmaengine_prep_slave_sg(chan, sgt->sgl, nents, conf.direction,
356 DMA_CTRL_ACK);
357 if (!txd) {
358 dma_unmap_sg(chan->device->dev, sgt->sgl, sgt->nents, dir);
359 return ERR_PTR(-ENOMEM);
360 }
361 return txd;
362}
363
364/**
365 * ep93xx_spi_dma_finish() - finishes with a DMA transfer
366 * @host: SPI host
367 * @dir: DMA transfer direction
368 *
369 * Function finishes with the DMA transfer. After this, the DMA buffer is
370 * unmapped.
371 */
372static void ep93xx_spi_dma_finish(struct spi_controller *host,
373 enum dma_data_direction dir)
374{
375 struct ep93xx_spi *espi = spi_controller_get_devdata(host);
376 struct dma_chan *chan;
377 struct sg_table *sgt;
378
379 if (dir == DMA_FROM_DEVICE) {
380 chan = espi->dma_rx;
381 sgt = &espi->rx_sgt;
382 } else {
383 chan = espi->dma_tx;
384 sgt = &espi->tx_sgt;
385 }
386
387 dma_unmap_sg(chan->device->dev, sgt->sgl, sgt->nents, dir);
388}
389
390static void ep93xx_spi_dma_callback(void *callback_param)
391{
392 struct spi_controller *host = callback_param;
393
394 ep93xx_spi_dma_finish(host, DMA_TO_DEVICE);
395 ep93xx_spi_dma_finish(host, DMA_FROM_DEVICE);
396
397 spi_finalize_current_transfer(host);
398}
399
400static int ep93xx_spi_dma_transfer(struct spi_controller *host)
401{
402 struct ep93xx_spi *espi = spi_controller_get_devdata(host);
403 struct dma_async_tx_descriptor *rxd, *txd;
404
405 rxd = ep93xx_spi_dma_prepare(host, DMA_FROM_DEVICE);
406 if (IS_ERR(rxd)) {
407 dev_err(&host->dev, "DMA RX failed: %ld\n", PTR_ERR(rxd));
408 return PTR_ERR(rxd);
409 }
410
411 txd = ep93xx_spi_dma_prepare(host, DMA_TO_DEVICE);
412 if (IS_ERR(txd)) {
413 ep93xx_spi_dma_finish(host, DMA_FROM_DEVICE);
414 dev_err(&host->dev, "DMA TX failed: %ld\n", PTR_ERR(txd));
415 return PTR_ERR(txd);
416 }
417
418 /* We are ready when RX is done */
419 rxd->callback = ep93xx_spi_dma_callback;
420 rxd->callback_param = host;
421
422 /* Now submit both descriptors and start DMA */
423 dmaengine_submit(rxd);
424 dmaengine_submit(txd);
425
426 dma_async_issue_pending(espi->dma_rx);
427 dma_async_issue_pending(espi->dma_tx);
428
429 /* signal that we need to wait for completion */
430 return 1;
431}
432
433static irqreturn_t ep93xx_spi_interrupt(int irq, void *dev_id)
434{
435 struct spi_controller *host = dev_id;
436 struct ep93xx_spi *espi = spi_controller_get_devdata(host);
437 u32 val;
438
439 /*
440 * If we got ROR (receive overrun) interrupt we know that something is
441 * wrong. Just abort the message.
442 */
443 if (readl(espi->mmio + SSPIIR) & SSPIIR_RORIS) {
444 /* clear the overrun interrupt */
445 writel(0, espi->mmio + SSPICR);
446 dev_warn(&host->dev,
447 "receive overrun, aborting the message\n");
448 host->cur_msg->status = -EIO;
449 } else {
450 /*
451 * Interrupt is either RX (RIS) or TX (TIS). For both cases we
452 * simply execute next data transfer.
453 */
454 if (ep93xx_spi_read_write(host)) {
455 /*
456 * In normal case, there still is some processing left
457 * for current transfer. Let's wait for the next
458 * interrupt then.
459 */
460 return IRQ_HANDLED;
461 }
462 }
463
464 /*
465 * Current transfer is finished, either with error or with success. In
466 * any case we disable interrupts and notify the worker to handle
467 * any post-processing of the message.
468 */
469 val = readl(espi->mmio + SSPCR1);
470 val &= ~(SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE);
471 writel(val, espi->mmio + SSPCR1);
472
473 spi_finalize_current_transfer(host);
474
475 return IRQ_HANDLED;
476}
477
478static int ep93xx_spi_transfer_one(struct spi_controller *host,
479 struct spi_device *spi,
480 struct spi_transfer *xfer)
481{
482 struct ep93xx_spi *espi = spi_controller_get_devdata(host);
483 u32 val;
484 int ret;
485
486 ret = ep93xx_spi_chip_setup(host, spi, xfer);
487 if (ret) {
488 dev_err(&host->dev, "failed to setup chip for transfer\n");
489 return ret;
490 }
491
492 host->cur_msg->state = xfer;
493 espi->rx = 0;
494 espi->tx = 0;
495
496 /*
497 * There is no point of setting up DMA for the transfers which will
498 * fit into the FIFO and can be transferred with a single interrupt.
499 * So in these cases we will be using PIO and don't bother for DMA.
500 */
501 if (espi->dma_rx && xfer->len > SPI_FIFO_SIZE)
502 return ep93xx_spi_dma_transfer(host);
503
504 /* Using PIO so prime the TX FIFO and enable interrupts */
505 ep93xx_spi_read_write(host);
506
507 val = readl(espi->mmio + SSPCR1);
508 val |= (SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE);
509 writel(val, espi->mmio + SSPCR1);
510
511 /* signal that we need to wait for completion */
512 return 1;
513}
514
515static int ep93xx_spi_prepare_message(struct spi_controller *host,
516 struct spi_message *msg)
517{
518 struct ep93xx_spi *espi = spi_controller_get_devdata(host);
519 unsigned long timeout;
520
521 /*
522 * Just to be sure: flush any data from RX FIFO.
523 */
524 timeout = jiffies + msecs_to_jiffies(SPI_TIMEOUT);
525 while (readl(espi->mmio + SSPSR) & SSPSR_RNE) {
526 if (time_after(jiffies, timeout)) {
527 dev_warn(&host->dev,
528 "timeout while flushing RX FIFO\n");
529 return -ETIMEDOUT;
530 }
531 readl(espi->mmio + SSPDR);
532 }
533
534 /*
535 * We explicitly handle FIFO level. This way we don't have to check TX
536 * FIFO status using %SSPSR_TNF bit which may cause RX FIFO overruns.
537 */
538 espi->fifo_level = 0;
539
540 return 0;
541}
542
543static int ep93xx_spi_prepare_hardware(struct spi_controller *host)
544{
545 struct ep93xx_spi *espi = spi_controller_get_devdata(host);
546 u32 val;
547 int ret;
548
549 ret = clk_prepare_enable(espi->clk);
550 if (ret)
551 return ret;
552
553 val = readl(espi->mmio + SSPCR1);
554 val |= SSPCR1_SSE;
555 writel(val, espi->mmio + SSPCR1);
556
557 return 0;
558}
559
560static int ep93xx_spi_unprepare_hardware(struct spi_controller *host)
561{
562 struct ep93xx_spi *espi = spi_controller_get_devdata(host);
563 u32 val;
564
565 val = readl(espi->mmio + SSPCR1);
566 val &= ~SSPCR1_SSE;
567 writel(val, espi->mmio + SSPCR1);
568
569 clk_disable_unprepare(espi->clk);
570
571 return 0;
572}
573
574static int ep93xx_spi_setup_dma(struct device *dev, struct ep93xx_spi *espi)
575{
576 int ret;
577
578 espi->zeropage = (void *)get_zeroed_page(GFP_KERNEL);
579 if (!espi->zeropage)
580 return -ENOMEM;
581
582 espi->dma_rx = dma_request_chan(dev, "rx");
583 if (IS_ERR(espi->dma_rx)) {
584 ret = dev_err_probe(dev, PTR_ERR(espi->dma_rx), "rx DMA setup failed");
585 goto fail_free_page;
586 }
587
588 espi->dma_tx = dma_request_chan(dev, "tx");
589 if (IS_ERR(espi->dma_tx)) {
590 ret = dev_err_probe(dev, PTR_ERR(espi->dma_tx), "tx DMA setup failed");
591 goto fail_release_rx;
592 }
593
594 return 0;
595
596fail_release_rx:
597 dma_release_channel(espi->dma_rx);
598 espi->dma_rx = NULL;
599fail_free_page:
600 free_page((unsigned long)espi->zeropage);
601
602 return ret;
603}
604
605static void ep93xx_spi_release_dma(struct ep93xx_spi *espi)
606{
607 if (espi->dma_rx) {
608 dma_release_channel(espi->dma_rx);
609 sg_free_table(&espi->rx_sgt);
610 }
611 if (espi->dma_tx) {
612 dma_release_channel(espi->dma_tx);
613 sg_free_table(&espi->tx_sgt);
614 }
615
616 if (espi->zeropage)
617 free_page((unsigned long)espi->zeropage);
618}
619
620static int ep93xx_spi_probe(struct platform_device *pdev)
621{
622 struct spi_controller *host;
623 struct ep93xx_spi *espi;
624 struct resource *res;
625 int irq;
626 int error;
627
628 irq = platform_get_irq(pdev, 0);
629 if (irq < 0)
630 return irq;
631
632 host = spi_alloc_host(&pdev->dev, sizeof(*espi));
633 if (!host)
634 return -ENOMEM;
635
636 host->use_gpio_descriptors = true;
637 host->prepare_transfer_hardware = ep93xx_spi_prepare_hardware;
638 host->unprepare_transfer_hardware = ep93xx_spi_unprepare_hardware;
639 host->prepare_message = ep93xx_spi_prepare_message;
640 host->transfer_one = ep93xx_spi_transfer_one;
641 host->bus_num = pdev->id;
642 host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
643 host->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
644 /*
645 * The SPI core will count the number of GPIO descriptors to figure
646 * out the number of chip selects available on the platform.
647 */
648 host->num_chipselect = 0;
649
650 platform_set_drvdata(pdev, host);
651
652 espi = spi_controller_get_devdata(host);
653
654 espi->clk = devm_clk_get(&pdev->dev, NULL);
655 if (IS_ERR(espi->clk)) {
656 dev_err(&pdev->dev, "unable to get spi clock\n");
657 error = PTR_ERR(espi->clk);
658 goto fail_release_host;
659 }
660
661 /*
662 * Calculate maximum and minimum supported clock rates
663 * for the controller.
664 */
665 host->max_speed_hz = clk_get_rate(espi->clk) / 2;
666 host->min_speed_hz = clk_get_rate(espi->clk) / (254 * 256);
667
668 espi->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
669 if (IS_ERR(espi->mmio)) {
670 error = PTR_ERR(espi->mmio);
671 goto fail_release_host;
672 }
673 espi->sspdr_phys = res->start + SSPDR;
674
675 error = devm_request_irq(&pdev->dev, irq, ep93xx_spi_interrupt,
676 0, "ep93xx-spi", host);
677 if (error) {
678 dev_err(&pdev->dev, "failed to request irq\n");
679 goto fail_release_host;
680 }
681
682 error = ep93xx_spi_setup_dma(&pdev->dev, espi);
683 if (error == -EPROBE_DEFER)
684 goto fail_release_host;
685
686 if (error)
687 dev_warn(&pdev->dev, "DMA setup failed. Falling back to PIO\n");
688
689 /* make sure that the hardware is disabled */
690 writel(0, espi->mmio + SSPCR1);
691
692 device_set_node(&host->dev, dev_fwnode(&pdev->dev));
693 error = devm_spi_register_controller(&pdev->dev, host);
694 if (error) {
695 dev_err(&pdev->dev, "failed to register SPI host\n");
696 goto fail_free_dma;
697 }
698
699 dev_info(&pdev->dev, "EP93xx SPI Controller at 0x%08lx irq %d\n",
700 (unsigned long)res->start, irq);
701
702 return 0;
703
704fail_free_dma:
705 ep93xx_spi_release_dma(espi);
706fail_release_host:
707 spi_controller_put(host);
708
709 return error;
710}
711
712static void ep93xx_spi_remove(struct platform_device *pdev)
713{
714 struct spi_controller *host = platform_get_drvdata(pdev);
715 struct ep93xx_spi *espi = spi_controller_get_devdata(host);
716
717 ep93xx_spi_release_dma(espi);
718}
719
720static const struct of_device_id ep93xx_spi_of_ids[] = {
721 { .compatible = "cirrus,ep9301-spi" },
722 { /* sentinel */ }
723};
724MODULE_DEVICE_TABLE(of, ep93xx_spi_of_ids);
725
726static struct platform_driver ep93xx_spi_driver = {
727 .driver = {
728 .name = "ep93xx-spi",
729 .of_match_table = ep93xx_spi_of_ids,
730 },
731 .probe = ep93xx_spi_probe,
732 .remove = ep93xx_spi_remove,
733};
734module_platform_driver(ep93xx_spi_driver);
735
736MODULE_DESCRIPTION("EP93xx SPI Controller driver");
737MODULE_AUTHOR("Mika Westerberg <mika.westerberg@iki.fi>");
738MODULE_LICENSE("GPL");
739MODULE_ALIAS("platform:ep93xx-spi");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Driver for Cirrus Logic EP93xx SPI controller.
4 *
5 * Copyright (C) 2010-2011 Mika Westerberg
6 *
7 * Explicit FIFO handling code was inspired by amba-pl022 driver.
8 *
9 * Chip select support using other than built-in GPIOs by H. Hartley Sweeten.
10 *
11 * For more information about the SPI controller see documentation on Cirrus
12 * Logic web site:
13 * http://www.cirrus.com/en/pubs/manual/EP93xx_Users_Guide_UM1.pdf
14 */
15
16#include <linux/io.h>
17#include <linux/clk.h>
18#include <linux/err.h>
19#include <linux/delay.h>
20#include <linux/device.h>
21#include <linux/dmaengine.h>
22#include <linux/bitops.h>
23#include <linux/interrupt.h>
24#include <linux/module.h>
25#include <linux/platform_device.h>
26#include <linux/sched.h>
27#include <linux/scatterlist.h>
28#include <linux/spi/spi.h>
29
30#include <linux/platform_data/dma-ep93xx.h>
31#include <linux/platform_data/spi-ep93xx.h>
32
33#define SSPCR0 0x0000
34#define SSPCR0_MODE_SHIFT 6
35#define SSPCR0_SCR_SHIFT 8
36
37#define SSPCR1 0x0004
38#define SSPCR1_RIE BIT(0)
39#define SSPCR1_TIE BIT(1)
40#define SSPCR1_RORIE BIT(2)
41#define SSPCR1_LBM BIT(3)
42#define SSPCR1_SSE BIT(4)
43#define SSPCR1_MS BIT(5)
44#define SSPCR1_SOD BIT(6)
45
46#define SSPDR 0x0008
47
48#define SSPSR 0x000c
49#define SSPSR_TFE BIT(0)
50#define SSPSR_TNF BIT(1)
51#define SSPSR_RNE BIT(2)
52#define SSPSR_RFF BIT(3)
53#define SSPSR_BSY BIT(4)
54#define SSPCPSR 0x0010
55
56#define SSPIIR 0x0014
57#define SSPIIR_RIS BIT(0)
58#define SSPIIR_TIS BIT(1)
59#define SSPIIR_RORIS BIT(2)
60#define SSPICR SSPIIR
61
62/* timeout in milliseconds */
63#define SPI_TIMEOUT 5
64/* maximum depth of RX/TX FIFO */
65#define SPI_FIFO_SIZE 8
66
67/**
68 * struct ep93xx_spi - EP93xx SPI controller structure
69 * @clk: clock for the controller
70 * @mmio: pointer to ioremap()'d registers
71 * @sspdr_phys: physical address of the SSPDR register
72 * @tx: current byte in transfer to transmit
73 * @rx: current byte in transfer to receive
74 * @fifo_level: how full is FIFO (%0..%SPI_FIFO_SIZE - %1). Receiving one
75 * frame decreases this level and sending one frame increases it.
76 * @dma_rx: RX DMA channel
77 * @dma_tx: TX DMA channel
78 * @dma_rx_data: RX parameters passed to the DMA engine
79 * @dma_tx_data: TX parameters passed to the DMA engine
80 * @rx_sgt: sg table for RX transfers
81 * @tx_sgt: sg table for TX transfers
82 * @zeropage: dummy page used as RX buffer when only TX buffer is passed in by
83 * the client
84 */
85struct ep93xx_spi {
86 struct clk *clk;
87 void __iomem *mmio;
88 unsigned long sspdr_phys;
89 size_t tx;
90 size_t rx;
91 size_t fifo_level;
92 struct dma_chan *dma_rx;
93 struct dma_chan *dma_tx;
94 struct ep93xx_dma_data dma_rx_data;
95 struct ep93xx_dma_data dma_tx_data;
96 struct sg_table rx_sgt;
97 struct sg_table tx_sgt;
98 void *zeropage;
99};
100
101/* converts bits per word to CR0.DSS value */
102#define bits_per_word_to_dss(bpw) ((bpw) - 1)
103
104/**
105 * ep93xx_spi_calc_divisors() - calculates SPI clock divisors
106 * @master: SPI master
107 * @rate: desired SPI output clock rate
108 * @div_cpsr: pointer to return the cpsr (pre-scaler) divider
109 * @div_scr: pointer to return the scr divider
110 */
111static int ep93xx_spi_calc_divisors(struct spi_master *master,
112 u32 rate, u8 *div_cpsr, u8 *div_scr)
113{
114 struct ep93xx_spi *espi = spi_master_get_devdata(master);
115 unsigned long spi_clk_rate = clk_get_rate(espi->clk);
116 int cpsr, scr;
117
118 /*
119 * Make sure that max value is between values supported by the
120 * controller.
121 */
122 rate = clamp(rate, master->min_speed_hz, master->max_speed_hz);
123
124 /*
125 * Calculate divisors so that we can get speed according the
126 * following formula:
127 * rate = spi_clock_rate / (cpsr * (1 + scr))
128 *
129 * cpsr must be even number and starts from 2, scr can be any number
130 * between 0 and 255.
131 */
132 for (cpsr = 2; cpsr <= 254; cpsr += 2) {
133 for (scr = 0; scr <= 255; scr++) {
134 if ((spi_clk_rate / (cpsr * (scr + 1))) <= rate) {
135 *div_scr = (u8)scr;
136 *div_cpsr = (u8)cpsr;
137 return 0;
138 }
139 }
140 }
141
142 return -EINVAL;
143}
144
145static int ep93xx_spi_chip_setup(struct spi_master *master,
146 struct spi_device *spi,
147 struct spi_transfer *xfer)
148{
149 struct ep93xx_spi *espi = spi_master_get_devdata(master);
150 u8 dss = bits_per_word_to_dss(xfer->bits_per_word);
151 u8 div_cpsr = 0;
152 u8 div_scr = 0;
153 u16 cr0;
154 int err;
155
156 err = ep93xx_spi_calc_divisors(master, xfer->speed_hz,
157 &div_cpsr, &div_scr);
158 if (err)
159 return err;
160
161 cr0 = div_scr << SSPCR0_SCR_SHIFT;
162 cr0 |= (spi->mode & (SPI_CPHA | SPI_CPOL)) << SSPCR0_MODE_SHIFT;
163 cr0 |= dss;
164
165 dev_dbg(&master->dev, "setup: mode %d, cpsr %d, scr %d, dss %d\n",
166 spi->mode, div_cpsr, div_scr, dss);
167 dev_dbg(&master->dev, "setup: cr0 %#x\n", cr0);
168
169 writel(div_cpsr, espi->mmio + SSPCPSR);
170 writel(cr0, espi->mmio + SSPCR0);
171
172 return 0;
173}
174
175static void ep93xx_do_write(struct spi_master *master)
176{
177 struct ep93xx_spi *espi = spi_master_get_devdata(master);
178 struct spi_transfer *xfer = master->cur_msg->state;
179 u32 val = 0;
180
181 if (xfer->bits_per_word > 8) {
182 if (xfer->tx_buf)
183 val = ((u16 *)xfer->tx_buf)[espi->tx];
184 espi->tx += 2;
185 } else {
186 if (xfer->tx_buf)
187 val = ((u8 *)xfer->tx_buf)[espi->tx];
188 espi->tx += 1;
189 }
190 writel(val, espi->mmio + SSPDR);
191}
192
193static void ep93xx_do_read(struct spi_master *master)
194{
195 struct ep93xx_spi *espi = spi_master_get_devdata(master);
196 struct spi_transfer *xfer = master->cur_msg->state;
197 u32 val;
198
199 val = readl(espi->mmio + SSPDR);
200 if (xfer->bits_per_word > 8) {
201 if (xfer->rx_buf)
202 ((u16 *)xfer->rx_buf)[espi->rx] = val;
203 espi->rx += 2;
204 } else {
205 if (xfer->rx_buf)
206 ((u8 *)xfer->rx_buf)[espi->rx] = val;
207 espi->rx += 1;
208 }
209}
210
211/**
212 * ep93xx_spi_read_write() - perform next RX/TX transfer
213 * @espi: ep93xx SPI controller struct
214 *
215 * This function transfers next bytes (or half-words) to/from RX/TX FIFOs. If
216 * called several times, the whole transfer will be completed. Returns
217 * %-EINPROGRESS when current transfer was not yet completed otherwise %0.
218 *
219 * When this function is finished, RX FIFO should be empty and TX FIFO should be
220 * full.
221 */
222static int ep93xx_spi_read_write(struct spi_master *master)
223{
224 struct ep93xx_spi *espi = spi_master_get_devdata(master);
225 struct spi_transfer *xfer = master->cur_msg->state;
226
227 /* read as long as RX FIFO has frames in it */
228 while ((readl(espi->mmio + SSPSR) & SSPSR_RNE)) {
229 ep93xx_do_read(master);
230 espi->fifo_level--;
231 }
232
233 /* write as long as TX FIFO has room */
234 while (espi->fifo_level < SPI_FIFO_SIZE && espi->tx < xfer->len) {
235 ep93xx_do_write(master);
236 espi->fifo_level++;
237 }
238
239 if (espi->rx == xfer->len)
240 return 0;
241
242 return -EINPROGRESS;
243}
244
245static enum dma_transfer_direction
246ep93xx_dma_data_to_trans_dir(enum dma_data_direction dir)
247{
248 switch (dir) {
249 case DMA_TO_DEVICE:
250 return DMA_MEM_TO_DEV;
251 case DMA_FROM_DEVICE:
252 return DMA_DEV_TO_MEM;
253 default:
254 return DMA_TRANS_NONE;
255 }
256}
257
258/**
259 * ep93xx_spi_dma_prepare() - prepares a DMA transfer
260 * @master: SPI master
261 * @dir: DMA transfer direction
262 *
263 * Function configures the DMA, maps the buffer and prepares the DMA
264 * descriptor. Returns a valid DMA descriptor in case of success and ERR_PTR
265 * in case of failure.
266 */
267static struct dma_async_tx_descriptor *
268ep93xx_spi_dma_prepare(struct spi_master *master,
269 enum dma_data_direction dir)
270{
271 struct ep93xx_spi *espi = spi_master_get_devdata(master);
272 struct spi_transfer *xfer = master->cur_msg->state;
273 struct dma_async_tx_descriptor *txd;
274 enum dma_slave_buswidth buswidth;
275 struct dma_slave_config conf;
276 struct scatterlist *sg;
277 struct sg_table *sgt;
278 struct dma_chan *chan;
279 const void *buf, *pbuf;
280 size_t len = xfer->len;
281 int i, ret, nents;
282
283 if (xfer->bits_per_word > 8)
284 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
285 else
286 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
287
288 memset(&conf, 0, sizeof(conf));
289 conf.direction = ep93xx_dma_data_to_trans_dir(dir);
290
291 if (dir == DMA_FROM_DEVICE) {
292 chan = espi->dma_rx;
293 buf = xfer->rx_buf;
294 sgt = &espi->rx_sgt;
295
296 conf.src_addr = espi->sspdr_phys;
297 conf.src_addr_width = buswidth;
298 } else {
299 chan = espi->dma_tx;
300 buf = xfer->tx_buf;
301 sgt = &espi->tx_sgt;
302
303 conf.dst_addr = espi->sspdr_phys;
304 conf.dst_addr_width = buswidth;
305 }
306
307 ret = dmaengine_slave_config(chan, &conf);
308 if (ret)
309 return ERR_PTR(ret);
310
311 /*
312 * We need to split the transfer into PAGE_SIZE'd chunks. This is
313 * because we are using @espi->zeropage to provide a zero RX buffer
314 * for the TX transfers and we have only allocated one page for that.
315 *
316 * For performance reasons we allocate a new sg_table only when
317 * needed. Otherwise we will re-use the current one. Eventually the
318 * last sg_table is released in ep93xx_spi_release_dma().
319 */
320
321 nents = DIV_ROUND_UP(len, PAGE_SIZE);
322 if (nents != sgt->nents) {
323 sg_free_table(sgt);
324
325 ret = sg_alloc_table(sgt, nents, GFP_KERNEL);
326 if (ret)
327 return ERR_PTR(ret);
328 }
329
330 pbuf = buf;
331 for_each_sg(sgt->sgl, sg, sgt->nents, i) {
332 size_t bytes = min_t(size_t, len, PAGE_SIZE);
333
334 if (buf) {
335 sg_set_page(sg, virt_to_page(pbuf), bytes,
336 offset_in_page(pbuf));
337 } else {
338 sg_set_page(sg, virt_to_page(espi->zeropage),
339 bytes, 0);
340 }
341
342 pbuf += bytes;
343 len -= bytes;
344 }
345
346 if (WARN_ON(len)) {
347 dev_warn(&master->dev, "len = %zu expected 0!\n", len);
348 return ERR_PTR(-EINVAL);
349 }
350
351 nents = dma_map_sg(chan->device->dev, sgt->sgl, sgt->nents, dir);
352 if (!nents)
353 return ERR_PTR(-ENOMEM);
354
355 txd = dmaengine_prep_slave_sg(chan, sgt->sgl, nents, conf.direction,
356 DMA_CTRL_ACK);
357 if (!txd) {
358 dma_unmap_sg(chan->device->dev, sgt->sgl, sgt->nents, dir);
359 return ERR_PTR(-ENOMEM);
360 }
361 return txd;
362}
363
364/**
365 * ep93xx_spi_dma_finish() - finishes with a DMA transfer
366 * @master: SPI master
367 * @dir: DMA transfer direction
368 *
369 * Function finishes with the DMA transfer. After this, the DMA buffer is
370 * unmapped.
371 */
372static void ep93xx_spi_dma_finish(struct spi_master *master,
373 enum dma_data_direction dir)
374{
375 struct ep93xx_spi *espi = spi_master_get_devdata(master);
376 struct dma_chan *chan;
377 struct sg_table *sgt;
378
379 if (dir == DMA_FROM_DEVICE) {
380 chan = espi->dma_rx;
381 sgt = &espi->rx_sgt;
382 } else {
383 chan = espi->dma_tx;
384 sgt = &espi->tx_sgt;
385 }
386
387 dma_unmap_sg(chan->device->dev, sgt->sgl, sgt->nents, dir);
388}
389
390static void ep93xx_spi_dma_callback(void *callback_param)
391{
392 struct spi_master *master = callback_param;
393
394 ep93xx_spi_dma_finish(master, DMA_TO_DEVICE);
395 ep93xx_spi_dma_finish(master, DMA_FROM_DEVICE);
396
397 spi_finalize_current_transfer(master);
398}
399
400static int ep93xx_spi_dma_transfer(struct spi_master *master)
401{
402 struct ep93xx_spi *espi = spi_master_get_devdata(master);
403 struct dma_async_tx_descriptor *rxd, *txd;
404
405 rxd = ep93xx_spi_dma_prepare(master, DMA_FROM_DEVICE);
406 if (IS_ERR(rxd)) {
407 dev_err(&master->dev, "DMA RX failed: %ld\n", PTR_ERR(rxd));
408 return PTR_ERR(rxd);
409 }
410
411 txd = ep93xx_spi_dma_prepare(master, DMA_TO_DEVICE);
412 if (IS_ERR(txd)) {
413 ep93xx_spi_dma_finish(master, DMA_FROM_DEVICE);
414 dev_err(&master->dev, "DMA TX failed: %ld\n", PTR_ERR(txd));
415 return PTR_ERR(txd);
416 }
417
418 /* We are ready when RX is done */
419 rxd->callback = ep93xx_spi_dma_callback;
420 rxd->callback_param = master;
421
422 /* Now submit both descriptors and start DMA */
423 dmaengine_submit(rxd);
424 dmaengine_submit(txd);
425
426 dma_async_issue_pending(espi->dma_rx);
427 dma_async_issue_pending(espi->dma_tx);
428
429 /* signal that we need to wait for completion */
430 return 1;
431}
432
433static irqreturn_t ep93xx_spi_interrupt(int irq, void *dev_id)
434{
435 struct spi_master *master = dev_id;
436 struct ep93xx_spi *espi = spi_master_get_devdata(master);
437 u32 val;
438
439 /*
440 * If we got ROR (receive overrun) interrupt we know that something is
441 * wrong. Just abort the message.
442 */
443 if (readl(espi->mmio + SSPIIR) & SSPIIR_RORIS) {
444 /* clear the overrun interrupt */
445 writel(0, espi->mmio + SSPICR);
446 dev_warn(&master->dev,
447 "receive overrun, aborting the message\n");
448 master->cur_msg->status = -EIO;
449 } else {
450 /*
451 * Interrupt is either RX (RIS) or TX (TIS). For both cases we
452 * simply execute next data transfer.
453 */
454 if (ep93xx_spi_read_write(master)) {
455 /*
456 * In normal case, there still is some processing left
457 * for current transfer. Let's wait for the next
458 * interrupt then.
459 */
460 return IRQ_HANDLED;
461 }
462 }
463
464 /*
465 * Current transfer is finished, either with error or with success. In
466 * any case we disable interrupts and notify the worker to handle
467 * any post-processing of the message.
468 */
469 val = readl(espi->mmio + SSPCR1);
470 val &= ~(SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE);
471 writel(val, espi->mmio + SSPCR1);
472
473 spi_finalize_current_transfer(master);
474
475 return IRQ_HANDLED;
476}
477
478static int ep93xx_spi_transfer_one(struct spi_master *master,
479 struct spi_device *spi,
480 struct spi_transfer *xfer)
481{
482 struct ep93xx_spi *espi = spi_master_get_devdata(master);
483 u32 val;
484 int ret;
485
486 ret = ep93xx_spi_chip_setup(master, spi, xfer);
487 if (ret) {
488 dev_err(&master->dev, "failed to setup chip for transfer\n");
489 return ret;
490 }
491
492 master->cur_msg->state = xfer;
493 espi->rx = 0;
494 espi->tx = 0;
495
496 /*
497 * There is no point of setting up DMA for the transfers which will
498 * fit into the FIFO and can be transferred with a single interrupt.
499 * So in these cases we will be using PIO and don't bother for DMA.
500 */
501 if (espi->dma_rx && xfer->len > SPI_FIFO_SIZE)
502 return ep93xx_spi_dma_transfer(master);
503
504 /* Using PIO so prime the TX FIFO and enable interrupts */
505 ep93xx_spi_read_write(master);
506
507 val = readl(espi->mmio + SSPCR1);
508 val |= (SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE);
509 writel(val, espi->mmio + SSPCR1);
510
511 /* signal that we need to wait for completion */
512 return 1;
513}
514
515static int ep93xx_spi_prepare_message(struct spi_master *master,
516 struct spi_message *msg)
517{
518 struct ep93xx_spi *espi = spi_master_get_devdata(master);
519 unsigned long timeout;
520
521 /*
522 * Just to be sure: flush any data from RX FIFO.
523 */
524 timeout = jiffies + msecs_to_jiffies(SPI_TIMEOUT);
525 while (readl(espi->mmio + SSPSR) & SSPSR_RNE) {
526 if (time_after(jiffies, timeout)) {
527 dev_warn(&master->dev,
528 "timeout while flushing RX FIFO\n");
529 return -ETIMEDOUT;
530 }
531 readl(espi->mmio + SSPDR);
532 }
533
534 /*
535 * We explicitly handle FIFO level. This way we don't have to check TX
536 * FIFO status using %SSPSR_TNF bit which may cause RX FIFO overruns.
537 */
538 espi->fifo_level = 0;
539
540 return 0;
541}
542
543static int ep93xx_spi_prepare_hardware(struct spi_master *master)
544{
545 struct ep93xx_spi *espi = spi_master_get_devdata(master);
546 u32 val;
547 int ret;
548
549 ret = clk_enable(espi->clk);
550 if (ret)
551 return ret;
552
553 val = readl(espi->mmio + SSPCR1);
554 val |= SSPCR1_SSE;
555 writel(val, espi->mmio + SSPCR1);
556
557 return 0;
558}
559
560static int ep93xx_spi_unprepare_hardware(struct spi_master *master)
561{
562 struct ep93xx_spi *espi = spi_master_get_devdata(master);
563 u32 val;
564
565 val = readl(espi->mmio + SSPCR1);
566 val &= ~SSPCR1_SSE;
567 writel(val, espi->mmio + SSPCR1);
568
569 clk_disable(espi->clk);
570
571 return 0;
572}
573
574static bool ep93xx_spi_dma_filter(struct dma_chan *chan, void *filter_param)
575{
576 if (ep93xx_dma_chan_is_m2p(chan))
577 return false;
578
579 chan->private = filter_param;
580 return true;
581}
582
583static int ep93xx_spi_setup_dma(struct ep93xx_spi *espi)
584{
585 dma_cap_mask_t mask;
586 int ret;
587
588 espi->zeropage = (void *)get_zeroed_page(GFP_KERNEL);
589 if (!espi->zeropage)
590 return -ENOMEM;
591
592 dma_cap_zero(mask);
593 dma_cap_set(DMA_SLAVE, mask);
594
595 espi->dma_rx_data.port = EP93XX_DMA_SSP;
596 espi->dma_rx_data.direction = DMA_DEV_TO_MEM;
597 espi->dma_rx_data.name = "ep93xx-spi-rx";
598
599 espi->dma_rx = dma_request_channel(mask, ep93xx_spi_dma_filter,
600 &espi->dma_rx_data);
601 if (!espi->dma_rx) {
602 ret = -ENODEV;
603 goto fail_free_page;
604 }
605
606 espi->dma_tx_data.port = EP93XX_DMA_SSP;
607 espi->dma_tx_data.direction = DMA_MEM_TO_DEV;
608 espi->dma_tx_data.name = "ep93xx-spi-tx";
609
610 espi->dma_tx = dma_request_channel(mask, ep93xx_spi_dma_filter,
611 &espi->dma_tx_data);
612 if (!espi->dma_tx) {
613 ret = -ENODEV;
614 goto fail_release_rx;
615 }
616
617 return 0;
618
619fail_release_rx:
620 dma_release_channel(espi->dma_rx);
621 espi->dma_rx = NULL;
622fail_free_page:
623 free_page((unsigned long)espi->zeropage);
624
625 return ret;
626}
627
628static void ep93xx_spi_release_dma(struct ep93xx_spi *espi)
629{
630 if (espi->dma_rx) {
631 dma_release_channel(espi->dma_rx);
632 sg_free_table(&espi->rx_sgt);
633 }
634 if (espi->dma_tx) {
635 dma_release_channel(espi->dma_tx);
636 sg_free_table(&espi->tx_sgt);
637 }
638
639 if (espi->zeropage)
640 free_page((unsigned long)espi->zeropage);
641}
642
643static int ep93xx_spi_probe(struct platform_device *pdev)
644{
645 struct spi_master *master;
646 struct ep93xx_spi_info *info;
647 struct ep93xx_spi *espi;
648 struct resource *res;
649 int irq;
650 int error;
651
652 info = dev_get_platdata(&pdev->dev);
653 if (!info) {
654 dev_err(&pdev->dev, "missing platform data\n");
655 return -EINVAL;
656 }
657
658 irq = platform_get_irq(pdev, 0);
659 if (irq < 0)
660 return -EBUSY;
661
662 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
663 if (!res) {
664 dev_err(&pdev->dev, "unable to get iomem resource\n");
665 return -ENODEV;
666 }
667
668 master = spi_alloc_master(&pdev->dev, sizeof(*espi));
669 if (!master)
670 return -ENOMEM;
671
672 master->use_gpio_descriptors = true;
673 master->prepare_transfer_hardware = ep93xx_spi_prepare_hardware;
674 master->unprepare_transfer_hardware = ep93xx_spi_unprepare_hardware;
675 master->prepare_message = ep93xx_spi_prepare_message;
676 master->transfer_one = ep93xx_spi_transfer_one;
677 master->bus_num = pdev->id;
678 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
679 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
680 /*
681 * The SPI core will count the number of GPIO descriptors to figure
682 * out the number of chip selects available on the platform.
683 */
684 master->num_chipselect = 0;
685
686 platform_set_drvdata(pdev, master);
687
688 espi = spi_master_get_devdata(master);
689
690 espi->clk = devm_clk_get(&pdev->dev, NULL);
691 if (IS_ERR(espi->clk)) {
692 dev_err(&pdev->dev, "unable to get spi clock\n");
693 error = PTR_ERR(espi->clk);
694 goto fail_release_master;
695 }
696
697 /*
698 * Calculate maximum and minimum supported clock rates
699 * for the controller.
700 */
701 master->max_speed_hz = clk_get_rate(espi->clk) / 2;
702 master->min_speed_hz = clk_get_rate(espi->clk) / (254 * 256);
703
704 espi->sspdr_phys = res->start + SSPDR;
705
706 espi->mmio = devm_ioremap_resource(&pdev->dev, res);
707 if (IS_ERR(espi->mmio)) {
708 error = PTR_ERR(espi->mmio);
709 goto fail_release_master;
710 }
711
712 error = devm_request_irq(&pdev->dev, irq, ep93xx_spi_interrupt,
713 0, "ep93xx-spi", master);
714 if (error) {
715 dev_err(&pdev->dev, "failed to request irq\n");
716 goto fail_release_master;
717 }
718
719 if (info->use_dma && ep93xx_spi_setup_dma(espi))
720 dev_warn(&pdev->dev, "DMA setup failed. Falling back to PIO\n");
721
722 /* make sure that the hardware is disabled */
723 writel(0, espi->mmio + SSPCR1);
724
725 error = devm_spi_register_master(&pdev->dev, master);
726 if (error) {
727 dev_err(&pdev->dev, "failed to register SPI master\n");
728 goto fail_free_dma;
729 }
730
731 dev_info(&pdev->dev, "EP93xx SPI Controller at 0x%08lx irq %d\n",
732 (unsigned long)res->start, irq);
733
734 return 0;
735
736fail_free_dma:
737 ep93xx_spi_release_dma(espi);
738fail_release_master:
739 spi_master_put(master);
740
741 return error;
742}
743
744static int ep93xx_spi_remove(struct platform_device *pdev)
745{
746 struct spi_master *master = platform_get_drvdata(pdev);
747 struct ep93xx_spi *espi = spi_master_get_devdata(master);
748
749 ep93xx_spi_release_dma(espi);
750
751 return 0;
752}
753
754static struct platform_driver ep93xx_spi_driver = {
755 .driver = {
756 .name = "ep93xx-spi",
757 },
758 .probe = ep93xx_spi_probe,
759 .remove = ep93xx_spi_remove,
760};
761module_platform_driver(ep93xx_spi_driver);
762
763MODULE_DESCRIPTION("EP93xx SPI Controller driver");
764MODULE_AUTHOR("Mika Westerberg <mika.westerberg@iki.fi>");
765MODULE_LICENSE("GPL");
766MODULE_ALIAS("platform:ep93xx-spi");