Loading...
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Intel IXP4xx HSS (synchronous serial port) driver for Linux
4 *
5 * Copyright (C) 2007-2008 Krzysztof Hałasa <khc@pm.waw.pl>
6 */
7
8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
10#include <linux/module.h>
11#include <linux/bitops.h>
12#include <linux/cdev.h>
13#include <linux/dma-mapping.h>
14#include <linux/dmapool.h>
15#include <linux/fs.h>
16#include <linux/hdlc.h>
17#include <linux/io.h>
18#include <linux/kernel.h>
19#include <linux/mfd/syscon.h>
20#include <linux/platform_device.h>
21#include <linux/poll.h>
22#include <linux/regmap.h>
23#include <linux/slab.h>
24#include <linux/gpio/consumer.h>
25#include <linux/of.h>
26#include <linux/soc/ixp4xx/npe.h>
27#include <linux/soc/ixp4xx/qmgr.h>
28#include <linux/soc/ixp4xx/cpu.h>
29
30/* This is what all IXP4xx platforms we know uses, if more frequencies
31 * are needed, we need to migrate to the clock framework.
32 */
33#define IXP4XX_TIMER_FREQ 66666000
34
35#define DEBUG_DESC 0
36#define DEBUG_RX 0
37#define DEBUG_TX 0
38#define DEBUG_PKT_BYTES 0
39#define DEBUG_CLOSE 0
40
41#define DRV_NAME "ixp4xx_hss"
42
43#define PKT_EXTRA_FLAGS 0 /* orig 1 */
44#define PKT_NUM_PIPES 1 /* 1, 2 or 4 */
45#define PKT_PIPE_FIFO_SIZEW 4 /* total 4 dwords per HSS */
46
47#define RX_DESCS 16 /* also length of all RX queues */
48#define TX_DESCS 16 /* also length of all TX queues */
49
50#define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
51#define RX_SIZE (HDLC_MAX_MRU + 4) /* NPE needs more space */
52#define MAX_CLOSE_WAIT 1000 /* microseconds */
53#define HSS_COUNT 2
54#define FRAME_SIZE 256 /* doesn't matter at this point */
55#define FRAME_OFFSET 0
56#define MAX_CHANNELS (FRAME_SIZE / 8)
57
58#define NAPI_WEIGHT 16
59
60/* Queue IDs */
61#define HSS0_PKT_RX_QUEUE 13 /* orig size = 32 dwords */
62#define HSS0_PKT_TX0_QUEUE 14 /* orig size = 16 dwords */
63#define HSS0_PKT_TX1_QUEUE 15
64#define HSS0_PKT_TX2_QUEUE 16
65#define HSS0_PKT_TX3_QUEUE 17
66#define HSS0_PKT_RXFREE0_QUEUE 18 /* orig size = 16 dwords */
67#define HSS0_PKT_RXFREE1_QUEUE 19
68#define HSS0_PKT_RXFREE2_QUEUE 20
69#define HSS0_PKT_RXFREE3_QUEUE 21
70#define HSS0_PKT_TXDONE_QUEUE 22 /* orig size = 64 dwords */
71
72#define HSS1_PKT_RX_QUEUE 0
73#define HSS1_PKT_TX0_QUEUE 5
74#define HSS1_PKT_TX1_QUEUE 6
75#define HSS1_PKT_TX2_QUEUE 7
76#define HSS1_PKT_TX3_QUEUE 8
77#define HSS1_PKT_RXFREE0_QUEUE 1
78#define HSS1_PKT_RXFREE1_QUEUE 2
79#define HSS1_PKT_RXFREE2_QUEUE 3
80#define HSS1_PKT_RXFREE3_QUEUE 4
81#define HSS1_PKT_TXDONE_QUEUE 9
82
83#define NPE_PKT_MODE_HDLC 0
84#define NPE_PKT_MODE_RAW 1
85#define NPE_PKT_MODE_56KMODE 2
86#define NPE_PKT_MODE_56KENDIAN_MSB 4
87
88/* PKT_PIPE_HDLC_CFG_WRITE flags */
89#define PKT_HDLC_IDLE_ONES 0x1 /* default = flags */
90#define PKT_HDLC_CRC_32 0x2 /* default = CRC-16 */
91#define PKT_HDLC_MSB_ENDIAN 0x4 /* default = LE */
92
93/* hss_config, PCRs */
94/* Frame sync sampling, default = active low */
95#define PCR_FRM_SYNC_ACTIVE_HIGH 0x40000000
96#define PCR_FRM_SYNC_FALLINGEDGE 0x80000000
97#define PCR_FRM_SYNC_RISINGEDGE 0xC0000000
98
99/* Frame sync pin: input (default) or output generated off a given clk edge */
100#define PCR_FRM_SYNC_OUTPUT_FALLING 0x20000000
101#define PCR_FRM_SYNC_OUTPUT_RISING 0x30000000
102
103/* Frame and data clock sampling on edge, default = falling */
104#define PCR_FCLK_EDGE_RISING 0x08000000
105#define PCR_DCLK_EDGE_RISING 0x04000000
106
107/* Clock direction, default = input */
108#define PCR_SYNC_CLK_DIR_OUTPUT 0x02000000
109
110/* Generate/Receive frame pulses, default = enabled */
111#define PCR_FRM_PULSE_DISABLED 0x01000000
112
113 /* Data rate is full (default) or half the configured clk speed */
114#define PCR_HALF_CLK_RATE 0x00200000
115
116/* Invert data between NPE and HSS FIFOs? (default = no) */
117#define PCR_DATA_POLARITY_INVERT 0x00100000
118
119/* TX/RX endianness, default = LSB */
120#define PCR_MSB_ENDIAN 0x00080000
121
122/* Normal (default) / open drain mode (TX only) */
123#define PCR_TX_PINS_OPEN_DRAIN 0x00040000
124
125/* No framing bit transmitted and expected on RX? (default = framing bit) */
126#define PCR_SOF_NO_FBIT 0x00020000
127
128/* Drive data pins? */
129#define PCR_TX_DATA_ENABLE 0x00010000
130
131/* Voice 56k type: drive the data pins low (default), high, high Z */
132#define PCR_TX_V56K_HIGH 0x00002000
133#define PCR_TX_V56K_HIGH_IMP 0x00004000
134
135/* Unassigned type: drive the data pins low (default), high, high Z */
136#define PCR_TX_UNASS_HIGH 0x00000800
137#define PCR_TX_UNASS_HIGH_IMP 0x00001000
138
139/* T1 @ 1.544MHz only: Fbit dictated in FIFO (default) or high Z */
140#define PCR_TX_FB_HIGH_IMP 0x00000400
141
142/* 56k data endiannes - which bit unused: high (default) or low */
143#define PCR_TX_56KE_BIT_0_UNUSED 0x00000200
144
145/* 56k data transmission type: 32/8 bit data (default) or 56K data */
146#define PCR_TX_56KS_56K_DATA 0x00000100
147
148/* hss_config, cCR */
149/* Number of packetized clients, default = 1 */
150#define CCR_NPE_HFIFO_2_HDLC 0x04000000
151#define CCR_NPE_HFIFO_3_OR_4HDLC 0x08000000
152
153/* default = no loopback */
154#define CCR_LOOPBACK 0x02000000
155
156/* HSS number, default = 0 (first) */
157#define CCR_SECOND_HSS 0x01000000
158
159/* hss_config, clkCR: main:10, num:10, denom:12 */
160#define CLK42X_SPEED_EXP ((0x3FF << 22) | (2 << 12) | 15) /*65 KHz*/
161
162#define CLK42X_SPEED_512KHZ ((130 << 22) | (2 << 12) | 15)
163#define CLK42X_SPEED_1536KHZ ((43 << 22) | (18 << 12) | 47)
164#define CLK42X_SPEED_1544KHZ ((43 << 22) | (33 << 12) | 192)
165#define CLK42X_SPEED_2048KHZ ((32 << 22) | (34 << 12) | 63)
166#define CLK42X_SPEED_4096KHZ ((16 << 22) | (34 << 12) | 127)
167#define CLK42X_SPEED_8192KHZ ((8 << 22) | (34 << 12) | 255)
168
169#define CLK46X_SPEED_512KHZ ((130 << 22) | (24 << 12) | 127)
170#define CLK46X_SPEED_1536KHZ ((43 << 22) | (152 << 12) | 383)
171#define CLK46X_SPEED_1544KHZ ((43 << 22) | (66 << 12) | 385)
172#define CLK46X_SPEED_2048KHZ ((32 << 22) | (280 << 12) | 511)
173#define CLK46X_SPEED_4096KHZ ((16 << 22) | (280 << 12) | 1023)
174#define CLK46X_SPEED_8192KHZ ((8 << 22) | (280 << 12) | 2047)
175
176/* HSS_CONFIG_CLOCK_CR register consists of 3 parts:
177 * A (10 bits), B (10 bits) and C (12 bits).
178 * IXP42x HSS clock generator operation (verified with an oscilloscope):
179 * Each clock bit takes 7.5 ns (1 / 133.xx MHz).
180 * The clock sequence consists of (C - B) states of 0s and 1s, each state is
181 * A bits wide. It's followed by (B + 1) states of 0s and 1s, each state is
182 * (A + 1) bits wide.
183 *
184 * The resulting average clock frequency (assuming 33.333 MHz oscillator) is:
185 * freq = 66.666 MHz / (A + (B + 1) / (C + 1))
186 * minimum freq = 66.666 MHz / (A + 1)
187 * maximum freq = 66.666 MHz / A
188 *
189 * Example: A = 2, B = 2, C = 7, CLOCK_CR register = 2 << 22 | 2 << 12 | 7
190 * freq = 66.666 MHz / (2 + (2 + 1) / (7 + 1)) = 28.07 MHz (Mb/s).
191 * The clock sequence is: 1100110011 (5 doubles) 000111000 (3 triples).
192 * The sequence takes (C - B) * A + (B + 1) * (A + 1) = 5 * 2 + 3 * 3 bits
193 * = 19 bits (each 7.5 ns long) = 142.5 ns (then the sequence repeats).
194 * The sequence consists of 4 complete clock periods, thus the average
195 * frequency (= clock rate) is 4 / 142.5 ns = 28.07 MHz (Mb/s).
196 * (max specified clock rate for IXP42x HSS is 8.192 Mb/s).
197 */
198
199/* hss_config, LUT entries */
200#define TDMMAP_UNASSIGNED 0
201#define TDMMAP_HDLC 1 /* HDLC - packetized */
202#define TDMMAP_VOICE56K 2 /* Voice56K - 7-bit channelized */
203#define TDMMAP_VOICE64K 3 /* Voice64K - 8-bit channelized */
204
205/* offsets into HSS config */
206#define HSS_CONFIG_TX_PCR 0x00 /* port configuration registers */
207#define HSS_CONFIG_RX_PCR 0x04
208#define HSS_CONFIG_CORE_CR 0x08 /* loopback control, HSS# */
209#define HSS_CONFIG_CLOCK_CR 0x0C /* clock generator control */
210#define HSS_CONFIG_TX_FCR 0x10 /* frame configuration registers */
211#define HSS_CONFIG_RX_FCR 0x14
212#define HSS_CONFIG_TX_LUT 0x18 /* channel look-up tables */
213#define HSS_CONFIG_RX_LUT 0x38
214
215/* NPE command codes */
216/* writes the ConfigWord value to the location specified by offset */
217#define PORT_CONFIG_WRITE 0x40
218
219/* triggers the NPE to load the contents of the configuration table */
220#define PORT_CONFIG_LOAD 0x41
221
222/* triggers the NPE to return an HssErrorReadResponse message */
223#define PORT_ERROR_READ 0x42
224
225/* triggers the NPE to reset internal status and enable the HssPacketized
226 * operation for the flow specified by pPipe
227 */
228#define PKT_PIPE_FLOW_ENABLE 0x50
229#define PKT_PIPE_FLOW_DISABLE 0x51
230#define PKT_NUM_PIPES_WRITE 0x52
231#define PKT_PIPE_FIFO_SIZEW_WRITE 0x53
232#define PKT_PIPE_HDLC_CFG_WRITE 0x54
233#define PKT_PIPE_IDLE_PATTERN_WRITE 0x55
234#define PKT_PIPE_RX_SIZE_WRITE 0x56
235#define PKT_PIPE_MODE_WRITE 0x57
236
237/* HDLC packet status values - desc->status */
238#define ERR_SHUTDOWN 1 /* stop or shutdown occurrence */
239#define ERR_HDLC_ALIGN 2 /* HDLC alignment error */
240#define ERR_HDLC_FCS 3 /* HDLC Frame Check Sum error */
241#define ERR_RXFREE_Q_EMPTY 4 /* RX-free queue became empty while receiving
242 * this packet (if buf_len < pkt_len)
243 */
244#define ERR_HDLC_TOO_LONG 5 /* HDLC frame size too long */
245#define ERR_HDLC_ABORT 6 /* abort sequence received */
246#define ERR_DISCONNECTING 7 /* disconnect is in progress */
247
248#ifdef __ARMEB__
249typedef struct sk_buff buffer_t;
250#define free_buffer dev_kfree_skb
251#define free_buffer_irq dev_consume_skb_irq
252#else
253typedef void buffer_t;
254#define free_buffer kfree
255#define free_buffer_irq kfree
256#endif
257
258struct port {
259 struct device *dev;
260 struct npe *npe;
261 unsigned int txreadyq;
262 unsigned int rxtrigq;
263 unsigned int rxfreeq;
264 unsigned int rxq;
265 unsigned int txq;
266 unsigned int txdoneq;
267 struct gpio_desc *cts;
268 struct gpio_desc *rts;
269 struct gpio_desc *dcd;
270 struct gpio_desc *dtr;
271 struct gpio_desc *clk_internal;
272 struct net_device *netdev;
273 struct napi_struct napi;
274 buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
275 struct desc *desc_tab; /* coherent */
276 dma_addr_t desc_tab_phys;
277 unsigned int id;
278 unsigned int clock_type, clock_rate, loopback;
279 unsigned int initialized, carrier;
280 u8 hdlc_cfg;
281 u32 clock_reg;
282};
283
284/* NPE message structure */
285struct msg {
286#ifdef __ARMEB__
287 u8 cmd, unused, hss_port, index;
288 union {
289 struct { u8 data8a, data8b, data8c, data8d; };
290 struct { u16 data16a, data16b; };
291 struct { u32 data32; };
292 };
293#else
294 u8 index, hss_port, unused, cmd;
295 union {
296 struct { u8 data8d, data8c, data8b, data8a; };
297 struct { u16 data16b, data16a; };
298 struct { u32 data32; };
299 };
300#endif
301};
302
303/* HDLC packet descriptor */
304struct desc {
305 u32 next; /* pointer to next buffer, unused */
306
307#ifdef __ARMEB__
308 u16 buf_len; /* buffer length */
309 u16 pkt_len; /* packet length */
310 u32 data; /* pointer to data buffer in RAM */
311 u8 status;
312 u8 error_count;
313 u16 __reserved;
314#else
315 u16 pkt_len; /* packet length */
316 u16 buf_len; /* buffer length */
317 u32 data; /* pointer to data buffer in RAM */
318 u16 __reserved;
319 u8 error_count;
320 u8 status;
321#endif
322 u32 __reserved1[4];
323};
324
325#define rx_desc_phys(port, n) ((port)->desc_tab_phys + \
326 (n) * sizeof(struct desc))
327#define rx_desc_ptr(port, n) (&(port)->desc_tab[n])
328
329#define tx_desc_phys(port, n) ((port)->desc_tab_phys + \
330 ((n) + RX_DESCS) * sizeof(struct desc))
331#define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS])
332
333/*****************************************************************************
334 * global variables
335 ****************************************************************************/
336
337static int ports_open;
338static struct dma_pool *dma_pool;
339static DEFINE_SPINLOCK(npe_lock);
340
341/*****************************************************************************
342 * utility functions
343 ****************************************************************************/
344
345static inline struct port *dev_to_port(struct net_device *dev)
346{
347 return dev_to_hdlc(dev)->priv;
348}
349
350#ifndef __ARMEB__
351static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
352{
353 int i;
354
355 for (i = 0; i < cnt; i++)
356 dest[i] = swab32(src[i]);
357}
358#endif
359
360/*****************************************************************************
361 * HSS access
362 ****************************************************************************/
363
364static void hss_npe_send(struct port *port, struct msg *msg, const char *what)
365{
366 u32 *val = (u32 *)msg;
367
368 if (npe_send_message(port->npe, msg, what)) {
369 pr_crit("HSS-%i: unable to send command [%08X:%08X] to %s\n",
370 port->id, val[0], val[1], npe_name(port->npe));
371 BUG();
372 }
373}
374
375static void hss_config_set_lut(struct port *port)
376{
377 struct msg msg;
378 int ch;
379
380 memset(&msg, 0, sizeof(msg));
381 msg.cmd = PORT_CONFIG_WRITE;
382 msg.hss_port = port->id;
383
384 for (ch = 0; ch < MAX_CHANNELS; ch++) {
385 msg.data32 >>= 2;
386 msg.data32 |= TDMMAP_HDLC << 30;
387
388 if (ch % 16 == 15) {
389 msg.index = HSS_CONFIG_TX_LUT + ((ch / 4) & ~3);
390 hss_npe_send(port, &msg, "HSS_SET_TX_LUT");
391
392 msg.index += HSS_CONFIG_RX_LUT - HSS_CONFIG_TX_LUT;
393 hss_npe_send(port, &msg, "HSS_SET_RX_LUT");
394 }
395 }
396}
397
398static void hss_config(struct port *port)
399{
400 struct msg msg;
401
402 memset(&msg, 0, sizeof(msg));
403 msg.cmd = PORT_CONFIG_WRITE;
404 msg.hss_port = port->id;
405 msg.index = HSS_CONFIG_TX_PCR;
406 msg.data32 = PCR_FRM_PULSE_DISABLED | PCR_MSB_ENDIAN |
407 PCR_TX_DATA_ENABLE | PCR_SOF_NO_FBIT;
408 if (port->clock_type == CLOCK_INT)
409 msg.data32 |= PCR_SYNC_CLK_DIR_OUTPUT;
410 hss_npe_send(port, &msg, "HSS_SET_TX_PCR");
411
412 msg.index = HSS_CONFIG_RX_PCR;
413 msg.data32 ^= PCR_TX_DATA_ENABLE | PCR_DCLK_EDGE_RISING;
414 hss_npe_send(port, &msg, "HSS_SET_RX_PCR");
415
416 memset(&msg, 0, sizeof(msg));
417 msg.cmd = PORT_CONFIG_WRITE;
418 msg.hss_port = port->id;
419 msg.index = HSS_CONFIG_CORE_CR;
420 msg.data32 = (port->loopback ? CCR_LOOPBACK : 0) |
421 (port->id ? CCR_SECOND_HSS : 0);
422 hss_npe_send(port, &msg, "HSS_SET_CORE_CR");
423
424 memset(&msg, 0, sizeof(msg));
425 msg.cmd = PORT_CONFIG_WRITE;
426 msg.hss_port = port->id;
427 msg.index = HSS_CONFIG_CLOCK_CR;
428 msg.data32 = port->clock_reg;
429 hss_npe_send(port, &msg, "HSS_SET_CLOCK_CR");
430
431 memset(&msg, 0, sizeof(msg));
432 msg.cmd = PORT_CONFIG_WRITE;
433 msg.hss_port = port->id;
434 msg.index = HSS_CONFIG_TX_FCR;
435 msg.data16a = FRAME_OFFSET;
436 msg.data16b = FRAME_SIZE - 1;
437 hss_npe_send(port, &msg, "HSS_SET_TX_FCR");
438
439 memset(&msg, 0, sizeof(msg));
440 msg.cmd = PORT_CONFIG_WRITE;
441 msg.hss_port = port->id;
442 msg.index = HSS_CONFIG_RX_FCR;
443 msg.data16a = FRAME_OFFSET;
444 msg.data16b = FRAME_SIZE - 1;
445 hss_npe_send(port, &msg, "HSS_SET_RX_FCR");
446
447 hss_config_set_lut(port);
448
449 memset(&msg, 0, sizeof(msg));
450 msg.cmd = PORT_CONFIG_LOAD;
451 msg.hss_port = port->id;
452 hss_npe_send(port, &msg, "HSS_LOAD_CONFIG");
453
454 if (npe_recv_message(port->npe, &msg, "HSS_LOAD_CONFIG") ||
455 /* HSS_LOAD_CONFIG for port #1 returns port_id = #4 */
456 msg.cmd != PORT_CONFIG_LOAD || msg.data32) {
457 pr_crit("HSS-%i: HSS_LOAD_CONFIG failed\n", port->id);
458 BUG();
459 }
460
461 /* HDLC may stop working without this - check FIXME */
462 npe_recv_message(port->npe, &msg, "FLUSH_IT");
463}
464
465static void hss_set_hdlc_cfg(struct port *port)
466{
467 struct msg msg;
468
469 memset(&msg, 0, sizeof(msg));
470 msg.cmd = PKT_PIPE_HDLC_CFG_WRITE;
471 msg.hss_port = port->id;
472 msg.data8a = port->hdlc_cfg; /* rx_cfg */
473 msg.data8b = port->hdlc_cfg | (PKT_EXTRA_FLAGS << 3); /* tx_cfg */
474 hss_npe_send(port, &msg, "HSS_SET_HDLC_CFG");
475}
476
477static u32 hss_get_status(struct port *port)
478{
479 struct msg msg;
480
481 memset(&msg, 0, sizeof(msg));
482 msg.cmd = PORT_ERROR_READ;
483 msg.hss_port = port->id;
484 hss_npe_send(port, &msg, "PORT_ERROR_READ");
485 if (npe_recv_message(port->npe, &msg, "PORT_ERROR_READ")) {
486 pr_crit("HSS-%i: unable to read HSS status\n", port->id);
487 BUG();
488 }
489
490 return msg.data32;
491}
492
493static void hss_start_hdlc(struct port *port)
494{
495 struct msg msg;
496
497 memset(&msg, 0, sizeof(msg));
498 msg.cmd = PKT_PIPE_FLOW_ENABLE;
499 msg.hss_port = port->id;
500 msg.data32 = 0;
501 hss_npe_send(port, &msg, "HSS_ENABLE_PKT_PIPE");
502}
503
504static void hss_stop_hdlc(struct port *port)
505{
506 struct msg msg;
507
508 memset(&msg, 0, sizeof(msg));
509 msg.cmd = PKT_PIPE_FLOW_DISABLE;
510 msg.hss_port = port->id;
511 hss_npe_send(port, &msg, "HSS_DISABLE_PKT_PIPE");
512 hss_get_status(port); /* make sure it's halted */
513}
514
515static int hss_load_firmware(struct port *port)
516{
517 struct msg msg;
518 int err;
519
520 if (port->initialized)
521 return 0;
522
523 if (!npe_running(port->npe)) {
524 err = npe_load_firmware(port->npe, npe_name(port->npe),
525 port->dev);
526 if (err)
527 return err;
528 }
529
530 /* HDLC mode configuration */
531 memset(&msg, 0, sizeof(msg));
532 msg.cmd = PKT_NUM_PIPES_WRITE;
533 msg.hss_port = port->id;
534 msg.data8a = PKT_NUM_PIPES;
535 hss_npe_send(port, &msg, "HSS_SET_PKT_PIPES");
536
537 msg.cmd = PKT_PIPE_FIFO_SIZEW_WRITE;
538 msg.data8a = PKT_PIPE_FIFO_SIZEW;
539 hss_npe_send(port, &msg, "HSS_SET_PKT_FIFO");
540
541 msg.cmd = PKT_PIPE_MODE_WRITE;
542 msg.data8a = NPE_PKT_MODE_HDLC;
543 /* msg.data8b = inv_mask */
544 /* msg.data8c = or_mask */
545 hss_npe_send(port, &msg, "HSS_SET_PKT_MODE");
546
547 msg.cmd = PKT_PIPE_RX_SIZE_WRITE;
548 msg.data16a = HDLC_MAX_MRU; /* including CRC */
549 hss_npe_send(port, &msg, "HSS_SET_PKT_RX_SIZE");
550
551 msg.cmd = PKT_PIPE_IDLE_PATTERN_WRITE;
552 msg.data32 = 0x7F7F7F7F; /* ??? FIXME */
553 hss_npe_send(port, &msg, "HSS_SET_PKT_IDLE");
554
555 port->initialized = 1;
556 return 0;
557}
558
559/*****************************************************************************
560 * packetized (HDLC) operation
561 ****************************************************************************/
562
563static inline void debug_pkt(struct net_device *dev, const char *func,
564 u8 *data, int len)
565{
566#if DEBUG_PKT_BYTES
567 int i;
568
569 printk(KERN_DEBUG "%s: %s(%i)", dev->name, func, len);
570 for (i = 0; i < len; i++) {
571 if (i >= DEBUG_PKT_BYTES)
572 break;
573 printk("%s%02X", !(i % 4) ? " " : "", data[i]);
574 }
575 printk("\n");
576#endif
577}
578
579static inline void debug_desc(u32 phys, struct desc *desc)
580{
581#if DEBUG_DESC
582 printk(KERN_DEBUG "%X: %X %3X %3X %08X %X %X\n",
583 phys, desc->next, desc->buf_len, desc->pkt_len,
584 desc->data, desc->status, desc->error_count);
585#endif
586}
587
588static inline int queue_get_desc(unsigned int queue, struct port *port,
589 int is_tx)
590{
591 u32 phys, tab_phys, n_desc;
592 struct desc *tab;
593
594 phys = qmgr_get_entry(queue);
595 if (!phys)
596 return -1;
597
598 BUG_ON(phys & 0x1F);
599 tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
600 tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
601 n_desc = (phys - tab_phys) / sizeof(struct desc);
602 BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));
603 debug_desc(phys, &tab[n_desc]);
604 BUG_ON(tab[n_desc].next);
605 return n_desc;
606}
607
608static inline void queue_put_desc(unsigned int queue, u32 phys,
609 struct desc *desc)
610{
611 debug_desc(phys, desc);
612 BUG_ON(phys & 0x1F);
613 qmgr_put_entry(queue, phys);
614 /* Don't check for queue overflow here, we've allocated sufficient
615 * length and queues >= 32 don't support this check anyway.
616 */
617}
618
619static inline void dma_unmap_tx(struct port *port, struct desc *desc)
620{
621#ifdef __ARMEB__
622 dma_unmap_single(&port->netdev->dev, desc->data,
623 desc->buf_len, DMA_TO_DEVICE);
624#else
625 dma_unmap_single(&port->netdev->dev, desc->data & ~3,
626 ALIGN((desc->data & 3) + desc->buf_len, 4),
627 DMA_TO_DEVICE);
628#endif
629}
630
631static void hss_hdlc_set_carrier(void *pdev, int carrier)
632{
633 struct net_device *netdev = pdev;
634 struct port *port = dev_to_port(netdev);
635 unsigned long flags;
636
637 spin_lock_irqsave(&npe_lock, flags);
638 port->carrier = carrier;
639 if (!port->loopback) {
640 if (carrier)
641 netif_carrier_on(netdev);
642 else
643 netif_carrier_off(netdev);
644 }
645 spin_unlock_irqrestore(&npe_lock, flags);
646}
647
648static void hss_hdlc_rx_irq(void *pdev)
649{
650 struct net_device *dev = pdev;
651 struct port *port = dev_to_port(dev);
652
653#if DEBUG_RX
654 printk(KERN_DEBUG "%s: hss_hdlc_rx_irq\n", dev->name);
655#endif
656 qmgr_disable_irq(port->rxq);
657 napi_schedule(&port->napi);
658}
659
660static int hss_hdlc_poll(struct napi_struct *napi, int budget)
661{
662 struct port *port = container_of(napi, struct port, napi);
663 struct net_device *dev = port->netdev;
664 unsigned int rxq = port->rxq;
665 unsigned int rxfreeq = port->rxfreeq;
666 int received = 0;
667
668#if DEBUG_RX
669 printk(KERN_DEBUG "%s: hss_hdlc_poll\n", dev->name);
670#endif
671
672 while (received < budget) {
673 struct sk_buff *skb;
674 struct desc *desc;
675 int n;
676#ifdef __ARMEB__
677 struct sk_buff *temp;
678 u32 phys;
679#endif
680
681 n = queue_get_desc(rxq, port, 0);
682 if (n < 0) {
683#if DEBUG_RX
684 printk(KERN_DEBUG "%s: hss_hdlc_poll"
685 " napi_complete\n", dev->name);
686#endif
687 napi_complete(napi);
688 qmgr_enable_irq(rxq);
689 if (!qmgr_stat_empty(rxq) &&
690 napi_schedule(napi)) {
691#if DEBUG_RX
692 printk(KERN_DEBUG "%s: hss_hdlc_poll"
693 " napi_schedule succeeded\n",
694 dev->name);
695#endif
696 qmgr_disable_irq(rxq);
697 continue;
698 }
699#if DEBUG_RX
700 printk(KERN_DEBUG "%s: hss_hdlc_poll all done\n",
701 dev->name);
702#endif
703 return received; /* all work done */
704 }
705
706 desc = rx_desc_ptr(port, n);
707#if 0 /* FIXME - error_count counts modulo 256, perhaps we should use it */
708 if (desc->error_count)
709 printk(KERN_DEBUG "%s: hss_hdlc_poll status 0x%02X"
710 " errors %u\n", dev->name, desc->status,
711 desc->error_count);
712#endif
713 skb = NULL;
714 switch (desc->status) {
715 case 0:
716#ifdef __ARMEB__
717 skb = netdev_alloc_skb(dev, RX_SIZE);
718 if (skb) {
719 phys = dma_map_single(&dev->dev, skb->data,
720 RX_SIZE,
721 DMA_FROM_DEVICE);
722 if (dma_mapping_error(&dev->dev, phys)) {
723 dev_kfree_skb(skb);
724 skb = NULL;
725 }
726 }
727#else
728 skb = netdev_alloc_skb(dev, desc->pkt_len);
729#endif
730 if (!skb)
731 dev->stats.rx_dropped++;
732 break;
733 case ERR_HDLC_ALIGN:
734 case ERR_HDLC_ABORT:
735 dev->stats.rx_frame_errors++;
736 dev->stats.rx_errors++;
737 break;
738 case ERR_HDLC_FCS:
739 dev->stats.rx_crc_errors++;
740 dev->stats.rx_errors++;
741 break;
742 case ERR_HDLC_TOO_LONG:
743 dev->stats.rx_length_errors++;
744 dev->stats.rx_errors++;
745 break;
746 default: /* FIXME - remove printk */
747 netdev_err(dev, "hss_hdlc_poll: status 0x%02X errors %u\n",
748 desc->status, desc->error_count);
749 dev->stats.rx_errors++;
750 }
751
752 if (!skb) {
753 /* put the desc back on RX-ready queue */
754 desc->buf_len = RX_SIZE;
755 desc->pkt_len = desc->status = 0;
756 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
757 continue;
758 }
759
760 /* process received frame */
761#ifdef __ARMEB__
762 temp = skb;
763 skb = port->rx_buff_tab[n];
764 dma_unmap_single(&dev->dev, desc->data,
765 RX_SIZE, DMA_FROM_DEVICE);
766#else
767 dma_sync_single_for_cpu(&dev->dev, desc->data,
768 RX_SIZE, DMA_FROM_DEVICE);
769 memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],
770 ALIGN(desc->pkt_len, 4) / 4);
771#endif
772 skb_put(skb, desc->pkt_len);
773
774 debug_pkt(dev, "hss_hdlc_poll", skb->data, skb->len);
775
776 skb->protocol = hdlc_type_trans(skb, dev);
777 dev->stats.rx_packets++;
778 dev->stats.rx_bytes += skb->len;
779 netif_receive_skb(skb);
780
781 /* put the new buffer on RX-free queue */
782#ifdef __ARMEB__
783 port->rx_buff_tab[n] = temp;
784 desc->data = phys;
785#endif
786 desc->buf_len = RX_SIZE;
787 desc->pkt_len = 0;
788 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
789 received++;
790 }
791#if DEBUG_RX
792 printk(KERN_DEBUG "hss_hdlc_poll: end, not all work done\n");
793#endif
794 return received; /* not all work done */
795}
796
797static void hss_hdlc_txdone_irq(void *pdev)
798{
799 struct net_device *dev = pdev;
800 struct port *port = dev_to_port(dev);
801 int n_desc;
802
803#if DEBUG_TX
804 printk(KERN_DEBUG DRV_NAME ": hss_hdlc_txdone_irq\n");
805#endif
806 while ((n_desc = queue_get_desc(port->txdoneq,
807 port, 1)) >= 0) {
808 struct desc *desc;
809 int start;
810
811 desc = tx_desc_ptr(port, n_desc);
812
813 dev->stats.tx_packets++;
814 dev->stats.tx_bytes += desc->pkt_len;
815
816 dma_unmap_tx(port, desc);
817#if DEBUG_TX
818 printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq free %p\n",
819 dev->name, port->tx_buff_tab[n_desc]);
820#endif
821 free_buffer_irq(port->tx_buff_tab[n_desc]);
822 port->tx_buff_tab[n_desc] = NULL;
823
824 start = qmgr_stat_below_low_watermark(port->txreadyq);
825 queue_put_desc(port->txreadyq,
826 tx_desc_phys(port, n_desc), desc);
827 if (start) { /* TX-ready queue was empty */
828#if DEBUG_TX
829 printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq xmit"
830 " ready\n", dev->name);
831#endif
832 netif_wake_queue(dev);
833 }
834 }
835}
836
837static int hss_hdlc_xmit(struct sk_buff *skb, struct net_device *dev)
838{
839 struct port *port = dev_to_port(dev);
840 unsigned int txreadyq = port->txreadyq;
841 int len, offset, bytes, n;
842 void *mem;
843 u32 phys;
844 struct desc *desc;
845
846#if DEBUG_TX
847 printk(KERN_DEBUG "%s: hss_hdlc_xmit\n", dev->name);
848#endif
849
850 if (unlikely(skb->len > HDLC_MAX_MRU)) {
851 dev_kfree_skb(skb);
852 dev->stats.tx_errors++;
853 return NETDEV_TX_OK;
854 }
855
856 debug_pkt(dev, "hss_hdlc_xmit", skb->data, skb->len);
857
858 len = skb->len;
859#ifdef __ARMEB__
860 offset = 0; /* no need to keep alignment */
861 bytes = len;
862 mem = skb->data;
863#else
864 offset = (int)skb->data & 3; /* keep 32-bit alignment */
865 bytes = ALIGN(offset + len, 4);
866 mem = kmalloc(bytes, GFP_ATOMIC);
867 if (!mem) {
868 dev_kfree_skb(skb);
869 dev->stats.tx_dropped++;
870 return NETDEV_TX_OK;
871 }
872 memcpy_swab32(mem, (u32 *)((uintptr_t)skb->data & ~3), bytes / 4);
873 dev_kfree_skb(skb);
874#endif
875
876 phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
877 if (dma_mapping_error(&dev->dev, phys)) {
878#ifdef __ARMEB__
879 dev_kfree_skb(skb);
880#else
881 kfree(mem);
882#endif
883 dev->stats.tx_dropped++;
884 return NETDEV_TX_OK;
885 }
886
887 n = queue_get_desc(txreadyq, port, 1);
888 BUG_ON(n < 0);
889 desc = tx_desc_ptr(port, n);
890
891#ifdef __ARMEB__
892 port->tx_buff_tab[n] = skb;
893#else
894 port->tx_buff_tab[n] = mem;
895#endif
896 desc->data = phys + offset;
897 desc->buf_len = desc->pkt_len = len;
898
899 wmb();
900 queue_put_desc(port->txq, tx_desc_phys(port, n), desc);
901
902 if (qmgr_stat_below_low_watermark(txreadyq)) { /* empty */
903#if DEBUG_TX
904 printk(KERN_DEBUG "%s: hss_hdlc_xmit queue full\n", dev->name);
905#endif
906 netif_stop_queue(dev);
907 /* we could miss TX ready interrupt */
908 if (!qmgr_stat_below_low_watermark(txreadyq)) {
909#if DEBUG_TX
910 printk(KERN_DEBUG "%s: hss_hdlc_xmit ready again\n",
911 dev->name);
912#endif
913 netif_wake_queue(dev);
914 }
915 }
916
917#if DEBUG_TX
918 printk(KERN_DEBUG "%s: hss_hdlc_xmit end\n", dev->name);
919#endif
920 return NETDEV_TX_OK;
921}
922
923static int request_hdlc_queues(struct port *port)
924{
925 int err;
926
927 err = qmgr_request_queue(port->rxfreeq, RX_DESCS, 0, 0,
928 "%s:RX-free", port->netdev->name);
929 if (err)
930 return err;
931
932 err = qmgr_request_queue(port->rxq, RX_DESCS, 0, 0,
933 "%s:RX", port->netdev->name);
934 if (err)
935 goto rel_rxfree;
936
937 err = qmgr_request_queue(port->txq, TX_DESCS, 0, 0,
938 "%s:TX", port->netdev->name);
939 if (err)
940 goto rel_rx;
941
942 err = qmgr_request_queue(port->txreadyq, TX_DESCS, 0, 0,
943 "%s:TX-ready", port->netdev->name);
944 if (err)
945 goto rel_tx;
946
947 err = qmgr_request_queue(port->txdoneq, TX_DESCS, 0, 0,
948 "%s:TX-done", port->netdev->name);
949 if (err)
950 goto rel_txready;
951 return 0;
952
953rel_txready:
954 qmgr_release_queue(port->txreadyq);
955rel_tx:
956 qmgr_release_queue(port->txq);
957rel_rx:
958 qmgr_release_queue(port->rxq);
959rel_rxfree:
960 qmgr_release_queue(port->rxfreeq);
961 printk(KERN_DEBUG "%s: unable to request hardware queues\n",
962 port->netdev->name);
963 return err;
964}
965
966static void release_hdlc_queues(struct port *port)
967{
968 qmgr_release_queue(port->rxfreeq);
969 qmgr_release_queue(port->rxq);
970 qmgr_release_queue(port->txdoneq);
971 qmgr_release_queue(port->txq);
972 qmgr_release_queue(port->txreadyq);
973}
974
975static int init_hdlc_queues(struct port *port)
976{
977 int i;
978
979 if (!ports_open) {
980 dma_pool = dma_pool_create(DRV_NAME, &port->netdev->dev,
981 POOL_ALLOC_SIZE, 32, 0);
982 if (!dma_pool)
983 return -ENOMEM;
984 }
985
986 port->desc_tab = dma_pool_zalloc(dma_pool, GFP_KERNEL,
987 &port->desc_tab_phys);
988 if (!port->desc_tab)
989 return -ENOMEM;
990 memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */
991 memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
992
993 /* Setup RX buffers */
994 for (i = 0; i < RX_DESCS; i++) {
995 struct desc *desc = rx_desc_ptr(port, i);
996 buffer_t *buff;
997 void *data;
998#ifdef __ARMEB__
999 buff = netdev_alloc_skb(port->netdev, RX_SIZE);
1000 if (!buff)
1001 return -ENOMEM;
1002 data = buff->data;
1003#else
1004 buff = kmalloc(RX_SIZE, GFP_KERNEL);
1005 if (!buff)
1006 return -ENOMEM;
1007 data = buff;
1008#endif
1009 desc->buf_len = RX_SIZE;
1010 desc->data = dma_map_single(&port->netdev->dev, data,
1011 RX_SIZE, DMA_FROM_DEVICE);
1012 if (dma_mapping_error(&port->netdev->dev, desc->data)) {
1013 free_buffer(buff);
1014 return -EIO;
1015 }
1016 port->rx_buff_tab[i] = buff;
1017 }
1018
1019 return 0;
1020}
1021
1022static void destroy_hdlc_queues(struct port *port)
1023{
1024 int i;
1025
1026 if (port->desc_tab) {
1027 for (i = 0; i < RX_DESCS; i++) {
1028 struct desc *desc = rx_desc_ptr(port, i);
1029 buffer_t *buff = port->rx_buff_tab[i];
1030
1031 if (buff) {
1032 dma_unmap_single(&port->netdev->dev,
1033 desc->data, RX_SIZE,
1034 DMA_FROM_DEVICE);
1035 free_buffer(buff);
1036 }
1037 }
1038 for (i = 0; i < TX_DESCS; i++) {
1039 struct desc *desc = tx_desc_ptr(port, i);
1040 buffer_t *buff = port->tx_buff_tab[i];
1041
1042 if (buff) {
1043 dma_unmap_tx(port, desc);
1044 free_buffer(buff);
1045 }
1046 }
1047 dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
1048 port->desc_tab = NULL;
1049 }
1050
1051 if (!ports_open && dma_pool) {
1052 dma_pool_destroy(dma_pool);
1053 dma_pool = NULL;
1054 }
1055}
1056
1057static irqreturn_t hss_hdlc_dcd_irq(int irq, void *data)
1058{
1059 struct net_device *dev = data;
1060 struct port *port = dev_to_port(dev);
1061 int val;
1062
1063 val = gpiod_get_value(port->dcd);
1064 hss_hdlc_set_carrier(dev, val);
1065
1066 return IRQ_HANDLED;
1067}
1068
1069static int hss_hdlc_open(struct net_device *dev)
1070{
1071 struct port *port = dev_to_port(dev);
1072 unsigned long flags;
1073 int i, err = 0;
1074 int val;
1075
1076 err = hdlc_open(dev);
1077 if (err)
1078 return err;
1079
1080 err = hss_load_firmware(port);
1081 if (err)
1082 goto err_hdlc_close;
1083
1084 err = request_hdlc_queues(port);
1085 if (err)
1086 goto err_hdlc_close;
1087
1088 err = init_hdlc_queues(port);
1089 if (err)
1090 goto err_destroy_queues;
1091
1092 spin_lock_irqsave(&npe_lock, flags);
1093
1094 /* Set the carrier, the GPIO is flagged active low so this will return
1095 * 1 if DCD is asserted.
1096 */
1097 val = gpiod_get_value(port->dcd);
1098 hss_hdlc_set_carrier(dev, val);
1099
1100 /* Set up an IRQ for DCD */
1101 err = request_irq(gpiod_to_irq(port->dcd), hss_hdlc_dcd_irq, 0, "IXP4xx HSS", dev);
1102 if (err) {
1103 dev_err(&dev->dev, "ixp4xx_hss: failed to request DCD IRQ (%i)\n", err);
1104 goto err_unlock;
1105 }
1106
1107 /* GPIOs are flagged active low so this asserts DTR and RTS */
1108 gpiod_set_value(port->dtr, 1);
1109 gpiod_set_value(port->rts, 1);
1110
1111 spin_unlock_irqrestore(&npe_lock, flags);
1112
1113 /* Populate queues with buffers, no failure after this point */
1114 for (i = 0; i < TX_DESCS; i++)
1115 queue_put_desc(port->txreadyq,
1116 tx_desc_phys(port, i), tx_desc_ptr(port, i));
1117
1118 for (i = 0; i < RX_DESCS; i++)
1119 queue_put_desc(port->rxfreeq,
1120 rx_desc_phys(port, i), rx_desc_ptr(port, i));
1121
1122 napi_enable(&port->napi);
1123 netif_start_queue(dev);
1124
1125 qmgr_set_irq(port->rxq, QUEUE_IRQ_SRC_NOT_EMPTY,
1126 hss_hdlc_rx_irq, dev);
1127
1128 qmgr_set_irq(port->txdoneq, QUEUE_IRQ_SRC_NOT_EMPTY,
1129 hss_hdlc_txdone_irq, dev);
1130 qmgr_enable_irq(port->txdoneq);
1131
1132 ports_open++;
1133
1134 hss_set_hdlc_cfg(port);
1135 hss_config(port);
1136
1137 hss_start_hdlc(port);
1138
1139 /* we may already have RX data, enables IRQ */
1140 napi_schedule(&port->napi);
1141 return 0;
1142
1143err_unlock:
1144 spin_unlock_irqrestore(&npe_lock, flags);
1145err_destroy_queues:
1146 destroy_hdlc_queues(port);
1147 release_hdlc_queues(port);
1148err_hdlc_close:
1149 hdlc_close(dev);
1150 return err;
1151}
1152
1153static int hss_hdlc_close(struct net_device *dev)
1154{
1155 struct port *port = dev_to_port(dev);
1156 unsigned long flags;
1157 int i, buffs = RX_DESCS; /* allocated RX buffers */
1158
1159 spin_lock_irqsave(&npe_lock, flags);
1160 ports_open--;
1161 qmgr_disable_irq(port->rxq);
1162 netif_stop_queue(dev);
1163 napi_disable(&port->napi);
1164
1165 hss_stop_hdlc(port);
1166
1167 while (queue_get_desc(port->rxfreeq, port, 0) >= 0)
1168 buffs--;
1169 while (queue_get_desc(port->rxq, port, 0) >= 0)
1170 buffs--;
1171
1172 if (buffs)
1173 netdev_crit(dev, "unable to drain RX queue, %i buffer(s) left in NPE\n",
1174 buffs);
1175
1176 buffs = TX_DESCS;
1177 while (queue_get_desc(port->txq, port, 1) >= 0)
1178 buffs--; /* cancel TX */
1179
1180 i = 0;
1181 do {
1182 while (queue_get_desc(port->txreadyq, port, 1) >= 0)
1183 buffs--;
1184 if (!buffs)
1185 break;
1186 } while (++i < MAX_CLOSE_WAIT);
1187
1188 if (buffs)
1189 netdev_crit(dev, "unable to drain TX queue, %i buffer(s) left in NPE\n",
1190 buffs);
1191#if DEBUG_CLOSE
1192 if (!buffs)
1193 printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i);
1194#endif
1195 qmgr_disable_irq(port->txdoneq);
1196
1197 free_irq(gpiod_to_irq(port->dcd), dev);
1198 /* GPIOs are flagged active low so this de-asserts DTR and RTS */
1199 gpiod_set_value(port->dtr, 0);
1200 gpiod_set_value(port->rts, 0);
1201 spin_unlock_irqrestore(&npe_lock, flags);
1202
1203 destroy_hdlc_queues(port);
1204 release_hdlc_queues(port);
1205 hdlc_close(dev);
1206 return 0;
1207}
1208
1209static int hss_hdlc_attach(struct net_device *dev, unsigned short encoding,
1210 unsigned short parity)
1211{
1212 struct port *port = dev_to_port(dev);
1213
1214 if (encoding != ENCODING_NRZ)
1215 return -EINVAL;
1216
1217 switch (parity) {
1218 case PARITY_CRC16_PR1_CCITT:
1219 port->hdlc_cfg = 0;
1220 return 0;
1221
1222 case PARITY_CRC32_PR1_CCITT:
1223 port->hdlc_cfg = PKT_HDLC_CRC_32;
1224 return 0;
1225
1226 default:
1227 return -EINVAL;
1228 }
1229}
1230
1231static u32 check_clock(u32 timer_freq, u32 rate, u32 a, u32 b, u32 c,
1232 u32 *best, u32 *best_diff, u32 *reg)
1233{
1234 /* a is 10-bit, b is 10-bit, c is 12-bit */
1235 u64 new_rate;
1236 u32 new_diff;
1237
1238 new_rate = timer_freq * (u64)(c + 1);
1239 do_div(new_rate, a * (c + 1) + b + 1);
1240 new_diff = abs((u32)new_rate - rate);
1241
1242 if (new_diff < *best_diff) {
1243 *best = new_rate;
1244 *best_diff = new_diff;
1245 *reg = (a << 22) | (b << 12) | c;
1246 }
1247 return new_diff;
1248}
1249
1250static void find_best_clock(u32 timer_freq, u32 rate, u32 *best, u32 *reg)
1251{
1252 u32 a, b, diff = 0xFFFFFFFF;
1253
1254 a = timer_freq / rate;
1255
1256 if (a > 0x3FF) { /* 10-bit value - we can go as slow as ca. 65 kb/s */
1257 check_clock(timer_freq, rate, 0x3FF, 1, 1, best, &diff, reg);
1258 return;
1259 }
1260 if (a == 0) { /* > 66.666 MHz */
1261 a = 1; /* minimum divider is 1 (a = 0, b = 1, c = 1) */
1262 rate = timer_freq;
1263 }
1264
1265 if (rate * a == timer_freq) { /* don't divide by 0 later */
1266 check_clock(timer_freq, rate, a - 1, 1, 1, best, &diff, reg);
1267 return;
1268 }
1269
1270 for (b = 0; b < 0x400; b++) {
1271 u64 c = (b + 1) * (u64)rate;
1272
1273 do_div(c, timer_freq - rate * a);
1274 c--;
1275 if (c >= 0xFFF) { /* 12-bit - no need to check more 'b's */
1276 if (b == 0 && /* also try a bit higher rate */
1277 !check_clock(timer_freq, rate, a - 1, 1, 1, best,
1278 &diff, reg))
1279 return;
1280 check_clock(timer_freq, rate, a, b, 0xFFF, best,
1281 &diff, reg);
1282 return;
1283 }
1284 if (!check_clock(timer_freq, rate, a, b, c, best, &diff, reg))
1285 return;
1286 if (!check_clock(timer_freq, rate, a, b, c + 1, best, &diff,
1287 reg))
1288 return;
1289 }
1290}
1291
1292static int hss_hdlc_set_clock(struct port *port, unsigned int clock_type)
1293{
1294 switch (clock_type) {
1295 case CLOCK_DEFAULT:
1296 case CLOCK_EXT:
1297 gpiod_set_value(port->clk_internal, 0);
1298 return CLOCK_EXT;
1299 case CLOCK_INT:
1300 gpiod_set_value(port->clk_internal, 1);
1301 return CLOCK_INT;
1302 default:
1303 return -EINVAL;
1304 }
1305}
1306
1307static int hss_hdlc_ioctl(struct net_device *dev, struct if_settings *ifs)
1308{
1309 const size_t size = sizeof(sync_serial_settings);
1310 sync_serial_settings new_line;
1311 sync_serial_settings __user *line = ifs->ifs_ifsu.sync;
1312 struct port *port = dev_to_port(dev);
1313 unsigned long flags;
1314 int clk;
1315
1316 switch (ifs->type) {
1317 case IF_GET_IFACE:
1318 ifs->type = IF_IFACE_V35;
1319 if (ifs->size < size) {
1320 ifs->size = size; /* data size wanted */
1321 return -ENOBUFS;
1322 }
1323 memset(&new_line, 0, sizeof(new_line));
1324 new_line.clock_type = port->clock_type;
1325 new_line.clock_rate = port->clock_rate;
1326 new_line.loopback = port->loopback;
1327 if (copy_to_user(line, &new_line, size))
1328 return -EFAULT;
1329 return 0;
1330
1331 case IF_IFACE_SYNC_SERIAL:
1332 case IF_IFACE_V35:
1333 if (!capable(CAP_NET_ADMIN))
1334 return -EPERM;
1335 if (copy_from_user(&new_line, line, size))
1336 return -EFAULT;
1337
1338 clk = new_line.clock_type;
1339 hss_hdlc_set_clock(port, clk);
1340
1341 if (clk != CLOCK_EXT && clk != CLOCK_INT)
1342 return -EINVAL; /* No such clock setting */
1343
1344 if (new_line.loopback != 0 && new_line.loopback != 1)
1345 return -EINVAL;
1346
1347 port->clock_type = clk; /* Update settings */
1348 if (clk == CLOCK_INT) {
1349 find_best_clock(IXP4XX_TIMER_FREQ,
1350 new_line.clock_rate,
1351 &port->clock_rate, &port->clock_reg);
1352 } else {
1353 port->clock_rate = 0;
1354 port->clock_reg = CLK42X_SPEED_2048KHZ;
1355 }
1356 port->loopback = new_line.loopback;
1357
1358 spin_lock_irqsave(&npe_lock, flags);
1359
1360 if (dev->flags & IFF_UP)
1361 hss_config(port);
1362
1363 if (port->loopback || port->carrier)
1364 netif_carrier_on(port->netdev);
1365 else
1366 netif_carrier_off(port->netdev);
1367 spin_unlock_irqrestore(&npe_lock, flags);
1368
1369 return 0;
1370
1371 default:
1372 return hdlc_ioctl(dev, ifs);
1373 }
1374}
1375
1376/*****************************************************************************
1377 * initialization
1378 ****************************************************************************/
1379
1380static const struct net_device_ops hss_hdlc_ops = {
1381 .ndo_open = hss_hdlc_open,
1382 .ndo_stop = hss_hdlc_close,
1383 .ndo_start_xmit = hdlc_start_xmit,
1384 .ndo_siocwandev = hss_hdlc_ioctl,
1385};
1386
1387static int ixp4xx_hss_probe(struct platform_device *pdev)
1388{
1389 struct of_phandle_args queue_spec;
1390 struct of_phandle_args npe_spec;
1391 struct device *dev = &pdev->dev;
1392 struct net_device *ndev;
1393 struct device_node *np;
1394 struct regmap *rmap;
1395 struct port *port;
1396 hdlc_device *hdlc;
1397 int err;
1398 u32 val;
1399
1400 /*
1401 * Go into the syscon and check if we have the HSS and HDLC
1402 * features available, else this will not work.
1403 */
1404 rmap = syscon_regmap_lookup_by_compatible("syscon");
1405 if (IS_ERR(rmap))
1406 return dev_err_probe(dev, PTR_ERR(rmap),
1407 "failed to look up syscon\n");
1408
1409 val = cpu_ixp4xx_features(rmap);
1410
1411 if ((val & (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS)) !=
1412 (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS)) {
1413 dev_err(dev, "HDLC and HSS feature unavailable in platform\n");
1414 return -ENODEV;
1415 }
1416
1417 np = dev->of_node;
1418
1419 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
1420 if (!port)
1421 return -ENOMEM;
1422
1423 err = of_parse_phandle_with_fixed_args(np, "intel,npe-handle", 1, 0,
1424 &npe_spec);
1425 if (err)
1426 return dev_err_probe(dev, err, "no NPE engine specified\n");
1427 /* NPE ID 0x00, 0x10, 0x20... */
1428 port->npe = npe_request(npe_spec.args[0] << 4);
1429 if (!port->npe) {
1430 dev_err(dev, "unable to obtain NPE instance\n");
1431 return -ENODEV;
1432 }
1433
1434 /* Get the TX ready queue as resource from queue manager */
1435 err = of_parse_phandle_with_fixed_args(np, "intek,queue-chl-txready", 1, 0,
1436 &queue_spec);
1437 if (err)
1438 return dev_err_probe(dev, err, "no txready queue phandle\n");
1439 port->txreadyq = queue_spec.args[0];
1440 /* Get the RX trig queue as resource from queue manager */
1441 err = of_parse_phandle_with_fixed_args(np, "intek,queue-chl-rxtrig", 1, 0,
1442 &queue_spec);
1443 if (err)
1444 return dev_err_probe(dev, err, "no rxtrig queue phandle\n");
1445 port->rxtrigq = queue_spec.args[0];
1446 /* Get the RX queue as resource from queue manager */
1447 err = of_parse_phandle_with_fixed_args(np, "intek,queue-pkt-rx", 1, 0,
1448 &queue_spec);
1449 if (err)
1450 return dev_err_probe(dev, err, "no RX queue phandle\n");
1451 port->rxq = queue_spec.args[0];
1452 /* Get the TX queue as resource from queue manager */
1453 err = of_parse_phandle_with_fixed_args(np, "intek,queue-pkt-tx", 1, 0,
1454 &queue_spec);
1455 if (err)
1456 return dev_err_probe(dev, err, "no RX queue phandle\n");
1457 port->txq = queue_spec.args[0];
1458 /* Get the RX free queue as resource from queue manager */
1459 err = of_parse_phandle_with_fixed_args(np, "intek,queue-pkt-rxfree", 1, 0,
1460 &queue_spec);
1461 if (err)
1462 return dev_err_probe(dev, err, "no RX free queue phandle\n");
1463 port->rxfreeq = queue_spec.args[0];
1464 /* Get the TX done queue as resource from queue manager */
1465 err = of_parse_phandle_with_fixed_args(np, "intek,queue-pkt-txdone", 1, 0,
1466 &queue_spec);
1467 if (err)
1468 return dev_err_probe(dev, err, "no TX done queue phandle\n");
1469 port->txdoneq = queue_spec.args[0];
1470
1471 /* Obtain all the line control GPIOs */
1472 port->cts = devm_gpiod_get(dev, "cts", GPIOD_OUT_LOW);
1473 if (IS_ERR(port->cts))
1474 return dev_err_probe(dev, PTR_ERR(port->cts), "unable to get CTS GPIO\n");
1475 port->rts = devm_gpiod_get(dev, "rts", GPIOD_OUT_LOW);
1476 if (IS_ERR(port->rts))
1477 return dev_err_probe(dev, PTR_ERR(port->rts), "unable to get RTS GPIO\n");
1478 port->dcd = devm_gpiod_get(dev, "dcd", GPIOD_IN);
1479 if (IS_ERR(port->dcd))
1480 return dev_err_probe(dev, PTR_ERR(port->dcd), "unable to get DCD GPIO\n");
1481 port->dtr = devm_gpiod_get(dev, "dtr", GPIOD_OUT_LOW);
1482 if (IS_ERR(port->dtr))
1483 return dev_err_probe(dev, PTR_ERR(port->dtr), "unable to get DTR GPIO\n");
1484 port->clk_internal = devm_gpiod_get(dev, "clk-internal", GPIOD_OUT_LOW);
1485 if (IS_ERR(port->clk_internal))
1486 return dev_err_probe(dev, PTR_ERR(port->clk_internal),
1487 "unable to get CLK internal GPIO\n");
1488
1489 ndev = alloc_hdlcdev(port);
1490 port->netdev = alloc_hdlcdev(port);
1491 if (!port->netdev) {
1492 err = -ENOMEM;
1493 goto err_plat;
1494 }
1495
1496 SET_NETDEV_DEV(ndev, &pdev->dev);
1497 hdlc = dev_to_hdlc(ndev);
1498 hdlc->attach = hss_hdlc_attach;
1499 hdlc->xmit = hss_hdlc_xmit;
1500 ndev->netdev_ops = &hss_hdlc_ops;
1501 ndev->tx_queue_len = 100;
1502 port->clock_type = CLOCK_EXT;
1503 port->clock_rate = 0;
1504 port->clock_reg = CLK42X_SPEED_2048KHZ;
1505 port->id = pdev->id;
1506 port->dev = &pdev->dev;
1507 netif_napi_add_weight(ndev, &port->napi, hss_hdlc_poll, NAPI_WEIGHT);
1508
1509 err = register_hdlc_device(ndev);
1510 if (err)
1511 goto err_free_netdev;
1512
1513 platform_set_drvdata(pdev, port);
1514
1515 netdev_info(ndev, "initialized\n");
1516 return 0;
1517
1518err_free_netdev:
1519 free_netdev(ndev);
1520err_plat:
1521 npe_release(port->npe);
1522 return err;
1523}
1524
1525static void ixp4xx_hss_remove(struct platform_device *pdev)
1526{
1527 struct port *port = platform_get_drvdata(pdev);
1528
1529 unregister_hdlc_device(port->netdev);
1530 free_netdev(port->netdev);
1531 npe_release(port->npe);
1532}
1533
1534static struct platform_driver ixp4xx_hss_driver = {
1535 .driver.name = DRV_NAME,
1536 .probe = ixp4xx_hss_probe,
1537 .remove = ixp4xx_hss_remove,
1538};
1539module_platform_driver(ixp4xx_hss_driver);
1540
1541MODULE_AUTHOR("Krzysztof Halasa");
1542MODULE_DESCRIPTION("Intel IXP4xx HSS driver");
1543MODULE_LICENSE("GPL v2");
1544MODULE_ALIAS("platform:ixp4xx_hss");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Intel IXP4xx HSS (synchronous serial port) driver for Linux
4 *
5 * Copyright (C) 2007-2008 Krzysztof Hałasa <khc@pm.waw.pl>
6 */
7
8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
10#include <linux/module.h>
11#include <linux/bitops.h>
12#include <linux/cdev.h>
13#include <linux/dma-mapping.h>
14#include <linux/dmapool.h>
15#include <linux/fs.h>
16#include <linux/hdlc.h>
17#include <linux/io.h>
18#include <linux/kernel.h>
19#include <linux/platform_device.h>
20#include <linux/poll.h>
21#include <linux/slab.h>
22#include <linux/soc/ixp4xx/npe.h>
23#include <linux/soc/ixp4xx/qmgr.h>
24
25#define DEBUG_DESC 0
26#define DEBUG_RX 0
27#define DEBUG_TX 0
28#define DEBUG_PKT_BYTES 0
29#define DEBUG_CLOSE 0
30
31#define DRV_NAME "ixp4xx_hss"
32
33#define PKT_EXTRA_FLAGS 0 /* orig 1 */
34#define PKT_NUM_PIPES 1 /* 1, 2 or 4 */
35#define PKT_PIPE_FIFO_SIZEW 4 /* total 4 dwords per HSS */
36
37#define RX_DESCS 16 /* also length of all RX queues */
38#define TX_DESCS 16 /* also length of all TX queues */
39
40#define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
41#define RX_SIZE (HDLC_MAX_MRU + 4) /* NPE needs more space */
42#define MAX_CLOSE_WAIT 1000 /* microseconds */
43#define HSS_COUNT 2
44#define FRAME_SIZE 256 /* doesn't matter at this point */
45#define FRAME_OFFSET 0
46#define MAX_CHANNELS (FRAME_SIZE / 8)
47
48#define NAPI_WEIGHT 16
49
50/* Queue IDs */
51#define HSS0_CHL_RXTRIG_QUEUE 12 /* orig size = 32 dwords */
52#define HSS0_PKT_RX_QUEUE 13 /* orig size = 32 dwords */
53#define HSS0_PKT_TX0_QUEUE 14 /* orig size = 16 dwords */
54#define HSS0_PKT_TX1_QUEUE 15
55#define HSS0_PKT_TX2_QUEUE 16
56#define HSS0_PKT_TX3_QUEUE 17
57#define HSS0_PKT_RXFREE0_QUEUE 18 /* orig size = 16 dwords */
58#define HSS0_PKT_RXFREE1_QUEUE 19
59#define HSS0_PKT_RXFREE2_QUEUE 20
60#define HSS0_PKT_RXFREE3_QUEUE 21
61#define HSS0_PKT_TXDONE_QUEUE 22 /* orig size = 64 dwords */
62
63#define HSS1_CHL_RXTRIG_QUEUE 10
64#define HSS1_PKT_RX_QUEUE 0
65#define HSS1_PKT_TX0_QUEUE 5
66#define HSS1_PKT_TX1_QUEUE 6
67#define HSS1_PKT_TX2_QUEUE 7
68#define HSS1_PKT_TX3_QUEUE 8
69#define HSS1_PKT_RXFREE0_QUEUE 1
70#define HSS1_PKT_RXFREE1_QUEUE 2
71#define HSS1_PKT_RXFREE2_QUEUE 3
72#define HSS1_PKT_RXFREE3_QUEUE 4
73#define HSS1_PKT_TXDONE_QUEUE 9
74
75#define NPE_PKT_MODE_HDLC 0
76#define NPE_PKT_MODE_RAW 1
77#define NPE_PKT_MODE_56KMODE 2
78#define NPE_PKT_MODE_56KENDIAN_MSB 4
79
80/* PKT_PIPE_HDLC_CFG_WRITE flags */
81#define PKT_HDLC_IDLE_ONES 0x1 /* default = flags */
82#define PKT_HDLC_CRC_32 0x2 /* default = CRC-16 */
83#define PKT_HDLC_MSB_ENDIAN 0x4 /* default = LE */
84
85
86/* hss_config, PCRs */
87/* Frame sync sampling, default = active low */
88#define PCR_FRM_SYNC_ACTIVE_HIGH 0x40000000
89#define PCR_FRM_SYNC_FALLINGEDGE 0x80000000
90#define PCR_FRM_SYNC_RISINGEDGE 0xC0000000
91
92/* Frame sync pin: input (default) or output generated off a given clk edge */
93#define PCR_FRM_SYNC_OUTPUT_FALLING 0x20000000
94#define PCR_FRM_SYNC_OUTPUT_RISING 0x30000000
95
96/* Frame and data clock sampling on edge, default = falling */
97#define PCR_FCLK_EDGE_RISING 0x08000000
98#define PCR_DCLK_EDGE_RISING 0x04000000
99
100/* Clock direction, default = input */
101#define PCR_SYNC_CLK_DIR_OUTPUT 0x02000000
102
103/* Generate/Receive frame pulses, default = enabled */
104#define PCR_FRM_PULSE_DISABLED 0x01000000
105
106 /* Data rate is full (default) or half the configured clk speed */
107#define PCR_HALF_CLK_RATE 0x00200000
108
109/* Invert data between NPE and HSS FIFOs? (default = no) */
110#define PCR_DATA_POLARITY_INVERT 0x00100000
111
112/* TX/RX endianness, default = LSB */
113#define PCR_MSB_ENDIAN 0x00080000
114
115/* Normal (default) / open drain mode (TX only) */
116#define PCR_TX_PINS_OPEN_DRAIN 0x00040000
117
118/* No framing bit transmitted and expected on RX? (default = framing bit) */
119#define PCR_SOF_NO_FBIT 0x00020000
120
121/* Drive data pins? */
122#define PCR_TX_DATA_ENABLE 0x00010000
123
124/* Voice 56k type: drive the data pins low (default), high, high Z */
125#define PCR_TX_V56K_HIGH 0x00002000
126#define PCR_TX_V56K_HIGH_IMP 0x00004000
127
128/* Unassigned type: drive the data pins low (default), high, high Z */
129#define PCR_TX_UNASS_HIGH 0x00000800
130#define PCR_TX_UNASS_HIGH_IMP 0x00001000
131
132/* T1 @ 1.544MHz only: Fbit dictated in FIFO (default) or high Z */
133#define PCR_TX_FB_HIGH_IMP 0x00000400
134
135/* 56k data endiannes - which bit unused: high (default) or low */
136#define PCR_TX_56KE_BIT_0_UNUSED 0x00000200
137
138/* 56k data transmission type: 32/8 bit data (default) or 56K data */
139#define PCR_TX_56KS_56K_DATA 0x00000100
140
141/* hss_config, cCR */
142/* Number of packetized clients, default = 1 */
143#define CCR_NPE_HFIFO_2_HDLC 0x04000000
144#define CCR_NPE_HFIFO_3_OR_4HDLC 0x08000000
145
146/* default = no loopback */
147#define CCR_LOOPBACK 0x02000000
148
149/* HSS number, default = 0 (first) */
150#define CCR_SECOND_HSS 0x01000000
151
152
153/* hss_config, clkCR: main:10, num:10, denom:12 */
154#define CLK42X_SPEED_EXP ((0x3FF << 22) | ( 2 << 12) | 15) /*65 KHz*/
155
156#define CLK42X_SPEED_512KHZ (( 130 << 22) | ( 2 << 12) | 15)
157#define CLK42X_SPEED_1536KHZ (( 43 << 22) | ( 18 << 12) | 47)
158#define CLK42X_SPEED_1544KHZ (( 43 << 22) | ( 33 << 12) | 192)
159#define CLK42X_SPEED_2048KHZ (( 32 << 22) | ( 34 << 12) | 63)
160#define CLK42X_SPEED_4096KHZ (( 16 << 22) | ( 34 << 12) | 127)
161#define CLK42X_SPEED_8192KHZ (( 8 << 22) | ( 34 << 12) | 255)
162
163#define CLK46X_SPEED_512KHZ (( 130 << 22) | ( 24 << 12) | 127)
164#define CLK46X_SPEED_1536KHZ (( 43 << 22) | (152 << 12) | 383)
165#define CLK46X_SPEED_1544KHZ (( 43 << 22) | ( 66 << 12) | 385)
166#define CLK46X_SPEED_2048KHZ (( 32 << 22) | (280 << 12) | 511)
167#define CLK46X_SPEED_4096KHZ (( 16 << 22) | (280 << 12) | 1023)
168#define CLK46X_SPEED_8192KHZ (( 8 << 22) | (280 << 12) | 2047)
169
170/*
171 * HSS_CONFIG_CLOCK_CR register consists of 3 parts:
172 * A (10 bits), B (10 bits) and C (12 bits).
173 * IXP42x HSS clock generator operation (verified with an oscilloscope):
174 * Each clock bit takes 7.5 ns (1 / 133.xx MHz).
175 * The clock sequence consists of (C - B) states of 0s and 1s, each state is
176 * A bits wide. It's followed by (B + 1) states of 0s and 1s, each state is
177 * (A + 1) bits wide.
178 *
179 * The resulting average clock frequency (assuming 33.333 MHz oscillator) is:
180 * freq = 66.666 MHz / (A + (B + 1) / (C + 1))
181 * minimum freq = 66.666 MHz / (A + 1)
182 * maximum freq = 66.666 MHz / A
183 *
184 * Example: A = 2, B = 2, C = 7, CLOCK_CR register = 2 << 22 | 2 << 12 | 7
185 * freq = 66.666 MHz / (2 + (2 + 1) / (7 + 1)) = 28.07 MHz (Mb/s).
186 * The clock sequence is: 1100110011 (5 doubles) 000111000 (3 triples).
187 * The sequence takes (C - B) * A + (B + 1) * (A + 1) = 5 * 2 + 3 * 3 bits
188 * = 19 bits (each 7.5 ns long) = 142.5 ns (then the sequence repeats).
189 * The sequence consists of 4 complete clock periods, thus the average
190 * frequency (= clock rate) is 4 / 142.5 ns = 28.07 MHz (Mb/s).
191 * (max specified clock rate for IXP42x HSS is 8.192 Mb/s).
192 */
193
194/* hss_config, LUT entries */
195#define TDMMAP_UNASSIGNED 0
196#define TDMMAP_HDLC 1 /* HDLC - packetized */
197#define TDMMAP_VOICE56K 2 /* Voice56K - 7-bit channelized */
198#define TDMMAP_VOICE64K 3 /* Voice64K - 8-bit channelized */
199
200/* offsets into HSS config */
201#define HSS_CONFIG_TX_PCR 0x00 /* port configuration registers */
202#define HSS_CONFIG_RX_PCR 0x04
203#define HSS_CONFIG_CORE_CR 0x08 /* loopback control, HSS# */
204#define HSS_CONFIG_CLOCK_CR 0x0C /* clock generator control */
205#define HSS_CONFIG_TX_FCR 0x10 /* frame configuration registers */
206#define HSS_CONFIG_RX_FCR 0x14
207#define HSS_CONFIG_TX_LUT 0x18 /* channel look-up tables */
208#define HSS_CONFIG_RX_LUT 0x38
209
210
211/* NPE command codes */
212/* writes the ConfigWord value to the location specified by offset */
213#define PORT_CONFIG_WRITE 0x40
214
215/* triggers the NPE to load the contents of the configuration table */
216#define PORT_CONFIG_LOAD 0x41
217
218/* triggers the NPE to return an HssErrorReadResponse message */
219#define PORT_ERROR_READ 0x42
220
221/* triggers the NPE to reset internal status and enable the HssPacketized
222 operation for the flow specified by pPipe */
223#define PKT_PIPE_FLOW_ENABLE 0x50
224#define PKT_PIPE_FLOW_DISABLE 0x51
225#define PKT_NUM_PIPES_WRITE 0x52
226#define PKT_PIPE_FIFO_SIZEW_WRITE 0x53
227#define PKT_PIPE_HDLC_CFG_WRITE 0x54
228#define PKT_PIPE_IDLE_PATTERN_WRITE 0x55
229#define PKT_PIPE_RX_SIZE_WRITE 0x56
230#define PKT_PIPE_MODE_WRITE 0x57
231
232/* HDLC packet status values - desc->status */
233#define ERR_SHUTDOWN 1 /* stop or shutdown occurrence */
234#define ERR_HDLC_ALIGN 2 /* HDLC alignment error */
235#define ERR_HDLC_FCS 3 /* HDLC Frame Check Sum error */
236#define ERR_RXFREE_Q_EMPTY 4 /* RX-free queue became empty while receiving
237 this packet (if buf_len < pkt_len) */
238#define ERR_HDLC_TOO_LONG 5 /* HDLC frame size too long */
239#define ERR_HDLC_ABORT 6 /* abort sequence received */
240#define ERR_DISCONNECTING 7 /* disconnect is in progress */
241
242
243#ifdef __ARMEB__
244typedef struct sk_buff buffer_t;
245#define free_buffer dev_kfree_skb
246#define free_buffer_irq dev_consume_skb_irq
247#else
248typedef void buffer_t;
249#define free_buffer kfree
250#define free_buffer_irq kfree
251#endif
252
253struct port {
254 struct device *dev;
255 struct npe *npe;
256 struct net_device *netdev;
257 struct napi_struct napi;
258 struct hss_plat_info *plat;
259 buffer_t *rx_buff_tab[RX_DESCS], *tx_buff_tab[TX_DESCS];
260 struct desc *desc_tab; /* coherent */
261 u32 desc_tab_phys;
262 unsigned int id;
263 unsigned int clock_type, clock_rate, loopback;
264 unsigned int initialized, carrier;
265 u8 hdlc_cfg;
266 u32 clock_reg;
267};
268
269/* NPE message structure */
270struct msg {
271#ifdef __ARMEB__
272 u8 cmd, unused, hss_port, index;
273 union {
274 struct { u8 data8a, data8b, data8c, data8d; };
275 struct { u16 data16a, data16b; };
276 struct { u32 data32; };
277 };
278#else
279 u8 index, hss_port, unused, cmd;
280 union {
281 struct { u8 data8d, data8c, data8b, data8a; };
282 struct { u16 data16b, data16a; };
283 struct { u32 data32; };
284 };
285#endif
286};
287
288/* HDLC packet descriptor */
289struct desc {
290 u32 next; /* pointer to next buffer, unused */
291
292#ifdef __ARMEB__
293 u16 buf_len; /* buffer length */
294 u16 pkt_len; /* packet length */
295 u32 data; /* pointer to data buffer in RAM */
296 u8 status;
297 u8 error_count;
298 u16 __reserved;
299#else
300 u16 pkt_len; /* packet length */
301 u16 buf_len; /* buffer length */
302 u32 data; /* pointer to data buffer in RAM */
303 u16 __reserved;
304 u8 error_count;
305 u8 status;
306#endif
307 u32 __reserved1[4];
308};
309
310
311#define rx_desc_phys(port, n) ((port)->desc_tab_phys + \
312 (n) * sizeof(struct desc))
313#define rx_desc_ptr(port, n) (&(port)->desc_tab[n])
314
315#define tx_desc_phys(port, n) ((port)->desc_tab_phys + \
316 ((n) + RX_DESCS) * sizeof(struct desc))
317#define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS])
318
319/*****************************************************************************
320 * global variables
321 ****************************************************************************/
322
323static int ports_open;
324static struct dma_pool *dma_pool;
325static spinlock_t npe_lock;
326
327static const struct {
328 int tx, txdone, rx, rxfree;
329}queue_ids[2] = {{HSS0_PKT_TX0_QUEUE, HSS0_PKT_TXDONE_QUEUE, HSS0_PKT_RX_QUEUE,
330 HSS0_PKT_RXFREE0_QUEUE},
331 {HSS1_PKT_TX0_QUEUE, HSS1_PKT_TXDONE_QUEUE, HSS1_PKT_RX_QUEUE,
332 HSS1_PKT_RXFREE0_QUEUE},
333};
334
335/*****************************************************************************
336 * utility functions
337 ****************************************************************************/
338
339static inline struct port* dev_to_port(struct net_device *dev)
340{
341 return dev_to_hdlc(dev)->priv;
342}
343
344#ifndef __ARMEB__
345static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
346{
347 int i;
348 for (i = 0; i < cnt; i++)
349 dest[i] = swab32(src[i]);
350}
351#endif
352
353/*****************************************************************************
354 * HSS access
355 ****************************************************************************/
356
357static void hss_npe_send(struct port *port, struct msg *msg, const char* what)
358{
359 u32 *val = (u32*)msg;
360 if (npe_send_message(port->npe, msg, what)) {
361 pr_crit("HSS-%i: unable to send command [%08X:%08X] to %s\n",
362 port->id, val[0], val[1], npe_name(port->npe));
363 BUG();
364 }
365}
366
367static void hss_config_set_lut(struct port *port)
368{
369 struct msg msg;
370 int ch;
371
372 memset(&msg, 0, sizeof(msg));
373 msg.cmd = PORT_CONFIG_WRITE;
374 msg.hss_port = port->id;
375
376 for (ch = 0; ch < MAX_CHANNELS; ch++) {
377 msg.data32 >>= 2;
378 msg.data32 |= TDMMAP_HDLC << 30;
379
380 if (ch % 16 == 15) {
381 msg.index = HSS_CONFIG_TX_LUT + ((ch / 4) & ~3);
382 hss_npe_send(port, &msg, "HSS_SET_TX_LUT");
383
384 msg.index += HSS_CONFIG_RX_LUT - HSS_CONFIG_TX_LUT;
385 hss_npe_send(port, &msg, "HSS_SET_RX_LUT");
386 }
387 }
388}
389
390static void hss_config(struct port *port)
391{
392 struct msg msg;
393
394 memset(&msg, 0, sizeof(msg));
395 msg.cmd = PORT_CONFIG_WRITE;
396 msg.hss_port = port->id;
397 msg.index = HSS_CONFIG_TX_PCR;
398 msg.data32 = PCR_FRM_PULSE_DISABLED | PCR_MSB_ENDIAN |
399 PCR_TX_DATA_ENABLE | PCR_SOF_NO_FBIT;
400 if (port->clock_type == CLOCK_INT)
401 msg.data32 |= PCR_SYNC_CLK_DIR_OUTPUT;
402 hss_npe_send(port, &msg, "HSS_SET_TX_PCR");
403
404 msg.index = HSS_CONFIG_RX_PCR;
405 msg.data32 ^= PCR_TX_DATA_ENABLE | PCR_DCLK_EDGE_RISING;
406 hss_npe_send(port, &msg, "HSS_SET_RX_PCR");
407
408 memset(&msg, 0, sizeof(msg));
409 msg.cmd = PORT_CONFIG_WRITE;
410 msg.hss_port = port->id;
411 msg.index = HSS_CONFIG_CORE_CR;
412 msg.data32 = (port->loopback ? CCR_LOOPBACK : 0) |
413 (port->id ? CCR_SECOND_HSS : 0);
414 hss_npe_send(port, &msg, "HSS_SET_CORE_CR");
415
416 memset(&msg, 0, sizeof(msg));
417 msg.cmd = PORT_CONFIG_WRITE;
418 msg.hss_port = port->id;
419 msg.index = HSS_CONFIG_CLOCK_CR;
420 msg.data32 = port->clock_reg;
421 hss_npe_send(port, &msg, "HSS_SET_CLOCK_CR");
422
423 memset(&msg, 0, sizeof(msg));
424 msg.cmd = PORT_CONFIG_WRITE;
425 msg.hss_port = port->id;
426 msg.index = HSS_CONFIG_TX_FCR;
427 msg.data16a = FRAME_OFFSET;
428 msg.data16b = FRAME_SIZE - 1;
429 hss_npe_send(port, &msg, "HSS_SET_TX_FCR");
430
431 memset(&msg, 0, sizeof(msg));
432 msg.cmd = PORT_CONFIG_WRITE;
433 msg.hss_port = port->id;
434 msg.index = HSS_CONFIG_RX_FCR;
435 msg.data16a = FRAME_OFFSET;
436 msg.data16b = FRAME_SIZE - 1;
437 hss_npe_send(port, &msg, "HSS_SET_RX_FCR");
438
439 hss_config_set_lut(port);
440
441 memset(&msg, 0, sizeof(msg));
442 msg.cmd = PORT_CONFIG_LOAD;
443 msg.hss_port = port->id;
444 hss_npe_send(port, &msg, "HSS_LOAD_CONFIG");
445
446 if (npe_recv_message(port->npe, &msg, "HSS_LOAD_CONFIG") ||
447 /* HSS_LOAD_CONFIG for port #1 returns port_id = #4 */
448 msg.cmd != PORT_CONFIG_LOAD || msg.data32) {
449 pr_crit("HSS-%i: HSS_LOAD_CONFIG failed\n", port->id);
450 BUG();
451 }
452
453 /* HDLC may stop working without this - check FIXME */
454 npe_recv_message(port->npe, &msg, "FLUSH_IT");
455}
456
457static void hss_set_hdlc_cfg(struct port *port)
458{
459 struct msg msg;
460
461 memset(&msg, 0, sizeof(msg));
462 msg.cmd = PKT_PIPE_HDLC_CFG_WRITE;
463 msg.hss_port = port->id;
464 msg.data8a = port->hdlc_cfg; /* rx_cfg */
465 msg.data8b = port->hdlc_cfg | (PKT_EXTRA_FLAGS << 3); /* tx_cfg */
466 hss_npe_send(port, &msg, "HSS_SET_HDLC_CFG");
467}
468
469static u32 hss_get_status(struct port *port)
470{
471 struct msg msg;
472
473 memset(&msg, 0, sizeof(msg));
474 msg.cmd = PORT_ERROR_READ;
475 msg.hss_port = port->id;
476 hss_npe_send(port, &msg, "PORT_ERROR_READ");
477 if (npe_recv_message(port->npe, &msg, "PORT_ERROR_READ")) {
478 pr_crit("HSS-%i: unable to read HSS status\n", port->id);
479 BUG();
480 }
481
482 return msg.data32;
483}
484
485static void hss_start_hdlc(struct port *port)
486{
487 struct msg msg;
488
489 memset(&msg, 0, sizeof(msg));
490 msg.cmd = PKT_PIPE_FLOW_ENABLE;
491 msg.hss_port = port->id;
492 msg.data32 = 0;
493 hss_npe_send(port, &msg, "HSS_ENABLE_PKT_PIPE");
494}
495
496static void hss_stop_hdlc(struct port *port)
497{
498 struct msg msg;
499
500 memset(&msg, 0, sizeof(msg));
501 msg.cmd = PKT_PIPE_FLOW_DISABLE;
502 msg.hss_port = port->id;
503 hss_npe_send(port, &msg, "HSS_DISABLE_PKT_PIPE");
504 hss_get_status(port); /* make sure it's halted */
505}
506
507static int hss_load_firmware(struct port *port)
508{
509 struct msg msg;
510 int err;
511
512 if (port->initialized)
513 return 0;
514
515 if (!npe_running(port->npe) &&
516 (err = npe_load_firmware(port->npe, npe_name(port->npe),
517 port->dev)))
518 return err;
519
520 /* HDLC mode configuration */
521 memset(&msg, 0, sizeof(msg));
522 msg.cmd = PKT_NUM_PIPES_WRITE;
523 msg.hss_port = port->id;
524 msg.data8a = PKT_NUM_PIPES;
525 hss_npe_send(port, &msg, "HSS_SET_PKT_PIPES");
526
527 msg.cmd = PKT_PIPE_FIFO_SIZEW_WRITE;
528 msg.data8a = PKT_PIPE_FIFO_SIZEW;
529 hss_npe_send(port, &msg, "HSS_SET_PKT_FIFO");
530
531 msg.cmd = PKT_PIPE_MODE_WRITE;
532 msg.data8a = NPE_PKT_MODE_HDLC;
533 /* msg.data8b = inv_mask */
534 /* msg.data8c = or_mask */
535 hss_npe_send(port, &msg, "HSS_SET_PKT_MODE");
536
537 msg.cmd = PKT_PIPE_RX_SIZE_WRITE;
538 msg.data16a = HDLC_MAX_MRU; /* including CRC */
539 hss_npe_send(port, &msg, "HSS_SET_PKT_RX_SIZE");
540
541 msg.cmd = PKT_PIPE_IDLE_PATTERN_WRITE;
542 msg.data32 = 0x7F7F7F7F; /* ??? FIXME */
543 hss_npe_send(port, &msg, "HSS_SET_PKT_IDLE");
544
545 port->initialized = 1;
546 return 0;
547}
548
549/*****************************************************************************
550 * packetized (HDLC) operation
551 ****************************************************************************/
552
553static inline void debug_pkt(struct net_device *dev, const char *func,
554 u8 *data, int len)
555{
556#if DEBUG_PKT_BYTES
557 int i;
558
559 printk(KERN_DEBUG "%s: %s(%i)", dev->name, func, len);
560 for (i = 0; i < len; i++) {
561 if (i >= DEBUG_PKT_BYTES)
562 break;
563 printk("%s%02X", !(i % 4) ? " " : "", data[i]);
564 }
565 printk("\n");
566#endif
567}
568
569
570static inline void debug_desc(u32 phys, struct desc *desc)
571{
572#if DEBUG_DESC
573 printk(KERN_DEBUG "%X: %X %3X %3X %08X %X %X\n",
574 phys, desc->next, desc->buf_len, desc->pkt_len,
575 desc->data, desc->status, desc->error_count);
576#endif
577}
578
579static inline int queue_get_desc(unsigned int queue, struct port *port,
580 int is_tx)
581{
582 u32 phys, tab_phys, n_desc;
583 struct desc *tab;
584
585 if (!(phys = qmgr_get_entry(queue)))
586 return -1;
587
588 BUG_ON(phys & 0x1F);
589 tab_phys = is_tx ? tx_desc_phys(port, 0) : rx_desc_phys(port, 0);
590 tab = is_tx ? tx_desc_ptr(port, 0) : rx_desc_ptr(port, 0);
591 n_desc = (phys - tab_phys) / sizeof(struct desc);
592 BUG_ON(n_desc >= (is_tx ? TX_DESCS : RX_DESCS));
593 debug_desc(phys, &tab[n_desc]);
594 BUG_ON(tab[n_desc].next);
595 return n_desc;
596}
597
598static inline void queue_put_desc(unsigned int queue, u32 phys,
599 struct desc *desc)
600{
601 debug_desc(phys, desc);
602 BUG_ON(phys & 0x1F);
603 qmgr_put_entry(queue, phys);
604 /* Don't check for queue overflow here, we've allocated sufficient
605 length and queues >= 32 don't support this check anyway. */
606}
607
608
609static inline void dma_unmap_tx(struct port *port, struct desc *desc)
610{
611#ifdef __ARMEB__
612 dma_unmap_single(&port->netdev->dev, desc->data,
613 desc->buf_len, DMA_TO_DEVICE);
614#else
615 dma_unmap_single(&port->netdev->dev, desc->data & ~3,
616 ALIGN((desc->data & 3) + desc->buf_len, 4),
617 DMA_TO_DEVICE);
618#endif
619}
620
621
622static void hss_hdlc_set_carrier(void *pdev, int carrier)
623{
624 struct net_device *netdev = pdev;
625 struct port *port = dev_to_port(netdev);
626 unsigned long flags;
627
628 spin_lock_irqsave(&npe_lock, flags);
629 port->carrier = carrier;
630 if (!port->loopback) {
631 if (carrier)
632 netif_carrier_on(netdev);
633 else
634 netif_carrier_off(netdev);
635 }
636 spin_unlock_irqrestore(&npe_lock, flags);
637}
638
639static void hss_hdlc_rx_irq(void *pdev)
640{
641 struct net_device *dev = pdev;
642 struct port *port = dev_to_port(dev);
643
644#if DEBUG_RX
645 printk(KERN_DEBUG "%s: hss_hdlc_rx_irq\n", dev->name);
646#endif
647 qmgr_disable_irq(queue_ids[port->id].rx);
648 napi_schedule(&port->napi);
649}
650
651static int hss_hdlc_poll(struct napi_struct *napi, int budget)
652{
653 struct port *port = container_of(napi, struct port, napi);
654 struct net_device *dev = port->netdev;
655 unsigned int rxq = queue_ids[port->id].rx;
656 unsigned int rxfreeq = queue_ids[port->id].rxfree;
657 int received = 0;
658
659#if DEBUG_RX
660 printk(KERN_DEBUG "%s: hss_hdlc_poll\n", dev->name);
661#endif
662
663 while (received < budget) {
664 struct sk_buff *skb;
665 struct desc *desc;
666 int n;
667#ifdef __ARMEB__
668 struct sk_buff *temp;
669 u32 phys;
670#endif
671
672 if ((n = queue_get_desc(rxq, port, 0)) < 0) {
673#if DEBUG_RX
674 printk(KERN_DEBUG "%s: hss_hdlc_poll"
675 " napi_complete\n", dev->name);
676#endif
677 napi_complete(napi);
678 qmgr_enable_irq(rxq);
679 if (!qmgr_stat_empty(rxq) &&
680 napi_reschedule(napi)) {
681#if DEBUG_RX
682 printk(KERN_DEBUG "%s: hss_hdlc_poll"
683 " napi_reschedule succeeded\n",
684 dev->name);
685#endif
686 qmgr_disable_irq(rxq);
687 continue;
688 }
689#if DEBUG_RX
690 printk(KERN_DEBUG "%s: hss_hdlc_poll all done\n",
691 dev->name);
692#endif
693 return received; /* all work done */
694 }
695
696 desc = rx_desc_ptr(port, n);
697#if 0 /* FIXME - error_count counts modulo 256, perhaps we should use it */
698 if (desc->error_count)
699 printk(KERN_DEBUG "%s: hss_hdlc_poll status 0x%02X"
700 " errors %u\n", dev->name, desc->status,
701 desc->error_count);
702#endif
703 skb = NULL;
704 switch (desc->status) {
705 case 0:
706#ifdef __ARMEB__
707 if ((skb = netdev_alloc_skb(dev, RX_SIZE)) != NULL) {
708 phys = dma_map_single(&dev->dev, skb->data,
709 RX_SIZE,
710 DMA_FROM_DEVICE);
711 if (dma_mapping_error(&dev->dev, phys)) {
712 dev_kfree_skb(skb);
713 skb = NULL;
714 }
715 }
716#else
717 skb = netdev_alloc_skb(dev, desc->pkt_len);
718#endif
719 if (!skb)
720 dev->stats.rx_dropped++;
721 break;
722 case ERR_HDLC_ALIGN:
723 case ERR_HDLC_ABORT:
724 dev->stats.rx_frame_errors++;
725 dev->stats.rx_errors++;
726 break;
727 case ERR_HDLC_FCS:
728 dev->stats.rx_crc_errors++;
729 dev->stats.rx_errors++;
730 break;
731 case ERR_HDLC_TOO_LONG:
732 dev->stats.rx_length_errors++;
733 dev->stats.rx_errors++;
734 break;
735 default: /* FIXME - remove printk */
736 netdev_err(dev, "hss_hdlc_poll: status 0x%02X errors %u\n",
737 desc->status, desc->error_count);
738 dev->stats.rx_errors++;
739 }
740
741 if (!skb) {
742 /* put the desc back on RX-ready queue */
743 desc->buf_len = RX_SIZE;
744 desc->pkt_len = desc->status = 0;
745 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
746 continue;
747 }
748
749 /* process received frame */
750#ifdef __ARMEB__
751 temp = skb;
752 skb = port->rx_buff_tab[n];
753 dma_unmap_single(&dev->dev, desc->data,
754 RX_SIZE, DMA_FROM_DEVICE);
755#else
756 dma_sync_single_for_cpu(&dev->dev, desc->data,
757 RX_SIZE, DMA_FROM_DEVICE);
758 memcpy_swab32((u32 *)skb->data, (u32 *)port->rx_buff_tab[n],
759 ALIGN(desc->pkt_len, 4) / 4);
760#endif
761 skb_put(skb, desc->pkt_len);
762
763 debug_pkt(dev, "hss_hdlc_poll", skb->data, skb->len);
764
765 skb->protocol = hdlc_type_trans(skb, dev);
766 dev->stats.rx_packets++;
767 dev->stats.rx_bytes += skb->len;
768 netif_receive_skb(skb);
769
770 /* put the new buffer on RX-free queue */
771#ifdef __ARMEB__
772 port->rx_buff_tab[n] = temp;
773 desc->data = phys;
774#endif
775 desc->buf_len = RX_SIZE;
776 desc->pkt_len = 0;
777 queue_put_desc(rxfreeq, rx_desc_phys(port, n), desc);
778 received++;
779 }
780#if DEBUG_RX
781 printk(KERN_DEBUG "hss_hdlc_poll: end, not all work done\n");
782#endif
783 return received; /* not all work done */
784}
785
786
787static void hss_hdlc_txdone_irq(void *pdev)
788{
789 struct net_device *dev = pdev;
790 struct port *port = dev_to_port(dev);
791 int n_desc;
792
793#if DEBUG_TX
794 printk(KERN_DEBUG DRV_NAME ": hss_hdlc_txdone_irq\n");
795#endif
796 while ((n_desc = queue_get_desc(queue_ids[port->id].txdone,
797 port, 1)) >= 0) {
798 struct desc *desc;
799 int start;
800
801 desc = tx_desc_ptr(port, n_desc);
802
803 dev->stats.tx_packets++;
804 dev->stats.tx_bytes += desc->pkt_len;
805
806 dma_unmap_tx(port, desc);
807#if DEBUG_TX
808 printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq free %p\n",
809 dev->name, port->tx_buff_tab[n_desc]);
810#endif
811 free_buffer_irq(port->tx_buff_tab[n_desc]);
812 port->tx_buff_tab[n_desc] = NULL;
813
814 start = qmgr_stat_below_low_watermark(port->plat->txreadyq);
815 queue_put_desc(port->plat->txreadyq,
816 tx_desc_phys(port, n_desc), desc);
817 if (start) { /* TX-ready queue was empty */
818#if DEBUG_TX
819 printk(KERN_DEBUG "%s: hss_hdlc_txdone_irq xmit"
820 " ready\n", dev->name);
821#endif
822 netif_wake_queue(dev);
823 }
824 }
825}
826
827static int hss_hdlc_xmit(struct sk_buff *skb, struct net_device *dev)
828{
829 struct port *port = dev_to_port(dev);
830 unsigned int txreadyq = port->plat->txreadyq;
831 int len, offset, bytes, n;
832 void *mem;
833 u32 phys;
834 struct desc *desc;
835
836#if DEBUG_TX
837 printk(KERN_DEBUG "%s: hss_hdlc_xmit\n", dev->name);
838#endif
839
840 if (unlikely(skb->len > HDLC_MAX_MRU)) {
841 dev_kfree_skb(skb);
842 dev->stats.tx_errors++;
843 return NETDEV_TX_OK;
844 }
845
846 debug_pkt(dev, "hss_hdlc_xmit", skb->data, skb->len);
847
848 len = skb->len;
849#ifdef __ARMEB__
850 offset = 0; /* no need to keep alignment */
851 bytes = len;
852 mem = skb->data;
853#else
854 offset = (int)skb->data & 3; /* keep 32-bit alignment */
855 bytes = ALIGN(offset + len, 4);
856 if (!(mem = kmalloc(bytes, GFP_ATOMIC))) {
857 dev_kfree_skb(skb);
858 dev->stats.tx_dropped++;
859 return NETDEV_TX_OK;
860 }
861 memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4);
862 dev_kfree_skb(skb);
863#endif
864
865 phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
866 if (dma_mapping_error(&dev->dev, phys)) {
867#ifdef __ARMEB__
868 dev_kfree_skb(skb);
869#else
870 kfree(mem);
871#endif
872 dev->stats.tx_dropped++;
873 return NETDEV_TX_OK;
874 }
875
876 n = queue_get_desc(txreadyq, port, 1);
877 BUG_ON(n < 0);
878 desc = tx_desc_ptr(port, n);
879
880#ifdef __ARMEB__
881 port->tx_buff_tab[n] = skb;
882#else
883 port->tx_buff_tab[n] = mem;
884#endif
885 desc->data = phys + offset;
886 desc->buf_len = desc->pkt_len = len;
887
888 wmb();
889 queue_put_desc(queue_ids[port->id].tx, tx_desc_phys(port, n), desc);
890
891 if (qmgr_stat_below_low_watermark(txreadyq)) { /* empty */
892#if DEBUG_TX
893 printk(KERN_DEBUG "%s: hss_hdlc_xmit queue full\n", dev->name);
894#endif
895 netif_stop_queue(dev);
896 /* we could miss TX ready interrupt */
897 if (!qmgr_stat_below_low_watermark(txreadyq)) {
898#if DEBUG_TX
899 printk(KERN_DEBUG "%s: hss_hdlc_xmit ready again\n",
900 dev->name);
901#endif
902 netif_wake_queue(dev);
903 }
904 }
905
906#if DEBUG_TX
907 printk(KERN_DEBUG "%s: hss_hdlc_xmit end\n", dev->name);
908#endif
909 return NETDEV_TX_OK;
910}
911
912
913static int request_hdlc_queues(struct port *port)
914{
915 int err;
916
917 err = qmgr_request_queue(queue_ids[port->id].rxfree, RX_DESCS, 0, 0,
918 "%s:RX-free", port->netdev->name);
919 if (err)
920 return err;
921
922 err = qmgr_request_queue(queue_ids[port->id].rx, RX_DESCS, 0, 0,
923 "%s:RX", port->netdev->name);
924 if (err)
925 goto rel_rxfree;
926
927 err = qmgr_request_queue(queue_ids[port->id].tx, TX_DESCS, 0, 0,
928 "%s:TX", port->netdev->name);
929 if (err)
930 goto rel_rx;
931
932 err = qmgr_request_queue(port->plat->txreadyq, TX_DESCS, 0, 0,
933 "%s:TX-ready", port->netdev->name);
934 if (err)
935 goto rel_tx;
936
937 err = qmgr_request_queue(queue_ids[port->id].txdone, TX_DESCS, 0, 0,
938 "%s:TX-done", port->netdev->name);
939 if (err)
940 goto rel_txready;
941 return 0;
942
943rel_txready:
944 qmgr_release_queue(port->plat->txreadyq);
945rel_tx:
946 qmgr_release_queue(queue_ids[port->id].tx);
947rel_rx:
948 qmgr_release_queue(queue_ids[port->id].rx);
949rel_rxfree:
950 qmgr_release_queue(queue_ids[port->id].rxfree);
951 printk(KERN_DEBUG "%s: unable to request hardware queues\n",
952 port->netdev->name);
953 return err;
954}
955
956static void release_hdlc_queues(struct port *port)
957{
958 qmgr_release_queue(queue_ids[port->id].rxfree);
959 qmgr_release_queue(queue_ids[port->id].rx);
960 qmgr_release_queue(queue_ids[port->id].txdone);
961 qmgr_release_queue(queue_ids[port->id].tx);
962 qmgr_release_queue(port->plat->txreadyq);
963}
964
965static int init_hdlc_queues(struct port *port)
966{
967 int i;
968
969 if (!ports_open) {
970 dma_pool = dma_pool_create(DRV_NAME, &port->netdev->dev,
971 POOL_ALLOC_SIZE, 32, 0);
972 if (!dma_pool)
973 return -ENOMEM;
974 }
975
976 if (!(port->desc_tab = dma_pool_alloc(dma_pool, GFP_KERNEL,
977 &port->desc_tab_phys)))
978 return -ENOMEM;
979 memset(port->desc_tab, 0, POOL_ALLOC_SIZE);
980 memset(port->rx_buff_tab, 0, sizeof(port->rx_buff_tab)); /* tables */
981 memset(port->tx_buff_tab, 0, sizeof(port->tx_buff_tab));
982
983 /* Setup RX buffers */
984 for (i = 0; i < RX_DESCS; i++) {
985 struct desc *desc = rx_desc_ptr(port, i);
986 buffer_t *buff;
987 void *data;
988#ifdef __ARMEB__
989 if (!(buff = netdev_alloc_skb(port->netdev, RX_SIZE)))
990 return -ENOMEM;
991 data = buff->data;
992#else
993 if (!(buff = kmalloc(RX_SIZE, GFP_KERNEL)))
994 return -ENOMEM;
995 data = buff;
996#endif
997 desc->buf_len = RX_SIZE;
998 desc->data = dma_map_single(&port->netdev->dev, data,
999 RX_SIZE, DMA_FROM_DEVICE);
1000 if (dma_mapping_error(&port->netdev->dev, desc->data)) {
1001 free_buffer(buff);
1002 return -EIO;
1003 }
1004 port->rx_buff_tab[i] = buff;
1005 }
1006
1007 return 0;
1008}
1009
1010static void destroy_hdlc_queues(struct port *port)
1011{
1012 int i;
1013
1014 if (port->desc_tab) {
1015 for (i = 0; i < RX_DESCS; i++) {
1016 struct desc *desc = rx_desc_ptr(port, i);
1017 buffer_t *buff = port->rx_buff_tab[i];
1018 if (buff) {
1019 dma_unmap_single(&port->netdev->dev,
1020 desc->data, RX_SIZE,
1021 DMA_FROM_DEVICE);
1022 free_buffer(buff);
1023 }
1024 }
1025 for (i = 0; i < TX_DESCS; i++) {
1026 struct desc *desc = tx_desc_ptr(port, i);
1027 buffer_t *buff = port->tx_buff_tab[i];
1028 if (buff) {
1029 dma_unmap_tx(port, desc);
1030 free_buffer(buff);
1031 }
1032 }
1033 dma_pool_free(dma_pool, port->desc_tab, port->desc_tab_phys);
1034 port->desc_tab = NULL;
1035 }
1036
1037 if (!ports_open && dma_pool) {
1038 dma_pool_destroy(dma_pool);
1039 dma_pool = NULL;
1040 }
1041}
1042
1043static int hss_hdlc_open(struct net_device *dev)
1044{
1045 struct port *port = dev_to_port(dev);
1046 unsigned long flags;
1047 int i, err = 0;
1048
1049 if ((err = hdlc_open(dev)))
1050 return err;
1051
1052 if ((err = hss_load_firmware(port)))
1053 goto err_hdlc_close;
1054
1055 if ((err = request_hdlc_queues(port)))
1056 goto err_hdlc_close;
1057
1058 if ((err = init_hdlc_queues(port)))
1059 goto err_destroy_queues;
1060
1061 spin_lock_irqsave(&npe_lock, flags);
1062 if (port->plat->open)
1063 if ((err = port->plat->open(port->id, dev,
1064 hss_hdlc_set_carrier)))
1065 goto err_unlock;
1066 spin_unlock_irqrestore(&npe_lock, flags);
1067
1068 /* Populate queues with buffers, no failure after this point */
1069 for (i = 0; i < TX_DESCS; i++)
1070 queue_put_desc(port->plat->txreadyq,
1071 tx_desc_phys(port, i), tx_desc_ptr(port, i));
1072
1073 for (i = 0; i < RX_DESCS; i++)
1074 queue_put_desc(queue_ids[port->id].rxfree,
1075 rx_desc_phys(port, i), rx_desc_ptr(port, i));
1076
1077 napi_enable(&port->napi);
1078 netif_start_queue(dev);
1079
1080 qmgr_set_irq(queue_ids[port->id].rx, QUEUE_IRQ_SRC_NOT_EMPTY,
1081 hss_hdlc_rx_irq, dev);
1082
1083 qmgr_set_irq(queue_ids[port->id].txdone, QUEUE_IRQ_SRC_NOT_EMPTY,
1084 hss_hdlc_txdone_irq, dev);
1085 qmgr_enable_irq(queue_ids[port->id].txdone);
1086
1087 ports_open++;
1088
1089 hss_set_hdlc_cfg(port);
1090 hss_config(port);
1091
1092 hss_start_hdlc(port);
1093
1094 /* we may already have RX data, enables IRQ */
1095 napi_schedule(&port->napi);
1096 return 0;
1097
1098err_unlock:
1099 spin_unlock_irqrestore(&npe_lock, flags);
1100err_destroy_queues:
1101 destroy_hdlc_queues(port);
1102 release_hdlc_queues(port);
1103err_hdlc_close:
1104 hdlc_close(dev);
1105 return err;
1106}
1107
1108static int hss_hdlc_close(struct net_device *dev)
1109{
1110 struct port *port = dev_to_port(dev);
1111 unsigned long flags;
1112 int i, buffs = RX_DESCS; /* allocated RX buffers */
1113
1114 spin_lock_irqsave(&npe_lock, flags);
1115 ports_open--;
1116 qmgr_disable_irq(queue_ids[port->id].rx);
1117 netif_stop_queue(dev);
1118 napi_disable(&port->napi);
1119
1120 hss_stop_hdlc(port);
1121
1122 while (queue_get_desc(queue_ids[port->id].rxfree, port, 0) >= 0)
1123 buffs--;
1124 while (queue_get_desc(queue_ids[port->id].rx, port, 0) >= 0)
1125 buffs--;
1126
1127 if (buffs)
1128 netdev_crit(dev, "unable to drain RX queue, %i buffer(s) left in NPE\n",
1129 buffs);
1130
1131 buffs = TX_DESCS;
1132 while (queue_get_desc(queue_ids[port->id].tx, port, 1) >= 0)
1133 buffs--; /* cancel TX */
1134
1135 i = 0;
1136 do {
1137 while (queue_get_desc(port->plat->txreadyq, port, 1) >= 0)
1138 buffs--;
1139 if (!buffs)
1140 break;
1141 } while (++i < MAX_CLOSE_WAIT);
1142
1143 if (buffs)
1144 netdev_crit(dev, "unable to drain TX queue, %i buffer(s) left in NPE\n",
1145 buffs);
1146#if DEBUG_CLOSE
1147 if (!buffs)
1148 printk(KERN_DEBUG "Draining TX queues took %i cycles\n", i);
1149#endif
1150 qmgr_disable_irq(queue_ids[port->id].txdone);
1151
1152 if (port->plat->close)
1153 port->plat->close(port->id, dev);
1154 spin_unlock_irqrestore(&npe_lock, flags);
1155
1156 destroy_hdlc_queues(port);
1157 release_hdlc_queues(port);
1158 hdlc_close(dev);
1159 return 0;
1160}
1161
1162
1163static int hss_hdlc_attach(struct net_device *dev, unsigned short encoding,
1164 unsigned short parity)
1165{
1166 struct port *port = dev_to_port(dev);
1167
1168 if (encoding != ENCODING_NRZ)
1169 return -EINVAL;
1170
1171 switch(parity) {
1172 case PARITY_CRC16_PR1_CCITT:
1173 port->hdlc_cfg = 0;
1174 return 0;
1175
1176 case PARITY_CRC32_PR1_CCITT:
1177 port->hdlc_cfg = PKT_HDLC_CRC_32;
1178 return 0;
1179
1180 default:
1181 return -EINVAL;
1182 }
1183}
1184
1185static u32 check_clock(u32 rate, u32 a, u32 b, u32 c,
1186 u32 *best, u32 *best_diff, u32 *reg)
1187{
1188 /* a is 10-bit, b is 10-bit, c is 12-bit */
1189 u64 new_rate;
1190 u32 new_diff;
1191
1192 new_rate = ixp4xx_timer_freq * (u64)(c + 1);
1193 do_div(new_rate, a * (c + 1) + b + 1);
1194 new_diff = abs((u32)new_rate - rate);
1195
1196 if (new_diff < *best_diff) {
1197 *best = new_rate;
1198 *best_diff = new_diff;
1199 *reg = (a << 22) | (b << 12) | c;
1200 }
1201 return new_diff;
1202}
1203
1204static void find_best_clock(u32 rate, u32 *best, u32 *reg)
1205{
1206 u32 a, b, diff = 0xFFFFFFFF;
1207
1208 a = ixp4xx_timer_freq / rate;
1209
1210 if (a > 0x3FF) { /* 10-bit value - we can go as slow as ca. 65 kb/s */
1211 check_clock(rate, 0x3FF, 1, 1, best, &diff, reg);
1212 return;
1213 }
1214 if (a == 0) { /* > 66.666 MHz */
1215 a = 1; /* minimum divider is 1 (a = 0, b = 1, c = 1) */
1216 rate = ixp4xx_timer_freq;
1217 }
1218
1219 if (rate * a == ixp4xx_timer_freq) { /* don't divide by 0 later */
1220 check_clock(rate, a - 1, 1, 1, best, &diff, reg);
1221 return;
1222 }
1223
1224 for (b = 0; b < 0x400; b++) {
1225 u64 c = (b + 1) * (u64)rate;
1226 do_div(c, ixp4xx_timer_freq - rate * a);
1227 c--;
1228 if (c >= 0xFFF) { /* 12-bit - no need to check more 'b's */
1229 if (b == 0 && /* also try a bit higher rate */
1230 !check_clock(rate, a - 1, 1, 1, best, &diff, reg))
1231 return;
1232 check_clock(rate, a, b, 0xFFF, best, &diff, reg);
1233 return;
1234 }
1235 if (!check_clock(rate, a, b, c, best, &diff, reg))
1236 return;
1237 if (!check_clock(rate, a, b, c + 1, best, &diff, reg))
1238 return;
1239 }
1240}
1241
1242static int hss_hdlc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1243{
1244 const size_t size = sizeof(sync_serial_settings);
1245 sync_serial_settings new_line;
1246 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1247 struct port *port = dev_to_port(dev);
1248 unsigned long flags;
1249 int clk;
1250
1251 if (cmd != SIOCWANDEV)
1252 return hdlc_ioctl(dev, ifr, cmd);
1253
1254 switch(ifr->ifr_settings.type) {
1255 case IF_GET_IFACE:
1256 ifr->ifr_settings.type = IF_IFACE_V35;
1257 if (ifr->ifr_settings.size < size) {
1258 ifr->ifr_settings.size = size; /* data size wanted */
1259 return -ENOBUFS;
1260 }
1261 memset(&new_line, 0, sizeof(new_line));
1262 new_line.clock_type = port->clock_type;
1263 new_line.clock_rate = port->clock_rate;
1264 new_line.loopback = port->loopback;
1265 if (copy_to_user(line, &new_line, size))
1266 return -EFAULT;
1267 return 0;
1268
1269 case IF_IFACE_SYNC_SERIAL:
1270 case IF_IFACE_V35:
1271 if(!capable(CAP_NET_ADMIN))
1272 return -EPERM;
1273 if (copy_from_user(&new_line, line, size))
1274 return -EFAULT;
1275
1276 clk = new_line.clock_type;
1277 if (port->plat->set_clock)
1278 clk = port->plat->set_clock(port->id, clk);
1279
1280 if (clk != CLOCK_EXT && clk != CLOCK_INT)
1281 return -EINVAL; /* No such clock setting */
1282
1283 if (new_line.loopback != 0 && new_line.loopback != 1)
1284 return -EINVAL;
1285
1286 port->clock_type = clk; /* Update settings */
1287 if (clk == CLOCK_INT)
1288 find_best_clock(new_line.clock_rate, &port->clock_rate,
1289 &port->clock_reg);
1290 else {
1291 port->clock_rate = 0;
1292 port->clock_reg = CLK42X_SPEED_2048KHZ;
1293 }
1294 port->loopback = new_line.loopback;
1295
1296 spin_lock_irqsave(&npe_lock, flags);
1297
1298 if (dev->flags & IFF_UP)
1299 hss_config(port);
1300
1301 if (port->loopback || port->carrier)
1302 netif_carrier_on(port->netdev);
1303 else
1304 netif_carrier_off(port->netdev);
1305 spin_unlock_irqrestore(&npe_lock, flags);
1306
1307 return 0;
1308
1309 default:
1310 return hdlc_ioctl(dev, ifr, cmd);
1311 }
1312}
1313
1314/*****************************************************************************
1315 * initialization
1316 ****************************************************************************/
1317
1318static const struct net_device_ops hss_hdlc_ops = {
1319 .ndo_open = hss_hdlc_open,
1320 .ndo_stop = hss_hdlc_close,
1321 .ndo_start_xmit = hdlc_start_xmit,
1322 .ndo_do_ioctl = hss_hdlc_ioctl,
1323};
1324
1325static int hss_init_one(struct platform_device *pdev)
1326{
1327 struct port *port;
1328 struct net_device *dev;
1329 hdlc_device *hdlc;
1330 int err;
1331
1332 if ((port = kzalloc(sizeof(*port), GFP_KERNEL)) == NULL)
1333 return -ENOMEM;
1334
1335 if ((port->npe = npe_request(0)) == NULL) {
1336 err = -ENODEV;
1337 goto err_free;
1338 }
1339
1340 if ((port->netdev = dev = alloc_hdlcdev(port)) == NULL) {
1341 err = -ENOMEM;
1342 goto err_plat;
1343 }
1344
1345 SET_NETDEV_DEV(dev, &pdev->dev);
1346 hdlc = dev_to_hdlc(dev);
1347 hdlc->attach = hss_hdlc_attach;
1348 hdlc->xmit = hss_hdlc_xmit;
1349 dev->netdev_ops = &hss_hdlc_ops;
1350 dev->tx_queue_len = 100;
1351 port->clock_type = CLOCK_EXT;
1352 port->clock_rate = 0;
1353 port->clock_reg = CLK42X_SPEED_2048KHZ;
1354 port->id = pdev->id;
1355 port->dev = &pdev->dev;
1356 port->plat = pdev->dev.platform_data;
1357 netif_napi_add(dev, &port->napi, hss_hdlc_poll, NAPI_WEIGHT);
1358
1359 if ((err = register_hdlc_device(dev)))
1360 goto err_free_netdev;
1361
1362 platform_set_drvdata(pdev, port);
1363
1364 netdev_info(dev, "initialized\n");
1365 return 0;
1366
1367err_free_netdev:
1368 free_netdev(dev);
1369err_plat:
1370 npe_release(port->npe);
1371err_free:
1372 kfree(port);
1373 return err;
1374}
1375
1376static int hss_remove_one(struct platform_device *pdev)
1377{
1378 struct port *port = platform_get_drvdata(pdev);
1379
1380 unregister_hdlc_device(port->netdev);
1381 free_netdev(port->netdev);
1382 npe_release(port->npe);
1383 kfree(port);
1384 return 0;
1385}
1386
1387static struct platform_driver ixp4xx_hss_driver = {
1388 .driver.name = DRV_NAME,
1389 .probe = hss_init_one,
1390 .remove = hss_remove_one,
1391};
1392
1393static int __init hss_init_module(void)
1394{
1395 if ((ixp4xx_read_feature_bits() &
1396 (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS)) !=
1397 (IXP4XX_FEATURE_HDLC | IXP4XX_FEATURE_HSS))
1398 return -ENODEV;
1399
1400 spin_lock_init(&npe_lock);
1401
1402 return platform_driver_register(&ixp4xx_hss_driver);
1403}
1404
1405static void __exit hss_cleanup_module(void)
1406{
1407 platform_driver_unregister(&ixp4xx_hss_driver);
1408}
1409
1410MODULE_AUTHOR("Krzysztof Halasa");
1411MODULE_DESCRIPTION("Intel IXP4xx HSS driver");
1412MODULE_LICENSE("GPL v2");
1413MODULE_ALIAS("platform:ixp4xx_hss");
1414module_init(hss_init_module);
1415module_exit(hss_cleanup_module);