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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * drivers/net/phy/micrel.c
4 *
5 * Driver for Micrel PHYs
6 *
7 * Author: David J. Choi
8 *
9 * Copyright (c) 2010-2013 Micrel, Inc.
10 * Copyright (c) 2014 Johan Hovold <johan@kernel.org>
11 *
12 * Support : Micrel Phys:
13 * Giga phys: ksz9021, ksz9031, ksz9131, lan8841, lan8814
14 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
15 * ksz8021, ksz8031, ksz8051,
16 * ksz8081, ksz8091,
17 * ksz8061,
18 * Switch : ksz8873, ksz886x
19 * ksz9477, lan8804
20 */
21
22#include <linux/bitfield.h>
23#include <linux/ethtool_netlink.h>
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/phy.h>
27#include <linux/micrel_phy.h>
28#include <linux/of.h>
29#include <linux/clk.h>
30#include <linux/delay.h>
31#include <linux/ptp_clock_kernel.h>
32#include <linux/ptp_clock.h>
33#include <linux/ptp_classify.h>
34#include <linux/net_tstamp.h>
35#include <linux/gpio/consumer.h>
36
37/* Operation Mode Strap Override */
38#define MII_KSZPHY_OMSO 0x16
39#define KSZPHY_OMSO_FACTORY_TEST BIT(15)
40#define KSZPHY_OMSO_B_CAST_OFF BIT(9)
41#define KSZPHY_OMSO_NAND_TREE_ON BIT(5)
42#define KSZPHY_OMSO_RMII_OVERRIDE BIT(1)
43#define KSZPHY_OMSO_MII_OVERRIDE BIT(0)
44
45/* general Interrupt control/status reg in vendor specific block. */
46#define MII_KSZPHY_INTCS 0x1B
47#define KSZPHY_INTCS_JABBER BIT(15)
48#define KSZPHY_INTCS_RECEIVE_ERR BIT(14)
49#define KSZPHY_INTCS_PAGE_RECEIVE BIT(13)
50#define KSZPHY_INTCS_PARELLEL BIT(12)
51#define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11)
52#define KSZPHY_INTCS_LINK_DOWN BIT(10)
53#define KSZPHY_INTCS_REMOTE_FAULT BIT(9)
54#define KSZPHY_INTCS_LINK_UP BIT(8)
55#define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\
56 KSZPHY_INTCS_LINK_DOWN)
57#define KSZPHY_INTCS_LINK_DOWN_STATUS BIT(2)
58#define KSZPHY_INTCS_LINK_UP_STATUS BIT(0)
59#define KSZPHY_INTCS_STATUS (KSZPHY_INTCS_LINK_DOWN_STATUS |\
60 KSZPHY_INTCS_LINK_UP_STATUS)
61
62/* LinkMD Control/Status */
63#define KSZ8081_LMD 0x1d
64#define KSZ8081_LMD_ENABLE_TEST BIT(15)
65#define KSZ8081_LMD_STAT_NORMAL 0
66#define KSZ8081_LMD_STAT_OPEN 1
67#define KSZ8081_LMD_STAT_SHORT 2
68#define KSZ8081_LMD_STAT_FAIL 3
69#define KSZ8081_LMD_STAT_MASK GENMASK(14, 13)
70/* Short cable (<10 meter) has been detected by LinkMD */
71#define KSZ8081_LMD_SHORT_INDICATOR BIT(12)
72#define KSZ8081_LMD_DELTA_TIME_MASK GENMASK(8, 0)
73
74#define KSZ9x31_LMD 0x12
75#define KSZ9x31_LMD_VCT_EN BIT(15)
76#define KSZ9x31_LMD_VCT_DIS_TX BIT(14)
77#define KSZ9x31_LMD_VCT_PAIR(n) (((n) & 0x3) << 12)
78#define KSZ9x31_LMD_VCT_SEL_RESULT 0
79#define KSZ9x31_LMD_VCT_SEL_THRES_HI BIT(10)
80#define KSZ9x31_LMD_VCT_SEL_THRES_LO BIT(11)
81#define KSZ9x31_LMD_VCT_SEL_MASK GENMASK(11, 10)
82#define KSZ9x31_LMD_VCT_ST_NORMAL 0
83#define KSZ9x31_LMD_VCT_ST_OPEN 1
84#define KSZ9x31_LMD_VCT_ST_SHORT 2
85#define KSZ9x31_LMD_VCT_ST_FAIL 3
86#define KSZ9x31_LMD_VCT_ST_MASK GENMASK(9, 8)
87#define KSZ9x31_LMD_VCT_DATA_REFLECTED_INVALID BIT(7)
88#define KSZ9x31_LMD_VCT_DATA_SIG_WAIT_TOO_LONG BIT(6)
89#define KSZ9x31_LMD_VCT_DATA_MASK100 BIT(5)
90#define KSZ9x31_LMD_VCT_DATA_NLP_FLP BIT(4)
91#define KSZ9x31_LMD_VCT_DATA_LO_PULSE_MASK GENMASK(3, 2)
92#define KSZ9x31_LMD_VCT_DATA_HI_PULSE_MASK GENMASK(1, 0)
93#define KSZ9x31_LMD_VCT_DATA_MASK GENMASK(7, 0)
94
95#define KSZPHY_WIRE_PAIR_MASK 0x3
96
97#define LAN8814_CABLE_DIAG 0x12
98#define LAN8814_CABLE_DIAG_STAT_MASK GENMASK(9, 8)
99#define LAN8814_CABLE_DIAG_VCT_DATA_MASK GENMASK(7, 0)
100#define LAN8814_PAIR_BIT_SHIFT 12
101
102#define LAN8814_WIRE_PAIR_MASK 0xF
103
104/* Lan8814 general Interrupt control/status reg in GPHY specific block. */
105#define LAN8814_INTC 0x18
106#define LAN8814_INTS 0x1B
107
108#define LAN8814_INT_LINK_DOWN BIT(2)
109#define LAN8814_INT_LINK_UP BIT(0)
110#define LAN8814_INT_LINK (LAN8814_INT_LINK_UP |\
111 LAN8814_INT_LINK_DOWN)
112
113#define LAN8814_INTR_CTRL_REG 0x34
114#define LAN8814_INTR_CTRL_REG_POLARITY BIT(1)
115#define LAN8814_INTR_CTRL_REG_INTR_ENABLE BIT(0)
116
117#define LAN8814_EEE_STATE 0x38
118#define LAN8814_EEE_STATE_MASK2P5P BIT(10)
119
120#define LAN8814_PD_CONTROLS 0x9d
121#define LAN8814_PD_CONTROLS_PD_MEAS_TIME_MASK GENMASK(3, 0)
122#define LAN8814_PD_CONTROLS_PD_MEAS_TIME_VAL 0xb
123
124/* Represents 1ppm adjustment in 2^32 format with
125 * each nsec contains 4 clock cycles.
126 * The value is calculated as following: (1/1000000)/((2^-32)/4)
127 */
128#define LAN8814_1PPM_FORMAT 17179
129
130/* Represents 1ppm adjustment in 2^32 format with
131 * each nsec contains 8 clock cycles.
132 * The value is calculated as following: (1/1000000)/((2^-32)/8)
133 */
134#define LAN8841_1PPM_FORMAT 34360
135
136#define PTP_RX_VERSION 0x0248
137#define PTP_TX_VERSION 0x0288
138#define PTP_MAX_VERSION(x) (((x) & GENMASK(7, 0)) << 8)
139#define PTP_MIN_VERSION(x) ((x) & GENMASK(7, 0))
140
141#define PTP_RX_MOD 0x024F
142#define PTP_RX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_ BIT(3)
143#define PTP_RX_TIMESTAMP_EN 0x024D
144#define PTP_TX_TIMESTAMP_EN 0x028D
145
146#define PTP_TIMESTAMP_EN_SYNC_ BIT(0)
147#define PTP_TIMESTAMP_EN_DREQ_ BIT(1)
148#define PTP_TIMESTAMP_EN_PDREQ_ BIT(2)
149#define PTP_TIMESTAMP_EN_PDRES_ BIT(3)
150
151#define PTP_TX_PARSE_L2_ADDR_EN 0x0284
152#define PTP_RX_PARSE_L2_ADDR_EN 0x0244
153
154#define PTP_TX_PARSE_IP_ADDR_EN 0x0285
155#define PTP_RX_PARSE_IP_ADDR_EN 0x0245
156#define LTC_HARD_RESET 0x023F
157#define LTC_HARD_RESET_ BIT(0)
158
159#define TSU_HARD_RESET 0x02C1
160#define TSU_HARD_RESET_ BIT(0)
161
162#define PTP_CMD_CTL 0x0200
163#define PTP_CMD_CTL_PTP_DISABLE_ BIT(0)
164#define PTP_CMD_CTL_PTP_ENABLE_ BIT(1)
165#define PTP_CMD_CTL_PTP_CLOCK_READ_ BIT(3)
166#define PTP_CMD_CTL_PTP_CLOCK_LOAD_ BIT(4)
167#define PTP_CMD_CTL_PTP_LTC_STEP_SEC_ BIT(5)
168#define PTP_CMD_CTL_PTP_LTC_STEP_NSEC_ BIT(6)
169
170#define PTP_COMMON_INT_ENA 0x0204
171#define PTP_COMMON_INT_ENA_GPIO_CAP_EN BIT(2)
172
173#define PTP_CLOCK_SET_SEC_HI 0x0205
174#define PTP_CLOCK_SET_SEC_MID 0x0206
175#define PTP_CLOCK_SET_SEC_LO 0x0207
176#define PTP_CLOCK_SET_NS_HI 0x0208
177#define PTP_CLOCK_SET_NS_LO 0x0209
178
179#define PTP_CLOCK_READ_SEC_HI 0x0229
180#define PTP_CLOCK_READ_SEC_MID 0x022A
181#define PTP_CLOCK_READ_SEC_LO 0x022B
182#define PTP_CLOCK_READ_NS_HI 0x022C
183#define PTP_CLOCK_READ_NS_LO 0x022D
184
185#define PTP_GPIO_SEL 0x0230
186#define PTP_GPIO_SEL_GPIO_SEL(pin) ((pin) << 8)
187#define PTP_GPIO_CAP_MAP_LO 0x0232
188
189#define PTP_GPIO_CAP_EN 0x0233
190#define PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(gpio) BIT(gpio)
191#define PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(gpio) (BIT(gpio) << 8)
192
193#define PTP_GPIO_RE_LTC_SEC_HI_CAP 0x0235
194#define PTP_GPIO_RE_LTC_SEC_LO_CAP 0x0236
195#define PTP_GPIO_RE_LTC_NS_HI_CAP 0x0237
196#define PTP_GPIO_RE_LTC_NS_LO_CAP 0x0238
197#define PTP_GPIO_FE_LTC_SEC_HI_CAP 0x0239
198#define PTP_GPIO_FE_LTC_SEC_LO_CAP 0x023A
199#define PTP_GPIO_FE_LTC_NS_HI_CAP 0x023B
200#define PTP_GPIO_FE_LTC_NS_LO_CAP 0x023C
201
202#define PTP_GPIO_CAP_STS 0x023D
203#define PTP_GPIO_CAP_STS_PTP_GPIO_RE_STS(gpio) BIT(gpio)
204#define PTP_GPIO_CAP_STS_PTP_GPIO_FE_STS(gpio) (BIT(gpio) << 8)
205
206#define PTP_OPERATING_MODE 0x0241
207#define PTP_OPERATING_MODE_STANDALONE_ BIT(0)
208
209#define PTP_TX_MOD 0x028F
210#define PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_ BIT(12)
211#define PTP_TX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_ BIT(3)
212
213#define PTP_RX_PARSE_CONFIG 0x0242
214#define PTP_RX_PARSE_CONFIG_LAYER2_EN_ BIT(0)
215#define PTP_RX_PARSE_CONFIG_IPV4_EN_ BIT(1)
216#define PTP_RX_PARSE_CONFIG_IPV6_EN_ BIT(2)
217
218#define PTP_TX_PARSE_CONFIG 0x0282
219#define PTP_TX_PARSE_CONFIG_LAYER2_EN_ BIT(0)
220#define PTP_TX_PARSE_CONFIG_IPV4_EN_ BIT(1)
221#define PTP_TX_PARSE_CONFIG_IPV6_EN_ BIT(2)
222
223#define PTP_CLOCK_RATE_ADJ_HI 0x020C
224#define PTP_CLOCK_RATE_ADJ_LO 0x020D
225#define PTP_CLOCK_RATE_ADJ_DIR_ BIT(15)
226
227#define PTP_LTC_STEP_ADJ_HI 0x0212
228#define PTP_LTC_STEP_ADJ_LO 0x0213
229#define PTP_LTC_STEP_ADJ_DIR_ BIT(15)
230
231#define LAN8814_INTR_STS_REG 0x0033
232#define LAN8814_INTR_STS_REG_1588_TSU0_ BIT(0)
233#define LAN8814_INTR_STS_REG_1588_TSU1_ BIT(1)
234#define LAN8814_INTR_STS_REG_1588_TSU2_ BIT(2)
235#define LAN8814_INTR_STS_REG_1588_TSU3_ BIT(3)
236
237#define PTP_CAP_INFO 0x022A
238#define PTP_CAP_INFO_TX_TS_CNT_GET_(reg_val) (((reg_val) & 0x0f00) >> 8)
239#define PTP_CAP_INFO_RX_TS_CNT_GET_(reg_val) ((reg_val) & 0x000f)
240
241#define PTP_TX_EGRESS_SEC_HI 0x0296
242#define PTP_TX_EGRESS_SEC_LO 0x0297
243#define PTP_TX_EGRESS_NS_HI 0x0294
244#define PTP_TX_EGRESS_NS_LO 0x0295
245#define PTP_TX_MSG_HEADER2 0x0299
246
247#define PTP_RX_INGRESS_SEC_HI 0x0256
248#define PTP_RX_INGRESS_SEC_LO 0x0257
249#define PTP_RX_INGRESS_NS_HI 0x0254
250#define PTP_RX_INGRESS_NS_LO 0x0255
251#define PTP_RX_MSG_HEADER2 0x0259
252
253#define PTP_TSU_INT_EN 0x0200
254#define PTP_TSU_INT_EN_PTP_TX_TS_OVRFL_EN_ BIT(3)
255#define PTP_TSU_INT_EN_PTP_TX_TS_EN_ BIT(2)
256#define PTP_TSU_INT_EN_PTP_RX_TS_OVRFL_EN_ BIT(1)
257#define PTP_TSU_INT_EN_PTP_RX_TS_EN_ BIT(0)
258
259#define PTP_TSU_INT_STS 0x0201
260#define PTP_TSU_INT_STS_PTP_TX_TS_OVRFL_INT_ BIT(3)
261#define PTP_TSU_INT_STS_PTP_TX_TS_EN_ BIT(2)
262#define PTP_TSU_INT_STS_PTP_RX_TS_OVRFL_INT_ BIT(1)
263#define PTP_TSU_INT_STS_PTP_RX_TS_EN_ BIT(0)
264
265#define LAN8814_LED_CTRL_1 0x0
266#define LAN8814_LED_CTRL_1_KSZ9031_LED_MODE_ BIT(6)
267
268/* PHY Control 1 */
269#define MII_KSZPHY_CTRL_1 0x1e
270#define KSZ8081_CTRL1_MDIX_STAT BIT(4)
271
272/* PHY Control 2 / PHY Control (if no PHY Control 1) */
273#define MII_KSZPHY_CTRL_2 0x1f
274#define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2
275/* bitmap of PHY register to set interrupt mode */
276#define KSZ8081_CTRL2_HP_MDIX BIT(15)
277#define KSZ8081_CTRL2_MDI_MDI_X_SELECT BIT(14)
278#define KSZ8081_CTRL2_DISABLE_AUTO_MDIX BIT(13)
279#define KSZ8081_CTRL2_FORCE_LINK BIT(11)
280#define KSZ8081_CTRL2_POWER_SAVING BIT(10)
281#define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9)
282#define KSZPHY_RMII_REF_CLK_SEL BIT(7)
283
284/* Write/read to/from extended registers */
285#define MII_KSZPHY_EXTREG 0x0b
286#define KSZPHY_EXTREG_WRITE 0x8000
287
288#define MII_KSZPHY_EXTREG_WRITE 0x0c
289#define MII_KSZPHY_EXTREG_READ 0x0d
290
291/* Extended registers */
292#define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104
293#define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105
294#define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106
295
296#define PS_TO_REG 200
297#define FIFO_SIZE 8
298
299#define LAN8814_PTP_GPIO_NUM 24
300#define LAN8814_PTP_PEROUT_NUM 2
301#define LAN8814_PTP_EXTTS_NUM 3
302
303#define LAN8814_BUFFER_TIME 2
304
305#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_200MS 13
306#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100MS 12
307#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50MS 11
308#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10MS 10
309#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5MS 9
310#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1MS 8
311#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500US 7
312#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100US 6
313#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50US 5
314#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10US 4
315#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5US 3
316#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1US 2
317#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500NS 1
318#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100NS 0
319
320#define LAN8814_GPIO_EN1 0x20
321#define LAN8814_GPIO_EN2 0x21
322#define LAN8814_GPIO_DIR1 0x22
323#define LAN8814_GPIO_DIR2 0x23
324#define LAN8814_GPIO_BUF1 0x24
325#define LAN8814_GPIO_BUF2 0x25
326
327#define LAN8814_GPIO_EN_ADDR(pin) \
328 ((pin) > 15 ? LAN8814_GPIO_EN1 : LAN8814_GPIO_EN2)
329#define LAN8814_GPIO_EN_BIT(pin) BIT(pin)
330#define LAN8814_GPIO_DIR_ADDR(pin) \
331 ((pin) > 15 ? LAN8814_GPIO_DIR1 : LAN8814_GPIO_DIR2)
332#define LAN8814_GPIO_DIR_BIT(pin) BIT(pin)
333#define LAN8814_GPIO_BUF_ADDR(pin) \
334 ((pin) > 15 ? LAN8814_GPIO_BUF1 : LAN8814_GPIO_BUF2)
335#define LAN8814_GPIO_BUF_BIT(pin) BIT(pin)
336
337#define LAN8814_EVENT_A 0
338#define LAN8814_EVENT_B 1
339
340#define LAN8814_PTP_GENERAL_CONFIG 0x0201
341#define LAN8814_PTP_GENERAL_CONFIG_LTC_EVENT_MASK(event) \
342 ((event) ? GENMASK(11, 8) : GENMASK(7, 4))
343#define LAN8814_PTP_GENERAL_CONFIG_LTC_EVENT_SET(event, value) \
344 (((value) & GENMASK(3, 0)) << (4 + ((event) << 2)))
345#define LAN8814_PTP_GENERAL_CONFIG_RELOAD_ADD_X(event) \
346 ((event) ? BIT(2) : BIT(0))
347#define LAN8814_PTP_GENERAL_CONFIG_POLARITY_X(event) \
348 ((event) ? BIT(3) : BIT(1))
349
350#define LAN8814_PTP_CLOCK_TARGET_SEC_HI(event) ((event) ? 0x21F : 0x215)
351#define LAN8814_PTP_CLOCK_TARGET_SEC_LO(event) ((event) ? 0x220 : 0x216)
352#define LAN8814_PTP_CLOCK_TARGET_NS_HI(event) ((event) ? 0x221 : 0x217)
353#define LAN8814_PTP_CLOCK_TARGET_NS_LO(event) ((event) ? 0x222 : 0x218)
354
355#define LAN8814_PTP_CLOCK_TARGET_RELOAD_SEC_HI(event) ((event) ? 0x223 : 0x219)
356#define LAN8814_PTP_CLOCK_TARGET_RELOAD_SEC_LO(event) ((event) ? 0x224 : 0x21A)
357#define LAN8814_PTP_CLOCK_TARGET_RELOAD_NS_HI(event) ((event) ? 0x225 : 0x21B)
358#define LAN8814_PTP_CLOCK_TARGET_RELOAD_NS_LO(event) ((event) ? 0x226 : 0x21C)
359
360/* Delay used to get the second part from the LTC */
361#define LAN8841_GET_SEC_LTC_DELAY (500 * NSEC_PER_MSEC)
362
363struct kszphy_hw_stat {
364 const char *string;
365 u8 reg;
366 u8 bits;
367};
368
369static struct kszphy_hw_stat kszphy_hw_stats[] = {
370 { "phy_receive_errors", 21, 16},
371 { "phy_idle_errors", 10, 8 },
372};
373
374struct kszphy_type {
375 u32 led_mode_reg;
376 u16 interrupt_level_mask;
377 u16 cable_diag_reg;
378 unsigned long pair_mask;
379 u16 disable_dll_tx_bit;
380 u16 disable_dll_rx_bit;
381 u16 disable_dll_mask;
382 bool has_broadcast_disable;
383 bool has_nand_tree_disable;
384 bool has_rmii_ref_clk_sel;
385};
386
387/* Shared structure between the PHYs of the same package. */
388struct lan8814_shared_priv {
389 struct phy_device *phydev;
390 struct ptp_clock *ptp_clock;
391 struct ptp_clock_info ptp_clock_info;
392 struct ptp_pin_desc *pin_config;
393
394 /* Lock for ptp_clock */
395 struct mutex shared_lock;
396};
397
398struct lan8814_ptp_rx_ts {
399 struct list_head list;
400 u32 seconds;
401 u32 nsec;
402 u16 seq_id;
403};
404
405struct kszphy_ptp_priv {
406 struct mii_timestamper mii_ts;
407 struct phy_device *phydev;
408
409 struct sk_buff_head tx_queue;
410 struct sk_buff_head rx_queue;
411
412 struct list_head rx_ts_list;
413 /* Lock for Rx ts fifo */
414 spinlock_t rx_ts_lock;
415
416 int hwts_tx_type;
417 enum hwtstamp_rx_filters rx_filter;
418 int layer;
419 int version;
420
421 struct ptp_clock *ptp_clock;
422 struct ptp_clock_info ptp_clock_info;
423 /* Lock for ptp_clock */
424 struct mutex ptp_lock;
425 struct ptp_pin_desc *pin_config;
426
427 s64 seconds;
428 /* Lock for accessing seconds */
429 spinlock_t seconds_lock;
430};
431
432struct kszphy_priv {
433 struct kszphy_ptp_priv ptp_priv;
434 const struct kszphy_type *type;
435 struct clk *clk;
436 int led_mode;
437 u16 vct_ctrl1000;
438 bool rmii_ref_clk_sel;
439 bool rmii_ref_clk_sel_val;
440 bool clk_enable;
441 u64 stats[ARRAY_SIZE(kszphy_hw_stats)];
442};
443
444static const struct kszphy_type lan8814_type = {
445 .led_mode_reg = ~LAN8814_LED_CTRL_1,
446 .cable_diag_reg = LAN8814_CABLE_DIAG,
447 .pair_mask = LAN8814_WIRE_PAIR_MASK,
448};
449
450static const struct kszphy_type ksz886x_type = {
451 .cable_diag_reg = KSZ8081_LMD,
452 .pair_mask = KSZPHY_WIRE_PAIR_MASK,
453};
454
455static const struct kszphy_type ksz8021_type = {
456 .led_mode_reg = MII_KSZPHY_CTRL_2,
457 .has_broadcast_disable = true,
458 .has_nand_tree_disable = true,
459 .has_rmii_ref_clk_sel = true,
460};
461
462static const struct kszphy_type ksz8041_type = {
463 .led_mode_reg = MII_KSZPHY_CTRL_1,
464};
465
466static const struct kszphy_type ksz8051_type = {
467 .led_mode_reg = MII_KSZPHY_CTRL_2,
468 .has_nand_tree_disable = true,
469};
470
471static const struct kszphy_type ksz8081_type = {
472 .led_mode_reg = MII_KSZPHY_CTRL_2,
473 .has_broadcast_disable = true,
474 .has_nand_tree_disable = true,
475 .has_rmii_ref_clk_sel = true,
476};
477
478static const struct kszphy_type ks8737_type = {
479 .interrupt_level_mask = BIT(14),
480};
481
482static const struct kszphy_type ksz9021_type = {
483 .interrupt_level_mask = BIT(14),
484};
485
486static const struct kszphy_type ksz9131_type = {
487 .interrupt_level_mask = BIT(14),
488 .disable_dll_tx_bit = BIT(12),
489 .disable_dll_rx_bit = BIT(12),
490 .disable_dll_mask = BIT_MASK(12),
491};
492
493static const struct kszphy_type lan8841_type = {
494 .disable_dll_tx_bit = BIT(14),
495 .disable_dll_rx_bit = BIT(14),
496 .disable_dll_mask = BIT_MASK(14),
497 .cable_diag_reg = LAN8814_CABLE_DIAG,
498 .pair_mask = LAN8814_WIRE_PAIR_MASK,
499};
500
501static int kszphy_extended_write(struct phy_device *phydev,
502 u32 regnum, u16 val)
503{
504 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
505 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
506}
507
508static int kszphy_extended_read(struct phy_device *phydev,
509 u32 regnum)
510{
511 phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
512 return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
513}
514
515static int kszphy_ack_interrupt(struct phy_device *phydev)
516{
517 /* bit[7..0] int status, which is a read and clear register. */
518 int rc;
519
520 rc = phy_read(phydev, MII_KSZPHY_INTCS);
521
522 return (rc < 0) ? rc : 0;
523}
524
525static int kszphy_config_intr(struct phy_device *phydev)
526{
527 const struct kszphy_type *type = phydev->drv->driver_data;
528 int temp, err;
529 u16 mask;
530
531 if (type && type->interrupt_level_mask)
532 mask = type->interrupt_level_mask;
533 else
534 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH;
535
536 /* set the interrupt pin active low */
537 temp = phy_read(phydev, MII_KSZPHY_CTRL);
538 if (temp < 0)
539 return temp;
540 temp &= ~mask;
541 phy_write(phydev, MII_KSZPHY_CTRL, temp);
542
543 /* enable / disable interrupts */
544 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
545 err = kszphy_ack_interrupt(phydev);
546 if (err)
547 return err;
548
549 err = phy_write(phydev, MII_KSZPHY_INTCS, KSZPHY_INTCS_ALL);
550 } else {
551 err = phy_write(phydev, MII_KSZPHY_INTCS, 0);
552 if (err)
553 return err;
554
555 err = kszphy_ack_interrupt(phydev);
556 }
557
558 return err;
559}
560
561static irqreturn_t kszphy_handle_interrupt(struct phy_device *phydev)
562{
563 int irq_status;
564
565 irq_status = phy_read(phydev, MII_KSZPHY_INTCS);
566 if (irq_status < 0) {
567 phy_error(phydev);
568 return IRQ_NONE;
569 }
570
571 if (!(irq_status & KSZPHY_INTCS_STATUS))
572 return IRQ_NONE;
573
574 phy_trigger_machine(phydev);
575
576 return IRQ_HANDLED;
577}
578
579static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)
580{
581 int ctrl;
582
583 ctrl = phy_read(phydev, MII_KSZPHY_CTRL);
584 if (ctrl < 0)
585 return ctrl;
586
587 if (val)
588 ctrl |= KSZPHY_RMII_REF_CLK_SEL;
589 else
590 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL;
591
592 return phy_write(phydev, MII_KSZPHY_CTRL, ctrl);
593}
594
595static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val)
596{
597 int rc, temp, shift;
598
599 switch (reg) {
600 case MII_KSZPHY_CTRL_1:
601 shift = 14;
602 break;
603 case MII_KSZPHY_CTRL_2:
604 shift = 4;
605 break;
606 default:
607 return -EINVAL;
608 }
609
610 temp = phy_read(phydev, reg);
611 if (temp < 0) {
612 rc = temp;
613 goto out;
614 }
615
616 temp &= ~(3 << shift);
617 temp |= val << shift;
618 rc = phy_write(phydev, reg, temp);
619out:
620 if (rc < 0)
621 phydev_err(phydev, "failed to set led mode\n");
622
623 return rc;
624}
625
626/* Disable PHY address 0 as the broadcast address, so that it can be used as a
627 * unique (non-broadcast) address on a shared bus.
628 */
629static int kszphy_broadcast_disable(struct phy_device *phydev)
630{
631 int ret;
632
633 ret = phy_read(phydev, MII_KSZPHY_OMSO);
634 if (ret < 0)
635 goto out;
636
637 ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
638out:
639 if (ret)
640 phydev_err(phydev, "failed to disable broadcast address\n");
641
642 return ret;
643}
644
645static int kszphy_nand_tree_disable(struct phy_device *phydev)
646{
647 int ret;
648
649 ret = phy_read(phydev, MII_KSZPHY_OMSO);
650 if (ret < 0)
651 goto out;
652
653 if (!(ret & KSZPHY_OMSO_NAND_TREE_ON))
654 return 0;
655
656 ret = phy_write(phydev, MII_KSZPHY_OMSO,
657 ret & ~KSZPHY_OMSO_NAND_TREE_ON);
658out:
659 if (ret)
660 phydev_err(phydev, "failed to disable NAND tree mode\n");
661
662 return ret;
663}
664
665/* Some config bits need to be set again on resume, handle them here. */
666static int kszphy_config_reset(struct phy_device *phydev)
667{
668 struct kszphy_priv *priv = phydev->priv;
669 int ret;
670
671 if (priv->rmii_ref_clk_sel) {
672 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val);
673 if (ret) {
674 phydev_err(phydev,
675 "failed to set rmii reference clock\n");
676 return ret;
677 }
678 }
679
680 if (priv->type && priv->led_mode >= 0)
681 kszphy_setup_led(phydev, priv->type->led_mode_reg, priv->led_mode);
682
683 return 0;
684}
685
686static int kszphy_config_init(struct phy_device *phydev)
687{
688 struct kszphy_priv *priv = phydev->priv;
689 const struct kszphy_type *type;
690
691 if (!priv)
692 return 0;
693
694 type = priv->type;
695
696 if (type && type->has_broadcast_disable)
697 kszphy_broadcast_disable(phydev);
698
699 if (type && type->has_nand_tree_disable)
700 kszphy_nand_tree_disable(phydev);
701
702 return kszphy_config_reset(phydev);
703}
704
705static int ksz8041_fiber_mode(struct phy_device *phydev)
706{
707 struct device_node *of_node = phydev->mdio.dev.of_node;
708
709 return of_property_read_bool(of_node, "micrel,fiber-mode");
710}
711
712static int ksz8041_config_init(struct phy_device *phydev)
713{
714 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
715
716 /* Limit supported and advertised modes in fiber mode */
717 if (ksz8041_fiber_mode(phydev)) {
718 phydev->dev_flags |= MICREL_PHY_FXEN;
719 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask);
720 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask);
721
722 linkmode_and(phydev->supported, phydev->supported, mask);
723 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
724 phydev->supported);
725 linkmode_and(phydev->advertising, phydev->advertising, mask);
726 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
727 phydev->advertising);
728 phydev->autoneg = AUTONEG_DISABLE;
729 }
730
731 return kszphy_config_init(phydev);
732}
733
734static int ksz8041_config_aneg(struct phy_device *phydev)
735{
736 /* Skip auto-negotiation in fiber mode */
737 if (phydev->dev_flags & MICREL_PHY_FXEN) {
738 phydev->speed = SPEED_100;
739 return 0;
740 }
741
742 return genphy_config_aneg(phydev);
743}
744
745static int ksz8051_ksz8795_match_phy_device(struct phy_device *phydev,
746 const bool ksz_8051)
747{
748 int ret;
749
750 if (!phy_id_compare(phydev->phy_id, PHY_ID_KSZ8051, MICREL_PHY_ID_MASK))
751 return 0;
752
753 ret = phy_read(phydev, MII_BMSR);
754 if (ret < 0)
755 return ret;
756
757 /* KSZ8051 PHY and KSZ8794/KSZ8795/KSZ8765 switch share the same
758 * exact PHY ID. However, they can be told apart by the extended
759 * capability registers presence. The KSZ8051 PHY has them while
760 * the switch does not.
761 */
762 ret &= BMSR_ERCAP;
763 if (ksz_8051)
764 return ret;
765 else
766 return !ret;
767}
768
769static int ksz8051_match_phy_device(struct phy_device *phydev)
770{
771 return ksz8051_ksz8795_match_phy_device(phydev, true);
772}
773
774static int ksz8081_config_init(struct phy_device *phydev)
775{
776 /* KSZPHY_OMSO_FACTORY_TEST is set at de-assertion of the reset line
777 * based on the RXER (KSZ8081RNA/RND) or TXC (KSZ8081MNX/RNB) pin. If a
778 * pull-down is missing, the factory test mode should be cleared by
779 * manually writing a 0.
780 */
781 phy_clear_bits(phydev, MII_KSZPHY_OMSO, KSZPHY_OMSO_FACTORY_TEST);
782
783 return kszphy_config_init(phydev);
784}
785
786static int ksz8081_config_mdix(struct phy_device *phydev, u8 ctrl)
787{
788 u16 val;
789
790 switch (ctrl) {
791 case ETH_TP_MDI:
792 val = KSZ8081_CTRL2_DISABLE_AUTO_MDIX;
793 break;
794 case ETH_TP_MDI_X:
795 val = KSZ8081_CTRL2_DISABLE_AUTO_MDIX |
796 KSZ8081_CTRL2_MDI_MDI_X_SELECT;
797 break;
798 case ETH_TP_MDI_AUTO:
799 val = 0;
800 break;
801 default:
802 return 0;
803 }
804
805 return phy_modify(phydev, MII_KSZPHY_CTRL_2,
806 KSZ8081_CTRL2_HP_MDIX |
807 KSZ8081_CTRL2_MDI_MDI_X_SELECT |
808 KSZ8081_CTRL2_DISABLE_AUTO_MDIX,
809 KSZ8081_CTRL2_HP_MDIX | val);
810}
811
812static int ksz8081_config_aneg(struct phy_device *phydev)
813{
814 int ret;
815
816 ret = genphy_config_aneg(phydev);
817 if (ret)
818 return ret;
819
820 /* The MDI-X configuration is automatically changed by the PHY after
821 * switching from autoneg off to on. So, take MDI-X configuration under
822 * own control and set it after autoneg configuration was done.
823 */
824 return ksz8081_config_mdix(phydev, phydev->mdix_ctrl);
825}
826
827static int ksz8081_mdix_update(struct phy_device *phydev)
828{
829 int ret;
830
831 ret = phy_read(phydev, MII_KSZPHY_CTRL_2);
832 if (ret < 0)
833 return ret;
834
835 if (ret & KSZ8081_CTRL2_DISABLE_AUTO_MDIX) {
836 if (ret & KSZ8081_CTRL2_MDI_MDI_X_SELECT)
837 phydev->mdix_ctrl = ETH_TP_MDI_X;
838 else
839 phydev->mdix_ctrl = ETH_TP_MDI;
840 } else {
841 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
842 }
843
844 ret = phy_read(phydev, MII_KSZPHY_CTRL_1);
845 if (ret < 0)
846 return ret;
847
848 if (ret & KSZ8081_CTRL1_MDIX_STAT)
849 phydev->mdix = ETH_TP_MDI;
850 else
851 phydev->mdix = ETH_TP_MDI_X;
852
853 return 0;
854}
855
856static int ksz8081_read_status(struct phy_device *phydev)
857{
858 int ret;
859
860 ret = ksz8081_mdix_update(phydev);
861 if (ret < 0)
862 return ret;
863
864 return genphy_read_status(phydev);
865}
866
867static int ksz8061_config_init(struct phy_device *phydev)
868{
869 int ret;
870
871 /* Chip can be powered down by the bootstrap code. */
872 ret = phy_read(phydev, MII_BMCR);
873 if (ret < 0)
874 return ret;
875 if (ret & BMCR_PDOWN) {
876 ret = phy_write(phydev, MII_BMCR, ret & ~BMCR_PDOWN);
877 if (ret < 0)
878 return ret;
879 usleep_range(1000, 2000);
880 }
881
882 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, 0xB61A);
883 if (ret)
884 return ret;
885
886 return kszphy_config_init(phydev);
887}
888
889static int ksz8795_match_phy_device(struct phy_device *phydev)
890{
891 return ksz8051_ksz8795_match_phy_device(phydev, false);
892}
893
894static int ksz9021_load_values_from_of(struct phy_device *phydev,
895 const struct device_node *of_node,
896 u16 reg,
897 const char *field1, const char *field2,
898 const char *field3, const char *field4)
899{
900 int val1 = -1;
901 int val2 = -2;
902 int val3 = -3;
903 int val4 = -4;
904 int newval;
905 int matches = 0;
906
907 if (!of_property_read_u32(of_node, field1, &val1))
908 matches++;
909
910 if (!of_property_read_u32(of_node, field2, &val2))
911 matches++;
912
913 if (!of_property_read_u32(of_node, field3, &val3))
914 matches++;
915
916 if (!of_property_read_u32(of_node, field4, &val4))
917 matches++;
918
919 if (!matches)
920 return 0;
921
922 if (matches < 4)
923 newval = kszphy_extended_read(phydev, reg);
924 else
925 newval = 0;
926
927 if (val1 != -1)
928 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
929
930 if (val2 != -2)
931 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
932
933 if (val3 != -3)
934 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
935
936 if (val4 != -4)
937 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
938
939 return kszphy_extended_write(phydev, reg, newval);
940}
941
942static int ksz9021_config_init(struct phy_device *phydev)
943{
944 const struct device_node *of_node;
945 const struct device *dev_walker;
946
947 /* The Micrel driver has a deprecated option to place phy OF
948 * properties in the MAC node. Walk up the tree of devices to
949 * find a device with an OF node.
950 */
951 dev_walker = &phydev->mdio.dev;
952 do {
953 of_node = dev_walker->of_node;
954 dev_walker = dev_walker->parent;
955
956 } while (!of_node && dev_walker);
957
958 if (of_node) {
959 ksz9021_load_values_from_of(phydev, of_node,
960 MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
961 "txen-skew-ps", "txc-skew-ps",
962 "rxdv-skew-ps", "rxc-skew-ps");
963 ksz9021_load_values_from_of(phydev, of_node,
964 MII_KSZPHY_RX_DATA_PAD_SKEW,
965 "rxd0-skew-ps", "rxd1-skew-ps",
966 "rxd2-skew-ps", "rxd3-skew-ps");
967 ksz9021_load_values_from_of(phydev, of_node,
968 MII_KSZPHY_TX_DATA_PAD_SKEW,
969 "txd0-skew-ps", "txd1-skew-ps",
970 "txd2-skew-ps", "txd3-skew-ps");
971 }
972 return 0;
973}
974
975#define KSZ9031_PS_TO_REG 60
976
977/* Extended registers */
978/* MMD Address 0x0 */
979#define MII_KSZ9031RN_FLP_BURST_TX_LO 3
980#define MII_KSZ9031RN_FLP_BURST_TX_HI 4
981
982/* MMD Address 0x2 */
983#define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
984#define MII_KSZ9031RN_RX_CTL_M GENMASK(7, 4)
985#define MII_KSZ9031RN_TX_CTL_M GENMASK(3, 0)
986
987#define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
988#define MII_KSZ9031RN_RXD3 GENMASK(15, 12)
989#define MII_KSZ9031RN_RXD2 GENMASK(11, 8)
990#define MII_KSZ9031RN_RXD1 GENMASK(7, 4)
991#define MII_KSZ9031RN_RXD0 GENMASK(3, 0)
992
993#define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6
994#define MII_KSZ9031RN_TXD3 GENMASK(15, 12)
995#define MII_KSZ9031RN_TXD2 GENMASK(11, 8)
996#define MII_KSZ9031RN_TXD1 GENMASK(7, 4)
997#define MII_KSZ9031RN_TXD0 GENMASK(3, 0)
998
999#define MII_KSZ9031RN_CLK_PAD_SKEW 8
1000#define MII_KSZ9031RN_GTX_CLK GENMASK(9, 5)
1001#define MII_KSZ9031RN_RX_CLK GENMASK(4, 0)
1002
1003/* KSZ9031 has internal RGMII_IDRX = 1.2ns and RGMII_IDTX = 0ns. To
1004 * provide different RGMII options we need to configure delay offset
1005 * for each pad relative to build in delay.
1006 */
1007/* keep rx as "No delay adjustment" and set rx_clk to +0.60ns to get delays of
1008 * 1.80ns
1009 */
1010#define RX_ID 0x7
1011#define RX_CLK_ID 0x19
1012
1013/* set rx to +0.30ns and rx_clk to -0.90ns to compensate the
1014 * internal 1.2ns delay.
1015 */
1016#define RX_ND 0xc
1017#define RX_CLK_ND 0x0
1018
1019/* set tx to -0.42ns and tx_clk to +0.96ns to get 1.38ns delay */
1020#define TX_ID 0x0
1021#define TX_CLK_ID 0x1f
1022
1023/* set tx and tx_clk to "No delay adjustment" to keep 0ns
1024 * dealy
1025 */
1026#define TX_ND 0x7
1027#define TX_CLK_ND 0xf
1028
1029/* MMD Address 0x1C */
1030#define MII_KSZ9031RN_EDPD 0x23
1031#define MII_KSZ9031RN_EDPD_ENABLE BIT(0)
1032
1033static int ksz9031_of_load_skew_values(struct phy_device *phydev,
1034 const struct device_node *of_node,
1035 u16 reg, size_t field_sz,
1036 const char *field[], u8 numfields,
1037 bool *update)
1038{
1039 int val[4] = {-1, -2, -3, -4};
1040 int matches = 0;
1041 u16 mask;
1042 u16 maxval;
1043 u16 newval;
1044 int i;
1045
1046 for (i = 0; i < numfields; i++)
1047 if (!of_property_read_u32(of_node, field[i], val + i))
1048 matches++;
1049
1050 if (!matches)
1051 return 0;
1052
1053 *update |= true;
1054
1055 if (matches < numfields)
1056 newval = phy_read_mmd(phydev, 2, reg);
1057 else
1058 newval = 0;
1059
1060 maxval = (field_sz == 4) ? 0xf : 0x1f;
1061 for (i = 0; i < numfields; i++)
1062 if (val[i] != -(i + 1)) {
1063 mask = 0xffff;
1064 mask ^= maxval << (field_sz * i);
1065 newval = (newval & mask) |
1066 (((val[i] / KSZ9031_PS_TO_REG) & maxval)
1067 << (field_sz * i));
1068 }
1069
1070 return phy_write_mmd(phydev, 2, reg, newval);
1071}
1072
1073/* Center KSZ9031RNX FLP timing at 16ms. */
1074static int ksz9031_center_flp_timing(struct phy_device *phydev)
1075{
1076 int result;
1077
1078 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_HI,
1079 0x0006);
1080 if (result)
1081 return result;
1082
1083 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_LO,
1084 0x1A80);
1085 if (result)
1086 return result;
1087
1088 return genphy_restart_aneg(phydev);
1089}
1090
1091/* Enable energy-detect power-down mode */
1092static int ksz9031_enable_edpd(struct phy_device *phydev)
1093{
1094 int reg;
1095
1096 reg = phy_read_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD);
1097 if (reg < 0)
1098 return reg;
1099 return phy_write_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD,
1100 reg | MII_KSZ9031RN_EDPD_ENABLE);
1101}
1102
1103static int ksz9031_config_rgmii_delay(struct phy_device *phydev)
1104{
1105 u16 rx, tx, rx_clk, tx_clk;
1106 int ret;
1107
1108 switch (phydev->interface) {
1109 case PHY_INTERFACE_MODE_RGMII:
1110 tx = TX_ND;
1111 tx_clk = TX_CLK_ND;
1112 rx = RX_ND;
1113 rx_clk = RX_CLK_ND;
1114 break;
1115 case PHY_INTERFACE_MODE_RGMII_ID:
1116 tx = TX_ID;
1117 tx_clk = TX_CLK_ID;
1118 rx = RX_ID;
1119 rx_clk = RX_CLK_ID;
1120 break;
1121 case PHY_INTERFACE_MODE_RGMII_RXID:
1122 tx = TX_ND;
1123 tx_clk = TX_CLK_ND;
1124 rx = RX_ID;
1125 rx_clk = RX_CLK_ID;
1126 break;
1127 case PHY_INTERFACE_MODE_RGMII_TXID:
1128 tx = TX_ID;
1129 tx_clk = TX_CLK_ID;
1130 rx = RX_ND;
1131 rx_clk = RX_CLK_ND;
1132 break;
1133 default:
1134 return 0;
1135 }
1136
1137 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_CONTROL_PAD_SKEW,
1138 FIELD_PREP(MII_KSZ9031RN_RX_CTL_M, rx) |
1139 FIELD_PREP(MII_KSZ9031RN_TX_CTL_M, tx));
1140 if (ret < 0)
1141 return ret;
1142
1143 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_RX_DATA_PAD_SKEW,
1144 FIELD_PREP(MII_KSZ9031RN_RXD3, rx) |
1145 FIELD_PREP(MII_KSZ9031RN_RXD2, rx) |
1146 FIELD_PREP(MII_KSZ9031RN_RXD1, rx) |
1147 FIELD_PREP(MII_KSZ9031RN_RXD0, rx));
1148 if (ret < 0)
1149 return ret;
1150
1151 ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_TX_DATA_PAD_SKEW,
1152 FIELD_PREP(MII_KSZ9031RN_TXD3, tx) |
1153 FIELD_PREP(MII_KSZ9031RN_TXD2, tx) |
1154 FIELD_PREP(MII_KSZ9031RN_TXD1, tx) |
1155 FIELD_PREP(MII_KSZ9031RN_TXD0, tx));
1156 if (ret < 0)
1157 return ret;
1158
1159 return phy_write_mmd(phydev, 2, MII_KSZ9031RN_CLK_PAD_SKEW,
1160 FIELD_PREP(MII_KSZ9031RN_GTX_CLK, tx_clk) |
1161 FIELD_PREP(MII_KSZ9031RN_RX_CLK, rx_clk));
1162}
1163
1164static int ksz9031_config_init(struct phy_device *phydev)
1165{
1166 const struct device_node *of_node;
1167 static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
1168 static const char *rx_data_skews[4] = {
1169 "rxd0-skew-ps", "rxd1-skew-ps",
1170 "rxd2-skew-ps", "rxd3-skew-ps"
1171 };
1172 static const char *tx_data_skews[4] = {
1173 "txd0-skew-ps", "txd1-skew-ps",
1174 "txd2-skew-ps", "txd3-skew-ps"
1175 };
1176 static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
1177 const struct device *dev_walker;
1178 int result;
1179
1180 result = ksz9031_enable_edpd(phydev);
1181 if (result < 0)
1182 return result;
1183
1184 /* The Micrel driver has a deprecated option to place phy OF
1185 * properties in the MAC node. Walk up the tree of devices to
1186 * find a device with an OF node.
1187 */
1188 dev_walker = &phydev->mdio.dev;
1189 do {
1190 of_node = dev_walker->of_node;
1191 dev_walker = dev_walker->parent;
1192 } while (!of_node && dev_walker);
1193
1194 if (of_node) {
1195 bool update = false;
1196
1197 if (phy_interface_is_rgmii(phydev)) {
1198 result = ksz9031_config_rgmii_delay(phydev);
1199 if (result < 0)
1200 return result;
1201 }
1202
1203 ksz9031_of_load_skew_values(phydev, of_node,
1204 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
1205 clk_skews, 2, &update);
1206
1207 ksz9031_of_load_skew_values(phydev, of_node,
1208 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
1209 control_skews, 2, &update);
1210
1211 ksz9031_of_load_skew_values(phydev, of_node,
1212 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
1213 rx_data_skews, 4, &update);
1214
1215 ksz9031_of_load_skew_values(phydev, of_node,
1216 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
1217 tx_data_skews, 4, &update);
1218
1219 if (update && !phy_interface_is_rgmii(phydev))
1220 phydev_warn(phydev,
1221 "*-skew-ps values should be used only with RGMII PHY modes\n");
1222
1223 /* Silicon Errata Sheet (DS80000691D or DS80000692D):
1224 * When the device links in the 1000BASE-T slave mode only,
1225 * the optional 125MHz reference output clock (CLK125_NDO)
1226 * has wide duty cycle variation.
1227 *
1228 * The optional CLK125_NDO clock does not meet the RGMII
1229 * 45/55 percent (min/max) duty cycle requirement and therefore
1230 * cannot be used directly by the MAC side for clocking
1231 * applications that have setup/hold time requirements on
1232 * rising and falling clock edges.
1233 *
1234 * Workaround:
1235 * Force the phy to be the master to receive a stable clock
1236 * which meets the duty cycle requirement.
1237 */
1238 if (of_property_read_bool(of_node, "micrel,force-master")) {
1239 result = phy_read(phydev, MII_CTRL1000);
1240 if (result < 0)
1241 goto err_force_master;
1242
1243 /* enable master mode, config & prefer master */
1244 result |= CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER;
1245 result = phy_write(phydev, MII_CTRL1000, result);
1246 if (result < 0)
1247 goto err_force_master;
1248 }
1249 }
1250
1251 return ksz9031_center_flp_timing(phydev);
1252
1253err_force_master:
1254 phydev_err(phydev, "failed to force the phy to master mode\n");
1255 return result;
1256}
1257
1258#define KSZ9131_SKEW_5BIT_MAX 2400
1259#define KSZ9131_SKEW_4BIT_MAX 800
1260#define KSZ9131_OFFSET 700
1261#define KSZ9131_STEP 100
1262
1263static int ksz9131_of_load_skew_values(struct phy_device *phydev,
1264 struct device_node *of_node,
1265 u16 reg, size_t field_sz,
1266 char *field[], u8 numfields)
1267{
1268 int val[4] = {-(1 + KSZ9131_OFFSET), -(2 + KSZ9131_OFFSET),
1269 -(3 + KSZ9131_OFFSET), -(4 + KSZ9131_OFFSET)};
1270 int skewval, skewmax = 0;
1271 int matches = 0;
1272 u16 maxval;
1273 u16 newval;
1274 u16 mask;
1275 int i;
1276
1277 /* psec properties in dts should mean x pico seconds */
1278 if (field_sz == 5)
1279 skewmax = KSZ9131_SKEW_5BIT_MAX;
1280 else
1281 skewmax = KSZ9131_SKEW_4BIT_MAX;
1282
1283 for (i = 0; i < numfields; i++)
1284 if (!of_property_read_s32(of_node, field[i], &skewval)) {
1285 if (skewval < -KSZ9131_OFFSET)
1286 skewval = -KSZ9131_OFFSET;
1287 else if (skewval > skewmax)
1288 skewval = skewmax;
1289
1290 val[i] = skewval + KSZ9131_OFFSET;
1291 matches++;
1292 }
1293
1294 if (!matches)
1295 return 0;
1296
1297 if (matches < numfields)
1298 newval = phy_read_mmd(phydev, 2, reg);
1299 else
1300 newval = 0;
1301
1302 maxval = (field_sz == 4) ? 0xf : 0x1f;
1303 for (i = 0; i < numfields; i++)
1304 if (val[i] != -(i + 1 + KSZ9131_OFFSET)) {
1305 mask = 0xffff;
1306 mask ^= maxval << (field_sz * i);
1307 newval = (newval & mask) |
1308 (((val[i] / KSZ9131_STEP) & maxval)
1309 << (field_sz * i));
1310 }
1311
1312 return phy_write_mmd(phydev, 2, reg, newval);
1313}
1314
1315#define KSZ9131RN_MMD_COMMON_CTRL_REG 2
1316#define KSZ9131RN_RXC_DLL_CTRL 76
1317#define KSZ9131RN_TXC_DLL_CTRL 77
1318#define KSZ9131RN_DLL_ENABLE_DELAY 0
1319
1320static int ksz9131_config_rgmii_delay(struct phy_device *phydev)
1321{
1322 const struct kszphy_type *type = phydev->drv->driver_data;
1323 u16 rxcdll_val, txcdll_val;
1324 int ret;
1325
1326 switch (phydev->interface) {
1327 case PHY_INTERFACE_MODE_RGMII:
1328 rxcdll_val = type->disable_dll_rx_bit;
1329 txcdll_val = type->disable_dll_tx_bit;
1330 break;
1331 case PHY_INTERFACE_MODE_RGMII_ID:
1332 rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1333 txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1334 break;
1335 case PHY_INTERFACE_MODE_RGMII_RXID:
1336 rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1337 txcdll_val = type->disable_dll_tx_bit;
1338 break;
1339 case PHY_INTERFACE_MODE_RGMII_TXID:
1340 rxcdll_val = type->disable_dll_rx_bit;
1341 txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1342 break;
1343 default:
1344 return 0;
1345 }
1346
1347 ret = phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
1348 KSZ9131RN_RXC_DLL_CTRL, type->disable_dll_mask,
1349 rxcdll_val);
1350 if (ret < 0)
1351 return ret;
1352
1353 return phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
1354 KSZ9131RN_TXC_DLL_CTRL, type->disable_dll_mask,
1355 txcdll_val);
1356}
1357
1358/* Silicon Errata DS80000693B
1359 *
1360 * When LEDs are configured in Individual Mode, LED1 is ON in a no-link
1361 * condition. Workaround is to set register 0x1e, bit 9, this way LED1 behaves
1362 * according to the datasheet (off if there is no link).
1363 */
1364static int ksz9131_led_errata(struct phy_device *phydev)
1365{
1366 int reg;
1367
1368 reg = phy_read_mmd(phydev, 2, 0);
1369 if (reg < 0)
1370 return reg;
1371
1372 if (!(reg & BIT(4)))
1373 return 0;
1374
1375 return phy_set_bits(phydev, 0x1e, BIT(9));
1376}
1377
1378static int ksz9131_config_init(struct phy_device *phydev)
1379{
1380 struct device_node *of_node;
1381 char *clk_skews[2] = {"rxc-skew-psec", "txc-skew-psec"};
1382 char *rx_data_skews[4] = {
1383 "rxd0-skew-psec", "rxd1-skew-psec",
1384 "rxd2-skew-psec", "rxd3-skew-psec"
1385 };
1386 char *tx_data_skews[4] = {
1387 "txd0-skew-psec", "txd1-skew-psec",
1388 "txd2-skew-psec", "txd3-skew-psec"
1389 };
1390 char *control_skews[2] = {"txen-skew-psec", "rxdv-skew-psec"};
1391 const struct device *dev_walker;
1392 int ret;
1393
1394 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1395
1396 dev_walker = &phydev->mdio.dev;
1397 do {
1398 of_node = dev_walker->of_node;
1399 dev_walker = dev_walker->parent;
1400 } while (!of_node && dev_walker);
1401
1402 if (!of_node)
1403 return 0;
1404
1405 if (phy_interface_is_rgmii(phydev)) {
1406 ret = ksz9131_config_rgmii_delay(phydev);
1407 if (ret < 0)
1408 return ret;
1409 }
1410
1411 ret = ksz9131_of_load_skew_values(phydev, of_node,
1412 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
1413 clk_skews, 2);
1414 if (ret < 0)
1415 return ret;
1416
1417 ret = ksz9131_of_load_skew_values(phydev, of_node,
1418 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
1419 control_skews, 2);
1420 if (ret < 0)
1421 return ret;
1422
1423 ret = ksz9131_of_load_skew_values(phydev, of_node,
1424 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
1425 rx_data_skews, 4);
1426 if (ret < 0)
1427 return ret;
1428
1429 ret = ksz9131_of_load_skew_values(phydev, of_node,
1430 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
1431 tx_data_skews, 4);
1432 if (ret < 0)
1433 return ret;
1434
1435 ret = ksz9131_led_errata(phydev);
1436 if (ret < 0)
1437 return ret;
1438
1439 return 0;
1440}
1441
1442#define MII_KSZ9131_AUTO_MDIX 0x1C
1443#define MII_KSZ9131_AUTO_MDI_SET BIT(7)
1444#define MII_KSZ9131_AUTO_MDIX_SWAP_OFF BIT(6)
1445#define MII_KSZ9131_DIG_AXAN_STS 0x14
1446#define MII_KSZ9131_DIG_AXAN_STS_LINK_DET BIT(14)
1447#define MII_KSZ9131_DIG_AXAN_STS_A_SELECT BIT(12)
1448
1449static int ksz9131_mdix_update(struct phy_device *phydev)
1450{
1451 int ret;
1452
1453 if (phydev->mdix_ctrl != ETH_TP_MDI_AUTO) {
1454 phydev->mdix = phydev->mdix_ctrl;
1455 } else {
1456 ret = phy_read(phydev, MII_KSZ9131_DIG_AXAN_STS);
1457 if (ret < 0)
1458 return ret;
1459
1460 if (ret & MII_KSZ9131_DIG_AXAN_STS_LINK_DET) {
1461 if (ret & MII_KSZ9131_DIG_AXAN_STS_A_SELECT)
1462 phydev->mdix = ETH_TP_MDI;
1463 else
1464 phydev->mdix = ETH_TP_MDI_X;
1465 } else {
1466 phydev->mdix = ETH_TP_MDI_INVALID;
1467 }
1468 }
1469
1470 return 0;
1471}
1472
1473static int ksz9131_config_mdix(struct phy_device *phydev, u8 ctrl)
1474{
1475 u16 val;
1476
1477 switch (ctrl) {
1478 case ETH_TP_MDI:
1479 val = MII_KSZ9131_AUTO_MDIX_SWAP_OFF |
1480 MII_KSZ9131_AUTO_MDI_SET;
1481 break;
1482 case ETH_TP_MDI_X:
1483 val = MII_KSZ9131_AUTO_MDIX_SWAP_OFF;
1484 break;
1485 case ETH_TP_MDI_AUTO:
1486 val = 0;
1487 break;
1488 default:
1489 return 0;
1490 }
1491
1492 return phy_modify(phydev, MII_KSZ9131_AUTO_MDIX,
1493 MII_KSZ9131_AUTO_MDIX_SWAP_OFF |
1494 MII_KSZ9131_AUTO_MDI_SET, val);
1495}
1496
1497static int ksz9131_read_status(struct phy_device *phydev)
1498{
1499 int ret;
1500
1501 ret = ksz9131_mdix_update(phydev);
1502 if (ret < 0)
1503 return ret;
1504
1505 return genphy_read_status(phydev);
1506}
1507
1508static int ksz9131_config_aneg(struct phy_device *phydev)
1509{
1510 int ret;
1511
1512 ret = ksz9131_config_mdix(phydev, phydev->mdix_ctrl);
1513 if (ret)
1514 return ret;
1515
1516 return genphy_config_aneg(phydev);
1517}
1518
1519static int ksz9477_get_features(struct phy_device *phydev)
1520{
1521 int ret;
1522
1523 ret = genphy_read_abilities(phydev);
1524 if (ret)
1525 return ret;
1526
1527 /* The "EEE control and capability 1" (Register 3.20) seems to be
1528 * influenced by the "EEE advertisement 1" (Register 7.60). Changes
1529 * on the 7.60 will affect 3.20. So, we need to construct our own list
1530 * of caps.
1531 * KSZ8563R should have 100BaseTX/Full only.
1532 */
1533 linkmode_and(phydev->supported_eee, phydev->supported,
1534 PHY_EEE_CAP1_FEATURES);
1535
1536 return 0;
1537}
1538
1539#define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
1540#define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6)
1541#define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4)
1542static int ksz8873mll_read_status(struct phy_device *phydev)
1543{
1544 int regval;
1545
1546 /* dummy read */
1547 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
1548
1549 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
1550
1551 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
1552 phydev->duplex = DUPLEX_HALF;
1553 else
1554 phydev->duplex = DUPLEX_FULL;
1555
1556 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
1557 phydev->speed = SPEED_10;
1558 else
1559 phydev->speed = SPEED_100;
1560
1561 phydev->link = 1;
1562 phydev->pause = phydev->asym_pause = 0;
1563
1564 return 0;
1565}
1566
1567static int ksz9031_get_features(struct phy_device *phydev)
1568{
1569 int ret;
1570
1571 ret = genphy_read_abilities(phydev);
1572 if (ret < 0)
1573 return ret;
1574
1575 /* Silicon Errata Sheet (DS80000691D or DS80000692D):
1576 * Whenever the device's Asymmetric Pause capability is set to 1,
1577 * link-up may fail after a link-up to link-down transition.
1578 *
1579 * The Errata Sheet is for ksz9031, but ksz9021 has the same issue
1580 *
1581 * Workaround:
1582 * Do not enable the Asymmetric Pause capability bit.
1583 */
1584 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported);
1585
1586 /* We force setting the Pause capability as the core will force the
1587 * Asymmetric Pause capability to 1 otherwise.
1588 */
1589 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported);
1590
1591 return 0;
1592}
1593
1594static int ksz9031_read_status(struct phy_device *phydev)
1595{
1596 int err;
1597 int regval;
1598
1599 err = genphy_read_status(phydev);
1600 if (err)
1601 return err;
1602
1603 /* Make sure the PHY is not broken. Read idle error count,
1604 * and reset the PHY if it is maxed out.
1605 */
1606 regval = phy_read(phydev, MII_STAT1000);
1607 if ((regval & 0xFF) == 0xFF) {
1608 phy_init_hw(phydev);
1609 phydev->link = 0;
1610 if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev))
1611 phydev->drv->config_intr(phydev);
1612 return genphy_config_aneg(phydev);
1613 }
1614
1615 return 0;
1616}
1617
1618static int ksz9x31_cable_test_start(struct phy_device *phydev)
1619{
1620 struct kszphy_priv *priv = phydev->priv;
1621 int ret;
1622
1623 /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1624 * Prior to running the cable diagnostics, Auto-negotiation should
1625 * be disabled, full duplex set and the link speed set to 1000Mbps
1626 * via the Basic Control Register.
1627 */
1628 ret = phy_modify(phydev, MII_BMCR,
1629 BMCR_SPEED1000 | BMCR_FULLDPLX |
1630 BMCR_ANENABLE | BMCR_SPEED100,
1631 BMCR_SPEED1000 | BMCR_FULLDPLX);
1632 if (ret)
1633 return ret;
1634
1635 /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1636 * The Master-Slave configuration should be set to Slave by writing
1637 * a value of 0x1000 to the Auto-Negotiation Master Slave Control
1638 * Register.
1639 */
1640 ret = phy_read(phydev, MII_CTRL1000);
1641 if (ret < 0)
1642 return ret;
1643
1644 /* Cache these bits, they need to be restored once LinkMD finishes. */
1645 priv->vct_ctrl1000 = ret & (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
1646 ret &= ~(CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
1647 ret |= CTL1000_ENABLE_MASTER;
1648
1649 return phy_write(phydev, MII_CTRL1000, ret);
1650}
1651
1652static int ksz9x31_cable_test_result_trans(u16 status)
1653{
1654 switch (FIELD_GET(KSZ9x31_LMD_VCT_ST_MASK, status)) {
1655 case KSZ9x31_LMD_VCT_ST_NORMAL:
1656 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
1657 case KSZ9x31_LMD_VCT_ST_OPEN:
1658 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
1659 case KSZ9x31_LMD_VCT_ST_SHORT:
1660 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
1661 case KSZ9x31_LMD_VCT_ST_FAIL:
1662 fallthrough;
1663 default:
1664 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
1665 }
1666}
1667
1668static bool ksz9x31_cable_test_failed(u16 status)
1669{
1670 int stat = FIELD_GET(KSZ9x31_LMD_VCT_ST_MASK, status);
1671
1672 return stat == KSZ9x31_LMD_VCT_ST_FAIL;
1673}
1674
1675static bool ksz9x31_cable_test_fault_length_valid(u16 status)
1676{
1677 switch (FIELD_GET(KSZ9x31_LMD_VCT_ST_MASK, status)) {
1678 case KSZ9x31_LMD_VCT_ST_OPEN:
1679 fallthrough;
1680 case KSZ9x31_LMD_VCT_ST_SHORT:
1681 return true;
1682 }
1683 return false;
1684}
1685
1686static int ksz9x31_cable_test_fault_length(struct phy_device *phydev, u16 stat)
1687{
1688 int dt = FIELD_GET(KSZ9x31_LMD_VCT_DATA_MASK, stat);
1689
1690 /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1691 *
1692 * distance to fault = (VCT_DATA - 22) * 4 / cable propagation velocity
1693 */
1694 if (phydev_id_compare(phydev, PHY_ID_KSZ9131))
1695 dt = clamp(dt - 22, 0, 255);
1696
1697 return (dt * 400) / 10;
1698}
1699
1700static int ksz9x31_cable_test_wait_for_completion(struct phy_device *phydev)
1701{
1702 int val, ret;
1703
1704 ret = phy_read_poll_timeout(phydev, KSZ9x31_LMD, val,
1705 !(val & KSZ9x31_LMD_VCT_EN),
1706 30000, 100000, true);
1707
1708 return ret < 0 ? ret : 0;
1709}
1710
1711static int ksz9x31_cable_test_get_pair(int pair)
1712{
1713 static const int ethtool_pair[] = {
1714 ETHTOOL_A_CABLE_PAIR_A,
1715 ETHTOOL_A_CABLE_PAIR_B,
1716 ETHTOOL_A_CABLE_PAIR_C,
1717 ETHTOOL_A_CABLE_PAIR_D,
1718 };
1719
1720 return ethtool_pair[pair];
1721}
1722
1723static int ksz9x31_cable_test_one_pair(struct phy_device *phydev, int pair)
1724{
1725 int ret, val;
1726
1727 /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1728 * To test each individual cable pair, set the cable pair in the Cable
1729 * Diagnostics Test Pair (VCT_PAIR[1:0]) field of the LinkMD Cable
1730 * Diagnostic Register, along with setting the Cable Diagnostics Test
1731 * Enable (VCT_EN) bit. The Cable Diagnostics Test Enable (VCT_EN) bit
1732 * will self clear when the test is concluded.
1733 */
1734 ret = phy_write(phydev, KSZ9x31_LMD,
1735 KSZ9x31_LMD_VCT_EN | KSZ9x31_LMD_VCT_PAIR(pair));
1736 if (ret)
1737 return ret;
1738
1739 ret = ksz9x31_cable_test_wait_for_completion(phydev);
1740 if (ret)
1741 return ret;
1742
1743 val = phy_read(phydev, KSZ9x31_LMD);
1744 if (val < 0)
1745 return val;
1746
1747 if (ksz9x31_cable_test_failed(val))
1748 return -EAGAIN;
1749
1750 ret = ethnl_cable_test_result(phydev,
1751 ksz9x31_cable_test_get_pair(pair),
1752 ksz9x31_cable_test_result_trans(val));
1753 if (ret)
1754 return ret;
1755
1756 if (!ksz9x31_cable_test_fault_length_valid(val))
1757 return 0;
1758
1759 return ethnl_cable_test_fault_length(phydev,
1760 ksz9x31_cable_test_get_pair(pair),
1761 ksz9x31_cable_test_fault_length(phydev, val));
1762}
1763
1764static int ksz9x31_cable_test_get_status(struct phy_device *phydev,
1765 bool *finished)
1766{
1767 struct kszphy_priv *priv = phydev->priv;
1768 unsigned long pair_mask = 0xf;
1769 int retries = 20;
1770 int pair, ret, rv;
1771
1772 *finished = false;
1773
1774 /* Try harder if link partner is active */
1775 while (pair_mask && retries--) {
1776 for_each_set_bit(pair, &pair_mask, 4) {
1777 ret = ksz9x31_cable_test_one_pair(phydev, pair);
1778 if (ret == -EAGAIN)
1779 continue;
1780 if (ret < 0)
1781 return ret;
1782 clear_bit(pair, &pair_mask);
1783 }
1784 /* If link partner is in autonegotiation mode it will send 2ms
1785 * of FLPs with at least 6ms of silence.
1786 * Add 2ms sleep to have better chances to hit this silence.
1787 */
1788 if (pair_mask)
1789 usleep_range(2000, 3000);
1790 }
1791
1792 /* Report remaining unfinished pair result as unknown. */
1793 for_each_set_bit(pair, &pair_mask, 4) {
1794 ret = ethnl_cable_test_result(phydev,
1795 ksz9x31_cable_test_get_pair(pair),
1796 ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC);
1797 }
1798
1799 *finished = true;
1800
1801 /* Restore cached bits from before LinkMD got started. */
1802 rv = phy_modify(phydev, MII_CTRL1000,
1803 CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER,
1804 priv->vct_ctrl1000);
1805 if (rv)
1806 return rv;
1807
1808 return ret;
1809}
1810
1811static int ksz8873mll_config_aneg(struct phy_device *phydev)
1812{
1813 return 0;
1814}
1815
1816static int ksz886x_config_mdix(struct phy_device *phydev, u8 ctrl)
1817{
1818 u16 val;
1819
1820 switch (ctrl) {
1821 case ETH_TP_MDI:
1822 val = KSZ886X_BMCR_DISABLE_AUTO_MDIX;
1823 break;
1824 case ETH_TP_MDI_X:
1825 /* Note: The naming of the bit KSZ886X_BMCR_FORCE_MDI is bit
1826 * counter intuitive, the "-X" in "1 = Force MDI" in the data
1827 * sheet seems to be missing:
1828 * 1 = Force MDI (sic!) (transmit on RX+/RX- pins)
1829 * 0 = Normal operation (transmit on TX+/TX- pins)
1830 */
1831 val = KSZ886X_BMCR_DISABLE_AUTO_MDIX | KSZ886X_BMCR_FORCE_MDI;
1832 break;
1833 case ETH_TP_MDI_AUTO:
1834 val = 0;
1835 break;
1836 default:
1837 return 0;
1838 }
1839
1840 return phy_modify(phydev, MII_BMCR,
1841 KSZ886X_BMCR_HP_MDIX | KSZ886X_BMCR_FORCE_MDI |
1842 KSZ886X_BMCR_DISABLE_AUTO_MDIX,
1843 KSZ886X_BMCR_HP_MDIX | val);
1844}
1845
1846static int ksz886x_config_aneg(struct phy_device *phydev)
1847{
1848 int ret;
1849
1850 ret = genphy_config_aneg(phydev);
1851 if (ret)
1852 return ret;
1853
1854 if (phydev->autoneg != AUTONEG_ENABLE) {
1855 /* When autonegotation is disabled, we need to manually force
1856 * the link state. If we don't do this, the PHY will keep
1857 * sending Fast Link Pulses (FLPs) which are part of the
1858 * autonegotiation process. This is not desired when
1859 * autonegotiation is off.
1860 */
1861 ret = phy_set_bits(phydev, MII_KSZPHY_CTRL,
1862 KSZ886X_CTRL_FORCE_LINK);
1863 if (ret)
1864 return ret;
1865 } else {
1866 /* If we had previously forced the link state, we need to
1867 * clear KSZ886X_CTRL_FORCE_LINK bit now. Otherwise, the PHY
1868 * will not perform autonegotiation.
1869 */
1870 ret = phy_clear_bits(phydev, MII_KSZPHY_CTRL,
1871 KSZ886X_CTRL_FORCE_LINK);
1872 if (ret)
1873 return ret;
1874 }
1875
1876 /* The MDI-X configuration is automatically changed by the PHY after
1877 * switching from autoneg off to on. So, take MDI-X configuration under
1878 * own control and set it after autoneg configuration was done.
1879 */
1880 return ksz886x_config_mdix(phydev, phydev->mdix_ctrl);
1881}
1882
1883static int ksz886x_mdix_update(struct phy_device *phydev)
1884{
1885 int ret;
1886
1887 ret = phy_read(phydev, MII_BMCR);
1888 if (ret < 0)
1889 return ret;
1890
1891 if (ret & KSZ886X_BMCR_DISABLE_AUTO_MDIX) {
1892 if (ret & KSZ886X_BMCR_FORCE_MDI)
1893 phydev->mdix_ctrl = ETH_TP_MDI_X;
1894 else
1895 phydev->mdix_ctrl = ETH_TP_MDI;
1896 } else {
1897 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1898 }
1899
1900 ret = phy_read(phydev, MII_KSZPHY_CTRL);
1901 if (ret < 0)
1902 return ret;
1903
1904 /* Same reverse logic as KSZ886X_BMCR_FORCE_MDI */
1905 if (ret & KSZ886X_CTRL_MDIX_STAT)
1906 phydev->mdix = ETH_TP_MDI_X;
1907 else
1908 phydev->mdix = ETH_TP_MDI;
1909
1910 return 0;
1911}
1912
1913static int ksz886x_read_status(struct phy_device *phydev)
1914{
1915 int ret;
1916
1917 ret = ksz886x_mdix_update(phydev);
1918 if (ret < 0)
1919 return ret;
1920
1921 return genphy_read_status(phydev);
1922}
1923
1924struct ksz9477_errata_write {
1925 u8 dev_addr;
1926 u8 reg_addr;
1927 u16 val;
1928};
1929
1930static const struct ksz9477_errata_write ksz9477_errata_writes[] = {
1931 /* Register settings are needed to improve PHY receive performance */
1932 {0x01, 0x6f, 0xdd0b},
1933 {0x01, 0x8f, 0x6032},
1934 {0x01, 0x9d, 0x248c},
1935 {0x01, 0x75, 0x0060},
1936 {0x01, 0xd3, 0x7777},
1937 {0x1c, 0x06, 0x3008},
1938 {0x1c, 0x08, 0x2000},
1939
1940 /* Transmit waveform amplitude can be improved (1000BASE-T, 100BASE-TX, 10BASE-Te) */
1941 {0x1c, 0x04, 0x00d0},
1942
1943 /* Register settings are required to meet data sheet supply current specifications */
1944 {0x1c, 0x13, 0x6eff},
1945 {0x1c, 0x14, 0xe6ff},
1946 {0x1c, 0x15, 0x6eff},
1947 {0x1c, 0x16, 0xe6ff},
1948 {0x1c, 0x17, 0x00ff},
1949 {0x1c, 0x18, 0x43ff},
1950 {0x1c, 0x19, 0xc3ff},
1951 {0x1c, 0x1a, 0x6fff},
1952 {0x1c, 0x1b, 0x07ff},
1953 {0x1c, 0x1c, 0x0fff},
1954 {0x1c, 0x1d, 0xe7ff},
1955 {0x1c, 0x1e, 0xefff},
1956 {0x1c, 0x20, 0xeeee},
1957};
1958
1959static int ksz9477_phy_errata(struct phy_device *phydev)
1960{
1961 int err;
1962 int i;
1963
1964 /* Apply PHY settings to address errata listed in
1965 * KSZ9477, KSZ9897, KSZ9896, KSZ9567, KSZ8565
1966 * Silicon Errata and Data Sheet Clarification documents.
1967 *
1968 * Document notes: Before configuring the PHY MMD registers, it is
1969 * necessary to set the PHY to 100 Mbps speed with auto-negotiation
1970 * disabled by writing to register 0xN100-0xN101. After writing the
1971 * MMD registers, and after all errata workarounds that involve PHY
1972 * register settings, write register 0xN100-0xN101 again to enable
1973 * and restart auto-negotiation.
1974 */
1975 err = phy_write(phydev, MII_BMCR, BMCR_SPEED100 | BMCR_FULLDPLX);
1976 if (err)
1977 return err;
1978
1979 for (i = 0; i < ARRAY_SIZE(ksz9477_errata_writes); ++i) {
1980 const struct ksz9477_errata_write *errata = &ksz9477_errata_writes[i];
1981
1982 err = phy_write_mmd(phydev, errata->dev_addr, errata->reg_addr, errata->val);
1983 if (err)
1984 return err;
1985 }
1986
1987 err = genphy_restart_aneg(phydev);
1988 if (err)
1989 return err;
1990
1991 return err;
1992}
1993
1994static int ksz9477_config_init(struct phy_device *phydev)
1995{
1996 int err;
1997
1998 /* Only KSZ9897 family of switches needs this fix. */
1999 if ((phydev->phy_id & 0xf) == 1) {
2000 err = ksz9477_phy_errata(phydev);
2001 if (err)
2002 return err;
2003 }
2004
2005 /* According to KSZ9477 Errata DS80000754C (Module 4) all EEE modes
2006 * in this switch shall be regarded as broken.
2007 */
2008 if (phydev->dev_flags & MICREL_NO_EEE)
2009 linkmode_fill(phydev->eee_broken_modes);
2010
2011 return kszphy_config_init(phydev);
2012}
2013
2014static int kszphy_get_sset_count(struct phy_device *phydev)
2015{
2016 return ARRAY_SIZE(kszphy_hw_stats);
2017}
2018
2019static void kszphy_get_strings(struct phy_device *phydev, u8 *data)
2020{
2021 int i;
2022
2023 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++)
2024 ethtool_puts(&data, kszphy_hw_stats[i].string);
2025}
2026
2027static u64 kszphy_get_stat(struct phy_device *phydev, int i)
2028{
2029 struct kszphy_hw_stat stat = kszphy_hw_stats[i];
2030 struct kszphy_priv *priv = phydev->priv;
2031 int val;
2032 u64 ret;
2033
2034 val = phy_read(phydev, stat.reg);
2035 if (val < 0) {
2036 ret = U64_MAX;
2037 } else {
2038 val = val & ((1 << stat.bits) - 1);
2039 priv->stats[i] += val;
2040 ret = priv->stats[i];
2041 }
2042
2043 return ret;
2044}
2045
2046static void kszphy_get_stats(struct phy_device *phydev,
2047 struct ethtool_stats *stats, u64 *data)
2048{
2049 int i;
2050
2051 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++)
2052 data[i] = kszphy_get_stat(phydev, i);
2053}
2054
2055static void kszphy_enable_clk(struct phy_device *phydev)
2056{
2057 struct kszphy_priv *priv = phydev->priv;
2058
2059 if (!priv->clk_enable && priv->clk) {
2060 clk_prepare_enable(priv->clk);
2061 priv->clk_enable = true;
2062 }
2063}
2064
2065static void kszphy_disable_clk(struct phy_device *phydev)
2066{
2067 struct kszphy_priv *priv = phydev->priv;
2068
2069 if (priv->clk_enable && priv->clk) {
2070 clk_disable_unprepare(priv->clk);
2071 priv->clk_enable = false;
2072 }
2073}
2074
2075static int kszphy_generic_resume(struct phy_device *phydev)
2076{
2077 kszphy_enable_clk(phydev);
2078
2079 return genphy_resume(phydev);
2080}
2081
2082static int kszphy_generic_suspend(struct phy_device *phydev)
2083{
2084 int ret;
2085
2086 ret = genphy_suspend(phydev);
2087 if (ret)
2088 return ret;
2089
2090 kszphy_disable_clk(phydev);
2091
2092 return 0;
2093}
2094
2095static int kszphy_suspend(struct phy_device *phydev)
2096{
2097 /* Disable PHY Interrupts */
2098 if (phy_interrupt_is_valid(phydev)) {
2099 phydev->interrupts = PHY_INTERRUPT_DISABLED;
2100 if (phydev->drv->config_intr)
2101 phydev->drv->config_intr(phydev);
2102 }
2103
2104 return kszphy_generic_suspend(phydev);
2105}
2106
2107static void kszphy_parse_led_mode(struct phy_device *phydev)
2108{
2109 const struct kszphy_type *type = phydev->drv->driver_data;
2110 const struct device_node *np = phydev->mdio.dev.of_node;
2111 struct kszphy_priv *priv = phydev->priv;
2112 int ret;
2113
2114 if (type && type->led_mode_reg) {
2115 ret = of_property_read_u32(np, "micrel,led-mode",
2116 &priv->led_mode);
2117
2118 if (ret)
2119 priv->led_mode = -1;
2120
2121 if (priv->led_mode > 3) {
2122 phydev_err(phydev, "invalid led mode: 0x%02x\n",
2123 priv->led_mode);
2124 priv->led_mode = -1;
2125 }
2126 } else {
2127 priv->led_mode = -1;
2128 }
2129}
2130
2131static int kszphy_resume(struct phy_device *phydev)
2132{
2133 int ret;
2134
2135 ret = kszphy_generic_resume(phydev);
2136 if (ret)
2137 return ret;
2138
2139 /* After switching from power-down to normal mode, an internal global
2140 * reset is automatically generated. Wait a minimum of 1 ms before
2141 * read/write access to the PHY registers.
2142 */
2143 usleep_range(1000, 2000);
2144
2145 ret = kszphy_config_reset(phydev);
2146 if (ret)
2147 return ret;
2148
2149 /* Enable PHY Interrupts */
2150 if (phy_interrupt_is_valid(phydev)) {
2151 phydev->interrupts = PHY_INTERRUPT_ENABLED;
2152 if (phydev->drv->config_intr)
2153 phydev->drv->config_intr(phydev);
2154 }
2155
2156 return 0;
2157}
2158
2159/* Because of errata DS80000700A, receiver error following software
2160 * power down. Suspend and resume callbacks only disable and enable
2161 * external rmii reference clock.
2162 */
2163static int ksz8041_resume(struct phy_device *phydev)
2164{
2165 kszphy_enable_clk(phydev);
2166
2167 return 0;
2168}
2169
2170static int ksz8041_suspend(struct phy_device *phydev)
2171{
2172 kszphy_disable_clk(phydev);
2173
2174 return 0;
2175}
2176
2177static int ksz9477_resume(struct phy_device *phydev)
2178{
2179 int ret;
2180
2181 /* No need to initialize registers if not powered down. */
2182 ret = phy_read(phydev, MII_BMCR);
2183 if (ret < 0)
2184 return ret;
2185 if (!(ret & BMCR_PDOWN))
2186 return 0;
2187
2188 genphy_resume(phydev);
2189
2190 /* After switching from power-down to normal mode, an internal global
2191 * reset is automatically generated. Wait a minimum of 1 ms before
2192 * read/write access to the PHY registers.
2193 */
2194 usleep_range(1000, 2000);
2195
2196 /* Only KSZ9897 family of switches needs this fix. */
2197 if ((phydev->phy_id & 0xf) == 1) {
2198 ret = ksz9477_phy_errata(phydev);
2199 if (ret)
2200 return ret;
2201 }
2202
2203 /* Enable PHY Interrupts */
2204 if (phy_interrupt_is_valid(phydev)) {
2205 phydev->interrupts = PHY_INTERRUPT_ENABLED;
2206 if (phydev->drv->config_intr)
2207 phydev->drv->config_intr(phydev);
2208 }
2209
2210 return 0;
2211}
2212
2213static int ksz8061_resume(struct phy_device *phydev)
2214{
2215 int ret;
2216
2217 /* This function can be called twice when the Ethernet device is on. */
2218 ret = phy_read(phydev, MII_BMCR);
2219 if (ret < 0)
2220 return ret;
2221 if (!(ret & BMCR_PDOWN))
2222 return 0;
2223
2224 ret = kszphy_generic_resume(phydev);
2225 if (ret)
2226 return ret;
2227
2228 usleep_range(1000, 2000);
2229
2230 /* Re-program the value after chip is reset. */
2231 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, 0xB61A);
2232 if (ret)
2233 return ret;
2234
2235 /* Enable PHY Interrupts */
2236 if (phy_interrupt_is_valid(phydev)) {
2237 phydev->interrupts = PHY_INTERRUPT_ENABLED;
2238 if (phydev->drv->config_intr)
2239 phydev->drv->config_intr(phydev);
2240 }
2241
2242 return 0;
2243}
2244
2245static int ksz8061_suspend(struct phy_device *phydev)
2246{
2247 return kszphy_suspend(phydev);
2248}
2249
2250static int kszphy_probe(struct phy_device *phydev)
2251{
2252 const struct kszphy_type *type = phydev->drv->driver_data;
2253 const struct device_node *np = phydev->mdio.dev.of_node;
2254 struct kszphy_priv *priv;
2255 struct clk *clk;
2256
2257 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
2258 if (!priv)
2259 return -ENOMEM;
2260
2261 phydev->priv = priv;
2262
2263 priv->type = type;
2264
2265 kszphy_parse_led_mode(phydev);
2266
2267 clk = devm_clk_get_optional_enabled(&phydev->mdio.dev, "rmii-ref");
2268 /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */
2269 if (!IS_ERR_OR_NULL(clk)) {
2270 unsigned long rate = clk_get_rate(clk);
2271 bool rmii_ref_clk_sel_25_mhz;
2272
2273 if (type)
2274 priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel;
2275 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np,
2276 "micrel,rmii-reference-clock-select-25-mhz");
2277
2278 if (rate > 24500000 && rate < 25500000) {
2279 priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz;
2280 } else if (rate > 49500000 && rate < 50500000) {
2281 priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz;
2282 } else {
2283 phydev_err(phydev, "Clock rate out of range: %ld\n",
2284 rate);
2285 return -EINVAL;
2286 }
2287 } else if (!clk) {
2288 /* unnamed clock from the generic ethernet-phy binding */
2289 clk = devm_clk_get_optional_enabled(&phydev->mdio.dev, NULL);
2290 }
2291
2292 if (IS_ERR(clk))
2293 return PTR_ERR(clk);
2294
2295 clk_disable_unprepare(clk);
2296 priv->clk = clk;
2297
2298 if (ksz8041_fiber_mode(phydev))
2299 phydev->port = PORT_FIBRE;
2300
2301 /* Support legacy board-file configuration */
2302 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
2303 priv->rmii_ref_clk_sel = true;
2304 priv->rmii_ref_clk_sel_val = true;
2305 }
2306
2307 return 0;
2308}
2309
2310static int lan8814_cable_test_start(struct phy_device *phydev)
2311{
2312 /* If autoneg is enabled, we won't be able to test cross pair
2313 * short. In this case, the PHY will "detect" a link and
2314 * confuse the internal state machine - disable auto neg here.
2315 * Set the speed to 1000mbit and full duplex.
2316 */
2317 return phy_modify(phydev, MII_BMCR, BMCR_ANENABLE | BMCR_SPEED100,
2318 BMCR_SPEED1000 | BMCR_FULLDPLX);
2319}
2320
2321static int ksz886x_cable_test_start(struct phy_device *phydev)
2322{
2323 if (phydev->dev_flags & MICREL_KSZ8_P1_ERRATA)
2324 return -EOPNOTSUPP;
2325
2326 /* If autoneg is enabled, we won't be able to test cross pair
2327 * short. In this case, the PHY will "detect" a link and
2328 * confuse the internal state machine - disable auto neg here.
2329 * If autoneg is disabled, we should set the speed to 10mbit.
2330 */
2331 return phy_clear_bits(phydev, MII_BMCR, BMCR_ANENABLE | BMCR_SPEED100);
2332}
2333
2334static __always_inline int ksz886x_cable_test_result_trans(u16 status, u16 mask)
2335{
2336 switch (FIELD_GET(mask, status)) {
2337 case KSZ8081_LMD_STAT_NORMAL:
2338 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
2339 case KSZ8081_LMD_STAT_SHORT:
2340 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
2341 case KSZ8081_LMD_STAT_OPEN:
2342 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
2343 case KSZ8081_LMD_STAT_FAIL:
2344 fallthrough;
2345 default:
2346 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
2347 }
2348}
2349
2350static __always_inline bool ksz886x_cable_test_failed(u16 status, u16 mask)
2351{
2352 return FIELD_GET(mask, status) ==
2353 KSZ8081_LMD_STAT_FAIL;
2354}
2355
2356static __always_inline bool ksz886x_cable_test_fault_length_valid(u16 status, u16 mask)
2357{
2358 switch (FIELD_GET(mask, status)) {
2359 case KSZ8081_LMD_STAT_OPEN:
2360 fallthrough;
2361 case KSZ8081_LMD_STAT_SHORT:
2362 return true;
2363 }
2364 return false;
2365}
2366
2367static __always_inline int ksz886x_cable_test_fault_length(struct phy_device *phydev,
2368 u16 status, u16 data_mask)
2369{
2370 int dt;
2371
2372 /* According to the data sheet the distance to the fault is
2373 * DELTA_TIME * 0.4 meters for ksz phys.
2374 * (DELTA_TIME - 22) * 0.8 for lan8814 phy.
2375 */
2376 dt = FIELD_GET(data_mask, status);
2377
2378 if (phydev_id_compare(phydev, PHY_ID_LAN8814))
2379 return ((dt - 22) * 800) / 10;
2380 else
2381 return (dt * 400) / 10;
2382}
2383
2384static int ksz886x_cable_test_wait_for_completion(struct phy_device *phydev)
2385{
2386 const struct kszphy_type *type = phydev->drv->driver_data;
2387 int val, ret;
2388
2389 ret = phy_read_poll_timeout(phydev, type->cable_diag_reg, val,
2390 !(val & KSZ8081_LMD_ENABLE_TEST),
2391 30000, 100000, true);
2392
2393 return ret < 0 ? ret : 0;
2394}
2395
2396static int lan8814_cable_test_one_pair(struct phy_device *phydev, int pair)
2397{
2398 static const int ethtool_pair[] = { ETHTOOL_A_CABLE_PAIR_A,
2399 ETHTOOL_A_CABLE_PAIR_B,
2400 ETHTOOL_A_CABLE_PAIR_C,
2401 ETHTOOL_A_CABLE_PAIR_D,
2402 };
2403 u32 fault_length;
2404 int ret;
2405 int val;
2406
2407 val = KSZ8081_LMD_ENABLE_TEST;
2408 val = val | (pair << LAN8814_PAIR_BIT_SHIFT);
2409
2410 ret = phy_write(phydev, LAN8814_CABLE_DIAG, val);
2411 if (ret < 0)
2412 return ret;
2413
2414 ret = ksz886x_cable_test_wait_for_completion(phydev);
2415 if (ret)
2416 return ret;
2417
2418 val = phy_read(phydev, LAN8814_CABLE_DIAG);
2419 if (val < 0)
2420 return val;
2421
2422 if (ksz886x_cable_test_failed(val, LAN8814_CABLE_DIAG_STAT_MASK))
2423 return -EAGAIN;
2424
2425 ret = ethnl_cable_test_result(phydev, ethtool_pair[pair],
2426 ksz886x_cable_test_result_trans(val,
2427 LAN8814_CABLE_DIAG_STAT_MASK
2428 ));
2429 if (ret)
2430 return ret;
2431
2432 if (!ksz886x_cable_test_fault_length_valid(val, LAN8814_CABLE_DIAG_STAT_MASK))
2433 return 0;
2434
2435 fault_length = ksz886x_cable_test_fault_length(phydev, val,
2436 LAN8814_CABLE_DIAG_VCT_DATA_MASK);
2437
2438 return ethnl_cable_test_fault_length(phydev, ethtool_pair[pair], fault_length);
2439}
2440
2441static int ksz886x_cable_test_one_pair(struct phy_device *phydev, int pair)
2442{
2443 static const int ethtool_pair[] = {
2444 ETHTOOL_A_CABLE_PAIR_A,
2445 ETHTOOL_A_CABLE_PAIR_B,
2446 };
2447 int ret, val, mdix;
2448 u32 fault_length;
2449
2450 /* There is no way to choice the pair, like we do one ksz9031.
2451 * We can workaround this limitation by using the MDI-X functionality.
2452 */
2453 if (pair == 0)
2454 mdix = ETH_TP_MDI;
2455 else
2456 mdix = ETH_TP_MDI_X;
2457
2458 switch (phydev->phy_id & MICREL_PHY_ID_MASK) {
2459 case PHY_ID_KSZ8081:
2460 ret = ksz8081_config_mdix(phydev, mdix);
2461 break;
2462 case PHY_ID_KSZ886X:
2463 ret = ksz886x_config_mdix(phydev, mdix);
2464 break;
2465 default:
2466 ret = -ENODEV;
2467 }
2468
2469 if (ret)
2470 return ret;
2471
2472 /* Now we are ready to fire. This command will send a 100ns pulse
2473 * to the pair.
2474 */
2475 ret = phy_write(phydev, KSZ8081_LMD, KSZ8081_LMD_ENABLE_TEST);
2476 if (ret)
2477 return ret;
2478
2479 ret = ksz886x_cable_test_wait_for_completion(phydev);
2480 if (ret)
2481 return ret;
2482
2483 val = phy_read(phydev, KSZ8081_LMD);
2484 if (val < 0)
2485 return val;
2486
2487 if (ksz886x_cable_test_failed(val, KSZ8081_LMD_STAT_MASK))
2488 return -EAGAIN;
2489
2490 ret = ethnl_cable_test_result(phydev, ethtool_pair[pair],
2491 ksz886x_cable_test_result_trans(val, KSZ8081_LMD_STAT_MASK));
2492 if (ret)
2493 return ret;
2494
2495 if (!ksz886x_cable_test_fault_length_valid(val, KSZ8081_LMD_STAT_MASK))
2496 return 0;
2497
2498 fault_length = ksz886x_cable_test_fault_length(phydev, val, KSZ8081_LMD_DELTA_TIME_MASK);
2499
2500 return ethnl_cable_test_fault_length(phydev, ethtool_pair[pair], fault_length);
2501}
2502
2503static int ksz886x_cable_test_get_status(struct phy_device *phydev,
2504 bool *finished)
2505{
2506 const struct kszphy_type *type = phydev->drv->driver_data;
2507 unsigned long pair_mask = type->pair_mask;
2508 int retries = 20;
2509 int ret = 0;
2510 int pair;
2511
2512 *finished = false;
2513
2514 /* Try harder if link partner is active */
2515 while (pair_mask && retries--) {
2516 for_each_set_bit(pair, &pair_mask, 4) {
2517 if (type->cable_diag_reg == LAN8814_CABLE_DIAG)
2518 ret = lan8814_cable_test_one_pair(phydev, pair);
2519 else
2520 ret = ksz886x_cable_test_one_pair(phydev, pair);
2521 if (ret == -EAGAIN)
2522 continue;
2523 if (ret < 0)
2524 return ret;
2525 clear_bit(pair, &pair_mask);
2526 }
2527 /* If link partner is in autonegotiation mode it will send 2ms
2528 * of FLPs with at least 6ms of silence.
2529 * Add 2ms sleep to have better chances to hit this silence.
2530 */
2531 if (pair_mask)
2532 msleep(2);
2533 }
2534
2535 *finished = true;
2536
2537 return ret;
2538}
2539
2540#define LAN_EXT_PAGE_ACCESS_CONTROL 0x16
2541#define LAN_EXT_PAGE_ACCESS_ADDRESS_DATA 0x17
2542#define LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC 0x4000
2543
2544#define LAN8814_QSGMII_SOFT_RESET 0x43
2545#define LAN8814_QSGMII_SOFT_RESET_BIT BIT(0)
2546#define LAN8814_QSGMII_PCS1G_ANEG_CONFIG 0x13
2547#define LAN8814_QSGMII_PCS1G_ANEG_CONFIG_ANEG_ENA BIT(3)
2548#define LAN8814_ALIGN_SWAP 0x4a
2549#define LAN8814_ALIGN_TX_A_B_SWAP 0x1
2550#define LAN8814_ALIGN_TX_A_B_SWAP_MASK GENMASK(2, 0)
2551
2552#define LAN8804_ALIGN_SWAP 0x4a
2553#define LAN8804_ALIGN_TX_A_B_SWAP 0x1
2554#define LAN8804_ALIGN_TX_A_B_SWAP_MASK GENMASK(2, 0)
2555#define LAN8814_CLOCK_MANAGEMENT 0xd
2556#define LAN8814_LINK_QUALITY 0x8e
2557
2558static int lanphy_read_page_reg(struct phy_device *phydev, int page, u32 addr)
2559{
2560 int data;
2561
2562 phy_lock_mdio_bus(phydev);
2563 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL, page);
2564 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, addr);
2565 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL,
2566 (page | LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC));
2567 data = __phy_read(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA);
2568 phy_unlock_mdio_bus(phydev);
2569
2570 return data;
2571}
2572
2573static int lanphy_write_page_reg(struct phy_device *phydev, int page, u16 addr,
2574 u16 val)
2575{
2576 phy_lock_mdio_bus(phydev);
2577 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL, page);
2578 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, addr);
2579 __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL,
2580 page | LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC);
2581
2582 val = __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, val);
2583 if (val != 0)
2584 phydev_err(phydev, "Error: phy_write has returned error %d\n",
2585 val);
2586 phy_unlock_mdio_bus(phydev);
2587 return val;
2588}
2589
2590static int lan8814_config_ts_intr(struct phy_device *phydev, bool enable)
2591{
2592 u16 val = 0;
2593
2594 if (enable)
2595 val = PTP_TSU_INT_EN_PTP_TX_TS_EN_ |
2596 PTP_TSU_INT_EN_PTP_TX_TS_OVRFL_EN_ |
2597 PTP_TSU_INT_EN_PTP_RX_TS_EN_ |
2598 PTP_TSU_INT_EN_PTP_RX_TS_OVRFL_EN_;
2599
2600 return lanphy_write_page_reg(phydev, 5, PTP_TSU_INT_EN, val);
2601}
2602
2603static void lan8814_ptp_rx_ts_get(struct phy_device *phydev,
2604 u32 *seconds, u32 *nano_seconds, u16 *seq_id)
2605{
2606 *seconds = lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_SEC_HI);
2607 *seconds = (*seconds << 16) |
2608 lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_SEC_LO);
2609
2610 *nano_seconds = lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_NS_HI);
2611 *nano_seconds = ((*nano_seconds & 0x3fff) << 16) |
2612 lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_NS_LO);
2613
2614 *seq_id = lanphy_read_page_reg(phydev, 5, PTP_RX_MSG_HEADER2);
2615}
2616
2617static void lan8814_ptp_tx_ts_get(struct phy_device *phydev,
2618 u32 *seconds, u32 *nano_seconds, u16 *seq_id)
2619{
2620 *seconds = lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_SEC_HI);
2621 *seconds = *seconds << 16 |
2622 lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_SEC_LO);
2623
2624 *nano_seconds = lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_NS_HI);
2625 *nano_seconds = ((*nano_seconds & 0x3fff) << 16) |
2626 lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_NS_LO);
2627
2628 *seq_id = lanphy_read_page_reg(phydev, 5, PTP_TX_MSG_HEADER2);
2629}
2630
2631static int lan8814_ts_info(struct mii_timestamper *mii_ts, struct kernel_ethtool_ts_info *info)
2632{
2633 struct kszphy_ptp_priv *ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2634 struct phy_device *phydev = ptp_priv->phydev;
2635 struct lan8814_shared_priv *shared = phydev->shared->priv;
2636
2637 info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |
2638 SOF_TIMESTAMPING_RX_HARDWARE |
2639 SOF_TIMESTAMPING_RAW_HARDWARE;
2640
2641 info->phc_index = ptp_clock_index(shared->ptp_clock);
2642
2643 info->tx_types =
2644 (1 << HWTSTAMP_TX_OFF) |
2645 (1 << HWTSTAMP_TX_ON) |
2646 (1 << HWTSTAMP_TX_ONESTEP_SYNC);
2647
2648 info->rx_filters =
2649 (1 << HWTSTAMP_FILTER_NONE) |
2650 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
2651 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
2652 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
2653 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
2654
2655 return 0;
2656}
2657
2658static void lan8814_flush_fifo(struct phy_device *phydev, bool egress)
2659{
2660 int i;
2661
2662 for (i = 0; i < FIFO_SIZE; ++i)
2663 lanphy_read_page_reg(phydev, 5,
2664 egress ? PTP_TX_MSG_HEADER2 : PTP_RX_MSG_HEADER2);
2665
2666 /* Read to clear overflow status bit */
2667 lanphy_read_page_reg(phydev, 5, PTP_TSU_INT_STS);
2668}
2669
2670static int lan8814_hwtstamp(struct mii_timestamper *mii_ts,
2671 struct kernel_hwtstamp_config *config,
2672 struct netlink_ext_ack *extack)
2673{
2674 struct kszphy_ptp_priv *ptp_priv =
2675 container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2676 struct lan8814_ptp_rx_ts *rx_ts, *tmp;
2677 int txcfg = 0, rxcfg = 0;
2678 int pkt_ts_enable;
2679 int tx_mod;
2680
2681 ptp_priv->hwts_tx_type = config->tx_type;
2682 ptp_priv->rx_filter = config->rx_filter;
2683
2684 switch (config->rx_filter) {
2685 case HWTSTAMP_FILTER_NONE:
2686 ptp_priv->layer = 0;
2687 ptp_priv->version = 0;
2688 break;
2689 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2690 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2691 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2692 ptp_priv->layer = PTP_CLASS_L4;
2693 ptp_priv->version = PTP_CLASS_V2;
2694 break;
2695 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2696 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
2697 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
2698 ptp_priv->layer = PTP_CLASS_L2;
2699 ptp_priv->version = PTP_CLASS_V2;
2700 break;
2701 case HWTSTAMP_FILTER_PTP_V2_EVENT:
2702 case HWTSTAMP_FILTER_PTP_V2_SYNC:
2703 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
2704 ptp_priv->layer = PTP_CLASS_L4 | PTP_CLASS_L2;
2705 ptp_priv->version = PTP_CLASS_V2;
2706 break;
2707 default:
2708 return -ERANGE;
2709 }
2710
2711 if (ptp_priv->layer & PTP_CLASS_L2) {
2712 rxcfg = PTP_RX_PARSE_CONFIG_LAYER2_EN_;
2713 txcfg = PTP_TX_PARSE_CONFIG_LAYER2_EN_;
2714 } else if (ptp_priv->layer & PTP_CLASS_L4) {
2715 rxcfg |= PTP_RX_PARSE_CONFIG_IPV4_EN_ | PTP_RX_PARSE_CONFIG_IPV6_EN_;
2716 txcfg |= PTP_TX_PARSE_CONFIG_IPV4_EN_ | PTP_TX_PARSE_CONFIG_IPV6_EN_;
2717 }
2718 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_RX_PARSE_CONFIG, rxcfg);
2719 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_PARSE_CONFIG, txcfg);
2720
2721 pkt_ts_enable = PTP_TIMESTAMP_EN_SYNC_ | PTP_TIMESTAMP_EN_DREQ_ |
2722 PTP_TIMESTAMP_EN_PDREQ_ | PTP_TIMESTAMP_EN_PDRES_;
2723 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_RX_TIMESTAMP_EN, pkt_ts_enable);
2724 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_TIMESTAMP_EN, pkt_ts_enable);
2725
2726 tx_mod = lanphy_read_page_reg(ptp_priv->phydev, 5, PTP_TX_MOD);
2727 if (ptp_priv->hwts_tx_type == HWTSTAMP_TX_ONESTEP_SYNC) {
2728 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_MOD,
2729 tx_mod | PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_);
2730 } else if (ptp_priv->hwts_tx_type == HWTSTAMP_TX_ON) {
2731 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_MOD,
2732 tx_mod & ~PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_);
2733 }
2734
2735 if (config->rx_filter != HWTSTAMP_FILTER_NONE)
2736 lan8814_config_ts_intr(ptp_priv->phydev, true);
2737 else
2738 lan8814_config_ts_intr(ptp_priv->phydev, false);
2739
2740 /* In case of multiple starts and stops, these needs to be cleared */
2741 list_for_each_entry_safe(rx_ts, tmp, &ptp_priv->rx_ts_list, list) {
2742 list_del(&rx_ts->list);
2743 kfree(rx_ts);
2744 }
2745 skb_queue_purge(&ptp_priv->rx_queue);
2746 skb_queue_purge(&ptp_priv->tx_queue);
2747
2748 lan8814_flush_fifo(ptp_priv->phydev, false);
2749 lan8814_flush_fifo(ptp_priv->phydev, true);
2750
2751 return 0;
2752}
2753
2754static void lan8814_txtstamp(struct mii_timestamper *mii_ts,
2755 struct sk_buff *skb, int type)
2756{
2757 struct kszphy_ptp_priv *ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2758
2759 switch (ptp_priv->hwts_tx_type) {
2760 case HWTSTAMP_TX_ONESTEP_SYNC:
2761 if (ptp_msg_is_sync(skb, type)) {
2762 kfree_skb(skb);
2763 return;
2764 }
2765 fallthrough;
2766 case HWTSTAMP_TX_ON:
2767 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2768 skb_queue_tail(&ptp_priv->tx_queue, skb);
2769 break;
2770 case HWTSTAMP_TX_OFF:
2771 default:
2772 kfree_skb(skb);
2773 break;
2774 }
2775}
2776
2777static bool lan8814_get_sig_rx(struct sk_buff *skb, u16 *sig)
2778{
2779 struct ptp_header *ptp_header;
2780 u32 type;
2781
2782 skb_push(skb, ETH_HLEN);
2783 type = ptp_classify_raw(skb);
2784 ptp_header = ptp_parse_header(skb, type);
2785 skb_pull_inline(skb, ETH_HLEN);
2786
2787 if (!ptp_header)
2788 return false;
2789
2790 *sig = (__force u16)(ntohs(ptp_header->sequence_id));
2791 return true;
2792}
2793
2794static bool lan8814_match_rx_skb(struct kszphy_ptp_priv *ptp_priv,
2795 struct sk_buff *skb)
2796{
2797 struct skb_shared_hwtstamps *shhwtstamps;
2798 struct lan8814_ptp_rx_ts *rx_ts, *tmp;
2799 unsigned long flags;
2800 bool ret = false;
2801 u16 skb_sig;
2802
2803 if (!lan8814_get_sig_rx(skb, &skb_sig))
2804 return ret;
2805
2806 /* Iterate over all RX timestamps and match it with the received skbs */
2807 spin_lock_irqsave(&ptp_priv->rx_ts_lock, flags);
2808 list_for_each_entry_safe(rx_ts, tmp, &ptp_priv->rx_ts_list, list) {
2809 /* Check if we found the signature we were looking for. */
2810 if (memcmp(&skb_sig, &rx_ts->seq_id, sizeof(rx_ts->seq_id)))
2811 continue;
2812
2813 shhwtstamps = skb_hwtstamps(skb);
2814 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2815 shhwtstamps->hwtstamp = ktime_set(rx_ts->seconds,
2816 rx_ts->nsec);
2817 list_del(&rx_ts->list);
2818 kfree(rx_ts);
2819
2820 ret = true;
2821 break;
2822 }
2823 spin_unlock_irqrestore(&ptp_priv->rx_ts_lock, flags);
2824
2825 if (ret)
2826 netif_rx(skb);
2827 return ret;
2828}
2829
2830static bool lan8814_rxtstamp(struct mii_timestamper *mii_ts, struct sk_buff *skb, int type)
2831{
2832 struct kszphy_ptp_priv *ptp_priv =
2833 container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2834
2835 if (ptp_priv->rx_filter == HWTSTAMP_FILTER_NONE ||
2836 type == PTP_CLASS_NONE)
2837 return false;
2838
2839 if ((type & ptp_priv->version) == 0 || (type & ptp_priv->layer) == 0)
2840 return false;
2841
2842 /* If we failed to match then add it to the queue for when the timestamp
2843 * will come
2844 */
2845 if (!lan8814_match_rx_skb(ptp_priv, skb))
2846 skb_queue_tail(&ptp_priv->rx_queue, skb);
2847
2848 return true;
2849}
2850
2851static void lan8814_ptp_clock_set(struct phy_device *phydev,
2852 time64_t sec, u32 nsec)
2853{
2854 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_SEC_LO, lower_16_bits(sec));
2855 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_SEC_MID, upper_16_bits(sec));
2856 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_SEC_HI, upper_32_bits(sec));
2857 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_NS_LO, lower_16_bits(nsec));
2858 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_NS_HI, upper_16_bits(nsec));
2859
2860 lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL, PTP_CMD_CTL_PTP_CLOCK_LOAD_);
2861}
2862
2863static void lan8814_ptp_clock_get(struct phy_device *phydev,
2864 time64_t *sec, u32 *nsec)
2865{
2866 lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL, PTP_CMD_CTL_PTP_CLOCK_READ_);
2867
2868 *sec = lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_SEC_HI);
2869 *sec <<= 16;
2870 *sec |= lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_SEC_MID);
2871 *sec <<= 16;
2872 *sec |= lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_SEC_LO);
2873
2874 *nsec = lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_NS_HI);
2875 *nsec <<= 16;
2876 *nsec |= lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_NS_LO);
2877}
2878
2879static int lan8814_ptpci_gettime64(struct ptp_clock_info *ptpci,
2880 struct timespec64 *ts)
2881{
2882 struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2883 ptp_clock_info);
2884 struct phy_device *phydev = shared->phydev;
2885 u32 nano_seconds;
2886 time64_t seconds;
2887
2888 mutex_lock(&shared->shared_lock);
2889 lan8814_ptp_clock_get(phydev, &seconds, &nano_seconds);
2890 mutex_unlock(&shared->shared_lock);
2891 ts->tv_sec = seconds;
2892 ts->tv_nsec = nano_seconds;
2893
2894 return 0;
2895}
2896
2897static int lan8814_ptpci_settime64(struct ptp_clock_info *ptpci,
2898 const struct timespec64 *ts)
2899{
2900 struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2901 ptp_clock_info);
2902 struct phy_device *phydev = shared->phydev;
2903
2904 mutex_lock(&shared->shared_lock);
2905 lan8814_ptp_clock_set(phydev, ts->tv_sec, ts->tv_nsec);
2906 mutex_unlock(&shared->shared_lock);
2907
2908 return 0;
2909}
2910
2911static void lan8814_ptp_set_target(struct phy_device *phydev, int event,
2912 s64 start_sec, u32 start_nsec)
2913{
2914 /* Set the start time */
2915 lanphy_write_page_reg(phydev, 4, LAN8814_PTP_CLOCK_TARGET_SEC_LO(event),
2916 lower_16_bits(start_sec));
2917 lanphy_write_page_reg(phydev, 4, LAN8814_PTP_CLOCK_TARGET_SEC_HI(event),
2918 upper_16_bits(start_sec));
2919
2920 lanphy_write_page_reg(phydev, 4, LAN8814_PTP_CLOCK_TARGET_NS_LO(event),
2921 lower_16_bits(start_nsec));
2922 lanphy_write_page_reg(phydev, 4, LAN8814_PTP_CLOCK_TARGET_NS_HI(event),
2923 upper_16_bits(start_nsec) & 0x3fff);
2924}
2925
2926static void lan8814_ptp_update_target(struct phy_device *phydev, time64_t sec)
2927{
2928 lan8814_ptp_set_target(phydev, LAN8814_EVENT_A,
2929 sec + LAN8814_BUFFER_TIME, 0);
2930 lan8814_ptp_set_target(phydev, LAN8814_EVENT_B,
2931 sec + LAN8814_BUFFER_TIME, 0);
2932}
2933
2934static void lan8814_ptp_clock_step(struct phy_device *phydev,
2935 s64 time_step_ns)
2936{
2937 u32 nano_seconds_step;
2938 u64 abs_time_step_ns;
2939 time64_t set_seconds;
2940 u32 nano_seconds;
2941 u32 remainder;
2942 s32 seconds;
2943
2944 if (time_step_ns > 15000000000LL) {
2945 /* convert to clock set */
2946 lan8814_ptp_clock_get(phydev, &set_seconds, &nano_seconds);
2947 set_seconds += div_u64_rem(time_step_ns, 1000000000LL,
2948 &remainder);
2949 nano_seconds += remainder;
2950 if (nano_seconds >= 1000000000) {
2951 set_seconds++;
2952 nano_seconds -= 1000000000;
2953 }
2954 lan8814_ptp_clock_set(phydev, set_seconds, nano_seconds);
2955 lan8814_ptp_update_target(phydev, set_seconds);
2956 return;
2957 } else if (time_step_ns < -15000000000LL) {
2958 /* convert to clock set */
2959 time_step_ns = -time_step_ns;
2960
2961 lan8814_ptp_clock_get(phydev, &set_seconds, &nano_seconds);
2962 set_seconds -= div_u64_rem(time_step_ns, 1000000000LL,
2963 &remainder);
2964 nano_seconds_step = remainder;
2965 if (nano_seconds < nano_seconds_step) {
2966 set_seconds--;
2967 nano_seconds += 1000000000;
2968 }
2969 nano_seconds -= nano_seconds_step;
2970 lan8814_ptp_clock_set(phydev, set_seconds, nano_seconds);
2971 lan8814_ptp_update_target(phydev, set_seconds);
2972 return;
2973 }
2974
2975 /* do clock step */
2976 if (time_step_ns >= 0) {
2977 abs_time_step_ns = (u64)time_step_ns;
2978 seconds = (s32)div_u64_rem(abs_time_step_ns, 1000000000,
2979 &remainder);
2980 nano_seconds = remainder;
2981 } else {
2982 abs_time_step_ns = (u64)(-time_step_ns);
2983 seconds = -((s32)div_u64_rem(abs_time_step_ns, 1000000000,
2984 &remainder));
2985 nano_seconds = remainder;
2986 if (nano_seconds > 0) {
2987 /* subtracting nano seconds is not allowed
2988 * convert to subtracting from seconds,
2989 * and adding to nanoseconds
2990 */
2991 seconds--;
2992 nano_seconds = (1000000000 - nano_seconds);
2993 }
2994 }
2995
2996 if (nano_seconds > 0) {
2997 /* add 8 ns to cover the likely normal increment */
2998 nano_seconds += 8;
2999 }
3000
3001 if (nano_seconds >= 1000000000) {
3002 /* carry into seconds */
3003 seconds++;
3004 nano_seconds -= 1000000000;
3005 }
3006
3007 while (seconds) {
3008 u32 nsec;
3009
3010 if (seconds > 0) {
3011 u32 adjustment_value = (u32)seconds;
3012 u16 adjustment_value_lo, adjustment_value_hi;
3013
3014 if (adjustment_value > 0xF)
3015 adjustment_value = 0xF;
3016
3017 adjustment_value_lo = adjustment_value & 0xffff;
3018 adjustment_value_hi = (adjustment_value >> 16) & 0x3fff;
3019
3020 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO,
3021 adjustment_value_lo);
3022 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI,
3023 PTP_LTC_STEP_ADJ_DIR_ |
3024 adjustment_value_hi);
3025 seconds -= ((s32)adjustment_value);
3026
3027 lan8814_ptp_clock_get(phydev, &set_seconds, &nsec);
3028 set_seconds -= adjustment_value;
3029 lan8814_ptp_update_target(phydev, set_seconds);
3030 } else {
3031 u32 adjustment_value = (u32)(-seconds);
3032 u16 adjustment_value_lo, adjustment_value_hi;
3033
3034 if (adjustment_value > 0xF)
3035 adjustment_value = 0xF;
3036
3037 adjustment_value_lo = adjustment_value & 0xffff;
3038 adjustment_value_hi = (adjustment_value >> 16) & 0x3fff;
3039
3040 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO,
3041 adjustment_value_lo);
3042 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI,
3043 adjustment_value_hi);
3044 seconds += ((s32)adjustment_value);
3045
3046 lan8814_ptp_clock_get(phydev, &set_seconds, &nsec);
3047 set_seconds += adjustment_value;
3048 lan8814_ptp_update_target(phydev, set_seconds);
3049 }
3050 lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL,
3051 PTP_CMD_CTL_PTP_LTC_STEP_SEC_);
3052 }
3053 if (nano_seconds) {
3054 u16 nano_seconds_lo;
3055 u16 nano_seconds_hi;
3056
3057 nano_seconds_lo = nano_seconds & 0xffff;
3058 nano_seconds_hi = (nano_seconds >> 16) & 0x3fff;
3059
3060 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO,
3061 nano_seconds_lo);
3062 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI,
3063 PTP_LTC_STEP_ADJ_DIR_ |
3064 nano_seconds_hi);
3065 lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL,
3066 PTP_CMD_CTL_PTP_LTC_STEP_NSEC_);
3067 }
3068}
3069
3070static int lan8814_ptpci_adjtime(struct ptp_clock_info *ptpci, s64 delta)
3071{
3072 struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
3073 ptp_clock_info);
3074 struct phy_device *phydev = shared->phydev;
3075
3076 mutex_lock(&shared->shared_lock);
3077 lan8814_ptp_clock_step(phydev, delta);
3078 mutex_unlock(&shared->shared_lock);
3079
3080 return 0;
3081}
3082
3083static int lan8814_ptpci_adjfine(struct ptp_clock_info *ptpci, long scaled_ppm)
3084{
3085 struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
3086 ptp_clock_info);
3087 struct phy_device *phydev = shared->phydev;
3088 u16 kszphy_rate_adj_lo, kszphy_rate_adj_hi;
3089 bool positive = true;
3090 u32 kszphy_rate_adj;
3091
3092 if (scaled_ppm < 0) {
3093 scaled_ppm = -scaled_ppm;
3094 positive = false;
3095 }
3096
3097 kszphy_rate_adj = LAN8814_1PPM_FORMAT * (scaled_ppm >> 16);
3098 kszphy_rate_adj += (LAN8814_1PPM_FORMAT * (0xffff & scaled_ppm)) >> 16;
3099
3100 kszphy_rate_adj_lo = kszphy_rate_adj & 0xffff;
3101 kszphy_rate_adj_hi = (kszphy_rate_adj >> 16) & 0x3fff;
3102
3103 if (positive)
3104 kszphy_rate_adj_hi |= PTP_CLOCK_RATE_ADJ_DIR_;
3105
3106 mutex_lock(&shared->shared_lock);
3107 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_RATE_ADJ_HI, kszphy_rate_adj_hi);
3108 lanphy_write_page_reg(phydev, 4, PTP_CLOCK_RATE_ADJ_LO, kszphy_rate_adj_lo);
3109 mutex_unlock(&shared->shared_lock);
3110
3111 return 0;
3112}
3113
3114static void lan8814_ptp_set_reload(struct phy_device *phydev, int event,
3115 s64 period_sec, u32 period_nsec)
3116{
3117 lanphy_write_page_reg(phydev, 4,
3118 LAN8814_PTP_CLOCK_TARGET_RELOAD_SEC_LO(event),
3119 lower_16_bits(period_sec));
3120 lanphy_write_page_reg(phydev, 4,
3121 LAN8814_PTP_CLOCK_TARGET_RELOAD_SEC_HI(event),
3122 upper_16_bits(period_sec));
3123
3124 lanphy_write_page_reg(phydev, 4,
3125 LAN8814_PTP_CLOCK_TARGET_RELOAD_NS_LO(event),
3126 lower_16_bits(period_nsec));
3127 lanphy_write_page_reg(phydev, 4,
3128 LAN8814_PTP_CLOCK_TARGET_RELOAD_NS_HI(event),
3129 upper_16_bits(period_nsec) & 0x3fff);
3130}
3131
3132static void lan8814_ptp_enable_event(struct phy_device *phydev, int event,
3133 int pulse_width)
3134{
3135 u16 val;
3136
3137 val = lanphy_read_page_reg(phydev, 4, LAN8814_PTP_GENERAL_CONFIG);
3138 /* Set the pulse width of the event */
3139 val &= ~(LAN8814_PTP_GENERAL_CONFIG_LTC_EVENT_MASK(event));
3140 /* Make sure that the target clock will be incremented each time when
3141 * local time reaches or pass it
3142 */
3143 val |= LAN8814_PTP_GENERAL_CONFIG_LTC_EVENT_SET(event, pulse_width);
3144 val &= ~(LAN8814_PTP_GENERAL_CONFIG_RELOAD_ADD_X(event));
3145 /* Set the polarity high */
3146 val |= LAN8814_PTP_GENERAL_CONFIG_POLARITY_X(event);
3147 lanphy_write_page_reg(phydev, 4, LAN8814_PTP_GENERAL_CONFIG, val);
3148}
3149
3150static void lan8814_ptp_disable_event(struct phy_device *phydev, int event)
3151{
3152 u16 val;
3153
3154 /* Set target to too far in the future, effectively disabling it */
3155 lan8814_ptp_set_target(phydev, event, 0xFFFFFFFF, 0);
3156
3157 /* And then reload once it recheas the target */
3158 val = lanphy_read_page_reg(phydev, 4, LAN8814_PTP_GENERAL_CONFIG);
3159 val |= LAN8814_PTP_GENERAL_CONFIG_RELOAD_ADD_X(event);
3160 lanphy_write_page_reg(phydev, 4, LAN8814_PTP_GENERAL_CONFIG, val);
3161}
3162
3163static void lan8814_ptp_perout_off(struct phy_device *phydev, int pin)
3164{
3165 u16 val;
3166
3167 /* Disable gpio alternate function,
3168 * 1: select as gpio,
3169 * 0: select alt func
3170 */
3171 val = lanphy_read_page_reg(phydev, 4, LAN8814_GPIO_EN_ADDR(pin));
3172 val |= LAN8814_GPIO_EN_BIT(pin);
3173 lanphy_write_page_reg(phydev, 4, LAN8814_GPIO_EN_ADDR(pin), val);
3174
3175 val = lanphy_read_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin));
3176 val &= ~LAN8814_GPIO_DIR_BIT(pin);
3177 lanphy_write_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin), val);
3178
3179 val = lanphy_read_page_reg(phydev, 4, LAN8814_GPIO_BUF_ADDR(pin));
3180 val &= ~LAN8814_GPIO_BUF_BIT(pin);
3181 lanphy_write_page_reg(phydev, 4, LAN8814_GPIO_BUF_ADDR(pin), val);
3182}
3183
3184static void lan8814_ptp_perout_on(struct phy_device *phydev, int pin)
3185{
3186 int val;
3187
3188 /* Set as gpio output */
3189 val = lanphy_read_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin));
3190 val |= LAN8814_GPIO_DIR_BIT(pin);
3191 lanphy_write_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin), val);
3192
3193 /* Enable gpio 0:for alternate function, 1:gpio */
3194 val = lanphy_read_page_reg(phydev, 4, LAN8814_GPIO_EN_ADDR(pin));
3195 val &= ~LAN8814_GPIO_EN_BIT(pin);
3196 lanphy_write_page_reg(phydev, 4, LAN8814_GPIO_EN_ADDR(pin), val);
3197
3198 /* Set buffer type to push pull */
3199 val = lanphy_read_page_reg(phydev, 4, LAN8814_GPIO_BUF_ADDR(pin));
3200 val |= LAN8814_GPIO_BUF_BIT(pin);
3201 lanphy_write_page_reg(phydev, 4, LAN8814_GPIO_BUF_ADDR(pin), val);
3202}
3203
3204static int lan8814_ptp_perout(struct ptp_clock_info *ptpci,
3205 struct ptp_clock_request *rq, int on)
3206{
3207 struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
3208 ptp_clock_info);
3209 struct phy_device *phydev = shared->phydev;
3210 struct timespec64 ts_on, ts_period;
3211 s64 on_nsec, period_nsec;
3212 int pulse_width;
3213 int pin, event;
3214
3215 /* Reject requests with unsupported flags */
3216 if (rq->perout.flags & ~PTP_PEROUT_DUTY_CYCLE)
3217 return -EOPNOTSUPP;
3218
3219 mutex_lock(&shared->shared_lock);
3220 event = rq->perout.index;
3221 pin = ptp_find_pin(shared->ptp_clock, PTP_PF_PEROUT, event);
3222 if (pin < 0 || pin >= LAN8814_PTP_PEROUT_NUM) {
3223 mutex_unlock(&shared->shared_lock);
3224 return -EBUSY;
3225 }
3226
3227 if (!on) {
3228 lan8814_ptp_perout_off(phydev, pin);
3229 lan8814_ptp_disable_event(phydev, event);
3230 mutex_unlock(&shared->shared_lock);
3231 return 0;
3232 }
3233
3234 ts_on.tv_sec = rq->perout.on.sec;
3235 ts_on.tv_nsec = rq->perout.on.nsec;
3236 on_nsec = timespec64_to_ns(&ts_on);
3237
3238 ts_period.tv_sec = rq->perout.period.sec;
3239 ts_period.tv_nsec = rq->perout.period.nsec;
3240 period_nsec = timespec64_to_ns(&ts_period);
3241
3242 if (period_nsec < 200) {
3243 pr_warn_ratelimited("%s: perout period too small, minimum is 200 nsec\n",
3244 phydev_name(phydev));
3245 mutex_unlock(&shared->shared_lock);
3246 return -EOPNOTSUPP;
3247 }
3248
3249 if (on_nsec >= period_nsec) {
3250 pr_warn_ratelimited("%s: pulse width must be smaller than period\n",
3251 phydev_name(phydev));
3252 mutex_unlock(&shared->shared_lock);
3253 return -EINVAL;
3254 }
3255
3256 switch (on_nsec) {
3257 case 200000000:
3258 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_200MS;
3259 break;
3260 case 100000000:
3261 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100MS;
3262 break;
3263 case 50000000:
3264 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50MS;
3265 break;
3266 case 10000000:
3267 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10MS;
3268 break;
3269 case 5000000:
3270 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5MS;
3271 break;
3272 case 1000000:
3273 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1MS;
3274 break;
3275 case 500000:
3276 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500US;
3277 break;
3278 case 100000:
3279 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100US;
3280 break;
3281 case 50000:
3282 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50US;
3283 break;
3284 case 10000:
3285 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10US;
3286 break;
3287 case 5000:
3288 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5US;
3289 break;
3290 case 1000:
3291 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1US;
3292 break;
3293 case 500:
3294 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500NS;
3295 break;
3296 case 100:
3297 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100NS;
3298 break;
3299 default:
3300 pr_warn_ratelimited("%s: Use default duty cycle of 100ns\n",
3301 phydev_name(phydev));
3302 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100NS;
3303 break;
3304 }
3305
3306 /* Configure to pulse every period */
3307 lan8814_ptp_enable_event(phydev, event, pulse_width);
3308 lan8814_ptp_set_target(phydev, event, rq->perout.start.sec,
3309 rq->perout.start.nsec);
3310 lan8814_ptp_set_reload(phydev, event, rq->perout.period.sec,
3311 rq->perout.period.nsec);
3312 lan8814_ptp_perout_on(phydev, pin);
3313 mutex_unlock(&shared->shared_lock);
3314
3315 return 0;
3316}
3317
3318static void lan8814_ptp_extts_on(struct phy_device *phydev, int pin, u32 flags)
3319{
3320 u16 tmp;
3321
3322 /* Set as gpio input */
3323 tmp = lanphy_read_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin));
3324 tmp &= ~LAN8814_GPIO_DIR_BIT(pin);
3325 lanphy_write_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin), tmp);
3326
3327 /* Map the pin to ltc pin 0 of the capture map registers */
3328 tmp = lanphy_read_page_reg(phydev, 4, PTP_GPIO_CAP_MAP_LO);
3329 tmp |= pin;
3330 lanphy_write_page_reg(phydev, 4, PTP_GPIO_CAP_MAP_LO, tmp);
3331
3332 /* Enable capture on the edges of the ltc pin */
3333 tmp = lanphy_read_page_reg(phydev, 4, PTP_GPIO_CAP_EN);
3334 if (flags & PTP_RISING_EDGE)
3335 tmp |= PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(0);
3336 if (flags & PTP_FALLING_EDGE)
3337 tmp |= PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(0);
3338 lanphy_write_page_reg(phydev, 4, PTP_GPIO_CAP_EN, tmp);
3339
3340 /* Enable interrupt top interrupt */
3341 tmp = lanphy_read_page_reg(phydev, 4, PTP_COMMON_INT_ENA);
3342 tmp |= PTP_COMMON_INT_ENA_GPIO_CAP_EN;
3343 lanphy_write_page_reg(phydev, 4, PTP_COMMON_INT_ENA, tmp);
3344}
3345
3346static void lan8814_ptp_extts_off(struct phy_device *phydev, int pin)
3347{
3348 u16 tmp;
3349
3350 /* Set as gpio out */
3351 tmp = lanphy_read_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin));
3352 tmp |= LAN8814_GPIO_DIR_BIT(pin);
3353 lanphy_write_page_reg(phydev, 4, LAN8814_GPIO_DIR_ADDR(pin), tmp);
3354
3355 /* Enable alternate, 0:for alternate function, 1:gpio */
3356 tmp = lanphy_read_page_reg(phydev, 4, LAN8814_GPIO_EN_ADDR(pin));
3357 tmp &= ~LAN8814_GPIO_EN_BIT(pin);
3358 lanphy_write_page_reg(phydev, 4, LAN8814_GPIO_EN_ADDR(pin), tmp);
3359
3360 /* Clear the mapping of pin to registers 0 of the capture registers */
3361 tmp = lanphy_read_page_reg(phydev, 4, PTP_GPIO_CAP_MAP_LO);
3362 tmp &= ~GENMASK(3, 0);
3363 lanphy_write_page_reg(phydev, 4, PTP_GPIO_CAP_MAP_LO, tmp);
3364
3365 /* Disable capture on both of the edges */
3366 tmp = lanphy_read_page_reg(phydev, 4, PTP_GPIO_CAP_EN);
3367 tmp &= ~PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(pin);
3368 tmp &= ~PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(pin);
3369 lanphy_write_page_reg(phydev, 4, PTP_GPIO_CAP_EN, tmp);
3370
3371 /* Disable interrupt top interrupt */
3372 tmp = lanphy_read_page_reg(phydev, 4, PTP_COMMON_INT_ENA);
3373 tmp &= ~PTP_COMMON_INT_ENA_GPIO_CAP_EN;
3374 lanphy_write_page_reg(phydev, 4, PTP_COMMON_INT_ENA, tmp);
3375}
3376
3377static int lan8814_ptp_extts(struct ptp_clock_info *ptpci,
3378 struct ptp_clock_request *rq, int on)
3379{
3380 struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
3381 ptp_clock_info);
3382 struct phy_device *phydev = shared->phydev;
3383 int pin;
3384
3385 if (rq->extts.flags & ~(PTP_ENABLE_FEATURE |
3386 PTP_EXTTS_EDGES |
3387 PTP_STRICT_FLAGS))
3388 return -EOPNOTSUPP;
3389
3390 pin = ptp_find_pin(shared->ptp_clock, PTP_PF_EXTTS,
3391 rq->extts.index);
3392 if (pin == -1 || pin != LAN8814_PTP_EXTTS_NUM)
3393 return -EINVAL;
3394
3395 mutex_lock(&shared->shared_lock);
3396 if (on)
3397 lan8814_ptp_extts_on(phydev, pin, rq->extts.flags);
3398 else
3399 lan8814_ptp_extts_off(phydev, pin);
3400
3401 mutex_unlock(&shared->shared_lock);
3402
3403 return 0;
3404}
3405
3406static int lan8814_ptpci_enable(struct ptp_clock_info *ptpci,
3407 struct ptp_clock_request *rq, int on)
3408{
3409 switch (rq->type) {
3410 case PTP_CLK_REQ_PEROUT:
3411 return lan8814_ptp_perout(ptpci, rq, on);
3412 case PTP_CLK_REQ_EXTTS:
3413 return lan8814_ptp_extts(ptpci, rq, on);
3414 default:
3415 return -EINVAL;
3416 }
3417}
3418
3419static int lan8814_ptpci_verify(struct ptp_clock_info *ptp, unsigned int pin,
3420 enum ptp_pin_function func, unsigned int chan)
3421{
3422 switch (func) {
3423 case PTP_PF_NONE:
3424 case PTP_PF_PEROUT:
3425 /* Only pins 0 and 1 can generate perout signals. And for pin 0
3426 * there is only chan 0 (event A) and for pin 1 there is only
3427 * chan 1 (event B)
3428 */
3429 if (pin >= LAN8814_PTP_PEROUT_NUM || pin != chan)
3430 return -1;
3431 break;
3432 case PTP_PF_EXTTS:
3433 if (pin != LAN8814_PTP_EXTTS_NUM)
3434 return -1;
3435 break;
3436 default:
3437 return -1;
3438 }
3439
3440 return 0;
3441}
3442
3443static bool lan8814_get_sig_tx(struct sk_buff *skb, u16 *sig)
3444{
3445 struct ptp_header *ptp_header;
3446 u32 type;
3447
3448 type = ptp_classify_raw(skb);
3449 ptp_header = ptp_parse_header(skb, type);
3450
3451 if (!ptp_header)
3452 return false;
3453
3454 *sig = (__force u16)(ntohs(ptp_header->sequence_id));
3455 return true;
3456}
3457
3458static void lan8814_match_tx_skb(struct kszphy_ptp_priv *ptp_priv,
3459 u32 seconds, u32 nsec, u16 seq_id)
3460{
3461 struct skb_shared_hwtstamps shhwtstamps;
3462 struct sk_buff *skb, *skb_tmp;
3463 unsigned long flags;
3464 bool ret = false;
3465 u16 skb_sig;
3466
3467 spin_lock_irqsave(&ptp_priv->tx_queue.lock, flags);
3468 skb_queue_walk_safe(&ptp_priv->tx_queue, skb, skb_tmp) {
3469 if (!lan8814_get_sig_tx(skb, &skb_sig))
3470 continue;
3471
3472 if (memcmp(&skb_sig, &seq_id, sizeof(seq_id)))
3473 continue;
3474
3475 __skb_unlink(skb, &ptp_priv->tx_queue);
3476 ret = true;
3477 break;
3478 }
3479 spin_unlock_irqrestore(&ptp_priv->tx_queue.lock, flags);
3480
3481 if (ret) {
3482 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
3483 shhwtstamps.hwtstamp = ktime_set(seconds, nsec);
3484 skb_complete_tx_timestamp(skb, &shhwtstamps);
3485 }
3486}
3487
3488static void lan8814_dequeue_tx_skb(struct kszphy_ptp_priv *ptp_priv)
3489{
3490 struct phy_device *phydev = ptp_priv->phydev;
3491 u32 seconds, nsec;
3492 u16 seq_id;
3493
3494 lan8814_ptp_tx_ts_get(phydev, &seconds, &nsec, &seq_id);
3495 lan8814_match_tx_skb(ptp_priv, seconds, nsec, seq_id);
3496}
3497
3498static void lan8814_get_tx_ts(struct kszphy_ptp_priv *ptp_priv)
3499{
3500 struct phy_device *phydev = ptp_priv->phydev;
3501 u32 reg;
3502
3503 do {
3504 lan8814_dequeue_tx_skb(ptp_priv);
3505
3506 /* If other timestamps are available in the FIFO,
3507 * process them.
3508 */
3509 reg = lanphy_read_page_reg(phydev, 5, PTP_CAP_INFO);
3510 } while (PTP_CAP_INFO_TX_TS_CNT_GET_(reg) > 0);
3511}
3512
3513static bool lan8814_match_skb(struct kszphy_ptp_priv *ptp_priv,
3514 struct lan8814_ptp_rx_ts *rx_ts)
3515{
3516 struct skb_shared_hwtstamps *shhwtstamps;
3517 struct sk_buff *skb, *skb_tmp;
3518 unsigned long flags;
3519 bool ret = false;
3520 u16 skb_sig;
3521
3522 spin_lock_irqsave(&ptp_priv->rx_queue.lock, flags);
3523 skb_queue_walk_safe(&ptp_priv->rx_queue, skb, skb_tmp) {
3524 if (!lan8814_get_sig_rx(skb, &skb_sig))
3525 continue;
3526
3527 if (memcmp(&skb_sig, &rx_ts->seq_id, sizeof(rx_ts->seq_id)))
3528 continue;
3529
3530 __skb_unlink(skb, &ptp_priv->rx_queue);
3531
3532 ret = true;
3533 break;
3534 }
3535 spin_unlock_irqrestore(&ptp_priv->rx_queue.lock, flags);
3536
3537 if (ret) {
3538 shhwtstamps = skb_hwtstamps(skb);
3539 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
3540 shhwtstamps->hwtstamp = ktime_set(rx_ts->seconds, rx_ts->nsec);
3541 netif_rx(skb);
3542 }
3543
3544 return ret;
3545}
3546
3547static void lan8814_match_rx_ts(struct kszphy_ptp_priv *ptp_priv,
3548 struct lan8814_ptp_rx_ts *rx_ts)
3549{
3550 unsigned long flags;
3551
3552 /* If we failed to match the skb add it to the queue for when
3553 * the frame will come
3554 */
3555 if (!lan8814_match_skb(ptp_priv, rx_ts)) {
3556 spin_lock_irqsave(&ptp_priv->rx_ts_lock, flags);
3557 list_add(&rx_ts->list, &ptp_priv->rx_ts_list);
3558 spin_unlock_irqrestore(&ptp_priv->rx_ts_lock, flags);
3559 } else {
3560 kfree(rx_ts);
3561 }
3562}
3563
3564static void lan8814_get_rx_ts(struct kszphy_ptp_priv *ptp_priv)
3565{
3566 struct phy_device *phydev = ptp_priv->phydev;
3567 struct lan8814_ptp_rx_ts *rx_ts;
3568 u32 reg;
3569
3570 do {
3571 rx_ts = kzalloc(sizeof(*rx_ts), GFP_KERNEL);
3572 if (!rx_ts)
3573 return;
3574
3575 lan8814_ptp_rx_ts_get(phydev, &rx_ts->seconds, &rx_ts->nsec,
3576 &rx_ts->seq_id);
3577 lan8814_match_rx_ts(ptp_priv, rx_ts);
3578
3579 /* If other timestamps are available in the FIFO,
3580 * process them.
3581 */
3582 reg = lanphy_read_page_reg(phydev, 5, PTP_CAP_INFO);
3583 } while (PTP_CAP_INFO_RX_TS_CNT_GET_(reg) > 0);
3584}
3585
3586static void lan8814_handle_ptp_interrupt(struct phy_device *phydev, u16 status)
3587{
3588 struct kszphy_priv *priv = phydev->priv;
3589 struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
3590
3591 if (status & PTP_TSU_INT_STS_PTP_TX_TS_EN_)
3592 lan8814_get_tx_ts(ptp_priv);
3593
3594 if (status & PTP_TSU_INT_STS_PTP_RX_TS_EN_)
3595 lan8814_get_rx_ts(ptp_priv);
3596
3597 if (status & PTP_TSU_INT_STS_PTP_TX_TS_OVRFL_INT_) {
3598 lan8814_flush_fifo(phydev, true);
3599 skb_queue_purge(&ptp_priv->tx_queue);
3600 }
3601
3602 if (status & PTP_TSU_INT_STS_PTP_RX_TS_OVRFL_INT_) {
3603 lan8814_flush_fifo(phydev, false);
3604 skb_queue_purge(&ptp_priv->rx_queue);
3605 }
3606}
3607
3608static int lan8814_gpio_process_cap(struct lan8814_shared_priv *shared)
3609{
3610 struct phy_device *phydev = shared->phydev;
3611 struct ptp_clock_event ptp_event = {0};
3612 unsigned long nsec;
3613 s64 sec;
3614 u16 tmp;
3615
3616 /* This is 0 because whatever was the input pin it was mapped it to
3617 * ltc gpio pin 0
3618 */
3619 tmp = lanphy_read_page_reg(phydev, 4, PTP_GPIO_SEL);
3620 tmp |= PTP_GPIO_SEL_GPIO_SEL(0);
3621 lanphy_write_page_reg(phydev, 4, PTP_GPIO_SEL, tmp);
3622
3623 tmp = lanphy_read_page_reg(phydev, 4, PTP_GPIO_CAP_STS);
3624 if (!(tmp & PTP_GPIO_CAP_STS_PTP_GPIO_RE_STS(0)) &&
3625 !(tmp & PTP_GPIO_CAP_STS_PTP_GPIO_FE_STS(0)))
3626 return -1;
3627
3628 if (tmp & BIT(0)) {
3629 sec = lanphy_read_page_reg(phydev, 4, PTP_GPIO_RE_LTC_SEC_HI_CAP);
3630 sec <<= 16;
3631 sec |= lanphy_read_page_reg(phydev, 4, PTP_GPIO_RE_LTC_SEC_LO_CAP);
3632
3633 nsec = lanphy_read_page_reg(phydev, 4, PTP_GPIO_RE_LTC_NS_HI_CAP) & 0x3fff;
3634 nsec <<= 16;
3635 nsec |= lanphy_read_page_reg(phydev, 4, PTP_GPIO_RE_LTC_NS_LO_CAP);
3636 } else {
3637 sec = lanphy_read_page_reg(phydev, 4, PTP_GPIO_FE_LTC_SEC_HI_CAP);
3638 sec <<= 16;
3639 sec |= lanphy_read_page_reg(phydev, 4, PTP_GPIO_FE_LTC_SEC_LO_CAP);
3640
3641 nsec = lanphy_read_page_reg(phydev, 4, PTP_GPIO_FE_LTC_NS_HI_CAP) & 0x3fff;
3642 nsec <<= 16;
3643 nsec |= lanphy_read_page_reg(phydev, 4, PTP_GPIO_RE_LTC_NS_LO_CAP);
3644 }
3645
3646 ptp_event.index = 0;
3647 ptp_event.timestamp = ktime_set(sec, nsec);
3648 ptp_event.type = PTP_CLOCK_EXTTS;
3649 ptp_clock_event(shared->ptp_clock, &ptp_event);
3650
3651 return 0;
3652}
3653
3654static int lan8814_handle_gpio_interrupt(struct phy_device *phydev, u16 status)
3655{
3656 struct lan8814_shared_priv *shared = phydev->shared->priv;
3657 int ret;
3658
3659 mutex_lock(&shared->shared_lock);
3660 ret = lan8814_gpio_process_cap(shared);
3661 mutex_unlock(&shared->shared_lock);
3662
3663 return ret;
3664}
3665
3666static int lan8804_config_init(struct phy_device *phydev)
3667{
3668 int val;
3669
3670 /* MDI-X setting for swap A,B transmit */
3671 val = lanphy_read_page_reg(phydev, 2, LAN8804_ALIGN_SWAP);
3672 val &= ~LAN8804_ALIGN_TX_A_B_SWAP_MASK;
3673 val |= LAN8804_ALIGN_TX_A_B_SWAP;
3674 lanphy_write_page_reg(phydev, 2, LAN8804_ALIGN_SWAP, val);
3675
3676 /* Make sure that the PHY will not stop generating the clock when the
3677 * link partner goes down
3678 */
3679 lanphy_write_page_reg(phydev, 31, LAN8814_CLOCK_MANAGEMENT, 0x27e);
3680 lanphy_read_page_reg(phydev, 1, LAN8814_LINK_QUALITY);
3681
3682 return 0;
3683}
3684
3685static irqreturn_t lan8804_handle_interrupt(struct phy_device *phydev)
3686{
3687 int status;
3688
3689 status = phy_read(phydev, LAN8814_INTS);
3690 if (status < 0) {
3691 phy_error(phydev);
3692 return IRQ_NONE;
3693 }
3694
3695 if (status > 0)
3696 phy_trigger_machine(phydev);
3697
3698 return IRQ_HANDLED;
3699}
3700
3701#define LAN8804_OUTPUT_CONTROL 25
3702#define LAN8804_OUTPUT_CONTROL_INTR_BUFFER BIT(14)
3703#define LAN8804_CONTROL 31
3704#define LAN8804_CONTROL_INTR_POLARITY BIT(14)
3705
3706static int lan8804_config_intr(struct phy_device *phydev)
3707{
3708 int err;
3709
3710 /* This is an internal PHY of lan966x and is not possible to change the
3711 * polarity on the GIC found in lan966x, therefore change the polarity
3712 * of the interrupt in the PHY from being active low instead of active
3713 * high.
3714 */
3715 phy_write(phydev, LAN8804_CONTROL, LAN8804_CONTROL_INTR_POLARITY);
3716
3717 /* By default interrupt buffer is open-drain in which case the interrupt
3718 * can be active only low. Therefore change the interrupt buffer to be
3719 * push-pull to be able to change interrupt polarity
3720 */
3721 phy_write(phydev, LAN8804_OUTPUT_CONTROL,
3722 LAN8804_OUTPUT_CONTROL_INTR_BUFFER);
3723
3724 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
3725 err = phy_read(phydev, LAN8814_INTS);
3726 if (err < 0)
3727 return err;
3728
3729 err = phy_write(phydev, LAN8814_INTC, LAN8814_INT_LINK);
3730 if (err)
3731 return err;
3732 } else {
3733 err = phy_write(phydev, LAN8814_INTC, 0);
3734 if (err)
3735 return err;
3736
3737 err = phy_read(phydev, LAN8814_INTS);
3738 if (err < 0)
3739 return err;
3740 }
3741
3742 return 0;
3743}
3744
3745static irqreturn_t lan8814_handle_interrupt(struct phy_device *phydev)
3746{
3747 int ret = IRQ_NONE;
3748 int irq_status;
3749
3750 irq_status = phy_read(phydev, LAN8814_INTS);
3751 if (irq_status < 0) {
3752 phy_error(phydev);
3753 return IRQ_NONE;
3754 }
3755
3756 if (irq_status & LAN8814_INT_LINK) {
3757 phy_trigger_machine(phydev);
3758 ret = IRQ_HANDLED;
3759 }
3760
3761 while (true) {
3762 irq_status = lanphy_read_page_reg(phydev, 5, PTP_TSU_INT_STS);
3763 if (!irq_status)
3764 break;
3765
3766 lan8814_handle_ptp_interrupt(phydev, irq_status);
3767 ret = IRQ_HANDLED;
3768 }
3769
3770 if (!lan8814_handle_gpio_interrupt(phydev, irq_status))
3771 ret = IRQ_HANDLED;
3772
3773 return ret;
3774}
3775
3776static int lan8814_ack_interrupt(struct phy_device *phydev)
3777{
3778 /* bit[12..0] int status, which is a read and clear register. */
3779 int rc;
3780
3781 rc = phy_read(phydev, LAN8814_INTS);
3782
3783 return (rc < 0) ? rc : 0;
3784}
3785
3786static int lan8814_config_intr(struct phy_device *phydev)
3787{
3788 int err;
3789
3790 lanphy_write_page_reg(phydev, 4, LAN8814_INTR_CTRL_REG,
3791 LAN8814_INTR_CTRL_REG_POLARITY |
3792 LAN8814_INTR_CTRL_REG_INTR_ENABLE);
3793
3794 /* enable / disable interrupts */
3795 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
3796 err = lan8814_ack_interrupt(phydev);
3797 if (err)
3798 return err;
3799
3800 err = phy_write(phydev, LAN8814_INTC, LAN8814_INT_LINK);
3801 } else {
3802 err = phy_write(phydev, LAN8814_INTC, 0);
3803 if (err)
3804 return err;
3805
3806 err = lan8814_ack_interrupt(phydev);
3807 }
3808
3809 return err;
3810}
3811
3812static void lan8814_ptp_init(struct phy_device *phydev)
3813{
3814 struct kszphy_priv *priv = phydev->priv;
3815 struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
3816 u32 temp;
3817
3818 if (!IS_ENABLED(CONFIG_PTP_1588_CLOCK) ||
3819 !IS_ENABLED(CONFIG_NETWORK_PHY_TIMESTAMPING))
3820 return;
3821
3822 lanphy_write_page_reg(phydev, 5, TSU_HARD_RESET, TSU_HARD_RESET_);
3823
3824 temp = lanphy_read_page_reg(phydev, 5, PTP_TX_MOD);
3825 temp |= PTP_TX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_;
3826 lanphy_write_page_reg(phydev, 5, PTP_TX_MOD, temp);
3827
3828 temp = lanphy_read_page_reg(phydev, 5, PTP_RX_MOD);
3829 temp |= PTP_RX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_;
3830 lanphy_write_page_reg(phydev, 5, PTP_RX_MOD, temp);
3831
3832 lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_CONFIG, 0);
3833 lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_CONFIG, 0);
3834
3835 /* Removing default registers configs related to L2 and IP */
3836 lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_L2_ADDR_EN, 0);
3837 lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_L2_ADDR_EN, 0);
3838 lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_IP_ADDR_EN, 0);
3839 lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_IP_ADDR_EN, 0);
3840
3841 /* Disable checking for minorVersionPTP field */
3842 lanphy_write_page_reg(phydev, 5, PTP_RX_VERSION,
3843 PTP_MAX_VERSION(0xff) | PTP_MIN_VERSION(0x0));
3844 lanphy_write_page_reg(phydev, 5, PTP_TX_VERSION,
3845 PTP_MAX_VERSION(0xff) | PTP_MIN_VERSION(0x0));
3846
3847 skb_queue_head_init(&ptp_priv->tx_queue);
3848 skb_queue_head_init(&ptp_priv->rx_queue);
3849 INIT_LIST_HEAD(&ptp_priv->rx_ts_list);
3850 spin_lock_init(&ptp_priv->rx_ts_lock);
3851
3852 ptp_priv->phydev = phydev;
3853
3854 ptp_priv->mii_ts.rxtstamp = lan8814_rxtstamp;
3855 ptp_priv->mii_ts.txtstamp = lan8814_txtstamp;
3856 ptp_priv->mii_ts.hwtstamp = lan8814_hwtstamp;
3857 ptp_priv->mii_ts.ts_info = lan8814_ts_info;
3858
3859 phydev->mii_ts = &ptp_priv->mii_ts;
3860
3861 /* Timestamp selected by default to keep legacy API */
3862 phydev->default_timestamp = true;
3863}
3864
3865static int lan8814_ptp_probe_once(struct phy_device *phydev)
3866{
3867 struct lan8814_shared_priv *shared = phydev->shared->priv;
3868
3869 /* Initialise shared lock for clock*/
3870 mutex_init(&shared->shared_lock);
3871
3872 shared->pin_config = devm_kmalloc_array(&phydev->mdio.dev,
3873 LAN8814_PTP_GPIO_NUM,
3874 sizeof(*shared->pin_config),
3875 GFP_KERNEL);
3876 if (!shared->pin_config)
3877 return -ENOMEM;
3878
3879 for (int i = 0; i < LAN8814_PTP_GPIO_NUM; i++) {
3880 struct ptp_pin_desc *ptp_pin = &shared->pin_config[i];
3881
3882 memset(ptp_pin, 0, sizeof(*ptp_pin));
3883 snprintf(ptp_pin->name,
3884 sizeof(ptp_pin->name), "lan8814_ptp_pin_%02d", i);
3885 ptp_pin->index = i;
3886 ptp_pin->func = PTP_PF_NONE;
3887 }
3888
3889 shared->ptp_clock_info.owner = THIS_MODULE;
3890 snprintf(shared->ptp_clock_info.name, 30, "%s", phydev->drv->name);
3891 shared->ptp_clock_info.max_adj = 31249999;
3892 shared->ptp_clock_info.n_alarm = 0;
3893 shared->ptp_clock_info.n_ext_ts = LAN8814_PTP_EXTTS_NUM;
3894 shared->ptp_clock_info.n_pins = LAN8814_PTP_GPIO_NUM;
3895 shared->ptp_clock_info.pps = 0;
3896 shared->ptp_clock_info.pin_config = shared->pin_config;
3897 shared->ptp_clock_info.n_per_out = LAN8814_PTP_PEROUT_NUM;
3898 shared->ptp_clock_info.adjfine = lan8814_ptpci_adjfine;
3899 shared->ptp_clock_info.adjtime = lan8814_ptpci_adjtime;
3900 shared->ptp_clock_info.gettime64 = lan8814_ptpci_gettime64;
3901 shared->ptp_clock_info.settime64 = lan8814_ptpci_settime64;
3902 shared->ptp_clock_info.getcrosststamp = NULL;
3903 shared->ptp_clock_info.enable = lan8814_ptpci_enable;
3904 shared->ptp_clock_info.verify = lan8814_ptpci_verify;
3905
3906 shared->ptp_clock = ptp_clock_register(&shared->ptp_clock_info,
3907 &phydev->mdio.dev);
3908 if (IS_ERR(shared->ptp_clock)) {
3909 phydev_err(phydev, "ptp_clock_register failed %lu\n",
3910 PTR_ERR(shared->ptp_clock));
3911 return -EINVAL;
3912 }
3913
3914 /* Check if PHC support is missing at the configuration level */
3915 if (!shared->ptp_clock)
3916 return 0;
3917
3918 phydev_dbg(phydev, "successfully registered ptp clock\n");
3919
3920 shared->phydev = phydev;
3921
3922 /* The EP.4 is shared between all the PHYs in the package and also it
3923 * can be accessed by any of the PHYs
3924 */
3925 lanphy_write_page_reg(phydev, 4, LTC_HARD_RESET, LTC_HARD_RESET_);
3926 lanphy_write_page_reg(phydev, 4, PTP_OPERATING_MODE,
3927 PTP_OPERATING_MODE_STANDALONE_);
3928
3929 /* Enable ptp to run LTC clock for ptp and gpio 1PPS operation */
3930 lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL, PTP_CMD_CTL_PTP_ENABLE_);
3931
3932 return 0;
3933}
3934
3935static void lan8814_setup_led(struct phy_device *phydev, int val)
3936{
3937 int temp;
3938
3939 temp = lanphy_read_page_reg(phydev, 5, LAN8814_LED_CTRL_1);
3940
3941 if (val)
3942 temp |= LAN8814_LED_CTRL_1_KSZ9031_LED_MODE_;
3943 else
3944 temp &= ~LAN8814_LED_CTRL_1_KSZ9031_LED_MODE_;
3945
3946 lanphy_write_page_reg(phydev, 5, LAN8814_LED_CTRL_1, temp);
3947}
3948
3949static int lan8814_config_init(struct phy_device *phydev)
3950{
3951 struct kszphy_priv *lan8814 = phydev->priv;
3952 int val;
3953
3954 /* Reset the PHY */
3955 val = lanphy_read_page_reg(phydev, 4, LAN8814_QSGMII_SOFT_RESET);
3956 val |= LAN8814_QSGMII_SOFT_RESET_BIT;
3957 lanphy_write_page_reg(phydev, 4, LAN8814_QSGMII_SOFT_RESET, val);
3958
3959 /* Disable ANEG with QSGMII PCS Host side */
3960 val = lanphy_read_page_reg(phydev, 5, LAN8814_QSGMII_PCS1G_ANEG_CONFIG);
3961 val &= ~LAN8814_QSGMII_PCS1G_ANEG_CONFIG_ANEG_ENA;
3962 lanphy_write_page_reg(phydev, 5, LAN8814_QSGMII_PCS1G_ANEG_CONFIG, val);
3963
3964 /* MDI-X setting for swap A,B transmit */
3965 val = lanphy_read_page_reg(phydev, 2, LAN8814_ALIGN_SWAP);
3966 val &= ~LAN8814_ALIGN_TX_A_B_SWAP_MASK;
3967 val |= LAN8814_ALIGN_TX_A_B_SWAP;
3968 lanphy_write_page_reg(phydev, 2, LAN8814_ALIGN_SWAP, val);
3969
3970 if (lan8814->led_mode >= 0)
3971 lan8814_setup_led(phydev, lan8814->led_mode);
3972
3973 return 0;
3974}
3975
3976/* It is expected that there will not be any 'lan8814_take_coma_mode'
3977 * function called in suspend. Because the GPIO line can be shared, so if one of
3978 * the phys goes back in coma mode, then all the other PHYs will go, which is
3979 * wrong.
3980 */
3981static int lan8814_release_coma_mode(struct phy_device *phydev)
3982{
3983 struct gpio_desc *gpiod;
3984
3985 gpiod = devm_gpiod_get_optional(&phydev->mdio.dev, "coma-mode",
3986 GPIOD_OUT_HIGH_OPEN_DRAIN |
3987 GPIOD_FLAGS_BIT_NONEXCLUSIVE);
3988 if (IS_ERR(gpiod))
3989 return PTR_ERR(gpiod);
3990
3991 gpiod_set_consumer_name(gpiod, "LAN8814 coma mode");
3992 gpiod_set_value_cansleep(gpiod, 0);
3993
3994 return 0;
3995}
3996
3997static void lan8814_clear_2psp_bit(struct phy_device *phydev)
3998{
3999 u16 val;
4000
4001 /* It was noticed that when traffic is passing through the PHY and the
4002 * cable is removed then the LED was still one even though there is no
4003 * link
4004 */
4005 val = lanphy_read_page_reg(phydev, 2, LAN8814_EEE_STATE);
4006 val &= ~LAN8814_EEE_STATE_MASK2P5P;
4007 lanphy_write_page_reg(phydev, 2, LAN8814_EEE_STATE, val);
4008}
4009
4010static void lan8814_update_meas_time(struct phy_device *phydev)
4011{
4012 u16 val;
4013
4014 /* By setting the measure time to a value of 0xb this will allow cables
4015 * longer than 100m to be used. This configuration can be used
4016 * regardless of the mode of operation of the PHY
4017 */
4018 val = lanphy_read_page_reg(phydev, 1, LAN8814_PD_CONTROLS);
4019 val &= ~LAN8814_PD_CONTROLS_PD_MEAS_TIME_MASK;
4020 val |= LAN8814_PD_CONTROLS_PD_MEAS_TIME_VAL;
4021 lanphy_write_page_reg(phydev, 1, LAN8814_PD_CONTROLS, val);
4022}
4023
4024static int lan8814_probe(struct phy_device *phydev)
4025{
4026 const struct kszphy_type *type = phydev->drv->driver_data;
4027 struct kszphy_priv *priv;
4028 u16 addr;
4029 int err;
4030
4031 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
4032 if (!priv)
4033 return -ENOMEM;
4034
4035 phydev->priv = priv;
4036
4037 priv->type = type;
4038
4039 kszphy_parse_led_mode(phydev);
4040
4041 /* Strap-in value for PHY address, below register read gives starting
4042 * phy address value
4043 */
4044 addr = lanphy_read_page_reg(phydev, 4, 0) & 0x1F;
4045 devm_phy_package_join(&phydev->mdio.dev, phydev,
4046 addr, sizeof(struct lan8814_shared_priv));
4047
4048 if (phy_package_init_once(phydev)) {
4049 err = lan8814_release_coma_mode(phydev);
4050 if (err)
4051 return err;
4052
4053 err = lan8814_ptp_probe_once(phydev);
4054 if (err)
4055 return err;
4056 }
4057
4058 lan8814_ptp_init(phydev);
4059
4060 /* Errata workarounds */
4061 lan8814_clear_2psp_bit(phydev);
4062 lan8814_update_meas_time(phydev);
4063
4064 return 0;
4065}
4066
4067#define LAN8841_MMD_TIMER_REG 0
4068#define LAN8841_MMD0_REGISTER_17 17
4069#define LAN8841_MMD0_REGISTER_17_DROP_OPT(x) ((x) & 0x3)
4070#define LAN8841_MMD0_REGISTER_17_XMIT_TOG_TX_DIS BIT(3)
4071#define LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG 2
4072#define LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG_MAGJACK BIT(14)
4073#define LAN8841_MMD_ANALOG_REG 28
4074#define LAN8841_ANALOG_CONTROL_1 1
4075#define LAN8841_ANALOG_CONTROL_1_PLL_TRIM(x) (((x) & 0x3) << 5)
4076#define LAN8841_ANALOG_CONTROL_10 13
4077#define LAN8841_ANALOG_CONTROL_10_PLL_DIV(x) ((x) & 0x3)
4078#define LAN8841_ANALOG_CONTROL_11 14
4079#define LAN8841_ANALOG_CONTROL_11_LDO_REF(x) (((x) & 0x7) << 12)
4080#define LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT 69
4081#define LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT_VAL 0xbffc
4082#define LAN8841_BTRX_POWER_DOWN 70
4083#define LAN8841_BTRX_POWER_DOWN_QBIAS_CH_A BIT(0)
4084#define LAN8841_BTRX_POWER_DOWN_BTRX_CH_A BIT(1)
4085#define LAN8841_BTRX_POWER_DOWN_QBIAS_CH_B BIT(2)
4086#define LAN8841_BTRX_POWER_DOWN_BTRX_CH_B BIT(3)
4087#define LAN8841_BTRX_POWER_DOWN_BTRX_CH_C BIT(5)
4088#define LAN8841_BTRX_POWER_DOWN_BTRX_CH_D BIT(7)
4089#define LAN8841_ADC_CHANNEL_MASK 198
4090#define LAN8841_PTP_RX_PARSE_L2_ADDR_EN 370
4091#define LAN8841_PTP_RX_PARSE_IP_ADDR_EN 371
4092#define LAN8841_PTP_RX_VERSION 374
4093#define LAN8841_PTP_TX_PARSE_L2_ADDR_EN 434
4094#define LAN8841_PTP_TX_PARSE_IP_ADDR_EN 435
4095#define LAN8841_PTP_TX_VERSION 438
4096#define LAN8841_PTP_CMD_CTL 256
4097#define LAN8841_PTP_CMD_CTL_PTP_ENABLE BIT(2)
4098#define LAN8841_PTP_CMD_CTL_PTP_DISABLE BIT(1)
4099#define LAN8841_PTP_CMD_CTL_PTP_RESET BIT(0)
4100#define LAN8841_PTP_RX_PARSE_CONFIG 368
4101#define LAN8841_PTP_TX_PARSE_CONFIG 432
4102#define LAN8841_PTP_RX_MODE 381
4103#define LAN8841_PTP_INSERT_TS_EN BIT(0)
4104#define LAN8841_PTP_INSERT_TS_32BIT BIT(1)
4105
4106static int lan8841_config_init(struct phy_device *phydev)
4107{
4108 int ret;
4109
4110 ret = ksz9131_config_init(phydev);
4111 if (ret)
4112 return ret;
4113
4114 /* Initialize the HW by resetting everything */
4115 phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4116 LAN8841_PTP_CMD_CTL,
4117 LAN8841_PTP_CMD_CTL_PTP_RESET,
4118 LAN8841_PTP_CMD_CTL_PTP_RESET);
4119
4120 phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4121 LAN8841_PTP_CMD_CTL,
4122 LAN8841_PTP_CMD_CTL_PTP_ENABLE,
4123 LAN8841_PTP_CMD_CTL_PTP_ENABLE);
4124
4125 /* Don't process any frames */
4126 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4127 LAN8841_PTP_RX_PARSE_CONFIG, 0);
4128 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4129 LAN8841_PTP_TX_PARSE_CONFIG, 0);
4130 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4131 LAN8841_PTP_TX_PARSE_L2_ADDR_EN, 0);
4132 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4133 LAN8841_PTP_RX_PARSE_L2_ADDR_EN, 0);
4134 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4135 LAN8841_PTP_TX_PARSE_IP_ADDR_EN, 0);
4136 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4137 LAN8841_PTP_RX_PARSE_IP_ADDR_EN, 0);
4138
4139 /* Disable checking for minorVersionPTP field */
4140 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4141 LAN8841_PTP_RX_VERSION, 0xff00);
4142 phy_write_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4143 LAN8841_PTP_TX_VERSION, 0xff00);
4144
4145 /* 100BT Clause 40 improvenent errata */
4146 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
4147 LAN8841_ANALOG_CONTROL_1,
4148 LAN8841_ANALOG_CONTROL_1_PLL_TRIM(0x2));
4149 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
4150 LAN8841_ANALOG_CONTROL_10,
4151 LAN8841_ANALOG_CONTROL_10_PLL_DIV(0x1));
4152
4153 /* 10M/100M Ethernet Signal Tuning Errata for Shorted-Center Tap
4154 * Magnetics
4155 */
4156 ret = phy_read_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4157 LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG);
4158 if (ret & LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG_MAGJACK) {
4159 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
4160 LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT,
4161 LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT_VAL);
4162 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
4163 LAN8841_BTRX_POWER_DOWN,
4164 LAN8841_BTRX_POWER_DOWN_QBIAS_CH_A |
4165 LAN8841_BTRX_POWER_DOWN_BTRX_CH_A |
4166 LAN8841_BTRX_POWER_DOWN_QBIAS_CH_B |
4167 LAN8841_BTRX_POWER_DOWN_BTRX_CH_B |
4168 LAN8841_BTRX_POWER_DOWN_BTRX_CH_C |
4169 LAN8841_BTRX_POWER_DOWN_BTRX_CH_D);
4170 }
4171
4172 /* LDO Adjustment errata */
4173 phy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,
4174 LAN8841_ANALOG_CONTROL_11,
4175 LAN8841_ANALOG_CONTROL_11_LDO_REF(1));
4176
4177 /* 100BT RGMII latency tuning errata */
4178 phy_write_mmd(phydev, MDIO_MMD_PMAPMD,
4179 LAN8841_ADC_CHANNEL_MASK, 0x0);
4180 phy_write_mmd(phydev, LAN8841_MMD_TIMER_REG,
4181 LAN8841_MMD0_REGISTER_17,
4182 LAN8841_MMD0_REGISTER_17_DROP_OPT(2) |
4183 LAN8841_MMD0_REGISTER_17_XMIT_TOG_TX_DIS);
4184
4185 return 0;
4186}
4187
4188#define LAN8841_OUTPUT_CTRL 25
4189#define LAN8841_OUTPUT_CTRL_INT_BUFFER BIT(14)
4190#define LAN8841_INT_PTP BIT(9)
4191
4192static int lan8841_config_intr(struct phy_device *phydev)
4193{
4194 int err;
4195
4196 phy_modify(phydev, LAN8841_OUTPUT_CTRL,
4197 LAN8841_OUTPUT_CTRL_INT_BUFFER, 0);
4198
4199 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
4200 err = phy_read(phydev, LAN8814_INTS);
4201 if (err < 0)
4202 return err;
4203
4204 /* Enable / disable interrupts. It is OK to enable PTP interrupt
4205 * even if it PTP is not enabled. Because the underneath blocks
4206 * will not enable the PTP so we will never get the PTP
4207 * interrupt.
4208 */
4209 err = phy_write(phydev, LAN8814_INTC,
4210 LAN8814_INT_LINK | LAN8841_INT_PTP);
4211 } else {
4212 err = phy_write(phydev, LAN8814_INTC, 0);
4213 if (err)
4214 return err;
4215
4216 err = phy_read(phydev, LAN8814_INTS);
4217 if (err < 0)
4218 return err;
4219
4220 /* Getting a positive value doesn't mean that is an error, it
4221 * just indicates what was the status. Therefore make sure to
4222 * clear the value and say that there is no error.
4223 */
4224 err = 0;
4225 }
4226
4227 return err;
4228}
4229
4230#define LAN8841_PTP_TX_EGRESS_SEC_LO 453
4231#define LAN8841_PTP_TX_EGRESS_SEC_HI 452
4232#define LAN8841_PTP_TX_EGRESS_NS_LO 451
4233#define LAN8841_PTP_TX_EGRESS_NS_HI 450
4234#define LAN8841_PTP_TX_EGRESS_NSEC_HI_VALID BIT(15)
4235#define LAN8841_PTP_TX_MSG_HEADER2 455
4236
4237static bool lan8841_ptp_get_tx_ts(struct kszphy_ptp_priv *ptp_priv,
4238 u32 *sec, u32 *nsec, u16 *seq)
4239{
4240 struct phy_device *phydev = ptp_priv->phydev;
4241
4242 *nsec = phy_read_mmd(phydev, 2, LAN8841_PTP_TX_EGRESS_NS_HI);
4243 if (!(*nsec & LAN8841_PTP_TX_EGRESS_NSEC_HI_VALID))
4244 return false;
4245
4246 *nsec = ((*nsec & 0x3fff) << 16);
4247 *nsec = *nsec | phy_read_mmd(phydev, 2, LAN8841_PTP_TX_EGRESS_NS_LO);
4248
4249 *sec = phy_read_mmd(phydev, 2, LAN8841_PTP_TX_EGRESS_SEC_HI);
4250 *sec = *sec << 16;
4251 *sec = *sec | phy_read_mmd(phydev, 2, LAN8841_PTP_TX_EGRESS_SEC_LO);
4252
4253 *seq = phy_read_mmd(phydev, 2, LAN8841_PTP_TX_MSG_HEADER2);
4254
4255 return true;
4256}
4257
4258static void lan8841_ptp_process_tx_ts(struct kszphy_ptp_priv *ptp_priv)
4259{
4260 u32 sec, nsec;
4261 u16 seq;
4262
4263 while (lan8841_ptp_get_tx_ts(ptp_priv, &sec, &nsec, &seq))
4264 lan8814_match_tx_skb(ptp_priv, sec, nsec, seq);
4265}
4266
4267#define LAN8841_PTP_INT_STS 259
4268#define LAN8841_PTP_INT_STS_PTP_TX_TS_OVRFL_INT BIT(13)
4269#define LAN8841_PTP_INT_STS_PTP_TX_TS_INT BIT(12)
4270#define LAN8841_PTP_INT_STS_PTP_GPIO_CAP_INT BIT(2)
4271
4272static void lan8841_ptp_flush_fifo(struct kszphy_ptp_priv *ptp_priv)
4273{
4274 struct phy_device *phydev = ptp_priv->phydev;
4275 int i;
4276
4277 for (i = 0; i < FIFO_SIZE; ++i)
4278 phy_read_mmd(phydev, 2, LAN8841_PTP_TX_MSG_HEADER2);
4279
4280 phy_read_mmd(phydev, 2, LAN8841_PTP_INT_STS);
4281}
4282
4283#define LAN8841_PTP_GPIO_CAP_STS 506
4284#define LAN8841_PTP_GPIO_SEL 327
4285#define LAN8841_PTP_GPIO_SEL_GPIO_SEL(gpio) ((gpio) << 8)
4286#define LAN8841_PTP_GPIO_RE_LTC_SEC_HI_CAP 498
4287#define LAN8841_PTP_GPIO_RE_LTC_SEC_LO_CAP 499
4288#define LAN8841_PTP_GPIO_RE_LTC_NS_HI_CAP 500
4289#define LAN8841_PTP_GPIO_RE_LTC_NS_LO_CAP 501
4290#define LAN8841_PTP_GPIO_FE_LTC_SEC_HI_CAP 502
4291#define LAN8841_PTP_GPIO_FE_LTC_SEC_LO_CAP 503
4292#define LAN8841_PTP_GPIO_FE_LTC_NS_HI_CAP 504
4293#define LAN8841_PTP_GPIO_FE_LTC_NS_LO_CAP 505
4294
4295static void lan8841_gpio_process_cap(struct kszphy_ptp_priv *ptp_priv)
4296{
4297 struct phy_device *phydev = ptp_priv->phydev;
4298 struct ptp_clock_event ptp_event = {0};
4299 int pin, ret, tmp;
4300 s32 sec, nsec;
4301
4302 pin = ptp_find_pin_unlocked(ptp_priv->ptp_clock, PTP_PF_EXTTS, 0);
4303 if (pin == -1)
4304 return;
4305
4306 tmp = phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_CAP_STS);
4307 if (tmp < 0)
4308 return;
4309
4310 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_GPIO_SEL,
4311 LAN8841_PTP_GPIO_SEL_GPIO_SEL(pin));
4312 if (ret)
4313 return;
4314
4315 mutex_lock(&ptp_priv->ptp_lock);
4316 if (tmp & BIT(pin)) {
4317 sec = phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_RE_LTC_SEC_HI_CAP);
4318 sec <<= 16;
4319 sec |= phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_RE_LTC_SEC_LO_CAP);
4320
4321 nsec = phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_RE_LTC_NS_HI_CAP) & 0x3fff;
4322 nsec <<= 16;
4323 nsec |= phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_RE_LTC_NS_LO_CAP);
4324 } else {
4325 sec = phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_FE_LTC_SEC_HI_CAP);
4326 sec <<= 16;
4327 sec |= phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_FE_LTC_SEC_LO_CAP);
4328
4329 nsec = phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_FE_LTC_NS_HI_CAP) & 0x3fff;
4330 nsec <<= 16;
4331 nsec |= phy_read_mmd(phydev, 2, LAN8841_PTP_GPIO_FE_LTC_NS_LO_CAP);
4332 }
4333 mutex_unlock(&ptp_priv->ptp_lock);
4334 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_GPIO_SEL, 0);
4335 if (ret)
4336 return;
4337
4338 ptp_event.index = 0;
4339 ptp_event.timestamp = ktime_set(sec, nsec);
4340 ptp_event.type = PTP_CLOCK_EXTTS;
4341 ptp_clock_event(ptp_priv->ptp_clock, &ptp_event);
4342}
4343
4344static void lan8841_handle_ptp_interrupt(struct phy_device *phydev)
4345{
4346 struct kszphy_priv *priv = phydev->priv;
4347 struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
4348 u16 status;
4349
4350 do {
4351 status = phy_read_mmd(phydev, 2, LAN8841_PTP_INT_STS);
4352
4353 if (status & LAN8841_PTP_INT_STS_PTP_TX_TS_INT)
4354 lan8841_ptp_process_tx_ts(ptp_priv);
4355
4356 if (status & LAN8841_PTP_INT_STS_PTP_GPIO_CAP_INT)
4357 lan8841_gpio_process_cap(ptp_priv);
4358
4359 if (status & LAN8841_PTP_INT_STS_PTP_TX_TS_OVRFL_INT) {
4360 lan8841_ptp_flush_fifo(ptp_priv);
4361 skb_queue_purge(&ptp_priv->tx_queue);
4362 }
4363
4364 } while (status & (LAN8841_PTP_INT_STS_PTP_TX_TS_INT |
4365 LAN8841_PTP_INT_STS_PTP_GPIO_CAP_INT |
4366 LAN8841_PTP_INT_STS_PTP_TX_TS_OVRFL_INT));
4367}
4368
4369#define LAN8841_INTS_PTP BIT(9)
4370
4371static irqreturn_t lan8841_handle_interrupt(struct phy_device *phydev)
4372{
4373 irqreturn_t ret = IRQ_NONE;
4374 int irq_status;
4375
4376 irq_status = phy_read(phydev, LAN8814_INTS);
4377 if (irq_status < 0) {
4378 phy_error(phydev);
4379 return IRQ_NONE;
4380 }
4381
4382 if (irq_status & LAN8814_INT_LINK) {
4383 phy_trigger_machine(phydev);
4384 ret = IRQ_HANDLED;
4385 }
4386
4387 if (irq_status & LAN8841_INTS_PTP) {
4388 lan8841_handle_ptp_interrupt(phydev);
4389 ret = IRQ_HANDLED;
4390 }
4391
4392 return ret;
4393}
4394
4395static int lan8841_ts_info(struct mii_timestamper *mii_ts,
4396 struct kernel_ethtool_ts_info *info)
4397{
4398 struct kszphy_ptp_priv *ptp_priv;
4399
4400 ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
4401
4402 info->phc_index = ptp_priv->ptp_clock ?
4403 ptp_clock_index(ptp_priv->ptp_clock) : -1;
4404 if (info->phc_index == -1)
4405 return 0;
4406
4407 info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |
4408 SOF_TIMESTAMPING_RX_HARDWARE |
4409 SOF_TIMESTAMPING_RAW_HARDWARE;
4410
4411 info->tx_types = (1 << HWTSTAMP_TX_OFF) |
4412 (1 << HWTSTAMP_TX_ON) |
4413 (1 << HWTSTAMP_TX_ONESTEP_SYNC);
4414
4415 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
4416 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
4417 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
4418 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
4419
4420 return 0;
4421}
4422
4423#define LAN8841_PTP_INT_EN 260
4424#define LAN8841_PTP_INT_EN_PTP_TX_TS_OVRFL_EN BIT(13)
4425#define LAN8841_PTP_INT_EN_PTP_TX_TS_EN BIT(12)
4426
4427static void lan8841_ptp_enable_processing(struct kszphy_ptp_priv *ptp_priv,
4428 bool enable)
4429{
4430 struct phy_device *phydev = ptp_priv->phydev;
4431
4432 if (enable) {
4433 /* Enable interrupts on the TX side */
4434 phy_modify_mmd(phydev, 2, LAN8841_PTP_INT_EN,
4435 LAN8841_PTP_INT_EN_PTP_TX_TS_OVRFL_EN |
4436 LAN8841_PTP_INT_EN_PTP_TX_TS_EN,
4437 LAN8841_PTP_INT_EN_PTP_TX_TS_OVRFL_EN |
4438 LAN8841_PTP_INT_EN_PTP_TX_TS_EN);
4439
4440 /* Enable the modification of the frame on RX side,
4441 * this will add the ns and 2 bits of sec in the reserved field
4442 * of the PTP header
4443 */
4444 phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4445 LAN8841_PTP_RX_MODE,
4446 LAN8841_PTP_INSERT_TS_EN |
4447 LAN8841_PTP_INSERT_TS_32BIT,
4448 LAN8841_PTP_INSERT_TS_EN |
4449 LAN8841_PTP_INSERT_TS_32BIT);
4450
4451 ptp_schedule_worker(ptp_priv->ptp_clock, 0);
4452 } else {
4453 /* Disable interrupts on the TX side */
4454 phy_modify_mmd(phydev, 2, LAN8841_PTP_INT_EN,
4455 LAN8841_PTP_INT_EN_PTP_TX_TS_OVRFL_EN |
4456 LAN8841_PTP_INT_EN_PTP_TX_TS_EN, 0);
4457
4458 /* Disable modification of the RX frames */
4459 phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
4460 LAN8841_PTP_RX_MODE,
4461 LAN8841_PTP_INSERT_TS_EN |
4462 LAN8841_PTP_INSERT_TS_32BIT, 0);
4463
4464 ptp_cancel_worker_sync(ptp_priv->ptp_clock);
4465 }
4466}
4467
4468#define LAN8841_PTP_RX_TIMESTAMP_EN 379
4469#define LAN8841_PTP_TX_TIMESTAMP_EN 443
4470#define LAN8841_PTP_TX_MOD 445
4471
4472static int lan8841_hwtstamp(struct mii_timestamper *mii_ts,
4473 struct kernel_hwtstamp_config *config,
4474 struct netlink_ext_ack *extack)
4475{
4476 struct kszphy_ptp_priv *ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
4477 struct phy_device *phydev = ptp_priv->phydev;
4478 int txcfg = 0, rxcfg = 0;
4479 int pkt_ts_enable;
4480
4481 ptp_priv->hwts_tx_type = config->tx_type;
4482 ptp_priv->rx_filter = config->rx_filter;
4483
4484 switch (config->rx_filter) {
4485 case HWTSTAMP_FILTER_NONE:
4486 ptp_priv->layer = 0;
4487 ptp_priv->version = 0;
4488 break;
4489 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
4490 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
4491 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
4492 ptp_priv->layer = PTP_CLASS_L4;
4493 ptp_priv->version = PTP_CLASS_V2;
4494 break;
4495 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
4496 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
4497 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
4498 ptp_priv->layer = PTP_CLASS_L2;
4499 ptp_priv->version = PTP_CLASS_V2;
4500 break;
4501 case HWTSTAMP_FILTER_PTP_V2_EVENT:
4502 case HWTSTAMP_FILTER_PTP_V2_SYNC:
4503 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
4504 ptp_priv->layer = PTP_CLASS_L4 | PTP_CLASS_L2;
4505 ptp_priv->version = PTP_CLASS_V2;
4506 break;
4507 default:
4508 return -ERANGE;
4509 }
4510
4511 /* Setup parsing of the frames and enable the timestamping for ptp
4512 * frames
4513 */
4514 if (ptp_priv->layer & PTP_CLASS_L2) {
4515 rxcfg |= PTP_RX_PARSE_CONFIG_LAYER2_EN_;
4516 txcfg |= PTP_TX_PARSE_CONFIG_LAYER2_EN_;
4517 } else if (ptp_priv->layer & PTP_CLASS_L4) {
4518 rxcfg |= PTP_RX_PARSE_CONFIG_IPV4_EN_ | PTP_RX_PARSE_CONFIG_IPV6_EN_;
4519 txcfg |= PTP_TX_PARSE_CONFIG_IPV4_EN_ | PTP_TX_PARSE_CONFIG_IPV6_EN_;
4520 }
4521
4522 phy_write_mmd(phydev, 2, LAN8841_PTP_RX_PARSE_CONFIG, rxcfg);
4523 phy_write_mmd(phydev, 2, LAN8841_PTP_TX_PARSE_CONFIG, txcfg);
4524
4525 pkt_ts_enable = PTP_TIMESTAMP_EN_SYNC_ | PTP_TIMESTAMP_EN_DREQ_ |
4526 PTP_TIMESTAMP_EN_PDREQ_ | PTP_TIMESTAMP_EN_PDRES_;
4527 phy_write_mmd(phydev, 2, LAN8841_PTP_RX_TIMESTAMP_EN, pkt_ts_enable);
4528 phy_write_mmd(phydev, 2, LAN8841_PTP_TX_TIMESTAMP_EN, pkt_ts_enable);
4529
4530 /* Enable / disable of the TX timestamp in the SYNC frames */
4531 phy_modify_mmd(phydev, 2, LAN8841_PTP_TX_MOD,
4532 PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_,
4533 ptp_priv->hwts_tx_type == HWTSTAMP_TX_ONESTEP_SYNC ?
4534 PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_ : 0);
4535
4536 /* Now enable/disable the timestamping */
4537 lan8841_ptp_enable_processing(ptp_priv,
4538 config->rx_filter != HWTSTAMP_FILTER_NONE);
4539
4540 skb_queue_purge(&ptp_priv->tx_queue);
4541
4542 lan8841_ptp_flush_fifo(ptp_priv);
4543
4544 return 0;
4545}
4546
4547static bool lan8841_rxtstamp(struct mii_timestamper *mii_ts,
4548 struct sk_buff *skb, int type)
4549{
4550 struct kszphy_ptp_priv *ptp_priv =
4551 container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
4552 struct ptp_header *header = ptp_parse_header(skb, type);
4553 struct skb_shared_hwtstamps *shhwtstamps;
4554 struct timespec64 ts;
4555 unsigned long flags;
4556 u32 ts_header;
4557
4558 if (!header)
4559 return false;
4560
4561 if (ptp_priv->rx_filter == HWTSTAMP_FILTER_NONE ||
4562 type == PTP_CLASS_NONE)
4563 return false;
4564
4565 if ((type & ptp_priv->version) == 0 || (type & ptp_priv->layer) == 0)
4566 return false;
4567
4568 spin_lock_irqsave(&ptp_priv->seconds_lock, flags);
4569 ts.tv_sec = ptp_priv->seconds;
4570 spin_unlock_irqrestore(&ptp_priv->seconds_lock, flags);
4571 ts_header = __be32_to_cpu(header->reserved2);
4572
4573 shhwtstamps = skb_hwtstamps(skb);
4574 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
4575
4576 /* Check for any wrap arounds for the second part */
4577 if ((ts.tv_sec & GENMASK(1, 0)) == 0 && (ts_header >> 30) == 3)
4578 ts.tv_sec -= GENMASK(1, 0) + 1;
4579 else if ((ts.tv_sec & GENMASK(1, 0)) == 3 && (ts_header >> 30) == 0)
4580 ts.tv_sec += 1;
4581
4582 shhwtstamps->hwtstamp =
4583 ktime_set((ts.tv_sec & ~(GENMASK(1, 0))) | ts_header >> 30,
4584 ts_header & GENMASK(29, 0));
4585 header->reserved2 = 0;
4586
4587 netif_rx(skb);
4588
4589 return true;
4590}
4591
4592#define LAN8841_EVENT_A 0
4593#define LAN8841_EVENT_B 1
4594#define LAN8841_PTP_LTC_TARGET_SEC_HI(event) ((event) == LAN8841_EVENT_A ? 278 : 288)
4595#define LAN8841_PTP_LTC_TARGET_SEC_LO(event) ((event) == LAN8841_EVENT_A ? 279 : 289)
4596#define LAN8841_PTP_LTC_TARGET_NS_HI(event) ((event) == LAN8841_EVENT_A ? 280 : 290)
4597#define LAN8841_PTP_LTC_TARGET_NS_LO(event) ((event) == LAN8841_EVENT_A ? 281 : 291)
4598
4599static int lan8841_ptp_set_target(struct kszphy_ptp_priv *ptp_priv, u8 event,
4600 s64 sec, u32 nsec)
4601{
4602 struct phy_device *phydev = ptp_priv->phydev;
4603 int ret;
4604
4605 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_SEC_HI(event),
4606 upper_16_bits(sec));
4607 if (ret)
4608 return ret;
4609
4610 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_SEC_LO(event),
4611 lower_16_bits(sec));
4612 if (ret)
4613 return ret;
4614
4615 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_NS_HI(event) & 0x3fff,
4616 upper_16_bits(nsec));
4617 if (ret)
4618 return ret;
4619
4620 return phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_NS_LO(event),
4621 lower_16_bits(nsec));
4622}
4623
4624#define LAN8841_BUFFER_TIME 2
4625
4626static int lan8841_ptp_update_target(struct kszphy_ptp_priv *ptp_priv,
4627 const struct timespec64 *ts)
4628{
4629 return lan8841_ptp_set_target(ptp_priv, LAN8841_EVENT_A,
4630 ts->tv_sec + LAN8841_BUFFER_TIME, 0);
4631}
4632
4633#define LAN8841_PTP_LTC_TARGET_RELOAD_SEC_HI(event) ((event) == LAN8841_EVENT_A ? 282 : 292)
4634#define LAN8841_PTP_LTC_TARGET_RELOAD_SEC_LO(event) ((event) == LAN8841_EVENT_A ? 283 : 293)
4635#define LAN8841_PTP_LTC_TARGET_RELOAD_NS_HI(event) ((event) == LAN8841_EVENT_A ? 284 : 294)
4636#define LAN8841_PTP_LTC_TARGET_RELOAD_NS_LO(event) ((event) == LAN8841_EVENT_A ? 285 : 295)
4637
4638static int lan8841_ptp_set_reload(struct kszphy_ptp_priv *ptp_priv, u8 event,
4639 s64 sec, u32 nsec)
4640{
4641 struct phy_device *phydev = ptp_priv->phydev;
4642 int ret;
4643
4644 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_RELOAD_SEC_HI(event),
4645 upper_16_bits(sec));
4646 if (ret)
4647 return ret;
4648
4649 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_RELOAD_SEC_LO(event),
4650 lower_16_bits(sec));
4651 if (ret)
4652 return ret;
4653
4654 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_RELOAD_NS_HI(event) & 0x3fff,
4655 upper_16_bits(nsec));
4656 if (ret)
4657 return ret;
4658
4659 return phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_TARGET_RELOAD_NS_LO(event),
4660 lower_16_bits(nsec));
4661}
4662
4663#define LAN8841_PTP_LTC_SET_SEC_HI 262
4664#define LAN8841_PTP_LTC_SET_SEC_MID 263
4665#define LAN8841_PTP_LTC_SET_SEC_LO 264
4666#define LAN8841_PTP_LTC_SET_NS_HI 265
4667#define LAN8841_PTP_LTC_SET_NS_LO 266
4668#define LAN8841_PTP_CMD_CTL_PTP_LTC_LOAD BIT(4)
4669
4670static int lan8841_ptp_settime64(struct ptp_clock_info *ptp,
4671 const struct timespec64 *ts)
4672{
4673 struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
4674 ptp_clock_info);
4675 struct phy_device *phydev = ptp_priv->phydev;
4676 unsigned long flags;
4677 int ret;
4678
4679 /* Set the value to be stored */
4680 mutex_lock(&ptp_priv->ptp_lock);
4681 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_SEC_LO, lower_16_bits(ts->tv_sec));
4682 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_SEC_MID, upper_16_bits(ts->tv_sec));
4683 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_SEC_HI, upper_32_bits(ts->tv_sec) & 0xffff);
4684 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_NS_LO, lower_16_bits(ts->tv_nsec));
4685 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_SET_NS_HI, upper_16_bits(ts->tv_nsec) & 0x3fff);
4686
4687 /* Set the command to load the LTC */
4688 phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL,
4689 LAN8841_PTP_CMD_CTL_PTP_LTC_LOAD);
4690 ret = lan8841_ptp_update_target(ptp_priv, ts);
4691 mutex_unlock(&ptp_priv->ptp_lock);
4692
4693 spin_lock_irqsave(&ptp_priv->seconds_lock, flags);
4694 ptp_priv->seconds = ts->tv_sec;
4695 spin_unlock_irqrestore(&ptp_priv->seconds_lock, flags);
4696
4697 return ret;
4698}
4699
4700#define LAN8841_PTP_LTC_RD_SEC_HI 358
4701#define LAN8841_PTP_LTC_RD_SEC_MID 359
4702#define LAN8841_PTP_LTC_RD_SEC_LO 360
4703#define LAN8841_PTP_LTC_RD_NS_HI 361
4704#define LAN8841_PTP_LTC_RD_NS_LO 362
4705#define LAN8841_PTP_CMD_CTL_PTP_LTC_READ BIT(3)
4706
4707static int lan8841_ptp_gettime64(struct ptp_clock_info *ptp,
4708 struct timespec64 *ts)
4709{
4710 struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
4711 ptp_clock_info);
4712 struct phy_device *phydev = ptp_priv->phydev;
4713 time64_t s;
4714 s64 ns;
4715
4716 mutex_lock(&ptp_priv->ptp_lock);
4717 /* Issue the command to read the LTC */
4718 phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL,
4719 LAN8841_PTP_CMD_CTL_PTP_LTC_READ);
4720
4721 /* Read the LTC */
4722 s = phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_HI);
4723 s <<= 16;
4724 s |= phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_MID);
4725 s <<= 16;
4726 s |= phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_LO);
4727
4728 ns = phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_NS_HI) & 0x3fff;
4729 ns <<= 16;
4730 ns |= phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_NS_LO);
4731 mutex_unlock(&ptp_priv->ptp_lock);
4732
4733 set_normalized_timespec64(ts, s, ns);
4734 return 0;
4735}
4736
4737static void lan8841_ptp_getseconds(struct ptp_clock_info *ptp,
4738 struct timespec64 *ts)
4739{
4740 struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
4741 ptp_clock_info);
4742 struct phy_device *phydev = ptp_priv->phydev;
4743 time64_t s;
4744
4745 mutex_lock(&ptp_priv->ptp_lock);
4746 /* Issue the command to read the LTC */
4747 phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL,
4748 LAN8841_PTP_CMD_CTL_PTP_LTC_READ);
4749
4750 /* Read the LTC */
4751 s = phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_HI);
4752 s <<= 16;
4753 s |= phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_MID);
4754 s <<= 16;
4755 s |= phy_read_mmd(phydev, 2, LAN8841_PTP_LTC_RD_SEC_LO);
4756 mutex_unlock(&ptp_priv->ptp_lock);
4757
4758 set_normalized_timespec64(ts, s, 0);
4759}
4760
4761#define LAN8841_PTP_LTC_STEP_ADJ_LO 276
4762#define LAN8841_PTP_LTC_STEP_ADJ_HI 275
4763#define LAN8841_PTP_LTC_STEP_ADJ_DIR BIT(15)
4764#define LAN8841_PTP_CMD_CTL_PTP_LTC_STEP_SECONDS BIT(5)
4765#define LAN8841_PTP_CMD_CTL_PTP_LTC_STEP_NANOSECONDS BIT(6)
4766
4767static int lan8841_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
4768{
4769 struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
4770 ptp_clock_info);
4771 struct phy_device *phydev = ptp_priv->phydev;
4772 struct timespec64 ts;
4773 bool add = true;
4774 u32 nsec;
4775 s32 sec;
4776 int ret;
4777
4778 /* The HW allows up to 15 sec to adjust the time, but here we limit to
4779 * 10 sec the adjustment. The reason is, in case the adjustment is 14
4780 * sec and 999999999 nsec, then we add 8ns to compansate the actual
4781 * increment so the value can be bigger than 15 sec. Therefore limit the
4782 * possible adjustments so we will not have these corner cases
4783 */
4784 if (delta > 10000000000LL || delta < -10000000000LL) {
4785 /* The timeadjustment is too big, so fall back using set time */
4786 u64 now;
4787
4788 ptp->gettime64(ptp, &ts);
4789
4790 now = ktime_to_ns(timespec64_to_ktime(ts));
4791 ts = ns_to_timespec64(now + delta);
4792
4793 ptp->settime64(ptp, &ts);
4794 return 0;
4795 }
4796
4797 sec = div_u64_rem(delta < 0 ? -delta : delta, NSEC_PER_SEC, &nsec);
4798 if (delta < 0 && nsec != 0) {
4799 /* It is not allowed to adjust low the nsec part, therefore
4800 * subtract more from second part and add to nanosecond such
4801 * that would roll over, so the second part will increase
4802 */
4803 sec--;
4804 nsec = NSEC_PER_SEC - nsec;
4805 }
4806
4807 /* Calculate the adjustments and the direction */
4808 if (delta < 0)
4809 add = false;
4810
4811 if (nsec > 0)
4812 /* add 8 ns to cover the likely normal increment */
4813 nsec += 8;
4814
4815 if (nsec >= NSEC_PER_SEC) {
4816 /* carry into seconds */
4817 sec++;
4818 nsec -= NSEC_PER_SEC;
4819 }
4820
4821 mutex_lock(&ptp_priv->ptp_lock);
4822 if (sec) {
4823 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_STEP_ADJ_LO, sec);
4824 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_STEP_ADJ_HI,
4825 add ? LAN8841_PTP_LTC_STEP_ADJ_DIR : 0);
4826 phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL,
4827 LAN8841_PTP_CMD_CTL_PTP_LTC_STEP_SECONDS);
4828 }
4829
4830 if (nsec) {
4831 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_STEP_ADJ_LO,
4832 nsec & 0xffff);
4833 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_STEP_ADJ_HI,
4834 (nsec >> 16) & 0x3fff);
4835 phy_write_mmd(phydev, 2, LAN8841_PTP_CMD_CTL,
4836 LAN8841_PTP_CMD_CTL_PTP_LTC_STEP_NANOSECONDS);
4837 }
4838 mutex_unlock(&ptp_priv->ptp_lock);
4839
4840 /* Update the target clock */
4841 ptp->gettime64(ptp, &ts);
4842 mutex_lock(&ptp_priv->ptp_lock);
4843 ret = lan8841_ptp_update_target(ptp_priv, &ts);
4844 mutex_unlock(&ptp_priv->ptp_lock);
4845
4846 return ret;
4847}
4848
4849#define LAN8841_PTP_LTC_RATE_ADJ_HI 269
4850#define LAN8841_PTP_LTC_RATE_ADJ_HI_DIR BIT(15)
4851#define LAN8841_PTP_LTC_RATE_ADJ_LO 270
4852
4853static int lan8841_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
4854{
4855 struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
4856 ptp_clock_info);
4857 struct phy_device *phydev = ptp_priv->phydev;
4858 bool faster = true;
4859 u32 rate;
4860
4861 if (!scaled_ppm)
4862 return 0;
4863
4864 if (scaled_ppm < 0) {
4865 scaled_ppm = -scaled_ppm;
4866 faster = false;
4867 }
4868
4869 rate = LAN8841_1PPM_FORMAT * (upper_16_bits(scaled_ppm));
4870 rate += (LAN8841_1PPM_FORMAT * (lower_16_bits(scaled_ppm))) >> 16;
4871
4872 mutex_lock(&ptp_priv->ptp_lock);
4873 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_RATE_ADJ_HI,
4874 faster ? LAN8841_PTP_LTC_RATE_ADJ_HI_DIR | (upper_16_bits(rate) & 0x3fff)
4875 : upper_16_bits(rate) & 0x3fff);
4876 phy_write_mmd(phydev, 2, LAN8841_PTP_LTC_RATE_ADJ_LO, lower_16_bits(rate));
4877 mutex_unlock(&ptp_priv->ptp_lock);
4878
4879 return 0;
4880}
4881
4882static int lan8841_ptp_verify(struct ptp_clock_info *ptp, unsigned int pin,
4883 enum ptp_pin_function func, unsigned int chan)
4884{
4885 switch (func) {
4886 case PTP_PF_NONE:
4887 case PTP_PF_PEROUT:
4888 case PTP_PF_EXTTS:
4889 break;
4890 default:
4891 return -1;
4892 }
4893
4894 return 0;
4895}
4896
4897#define LAN8841_PTP_GPIO_NUM 10
4898#define LAN8841_GPIO_EN 128
4899#define LAN8841_GPIO_DIR 129
4900#define LAN8841_GPIO_BUF 130
4901
4902static int lan8841_ptp_perout_off(struct kszphy_ptp_priv *ptp_priv, int pin)
4903{
4904 struct phy_device *phydev = ptp_priv->phydev;
4905 int ret;
4906
4907 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin));
4908 if (ret)
4909 return ret;
4910
4911 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_DIR, BIT(pin));
4912 if (ret)
4913 return ret;
4914
4915 return phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_BUF, BIT(pin));
4916}
4917
4918static int lan8841_ptp_perout_on(struct kszphy_ptp_priv *ptp_priv, int pin)
4919{
4920 struct phy_device *phydev = ptp_priv->phydev;
4921 int ret;
4922
4923 ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin));
4924 if (ret)
4925 return ret;
4926
4927 ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_DIR, BIT(pin));
4928 if (ret)
4929 return ret;
4930
4931 return phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_BUF, BIT(pin));
4932}
4933
4934#define LAN8841_GPIO_DATA_SEL1 131
4935#define LAN8841_GPIO_DATA_SEL2 132
4936#define LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_MASK GENMASK(2, 0)
4937#define LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_A 1
4938#define LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_B 2
4939#define LAN8841_PTP_GENERAL_CONFIG 257
4940#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_A BIT(1)
4941#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_B BIT(3)
4942#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A_MASK GENMASK(7, 4)
4943#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B_MASK GENMASK(11, 8)
4944#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A 4
4945#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B 7
4946
4947static int lan8841_ptp_remove_event(struct kszphy_ptp_priv *ptp_priv, int pin,
4948 u8 event)
4949{
4950 struct phy_device *phydev = ptp_priv->phydev;
4951 u16 tmp;
4952 int ret;
4953
4954 /* Now remove pin from the event. GPIO_DATA_SEL1 contains the GPIO
4955 * pins 0-4 while GPIO_DATA_SEL2 contains GPIO pins 5-9, therefore
4956 * depending on the pin, it requires to read a different register
4957 */
4958 if (pin < 5) {
4959 tmp = LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_MASK << (3 * pin);
4960 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL1, tmp);
4961 } else {
4962 tmp = LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_MASK << (3 * (pin - 5));
4963 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL2, tmp);
4964 }
4965 if (ret)
4966 return ret;
4967
4968 /* Disable the event */
4969 if (event == LAN8841_EVENT_A)
4970 tmp = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_A |
4971 LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A_MASK;
4972 else
4973 tmp = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_B |
4974 LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B_MASK;
4975 return phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_EN, tmp);
4976}
4977
4978static int lan8841_ptp_enable_event(struct kszphy_ptp_priv *ptp_priv, int pin,
4979 u8 event, int pulse_width)
4980{
4981 struct phy_device *phydev = ptp_priv->phydev;
4982 u16 tmp;
4983 int ret;
4984
4985 /* Enable the event */
4986 if (event == LAN8841_EVENT_A)
4987 ret = phy_modify_mmd(phydev, 2, LAN8841_PTP_GENERAL_CONFIG,
4988 LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_A |
4989 LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A_MASK,
4990 LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_A |
4991 pulse_width << LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_A);
4992 else
4993 ret = phy_modify_mmd(phydev, 2, LAN8841_PTP_GENERAL_CONFIG,
4994 LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_B |
4995 LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B_MASK,
4996 LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_POL_B |
4997 pulse_width << LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_B);
4998 if (ret)
4999 return ret;
5000
5001 /* Now connect the pin to the event. GPIO_DATA_SEL1 contains the GPIO
5002 * pins 0-4 while GPIO_DATA_SEL2 contains GPIO pins 5-9, therefore
5003 * depending on the pin, it requires to read a different register
5004 */
5005 if (event == LAN8841_EVENT_A)
5006 tmp = LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_A;
5007 else
5008 tmp = LAN8841_GPIO_DATA_SEL_GPIO_DATA_SEL_EVENT_B;
5009
5010 if (pin < 5)
5011 ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL1,
5012 tmp << (3 * pin));
5013 else
5014 ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_DATA_SEL2,
5015 tmp << (3 * (pin - 5)));
5016
5017 return ret;
5018}
5019
5020#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_200MS 13
5021#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100MS 12
5022#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50MS 11
5023#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10MS 10
5024#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5MS 9
5025#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1MS 8
5026#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500US 7
5027#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100US 6
5028#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50US 5
5029#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10US 4
5030#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5US 3
5031#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1US 2
5032#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500NS 1
5033#define LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100NS 0
5034
5035static int lan8841_ptp_perout(struct ptp_clock_info *ptp,
5036 struct ptp_clock_request *rq, int on)
5037{
5038 struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
5039 ptp_clock_info);
5040 struct phy_device *phydev = ptp_priv->phydev;
5041 struct timespec64 ts_on, ts_period;
5042 s64 on_nsec, period_nsec;
5043 int pulse_width;
5044 int pin;
5045 int ret;
5046
5047 if (rq->perout.flags & ~PTP_PEROUT_DUTY_CYCLE)
5048 return -EOPNOTSUPP;
5049
5050 pin = ptp_find_pin(ptp_priv->ptp_clock, PTP_PF_PEROUT, rq->perout.index);
5051 if (pin == -1 || pin >= LAN8841_PTP_GPIO_NUM)
5052 return -EINVAL;
5053
5054 if (!on) {
5055 ret = lan8841_ptp_perout_off(ptp_priv, pin);
5056 if (ret)
5057 return ret;
5058
5059 return lan8841_ptp_remove_event(ptp_priv, LAN8841_EVENT_A, pin);
5060 }
5061
5062 ts_on.tv_sec = rq->perout.on.sec;
5063 ts_on.tv_nsec = rq->perout.on.nsec;
5064 on_nsec = timespec64_to_ns(&ts_on);
5065
5066 ts_period.tv_sec = rq->perout.period.sec;
5067 ts_period.tv_nsec = rq->perout.period.nsec;
5068 period_nsec = timespec64_to_ns(&ts_period);
5069
5070 if (period_nsec < 200) {
5071 pr_warn_ratelimited("%s: perout period too small, minimum is 200 nsec\n",
5072 phydev_name(phydev));
5073 return -EOPNOTSUPP;
5074 }
5075
5076 if (on_nsec >= period_nsec) {
5077 pr_warn_ratelimited("%s: pulse width must be smaller than period\n",
5078 phydev_name(phydev));
5079 return -EINVAL;
5080 }
5081
5082 switch (on_nsec) {
5083 case 200000000:
5084 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_200MS;
5085 break;
5086 case 100000000:
5087 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100MS;
5088 break;
5089 case 50000000:
5090 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50MS;
5091 break;
5092 case 10000000:
5093 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10MS;
5094 break;
5095 case 5000000:
5096 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5MS;
5097 break;
5098 case 1000000:
5099 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1MS;
5100 break;
5101 case 500000:
5102 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500US;
5103 break;
5104 case 100000:
5105 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100US;
5106 break;
5107 case 50000:
5108 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_50US;
5109 break;
5110 case 10000:
5111 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_10US;
5112 break;
5113 case 5000:
5114 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_5US;
5115 break;
5116 case 1000:
5117 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_1US;
5118 break;
5119 case 500:
5120 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_500NS;
5121 break;
5122 case 100:
5123 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100NS;
5124 break;
5125 default:
5126 pr_warn_ratelimited("%s: Use default duty cycle of 100ns\n",
5127 phydev_name(phydev));
5128 pulse_width = LAN8841_PTP_GENERAL_CONFIG_LTC_EVENT_100NS;
5129 break;
5130 }
5131
5132 mutex_lock(&ptp_priv->ptp_lock);
5133 ret = lan8841_ptp_set_target(ptp_priv, LAN8841_EVENT_A, rq->perout.start.sec,
5134 rq->perout.start.nsec);
5135 mutex_unlock(&ptp_priv->ptp_lock);
5136 if (ret)
5137 return ret;
5138
5139 ret = lan8841_ptp_set_reload(ptp_priv, LAN8841_EVENT_A, rq->perout.period.sec,
5140 rq->perout.period.nsec);
5141 if (ret)
5142 return ret;
5143
5144 ret = lan8841_ptp_enable_event(ptp_priv, pin, LAN8841_EVENT_A,
5145 pulse_width);
5146 if (ret)
5147 return ret;
5148
5149 ret = lan8841_ptp_perout_on(ptp_priv, pin);
5150 if (ret)
5151 lan8841_ptp_remove_event(ptp_priv, pin, LAN8841_EVENT_A);
5152
5153 return ret;
5154}
5155
5156#define LAN8841_PTP_GPIO_CAP_EN 496
5157#define LAN8841_PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(gpio) (BIT(gpio))
5158#define LAN8841_PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(gpio) (BIT(gpio) << 8)
5159#define LAN8841_PTP_INT_EN_PTP_GPIO_CAP_EN BIT(2)
5160
5161static int lan8841_ptp_extts_on(struct kszphy_ptp_priv *ptp_priv, int pin,
5162 u32 flags)
5163{
5164 struct phy_device *phydev = ptp_priv->phydev;
5165 u16 tmp = 0;
5166 int ret;
5167
5168 /* Set GPIO to be intput */
5169 ret = phy_set_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin));
5170 if (ret)
5171 return ret;
5172
5173 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_BUF, BIT(pin));
5174 if (ret)
5175 return ret;
5176
5177 /* Enable capture on the edges of the pin */
5178 if (flags & PTP_RISING_EDGE)
5179 tmp |= LAN8841_PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(pin);
5180 if (flags & PTP_FALLING_EDGE)
5181 tmp |= LAN8841_PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(pin);
5182 ret = phy_write_mmd(phydev, 2, LAN8841_PTP_GPIO_CAP_EN, tmp);
5183 if (ret)
5184 return ret;
5185
5186 /* Enable interrupt */
5187 return phy_modify_mmd(phydev, 2, LAN8841_PTP_INT_EN,
5188 LAN8841_PTP_INT_EN_PTP_GPIO_CAP_EN,
5189 LAN8841_PTP_INT_EN_PTP_GPIO_CAP_EN);
5190}
5191
5192static int lan8841_ptp_extts_off(struct kszphy_ptp_priv *ptp_priv, int pin)
5193{
5194 struct phy_device *phydev = ptp_priv->phydev;
5195 int ret;
5196
5197 /* Set GPIO to be output */
5198 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_EN, BIT(pin));
5199 if (ret)
5200 return ret;
5201
5202 ret = phy_clear_bits_mmd(phydev, 2, LAN8841_GPIO_BUF, BIT(pin));
5203 if (ret)
5204 return ret;
5205
5206 /* Disable capture on both of the edges */
5207 ret = phy_modify_mmd(phydev, 2, LAN8841_PTP_GPIO_CAP_EN,
5208 LAN8841_PTP_GPIO_CAP_EN_GPIO_RE_CAPTURE_ENABLE(pin) |
5209 LAN8841_PTP_GPIO_CAP_EN_GPIO_FE_CAPTURE_ENABLE(pin),
5210 0);
5211 if (ret)
5212 return ret;
5213
5214 /* Disable interrupt */
5215 return phy_modify_mmd(phydev, 2, LAN8841_PTP_INT_EN,
5216 LAN8841_PTP_INT_EN_PTP_GPIO_CAP_EN,
5217 0);
5218}
5219
5220static int lan8841_ptp_extts(struct ptp_clock_info *ptp,
5221 struct ptp_clock_request *rq, int on)
5222{
5223 struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
5224 ptp_clock_info);
5225 int pin;
5226 int ret;
5227
5228 /* Reject requests with unsupported flags */
5229 if (rq->extts.flags & ~(PTP_ENABLE_FEATURE |
5230 PTP_EXTTS_EDGES |
5231 PTP_STRICT_FLAGS))
5232 return -EOPNOTSUPP;
5233
5234 pin = ptp_find_pin(ptp_priv->ptp_clock, PTP_PF_EXTTS, rq->extts.index);
5235 if (pin == -1 || pin >= LAN8841_PTP_GPIO_NUM)
5236 return -EINVAL;
5237
5238 mutex_lock(&ptp_priv->ptp_lock);
5239 if (on)
5240 ret = lan8841_ptp_extts_on(ptp_priv, pin, rq->extts.flags);
5241 else
5242 ret = lan8841_ptp_extts_off(ptp_priv, pin);
5243 mutex_unlock(&ptp_priv->ptp_lock);
5244
5245 return ret;
5246}
5247
5248static int lan8841_ptp_enable(struct ptp_clock_info *ptp,
5249 struct ptp_clock_request *rq, int on)
5250{
5251 switch (rq->type) {
5252 case PTP_CLK_REQ_EXTTS:
5253 return lan8841_ptp_extts(ptp, rq, on);
5254 case PTP_CLK_REQ_PEROUT:
5255 return lan8841_ptp_perout(ptp, rq, on);
5256 default:
5257 return -EOPNOTSUPP;
5258 }
5259
5260 return 0;
5261}
5262
5263static long lan8841_ptp_do_aux_work(struct ptp_clock_info *ptp)
5264{
5265 struct kszphy_ptp_priv *ptp_priv = container_of(ptp, struct kszphy_ptp_priv,
5266 ptp_clock_info);
5267 struct timespec64 ts;
5268 unsigned long flags;
5269
5270 lan8841_ptp_getseconds(&ptp_priv->ptp_clock_info, &ts);
5271
5272 spin_lock_irqsave(&ptp_priv->seconds_lock, flags);
5273 ptp_priv->seconds = ts.tv_sec;
5274 spin_unlock_irqrestore(&ptp_priv->seconds_lock, flags);
5275
5276 return nsecs_to_jiffies(LAN8841_GET_SEC_LTC_DELAY);
5277}
5278
5279static struct ptp_clock_info lan8841_ptp_clock_info = {
5280 .owner = THIS_MODULE,
5281 .name = "lan8841 ptp",
5282 .max_adj = 31249999,
5283 .gettime64 = lan8841_ptp_gettime64,
5284 .settime64 = lan8841_ptp_settime64,
5285 .adjtime = lan8841_ptp_adjtime,
5286 .adjfine = lan8841_ptp_adjfine,
5287 .verify = lan8841_ptp_verify,
5288 .enable = lan8841_ptp_enable,
5289 .do_aux_work = lan8841_ptp_do_aux_work,
5290 .n_per_out = LAN8841_PTP_GPIO_NUM,
5291 .n_ext_ts = LAN8841_PTP_GPIO_NUM,
5292 .n_pins = LAN8841_PTP_GPIO_NUM,
5293};
5294
5295#define LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER 3
5296#define LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER_STRAP_RGMII_EN BIT(0)
5297
5298static int lan8841_probe(struct phy_device *phydev)
5299{
5300 struct kszphy_ptp_priv *ptp_priv;
5301 struct kszphy_priv *priv;
5302 int err;
5303
5304 err = kszphy_probe(phydev);
5305 if (err)
5306 return err;
5307
5308 if (phy_read_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
5309 LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER) &
5310 LAN8841_OPERATION_MODE_STRAP_LOW_REGISTER_STRAP_RGMII_EN)
5311 phydev->interface = PHY_INTERFACE_MODE_RGMII_RXID;
5312
5313 /* Register the clock */
5314 if (!IS_ENABLED(CONFIG_NETWORK_PHY_TIMESTAMPING))
5315 return 0;
5316
5317 priv = phydev->priv;
5318 ptp_priv = &priv->ptp_priv;
5319
5320 ptp_priv->pin_config = devm_kcalloc(&phydev->mdio.dev,
5321 LAN8841_PTP_GPIO_NUM,
5322 sizeof(*ptp_priv->pin_config),
5323 GFP_KERNEL);
5324 if (!ptp_priv->pin_config)
5325 return -ENOMEM;
5326
5327 for (int i = 0; i < LAN8841_PTP_GPIO_NUM; ++i) {
5328 struct ptp_pin_desc *p = &ptp_priv->pin_config[i];
5329
5330 snprintf(p->name, sizeof(p->name), "pin%d", i);
5331 p->index = i;
5332 p->func = PTP_PF_NONE;
5333 }
5334
5335 ptp_priv->ptp_clock_info = lan8841_ptp_clock_info;
5336 ptp_priv->ptp_clock_info.pin_config = ptp_priv->pin_config;
5337 ptp_priv->ptp_clock = ptp_clock_register(&ptp_priv->ptp_clock_info,
5338 &phydev->mdio.dev);
5339 if (IS_ERR(ptp_priv->ptp_clock)) {
5340 phydev_err(phydev, "ptp_clock_register failed: %lu\n",
5341 PTR_ERR(ptp_priv->ptp_clock));
5342 return -EINVAL;
5343 }
5344
5345 if (!ptp_priv->ptp_clock)
5346 return 0;
5347
5348 /* Initialize the SW */
5349 skb_queue_head_init(&ptp_priv->tx_queue);
5350 ptp_priv->phydev = phydev;
5351 mutex_init(&ptp_priv->ptp_lock);
5352 spin_lock_init(&ptp_priv->seconds_lock);
5353
5354 ptp_priv->mii_ts.rxtstamp = lan8841_rxtstamp;
5355 ptp_priv->mii_ts.txtstamp = lan8814_txtstamp;
5356 ptp_priv->mii_ts.hwtstamp = lan8841_hwtstamp;
5357 ptp_priv->mii_ts.ts_info = lan8841_ts_info;
5358
5359 phydev->mii_ts = &ptp_priv->mii_ts;
5360
5361 /* Timestamp selected by default to keep legacy API */
5362 phydev->default_timestamp = true;
5363
5364 return 0;
5365}
5366
5367static int lan8804_resume(struct phy_device *phydev)
5368{
5369 return kszphy_resume(phydev);
5370}
5371
5372static int lan8804_suspend(struct phy_device *phydev)
5373{
5374 return kszphy_generic_suspend(phydev);
5375}
5376
5377static int lan8841_resume(struct phy_device *phydev)
5378{
5379 return kszphy_generic_resume(phydev);
5380}
5381
5382static int lan8841_suspend(struct phy_device *phydev)
5383{
5384 struct kszphy_priv *priv = phydev->priv;
5385 struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
5386
5387 if (ptp_priv->ptp_clock)
5388 ptp_cancel_worker_sync(ptp_priv->ptp_clock);
5389
5390 return kszphy_generic_suspend(phydev);
5391}
5392
5393static struct phy_driver ksphy_driver[] = {
5394{
5395 .phy_id = PHY_ID_KS8737,
5396 .phy_id_mask = MICREL_PHY_ID_MASK,
5397 .name = "Micrel KS8737",
5398 /* PHY_BASIC_FEATURES */
5399 .driver_data = &ks8737_type,
5400 .probe = kszphy_probe,
5401 .config_init = kszphy_config_init,
5402 .config_intr = kszphy_config_intr,
5403 .handle_interrupt = kszphy_handle_interrupt,
5404 .suspend = kszphy_suspend,
5405 .resume = kszphy_resume,
5406}, {
5407 .phy_id = PHY_ID_KSZ8021,
5408 .phy_id_mask = 0x00ffffff,
5409 .name = "Micrel KSZ8021 or KSZ8031",
5410 /* PHY_BASIC_FEATURES */
5411 .driver_data = &ksz8021_type,
5412 .probe = kszphy_probe,
5413 .config_init = kszphy_config_init,
5414 .config_intr = kszphy_config_intr,
5415 .handle_interrupt = kszphy_handle_interrupt,
5416 .get_sset_count = kszphy_get_sset_count,
5417 .get_strings = kszphy_get_strings,
5418 .get_stats = kszphy_get_stats,
5419 .suspend = kszphy_suspend,
5420 .resume = kszphy_resume,
5421}, {
5422 .phy_id = PHY_ID_KSZ8031,
5423 .phy_id_mask = 0x00ffffff,
5424 .name = "Micrel KSZ8031",
5425 /* PHY_BASIC_FEATURES */
5426 .driver_data = &ksz8021_type,
5427 .probe = kszphy_probe,
5428 .config_init = kszphy_config_init,
5429 .config_intr = kszphy_config_intr,
5430 .handle_interrupt = kszphy_handle_interrupt,
5431 .get_sset_count = kszphy_get_sset_count,
5432 .get_strings = kszphy_get_strings,
5433 .get_stats = kszphy_get_stats,
5434 .suspend = kszphy_suspend,
5435 .resume = kszphy_resume,
5436}, {
5437 .phy_id = PHY_ID_KSZ8041,
5438 .phy_id_mask = MICREL_PHY_ID_MASK,
5439 .name = "Micrel KSZ8041",
5440 /* PHY_BASIC_FEATURES */
5441 .driver_data = &ksz8041_type,
5442 .probe = kszphy_probe,
5443 .config_init = ksz8041_config_init,
5444 .config_aneg = ksz8041_config_aneg,
5445 .config_intr = kszphy_config_intr,
5446 .handle_interrupt = kszphy_handle_interrupt,
5447 .get_sset_count = kszphy_get_sset_count,
5448 .get_strings = kszphy_get_strings,
5449 .get_stats = kszphy_get_stats,
5450 .suspend = ksz8041_suspend,
5451 .resume = ksz8041_resume,
5452}, {
5453 .phy_id = PHY_ID_KSZ8041RNLI,
5454 .phy_id_mask = MICREL_PHY_ID_MASK,
5455 .name = "Micrel KSZ8041RNLI",
5456 /* PHY_BASIC_FEATURES */
5457 .driver_data = &ksz8041_type,
5458 .probe = kszphy_probe,
5459 .config_init = kszphy_config_init,
5460 .config_intr = kszphy_config_intr,
5461 .handle_interrupt = kszphy_handle_interrupt,
5462 .get_sset_count = kszphy_get_sset_count,
5463 .get_strings = kszphy_get_strings,
5464 .get_stats = kszphy_get_stats,
5465 .suspend = kszphy_suspend,
5466 .resume = kszphy_resume,
5467}, {
5468 .name = "Micrel KSZ8051",
5469 /* PHY_BASIC_FEATURES */
5470 .driver_data = &ksz8051_type,
5471 .probe = kszphy_probe,
5472 .config_init = kszphy_config_init,
5473 .config_intr = kszphy_config_intr,
5474 .handle_interrupt = kszphy_handle_interrupt,
5475 .get_sset_count = kszphy_get_sset_count,
5476 .get_strings = kszphy_get_strings,
5477 .get_stats = kszphy_get_stats,
5478 .match_phy_device = ksz8051_match_phy_device,
5479 .suspend = kszphy_suspend,
5480 .resume = kszphy_resume,
5481}, {
5482 .phy_id = PHY_ID_KSZ8001,
5483 .name = "Micrel KSZ8001 or KS8721",
5484 .phy_id_mask = 0x00fffffc,
5485 /* PHY_BASIC_FEATURES */
5486 .driver_data = &ksz8041_type,
5487 .probe = kszphy_probe,
5488 .config_init = kszphy_config_init,
5489 .config_intr = kszphy_config_intr,
5490 .handle_interrupt = kszphy_handle_interrupt,
5491 .get_sset_count = kszphy_get_sset_count,
5492 .get_strings = kszphy_get_strings,
5493 .get_stats = kszphy_get_stats,
5494 .suspend = kszphy_suspend,
5495 .resume = kszphy_resume,
5496}, {
5497 .phy_id = PHY_ID_KSZ8081,
5498 .name = "Micrel KSZ8081 or KSZ8091",
5499 .phy_id_mask = MICREL_PHY_ID_MASK,
5500 .flags = PHY_POLL_CABLE_TEST,
5501 /* PHY_BASIC_FEATURES */
5502 .driver_data = &ksz8081_type,
5503 .probe = kszphy_probe,
5504 .config_init = ksz8081_config_init,
5505 .soft_reset = genphy_soft_reset,
5506 .config_aneg = ksz8081_config_aneg,
5507 .read_status = ksz8081_read_status,
5508 .config_intr = kszphy_config_intr,
5509 .handle_interrupt = kszphy_handle_interrupt,
5510 .get_sset_count = kszphy_get_sset_count,
5511 .get_strings = kszphy_get_strings,
5512 .get_stats = kszphy_get_stats,
5513 .suspend = kszphy_suspend,
5514 .resume = kszphy_resume,
5515 .cable_test_start = ksz886x_cable_test_start,
5516 .cable_test_get_status = ksz886x_cable_test_get_status,
5517}, {
5518 .phy_id = PHY_ID_KSZ8061,
5519 .name = "Micrel KSZ8061",
5520 .phy_id_mask = MICREL_PHY_ID_MASK,
5521 /* PHY_BASIC_FEATURES */
5522 .probe = kszphy_probe,
5523 .config_init = ksz8061_config_init,
5524 .soft_reset = genphy_soft_reset,
5525 .config_intr = kszphy_config_intr,
5526 .handle_interrupt = kszphy_handle_interrupt,
5527 .suspend = ksz8061_suspend,
5528 .resume = ksz8061_resume,
5529}, {
5530 .phy_id = PHY_ID_KSZ9021,
5531 .phy_id_mask = 0x000ffffe,
5532 .name = "Micrel KSZ9021 Gigabit PHY",
5533 /* PHY_GBIT_FEATURES */
5534 .driver_data = &ksz9021_type,
5535 .probe = kszphy_probe,
5536 .get_features = ksz9031_get_features,
5537 .config_init = ksz9021_config_init,
5538 .config_intr = kszphy_config_intr,
5539 .handle_interrupt = kszphy_handle_interrupt,
5540 .get_sset_count = kszphy_get_sset_count,
5541 .get_strings = kszphy_get_strings,
5542 .get_stats = kszphy_get_stats,
5543 .suspend = kszphy_suspend,
5544 .resume = kszphy_resume,
5545 .read_mmd = genphy_read_mmd_unsupported,
5546 .write_mmd = genphy_write_mmd_unsupported,
5547}, {
5548 .phy_id = PHY_ID_KSZ9031,
5549 .phy_id_mask = MICREL_PHY_ID_MASK,
5550 .name = "Micrel KSZ9031 Gigabit PHY",
5551 .flags = PHY_POLL_CABLE_TEST,
5552 .driver_data = &ksz9021_type,
5553 .probe = kszphy_probe,
5554 .get_features = ksz9031_get_features,
5555 .config_init = ksz9031_config_init,
5556 .soft_reset = genphy_soft_reset,
5557 .read_status = ksz9031_read_status,
5558 .config_intr = kszphy_config_intr,
5559 .handle_interrupt = kszphy_handle_interrupt,
5560 .get_sset_count = kszphy_get_sset_count,
5561 .get_strings = kszphy_get_strings,
5562 .get_stats = kszphy_get_stats,
5563 .suspend = kszphy_suspend,
5564 .resume = kszphy_resume,
5565 .cable_test_start = ksz9x31_cable_test_start,
5566 .cable_test_get_status = ksz9x31_cable_test_get_status,
5567}, {
5568 .phy_id = PHY_ID_LAN8814,
5569 .phy_id_mask = MICREL_PHY_ID_MASK,
5570 .name = "Microchip INDY Gigabit Quad PHY",
5571 .flags = PHY_POLL_CABLE_TEST,
5572 .config_init = lan8814_config_init,
5573 .driver_data = &lan8814_type,
5574 .probe = lan8814_probe,
5575 .soft_reset = genphy_soft_reset,
5576 .read_status = ksz9031_read_status,
5577 .get_sset_count = kszphy_get_sset_count,
5578 .get_strings = kszphy_get_strings,
5579 .get_stats = kszphy_get_stats,
5580 .suspend = genphy_suspend,
5581 .resume = kszphy_resume,
5582 .config_intr = lan8814_config_intr,
5583 .handle_interrupt = lan8814_handle_interrupt,
5584 .cable_test_start = lan8814_cable_test_start,
5585 .cable_test_get_status = ksz886x_cable_test_get_status,
5586}, {
5587 .phy_id = PHY_ID_LAN8804,
5588 .phy_id_mask = MICREL_PHY_ID_MASK,
5589 .name = "Microchip LAN966X Gigabit PHY",
5590 .config_init = lan8804_config_init,
5591 .driver_data = &ksz9021_type,
5592 .probe = kszphy_probe,
5593 .soft_reset = genphy_soft_reset,
5594 .read_status = ksz9031_read_status,
5595 .get_sset_count = kszphy_get_sset_count,
5596 .get_strings = kszphy_get_strings,
5597 .get_stats = kszphy_get_stats,
5598 .suspend = lan8804_suspend,
5599 .resume = lan8804_resume,
5600 .config_intr = lan8804_config_intr,
5601 .handle_interrupt = lan8804_handle_interrupt,
5602}, {
5603 .phy_id = PHY_ID_LAN8841,
5604 .phy_id_mask = MICREL_PHY_ID_MASK,
5605 .name = "Microchip LAN8841 Gigabit PHY",
5606 .flags = PHY_POLL_CABLE_TEST,
5607 .driver_data = &lan8841_type,
5608 .config_init = lan8841_config_init,
5609 .probe = lan8841_probe,
5610 .soft_reset = genphy_soft_reset,
5611 .config_intr = lan8841_config_intr,
5612 .handle_interrupt = lan8841_handle_interrupt,
5613 .get_sset_count = kszphy_get_sset_count,
5614 .get_strings = kszphy_get_strings,
5615 .get_stats = kszphy_get_stats,
5616 .suspend = lan8841_suspend,
5617 .resume = lan8841_resume,
5618 .cable_test_start = lan8814_cable_test_start,
5619 .cable_test_get_status = ksz886x_cable_test_get_status,
5620}, {
5621 .phy_id = PHY_ID_KSZ9131,
5622 .phy_id_mask = MICREL_PHY_ID_MASK,
5623 .name = "Microchip KSZ9131 Gigabit PHY",
5624 /* PHY_GBIT_FEATURES */
5625 .flags = PHY_POLL_CABLE_TEST,
5626 .driver_data = &ksz9131_type,
5627 .probe = kszphy_probe,
5628 .soft_reset = genphy_soft_reset,
5629 .config_init = ksz9131_config_init,
5630 .config_intr = kszphy_config_intr,
5631 .config_aneg = ksz9131_config_aneg,
5632 .read_status = ksz9131_read_status,
5633 .handle_interrupt = kszphy_handle_interrupt,
5634 .get_sset_count = kszphy_get_sset_count,
5635 .get_strings = kszphy_get_strings,
5636 .get_stats = kszphy_get_stats,
5637 .suspend = kszphy_suspend,
5638 .resume = kszphy_resume,
5639 .cable_test_start = ksz9x31_cable_test_start,
5640 .cable_test_get_status = ksz9x31_cable_test_get_status,
5641 .get_features = ksz9477_get_features,
5642}, {
5643 .phy_id = PHY_ID_KSZ8873MLL,
5644 .phy_id_mask = MICREL_PHY_ID_MASK,
5645 .name = "Micrel KSZ8873MLL Switch",
5646 /* PHY_BASIC_FEATURES */
5647 .config_init = kszphy_config_init,
5648 .config_aneg = ksz8873mll_config_aneg,
5649 .read_status = ksz8873mll_read_status,
5650 .suspend = genphy_suspend,
5651 .resume = genphy_resume,
5652}, {
5653 .phy_id = PHY_ID_KSZ886X,
5654 .phy_id_mask = MICREL_PHY_ID_MASK,
5655 .name = "Micrel KSZ8851 Ethernet MAC or KSZ886X Switch",
5656 .driver_data = &ksz886x_type,
5657 /* PHY_BASIC_FEATURES */
5658 .flags = PHY_POLL_CABLE_TEST,
5659 .config_init = kszphy_config_init,
5660 .config_aneg = ksz886x_config_aneg,
5661 .read_status = ksz886x_read_status,
5662 .suspend = genphy_suspend,
5663 .resume = genphy_resume,
5664 .cable_test_start = ksz886x_cable_test_start,
5665 .cable_test_get_status = ksz886x_cable_test_get_status,
5666}, {
5667 .name = "Micrel KSZ87XX Switch",
5668 /* PHY_BASIC_FEATURES */
5669 .config_init = kszphy_config_init,
5670 .match_phy_device = ksz8795_match_phy_device,
5671 .suspend = genphy_suspend,
5672 .resume = genphy_resume,
5673}, {
5674 .phy_id = PHY_ID_KSZ9477,
5675 .phy_id_mask = MICREL_PHY_ID_MASK,
5676 .name = "Microchip KSZ9477",
5677 /* PHY_GBIT_FEATURES */
5678 .config_init = ksz9477_config_init,
5679 .config_intr = kszphy_config_intr,
5680 .handle_interrupt = kszphy_handle_interrupt,
5681 .suspend = genphy_suspend,
5682 .resume = ksz9477_resume,
5683 .get_features = ksz9477_get_features,
5684} };
5685
5686module_phy_driver(ksphy_driver);
5687
5688MODULE_DESCRIPTION("Micrel PHY driver");
5689MODULE_AUTHOR("David J. Choi");
5690MODULE_LICENSE("GPL");
5691
5692static struct mdio_device_id __maybe_unused micrel_tbl[] = {
5693 { PHY_ID_KSZ9021, 0x000ffffe },
5694 { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK },
5695 { PHY_ID_KSZ9131, MICREL_PHY_ID_MASK },
5696 { PHY_ID_KSZ8001, 0x00fffffc },
5697 { PHY_ID_KS8737, MICREL_PHY_ID_MASK },
5698 { PHY_ID_KSZ8021, 0x00ffffff },
5699 { PHY_ID_KSZ8031, 0x00ffffff },
5700 { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK },
5701 { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK },
5702 { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK },
5703 { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK },
5704 { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK },
5705 { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK },
5706 { PHY_ID_KSZ9477, MICREL_PHY_ID_MASK },
5707 { PHY_ID_LAN8814, MICREL_PHY_ID_MASK },
5708 { PHY_ID_LAN8804, MICREL_PHY_ID_MASK },
5709 { PHY_ID_LAN8841, MICREL_PHY_ID_MASK },
5710 { }
5711};
5712
5713MODULE_DEVICE_TABLE(mdio, micrel_tbl);
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * drivers/net/phy/micrel.c
4 *
5 * Driver for Micrel PHYs
6 *
7 * Author: David J. Choi
8 *
9 * Copyright (c) 2010-2013 Micrel, Inc.
10 * Copyright (c) 2014 Johan Hovold <johan@kernel.org>
11 *
12 * Support : Micrel Phys:
13 * Giga phys: ksz9021, ksz9031, ksz9131
14 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
15 * ksz8021, ksz8031, ksz8051,
16 * ksz8081, ksz8091,
17 * ksz8061,
18 * Switch : ksz8873, ksz886x
19 * ksz9477
20 */
21
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/phy.h>
25#include <linux/micrel_phy.h>
26#include <linux/of.h>
27#include <linux/clk.h>
28
29/* Operation Mode Strap Override */
30#define MII_KSZPHY_OMSO 0x16
31#define KSZPHY_OMSO_FACTORY_TEST BIT(15)
32#define KSZPHY_OMSO_B_CAST_OFF BIT(9)
33#define KSZPHY_OMSO_NAND_TREE_ON BIT(5)
34#define KSZPHY_OMSO_RMII_OVERRIDE BIT(1)
35#define KSZPHY_OMSO_MII_OVERRIDE BIT(0)
36
37/* general Interrupt control/status reg in vendor specific block. */
38#define MII_KSZPHY_INTCS 0x1B
39#define KSZPHY_INTCS_JABBER BIT(15)
40#define KSZPHY_INTCS_RECEIVE_ERR BIT(14)
41#define KSZPHY_INTCS_PAGE_RECEIVE BIT(13)
42#define KSZPHY_INTCS_PARELLEL BIT(12)
43#define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11)
44#define KSZPHY_INTCS_LINK_DOWN BIT(10)
45#define KSZPHY_INTCS_REMOTE_FAULT BIT(9)
46#define KSZPHY_INTCS_LINK_UP BIT(8)
47#define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\
48 KSZPHY_INTCS_LINK_DOWN)
49
50/* PHY Control 1 */
51#define MII_KSZPHY_CTRL_1 0x1e
52
53/* PHY Control 2 / PHY Control (if no PHY Control 1) */
54#define MII_KSZPHY_CTRL_2 0x1f
55#define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2
56/* bitmap of PHY register to set interrupt mode */
57#define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9)
58#define KSZPHY_RMII_REF_CLK_SEL BIT(7)
59
60/* Write/read to/from extended registers */
61#define MII_KSZPHY_EXTREG 0x0b
62#define KSZPHY_EXTREG_WRITE 0x8000
63
64#define MII_KSZPHY_EXTREG_WRITE 0x0c
65#define MII_KSZPHY_EXTREG_READ 0x0d
66
67/* Extended registers */
68#define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104
69#define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105
70#define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106
71
72#define PS_TO_REG 200
73
74struct kszphy_hw_stat {
75 const char *string;
76 u8 reg;
77 u8 bits;
78};
79
80static struct kszphy_hw_stat kszphy_hw_stats[] = {
81 { "phy_receive_errors", 21, 16},
82 { "phy_idle_errors", 10, 8 },
83};
84
85struct kszphy_type {
86 u32 led_mode_reg;
87 u16 interrupt_level_mask;
88 bool has_broadcast_disable;
89 bool has_nand_tree_disable;
90 bool has_rmii_ref_clk_sel;
91};
92
93struct kszphy_priv {
94 const struct kszphy_type *type;
95 int led_mode;
96 bool rmii_ref_clk_sel;
97 bool rmii_ref_clk_sel_val;
98 u64 stats[ARRAY_SIZE(kszphy_hw_stats)];
99};
100
101static const struct kszphy_type ksz8021_type = {
102 .led_mode_reg = MII_KSZPHY_CTRL_2,
103 .has_broadcast_disable = true,
104 .has_nand_tree_disable = true,
105 .has_rmii_ref_clk_sel = true,
106};
107
108static const struct kszphy_type ksz8041_type = {
109 .led_mode_reg = MII_KSZPHY_CTRL_1,
110};
111
112static const struct kszphy_type ksz8051_type = {
113 .led_mode_reg = MII_KSZPHY_CTRL_2,
114 .has_nand_tree_disable = true,
115};
116
117static const struct kszphy_type ksz8081_type = {
118 .led_mode_reg = MII_KSZPHY_CTRL_2,
119 .has_broadcast_disable = true,
120 .has_nand_tree_disable = true,
121 .has_rmii_ref_clk_sel = true,
122};
123
124static const struct kszphy_type ks8737_type = {
125 .interrupt_level_mask = BIT(14),
126};
127
128static const struct kszphy_type ksz9021_type = {
129 .interrupt_level_mask = BIT(14),
130};
131
132static int kszphy_extended_write(struct phy_device *phydev,
133 u32 regnum, u16 val)
134{
135 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
136 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
137}
138
139static int kszphy_extended_read(struct phy_device *phydev,
140 u32 regnum)
141{
142 phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
143 return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
144}
145
146static int kszphy_ack_interrupt(struct phy_device *phydev)
147{
148 /* bit[7..0] int status, which is a read and clear register. */
149 int rc;
150
151 rc = phy_read(phydev, MII_KSZPHY_INTCS);
152
153 return (rc < 0) ? rc : 0;
154}
155
156static int kszphy_config_intr(struct phy_device *phydev)
157{
158 const struct kszphy_type *type = phydev->drv->driver_data;
159 int temp;
160 u16 mask;
161
162 if (type && type->interrupt_level_mask)
163 mask = type->interrupt_level_mask;
164 else
165 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH;
166
167 /* set the interrupt pin active low */
168 temp = phy_read(phydev, MII_KSZPHY_CTRL);
169 if (temp < 0)
170 return temp;
171 temp &= ~mask;
172 phy_write(phydev, MII_KSZPHY_CTRL, temp);
173
174 /* enable / disable interrupts */
175 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
176 temp = KSZPHY_INTCS_ALL;
177 else
178 temp = 0;
179
180 return phy_write(phydev, MII_KSZPHY_INTCS, temp);
181}
182
183static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)
184{
185 int ctrl;
186
187 ctrl = phy_read(phydev, MII_KSZPHY_CTRL);
188 if (ctrl < 0)
189 return ctrl;
190
191 if (val)
192 ctrl |= KSZPHY_RMII_REF_CLK_SEL;
193 else
194 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL;
195
196 return phy_write(phydev, MII_KSZPHY_CTRL, ctrl);
197}
198
199static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val)
200{
201 int rc, temp, shift;
202
203 switch (reg) {
204 case MII_KSZPHY_CTRL_1:
205 shift = 14;
206 break;
207 case MII_KSZPHY_CTRL_2:
208 shift = 4;
209 break;
210 default:
211 return -EINVAL;
212 }
213
214 temp = phy_read(phydev, reg);
215 if (temp < 0) {
216 rc = temp;
217 goto out;
218 }
219
220 temp &= ~(3 << shift);
221 temp |= val << shift;
222 rc = phy_write(phydev, reg, temp);
223out:
224 if (rc < 0)
225 phydev_err(phydev, "failed to set led mode\n");
226
227 return rc;
228}
229
230/* Disable PHY address 0 as the broadcast address, so that it can be used as a
231 * unique (non-broadcast) address on a shared bus.
232 */
233static int kszphy_broadcast_disable(struct phy_device *phydev)
234{
235 int ret;
236
237 ret = phy_read(phydev, MII_KSZPHY_OMSO);
238 if (ret < 0)
239 goto out;
240
241 ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
242out:
243 if (ret)
244 phydev_err(phydev, "failed to disable broadcast address\n");
245
246 return ret;
247}
248
249static int kszphy_nand_tree_disable(struct phy_device *phydev)
250{
251 int ret;
252
253 ret = phy_read(phydev, MII_KSZPHY_OMSO);
254 if (ret < 0)
255 goto out;
256
257 if (!(ret & KSZPHY_OMSO_NAND_TREE_ON))
258 return 0;
259
260 ret = phy_write(phydev, MII_KSZPHY_OMSO,
261 ret & ~KSZPHY_OMSO_NAND_TREE_ON);
262out:
263 if (ret)
264 phydev_err(phydev, "failed to disable NAND tree mode\n");
265
266 return ret;
267}
268
269/* Some config bits need to be set again on resume, handle them here. */
270static int kszphy_config_reset(struct phy_device *phydev)
271{
272 struct kszphy_priv *priv = phydev->priv;
273 int ret;
274
275 if (priv->rmii_ref_clk_sel) {
276 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val);
277 if (ret) {
278 phydev_err(phydev,
279 "failed to set rmii reference clock\n");
280 return ret;
281 }
282 }
283
284 if (priv->led_mode >= 0)
285 kszphy_setup_led(phydev, priv->type->led_mode_reg, priv->led_mode);
286
287 return 0;
288}
289
290static int kszphy_config_init(struct phy_device *phydev)
291{
292 struct kszphy_priv *priv = phydev->priv;
293 const struct kszphy_type *type;
294
295 if (!priv)
296 return 0;
297
298 type = priv->type;
299
300 if (type->has_broadcast_disable)
301 kszphy_broadcast_disable(phydev);
302
303 if (type->has_nand_tree_disable)
304 kszphy_nand_tree_disable(phydev);
305
306 return kszphy_config_reset(phydev);
307}
308
309static int ksz8041_config_init(struct phy_device *phydev)
310{
311 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
312
313 struct device_node *of_node = phydev->mdio.dev.of_node;
314
315 /* Limit supported and advertised modes in fiber mode */
316 if (of_property_read_bool(of_node, "micrel,fiber-mode")) {
317 phydev->dev_flags |= MICREL_PHY_FXEN;
318 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask);
319 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask);
320
321 linkmode_and(phydev->supported, phydev->supported, mask);
322 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
323 phydev->supported);
324 linkmode_and(phydev->advertising, phydev->advertising, mask);
325 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
326 phydev->advertising);
327 phydev->autoneg = AUTONEG_DISABLE;
328 }
329
330 return kszphy_config_init(phydev);
331}
332
333static int ksz8041_config_aneg(struct phy_device *phydev)
334{
335 /* Skip auto-negotiation in fiber mode */
336 if (phydev->dev_flags & MICREL_PHY_FXEN) {
337 phydev->speed = SPEED_100;
338 return 0;
339 }
340
341 return genphy_config_aneg(phydev);
342}
343
344static int ksz8051_ksz8795_match_phy_device(struct phy_device *phydev,
345 const u32 ksz_phy_id)
346{
347 int ret;
348
349 if ((phydev->phy_id & MICREL_PHY_ID_MASK) != ksz_phy_id)
350 return 0;
351
352 ret = phy_read(phydev, MII_BMSR);
353 if (ret < 0)
354 return ret;
355
356 /* KSZ8051 PHY and KSZ8794/KSZ8795/KSZ8765 switch share the same
357 * exact PHY ID. However, they can be told apart by the extended
358 * capability registers presence. The KSZ8051 PHY has them while
359 * the switch does not.
360 */
361 ret &= BMSR_ERCAP;
362 if (ksz_phy_id == PHY_ID_KSZ8051)
363 return ret;
364 else
365 return !ret;
366}
367
368static int ksz8051_match_phy_device(struct phy_device *phydev)
369{
370 return ksz8051_ksz8795_match_phy_device(phydev, PHY_ID_KSZ8051);
371}
372
373static int ksz8081_config_init(struct phy_device *phydev)
374{
375 /* KSZPHY_OMSO_FACTORY_TEST is set at de-assertion of the reset line
376 * based on the RXER (KSZ8081RNA/RND) or TXC (KSZ8081MNX/RNB) pin. If a
377 * pull-down is missing, the factory test mode should be cleared by
378 * manually writing a 0.
379 */
380 phy_clear_bits(phydev, MII_KSZPHY_OMSO, KSZPHY_OMSO_FACTORY_TEST);
381
382 return kszphy_config_init(phydev);
383}
384
385static int ksz8061_config_init(struct phy_device *phydev)
386{
387 int ret;
388
389 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, 0xB61A);
390 if (ret)
391 return ret;
392
393 return kszphy_config_init(phydev);
394}
395
396static int ksz8795_match_phy_device(struct phy_device *phydev)
397{
398 return ksz8051_ksz8795_match_phy_device(phydev, PHY_ID_KSZ87XX);
399}
400
401static int ksz9021_load_values_from_of(struct phy_device *phydev,
402 const struct device_node *of_node,
403 u16 reg,
404 const char *field1, const char *field2,
405 const char *field3, const char *field4)
406{
407 int val1 = -1;
408 int val2 = -2;
409 int val3 = -3;
410 int val4 = -4;
411 int newval;
412 int matches = 0;
413
414 if (!of_property_read_u32(of_node, field1, &val1))
415 matches++;
416
417 if (!of_property_read_u32(of_node, field2, &val2))
418 matches++;
419
420 if (!of_property_read_u32(of_node, field3, &val3))
421 matches++;
422
423 if (!of_property_read_u32(of_node, field4, &val4))
424 matches++;
425
426 if (!matches)
427 return 0;
428
429 if (matches < 4)
430 newval = kszphy_extended_read(phydev, reg);
431 else
432 newval = 0;
433
434 if (val1 != -1)
435 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
436
437 if (val2 != -2)
438 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
439
440 if (val3 != -3)
441 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
442
443 if (val4 != -4)
444 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
445
446 return kszphy_extended_write(phydev, reg, newval);
447}
448
449static int ksz9021_config_init(struct phy_device *phydev)
450{
451 const struct device *dev = &phydev->mdio.dev;
452 const struct device_node *of_node = dev->of_node;
453 const struct device *dev_walker;
454
455 /* The Micrel driver has a deprecated option to place phy OF
456 * properties in the MAC node. Walk up the tree of devices to
457 * find a device with an OF node.
458 */
459 dev_walker = &phydev->mdio.dev;
460 do {
461 of_node = dev_walker->of_node;
462 dev_walker = dev_walker->parent;
463
464 } while (!of_node && dev_walker);
465
466 if (of_node) {
467 ksz9021_load_values_from_of(phydev, of_node,
468 MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
469 "txen-skew-ps", "txc-skew-ps",
470 "rxdv-skew-ps", "rxc-skew-ps");
471 ksz9021_load_values_from_of(phydev, of_node,
472 MII_KSZPHY_RX_DATA_PAD_SKEW,
473 "rxd0-skew-ps", "rxd1-skew-ps",
474 "rxd2-skew-ps", "rxd3-skew-ps");
475 ksz9021_load_values_from_of(phydev, of_node,
476 MII_KSZPHY_TX_DATA_PAD_SKEW,
477 "txd0-skew-ps", "txd1-skew-ps",
478 "txd2-skew-ps", "txd3-skew-ps");
479 }
480 return 0;
481}
482
483#define KSZ9031_PS_TO_REG 60
484
485/* Extended registers */
486/* MMD Address 0x0 */
487#define MII_KSZ9031RN_FLP_BURST_TX_LO 3
488#define MII_KSZ9031RN_FLP_BURST_TX_HI 4
489
490/* MMD Address 0x2 */
491#define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
492#define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
493#define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6
494#define MII_KSZ9031RN_CLK_PAD_SKEW 8
495
496/* MMD Address 0x1C */
497#define MII_KSZ9031RN_EDPD 0x23
498#define MII_KSZ9031RN_EDPD_ENABLE BIT(0)
499
500static int ksz9031_of_load_skew_values(struct phy_device *phydev,
501 const struct device_node *of_node,
502 u16 reg, size_t field_sz,
503 const char *field[], u8 numfields)
504{
505 int val[4] = {-1, -2, -3, -4};
506 int matches = 0;
507 u16 mask;
508 u16 maxval;
509 u16 newval;
510 int i;
511
512 for (i = 0; i < numfields; i++)
513 if (!of_property_read_u32(of_node, field[i], val + i))
514 matches++;
515
516 if (!matches)
517 return 0;
518
519 if (matches < numfields)
520 newval = phy_read_mmd(phydev, 2, reg);
521 else
522 newval = 0;
523
524 maxval = (field_sz == 4) ? 0xf : 0x1f;
525 for (i = 0; i < numfields; i++)
526 if (val[i] != -(i + 1)) {
527 mask = 0xffff;
528 mask ^= maxval << (field_sz * i);
529 newval = (newval & mask) |
530 (((val[i] / KSZ9031_PS_TO_REG) & maxval)
531 << (field_sz * i));
532 }
533
534 return phy_write_mmd(phydev, 2, reg, newval);
535}
536
537/* Center KSZ9031RNX FLP timing at 16ms. */
538static int ksz9031_center_flp_timing(struct phy_device *phydev)
539{
540 int result;
541
542 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_HI,
543 0x0006);
544 if (result)
545 return result;
546
547 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_LO,
548 0x1A80);
549 if (result)
550 return result;
551
552 return genphy_restart_aneg(phydev);
553}
554
555/* Enable energy-detect power-down mode */
556static int ksz9031_enable_edpd(struct phy_device *phydev)
557{
558 int reg;
559
560 reg = phy_read_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD);
561 if (reg < 0)
562 return reg;
563 return phy_write_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD,
564 reg | MII_KSZ9031RN_EDPD_ENABLE);
565}
566
567static int ksz9031_config_init(struct phy_device *phydev)
568{
569 const struct device *dev = &phydev->mdio.dev;
570 const struct device_node *of_node = dev->of_node;
571 static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
572 static const char *rx_data_skews[4] = {
573 "rxd0-skew-ps", "rxd1-skew-ps",
574 "rxd2-skew-ps", "rxd3-skew-ps"
575 };
576 static const char *tx_data_skews[4] = {
577 "txd0-skew-ps", "txd1-skew-ps",
578 "txd2-skew-ps", "txd3-skew-ps"
579 };
580 static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
581 const struct device *dev_walker;
582 int result;
583
584 result = ksz9031_enable_edpd(phydev);
585 if (result < 0)
586 return result;
587
588 /* The Micrel driver has a deprecated option to place phy OF
589 * properties in the MAC node. Walk up the tree of devices to
590 * find a device with an OF node.
591 */
592 dev_walker = &phydev->mdio.dev;
593 do {
594 of_node = dev_walker->of_node;
595 dev_walker = dev_walker->parent;
596 } while (!of_node && dev_walker);
597
598 if (of_node) {
599 ksz9031_of_load_skew_values(phydev, of_node,
600 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
601 clk_skews, 2);
602
603 ksz9031_of_load_skew_values(phydev, of_node,
604 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
605 control_skews, 2);
606
607 ksz9031_of_load_skew_values(phydev, of_node,
608 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
609 rx_data_skews, 4);
610
611 ksz9031_of_load_skew_values(phydev, of_node,
612 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
613 tx_data_skews, 4);
614
615 /* Silicon Errata Sheet (DS80000691D or DS80000692D):
616 * When the device links in the 1000BASE-T slave mode only,
617 * the optional 125MHz reference output clock (CLK125_NDO)
618 * has wide duty cycle variation.
619 *
620 * The optional CLK125_NDO clock does not meet the RGMII
621 * 45/55 percent (min/max) duty cycle requirement and therefore
622 * cannot be used directly by the MAC side for clocking
623 * applications that have setup/hold time requirements on
624 * rising and falling clock edges.
625 *
626 * Workaround:
627 * Force the phy to be the master to receive a stable clock
628 * which meets the duty cycle requirement.
629 */
630 if (of_property_read_bool(of_node, "micrel,force-master")) {
631 result = phy_read(phydev, MII_CTRL1000);
632 if (result < 0)
633 goto err_force_master;
634
635 /* enable master mode, config & prefer master */
636 result |= CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER;
637 result = phy_write(phydev, MII_CTRL1000, result);
638 if (result < 0)
639 goto err_force_master;
640 }
641 }
642
643 return ksz9031_center_flp_timing(phydev);
644
645err_force_master:
646 phydev_err(phydev, "failed to force the phy to master mode\n");
647 return result;
648}
649
650#define KSZ9131_SKEW_5BIT_MAX 2400
651#define KSZ9131_SKEW_4BIT_MAX 800
652#define KSZ9131_OFFSET 700
653#define KSZ9131_STEP 100
654
655static int ksz9131_of_load_skew_values(struct phy_device *phydev,
656 struct device_node *of_node,
657 u16 reg, size_t field_sz,
658 char *field[], u8 numfields)
659{
660 int val[4] = {-(1 + KSZ9131_OFFSET), -(2 + KSZ9131_OFFSET),
661 -(3 + KSZ9131_OFFSET), -(4 + KSZ9131_OFFSET)};
662 int skewval, skewmax = 0;
663 int matches = 0;
664 u16 maxval;
665 u16 newval;
666 u16 mask;
667 int i;
668
669 /* psec properties in dts should mean x pico seconds */
670 if (field_sz == 5)
671 skewmax = KSZ9131_SKEW_5BIT_MAX;
672 else
673 skewmax = KSZ9131_SKEW_4BIT_MAX;
674
675 for (i = 0; i < numfields; i++)
676 if (!of_property_read_s32(of_node, field[i], &skewval)) {
677 if (skewval < -KSZ9131_OFFSET)
678 skewval = -KSZ9131_OFFSET;
679 else if (skewval > skewmax)
680 skewval = skewmax;
681
682 val[i] = skewval + KSZ9131_OFFSET;
683 matches++;
684 }
685
686 if (!matches)
687 return 0;
688
689 if (matches < numfields)
690 newval = phy_read_mmd(phydev, 2, reg);
691 else
692 newval = 0;
693
694 maxval = (field_sz == 4) ? 0xf : 0x1f;
695 for (i = 0; i < numfields; i++)
696 if (val[i] != -(i + 1 + KSZ9131_OFFSET)) {
697 mask = 0xffff;
698 mask ^= maxval << (field_sz * i);
699 newval = (newval & mask) |
700 (((val[i] / KSZ9131_STEP) & maxval)
701 << (field_sz * i));
702 }
703
704 return phy_write_mmd(phydev, 2, reg, newval);
705}
706
707static int ksz9131_config_init(struct phy_device *phydev)
708{
709 const struct device *dev = &phydev->mdio.dev;
710 struct device_node *of_node = dev->of_node;
711 char *clk_skews[2] = {"rxc-skew-psec", "txc-skew-psec"};
712 char *rx_data_skews[4] = {
713 "rxd0-skew-psec", "rxd1-skew-psec",
714 "rxd2-skew-psec", "rxd3-skew-psec"
715 };
716 char *tx_data_skews[4] = {
717 "txd0-skew-psec", "txd1-skew-psec",
718 "txd2-skew-psec", "txd3-skew-psec"
719 };
720 char *control_skews[2] = {"txen-skew-psec", "rxdv-skew-psec"};
721 const struct device *dev_walker;
722 int ret;
723
724 dev_walker = &phydev->mdio.dev;
725 do {
726 of_node = dev_walker->of_node;
727 dev_walker = dev_walker->parent;
728 } while (!of_node && dev_walker);
729
730 if (!of_node)
731 return 0;
732
733 ret = ksz9131_of_load_skew_values(phydev, of_node,
734 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
735 clk_skews, 2);
736 if (ret < 0)
737 return ret;
738
739 ret = ksz9131_of_load_skew_values(phydev, of_node,
740 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
741 control_skews, 2);
742 if (ret < 0)
743 return ret;
744
745 ret = ksz9131_of_load_skew_values(phydev, of_node,
746 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
747 rx_data_skews, 4);
748 if (ret < 0)
749 return ret;
750
751 ret = ksz9131_of_load_skew_values(phydev, of_node,
752 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
753 tx_data_skews, 4);
754 if (ret < 0)
755 return ret;
756
757 return 0;
758}
759
760#define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
761#define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6)
762#define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4)
763static int ksz8873mll_read_status(struct phy_device *phydev)
764{
765 int regval;
766
767 /* dummy read */
768 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
769
770 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
771
772 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
773 phydev->duplex = DUPLEX_HALF;
774 else
775 phydev->duplex = DUPLEX_FULL;
776
777 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
778 phydev->speed = SPEED_10;
779 else
780 phydev->speed = SPEED_100;
781
782 phydev->link = 1;
783 phydev->pause = phydev->asym_pause = 0;
784
785 return 0;
786}
787
788static int ksz9031_get_features(struct phy_device *phydev)
789{
790 int ret;
791
792 ret = genphy_read_abilities(phydev);
793 if (ret < 0)
794 return ret;
795
796 /* Silicon Errata Sheet (DS80000691D or DS80000692D):
797 * Whenever the device's Asymmetric Pause capability is set to 1,
798 * link-up may fail after a link-up to link-down transition.
799 *
800 * The Errata Sheet is for ksz9031, but ksz9021 has the same issue
801 *
802 * Workaround:
803 * Do not enable the Asymmetric Pause capability bit.
804 */
805 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported);
806
807 /* We force setting the Pause capability as the core will force the
808 * Asymmetric Pause capability to 1 otherwise.
809 */
810 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported);
811
812 return 0;
813}
814
815static int ksz9031_read_status(struct phy_device *phydev)
816{
817 int err;
818 int regval;
819
820 err = genphy_read_status(phydev);
821 if (err)
822 return err;
823
824 /* Make sure the PHY is not broken. Read idle error count,
825 * and reset the PHY if it is maxed out.
826 */
827 regval = phy_read(phydev, MII_STAT1000);
828 if ((regval & 0xFF) == 0xFF) {
829 phy_init_hw(phydev);
830 phydev->link = 0;
831 if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev))
832 phydev->drv->config_intr(phydev);
833 return genphy_config_aneg(phydev);
834 }
835
836 return 0;
837}
838
839static int ksz8873mll_config_aneg(struct phy_device *phydev)
840{
841 return 0;
842}
843
844static int kszphy_get_sset_count(struct phy_device *phydev)
845{
846 return ARRAY_SIZE(kszphy_hw_stats);
847}
848
849static void kszphy_get_strings(struct phy_device *phydev, u8 *data)
850{
851 int i;
852
853 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) {
854 strlcpy(data + i * ETH_GSTRING_LEN,
855 kszphy_hw_stats[i].string, ETH_GSTRING_LEN);
856 }
857}
858
859static u64 kszphy_get_stat(struct phy_device *phydev, int i)
860{
861 struct kszphy_hw_stat stat = kszphy_hw_stats[i];
862 struct kszphy_priv *priv = phydev->priv;
863 int val;
864 u64 ret;
865
866 val = phy_read(phydev, stat.reg);
867 if (val < 0) {
868 ret = U64_MAX;
869 } else {
870 val = val & ((1 << stat.bits) - 1);
871 priv->stats[i] += val;
872 ret = priv->stats[i];
873 }
874
875 return ret;
876}
877
878static void kszphy_get_stats(struct phy_device *phydev,
879 struct ethtool_stats *stats, u64 *data)
880{
881 int i;
882
883 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++)
884 data[i] = kszphy_get_stat(phydev, i);
885}
886
887static int kszphy_suspend(struct phy_device *phydev)
888{
889 /* Disable PHY Interrupts */
890 if (phy_interrupt_is_valid(phydev)) {
891 phydev->interrupts = PHY_INTERRUPT_DISABLED;
892 if (phydev->drv->config_intr)
893 phydev->drv->config_intr(phydev);
894 }
895
896 return genphy_suspend(phydev);
897}
898
899static int kszphy_resume(struct phy_device *phydev)
900{
901 int ret;
902
903 genphy_resume(phydev);
904
905 ret = kszphy_config_reset(phydev);
906 if (ret)
907 return ret;
908
909 /* Enable PHY Interrupts */
910 if (phy_interrupt_is_valid(phydev)) {
911 phydev->interrupts = PHY_INTERRUPT_ENABLED;
912 if (phydev->drv->config_intr)
913 phydev->drv->config_intr(phydev);
914 }
915
916 return 0;
917}
918
919static int kszphy_probe(struct phy_device *phydev)
920{
921 const struct kszphy_type *type = phydev->drv->driver_data;
922 const struct device_node *np = phydev->mdio.dev.of_node;
923 struct kszphy_priv *priv;
924 struct clk *clk;
925 int ret;
926
927 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
928 if (!priv)
929 return -ENOMEM;
930
931 phydev->priv = priv;
932
933 priv->type = type;
934
935 if (type->led_mode_reg) {
936 ret = of_property_read_u32(np, "micrel,led-mode",
937 &priv->led_mode);
938 if (ret)
939 priv->led_mode = -1;
940
941 if (priv->led_mode > 3) {
942 phydev_err(phydev, "invalid led mode: 0x%02x\n",
943 priv->led_mode);
944 priv->led_mode = -1;
945 }
946 } else {
947 priv->led_mode = -1;
948 }
949
950 clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref");
951 /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */
952 if (!IS_ERR_OR_NULL(clk)) {
953 unsigned long rate = clk_get_rate(clk);
954 bool rmii_ref_clk_sel_25_mhz;
955
956 priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel;
957 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np,
958 "micrel,rmii-reference-clock-select-25-mhz");
959
960 if (rate > 24500000 && rate < 25500000) {
961 priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz;
962 } else if (rate > 49500000 && rate < 50500000) {
963 priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz;
964 } else {
965 phydev_err(phydev, "Clock rate out of range: %ld\n",
966 rate);
967 return -EINVAL;
968 }
969 }
970
971 /* Support legacy board-file configuration */
972 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
973 priv->rmii_ref_clk_sel = true;
974 priv->rmii_ref_clk_sel_val = true;
975 }
976
977 return 0;
978}
979
980static struct phy_driver ksphy_driver[] = {
981{
982 .phy_id = PHY_ID_KS8737,
983 .phy_id_mask = MICREL_PHY_ID_MASK,
984 .name = "Micrel KS8737",
985 /* PHY_BASIC_FEATURES */
986 .driver_data = &ks8737_type,
987 .config_init = kszphy_config_init,
988 .ack_interrupt = kszphy_ack_interrupt,
989 .config_intr = kszphy_config_intr,
990 .suspend = genphy_suspend,
991 .resume = genphy_resume,
992}, {
993 .phy_id = PHY_ID_KSZ8021,
994 .phy_id_mask = 0x00ffffff,
995 .name = "Micrel KSZ8021 or KSZ8031",
996 /* PHY_BASIC_FEATURES */
997 .driver_data = &ksz8021_type,
998 .probe = kszphy_probe,
999 .config_init = kszphy_config_init,
1000 .ack_interrupt = kszphy_ack_interrupt,
1001 .config_intr = kszphy_config_intr,
1002 .get_sset_count = kszphy_get_sset_count,
1003 .get_strings = kszphy_get_strings,
1004 .get_stats = kszphy_get_stats,
1005 .suspend = genphy_suspend,
1006 .resume = genphy_resume,
1007}, {
1008 .phy_id = PHY_ID_KSZ8031,
1009 .phy_id_mask = 0x00ffffff,
1010 .name = "Micrel KSZ8031",
1011 /* PHY_BASIC_FEATURES */
1012 .driver_data = &ksz8021_type,
1013 .probe = kszphy_probe,
1014 .config_init = kszphy_config_init,
1015 .ack_interrupt = kszphy_ack_interrupt,
1016 .config_intr = kszphy_config_intr,
1017 .get_sset_count = kszphy_get_sset_count,
1018 .get_strings = kszphy_get_strings,
1019 .get_stats = kszphy_get_stats,
1020 .suspend = genphy_suspend,
1021 .resume = genphy_resume,
1022}, {
1023 .phy_id = PHY_ID_KSZ8041,
1024 .phy_id_mask = MICREL_PHY_ID_MASK,
1025 .name = "Micrel KSZ8041",
1026 /* PHY_BASIC_FEATURES */
1027 .driver_data = &ksz8041_type,
1028 .probe = kszphy_probe,
1029 .config_init = ksz8041_config_init,
1030 .config_aneg = ksz8041_config_aneg,
1031 .ack_interrupt = kszphy_ack_interrupt,
1032 .config_intr = kszphy_config_intr,
1033 .get_sset_count = kszphy_get_sset_count,
1034 .get_strings = kszphy_get_strings,
1035 .get_stats = kszphy_get_stats,
1036 .suspend = genphy_suspend,
1037 .resume = genphy_resume,
1038}, {
1039 .phy_id = PHY_ID_KSZ8041RNLI,
1040 .phy_id_mask = MICREL_PHY_ID_MASK,
1041 .name = "Micrel KSZ8041RNLI",
1042 /* PHY_BASIC_FEATURES */
1043 .driver_data = &ksz8041_type,
1044 .probe = kszphy_probe,
1045 .config_init = kszphy_config_init,
1046 .ack_interrupt = kszphy_ack_interrupt,
1047 .config_intr = kszphy_config_intr,
1048 .get_sset_count = kszphy_get_sset_count,
1049 .get_strings = kszphy_get_strings,
1050 .get_stats = kszphy_get_stats,
1051 .suspend = genphy_suspend,
1052 .resume = genphy_resume,
1053}, {
1054 .name = "Micrel KSZ8051",
1055 /* PHY_BASIC_FEATURES */
1056 .driver_data = &ksz8051_type,
1057 .probe = kszphy_probe,
1058 .config_init = kszphy_config_init,
1059 .ack_interrupt = kszphy_ack_interrupt,
1060 .config_intr = kszphy_config_intr,
1061 .get_sset_count = kszphy_get_sset_count,
1062 .get_strings = kszphy_get_strings,
1063 .get_stats = kszphy_get_stats,
1064 .match_phy_device = ksz8051_match_phy_device,
1065 .suspend = genphy_suspend,
1066 .resume = genphy_resume,
1067}, {
1068 .phy_id = PHY_ID_KSZ8001,
1069 .name = "Micrel KSZ8001 or KS8721",
1070 .phy_id_mask = 0x00fffffc,
1071 /* PHY_BASIC_FEATURES */
1072 .driver_data = &ksz8041_type,
1073 .probe = kszphy_probe,
1074 .config_init = kszphy_config_init,
1075 .ack_interrupt = kszphy_ack_interrupt,
1076 .config_intr = kszphy_config_intr,
1077 .get_sset_count = kszphy_get_sset_count,
1078 .get_strings = kszphy_get_strings,
1079 .get_stats = kszphy_get_stats,
1080 .suspend = genphy_suspend,
1081 .resume = genphy_resume,
1082}, {
1083 .phy_id = PHY_ID_KSZ8081,
1084 .name = "Micrel KSZ8081 or KSZ8091",
1085 .phy_id_mask = MICREL_PHY_ID_MASK,
1086 /* PHY_BASIC_FEATURES */
1087 .driver_data = &ksz8081_type,
1088 .probe = kszphy_probe,
1089 .config_init = ksz8081_config_init,
1090 .ack_interrupt = kszphy_ack_interrupt,
1091 .config_intr = kszphy_config_intr,
1092 .get_sset_count = kszphy_get_sset_count,
1093 .get_strings = kszphy_get_strings,
1094 .get_stats = kszphy_get_stats,
1095 .suspend = kszphy_suspend,
1096 .resume = kszphy_resume,
1097}, {
1098 .phy_id = PHY_ID_KSZ8061,
1099 .name = "Micrel KSZ8061",
1100 .phy_id_mask = MICREL_PHY_ID_MASK,
1101 /* PHY_BASIC_FEATURES */
1102 .config_init = ksz8061_config_init,
1103 .ack_interrupt = kszphy_ack_interrupt,
1104 .config_intr = kszphy_config_intr,
1105 .suspend = genphy_suspend,
1106 .resume = genphy_resume,
1107}, {
1108 .phy_id = PHY_ID_KSZ9021,
1109 .phy_id_mask = 0x000ffffe,
1110 .name = "Micrel KSZ9021 Gigabit PHY",
1111 /* PHY_GBIT_FEATURES */
1112 .driver_data = &ksz9021_type,
1113 .probe = kszphy_probe,
1114 .get_features = ksz9031_get_features,
1115 .config_init = ksz9021_config_init,
1116 .ack_interrupt = kszphy_ack_interrupt,
1117 .config_intr = kszphy_config_intr,
1118 .get_sset_count = kszphy_get_sset_count,
1119 .get_strings = kszphy_get_strings,
1120 .get_stats = kszphy_get_stats,
1121 .suspend = genphy_suspend,
1122 .resume = genphy_resume,
1123 .read_mmd = genphy_read_mmd_unsupported,
1124 .write_mmd = genphy_write_mmd_unsupported,
1125}, {
1126 .phy_id = PHY_ID_KSZ9031,
1127 .phy_id_mask = MICREL_PHY_ID_MASK,
1128 .name = "Micrel KSZ9031 Gigabit PHY",
1129 .driver_data = &ksz9021_type,
1130 .probe = kszphy_probe,
1131 .get_features = ksz9031_get_features,
1132 .config_init = ksz9031_config_init,
1133 .soft_reset = genphy_soft_reset,
1134 .read_status = ksz9031_read_status,
1135 .ack_interrupt = kszphy_ack_interrupt,
1136 .config_intr = kszphy_config_intr,
1137 .get_sset_count = kszphy_get_sset_count,
1138 .get_strings = kszphy_get_strings,
1139 .get_stats = kszphy_get_stats,
1140 .suspend = genphy_suspend,
1141 .resume = kszphy_resume,
1142}, {
1143 .phy_id = PHY_ID_KSZ9131,
1144 .phy_id_mask = MICREL_PHY_ID_MASK,
1145 .name = "Microchip KSZ9131 Gigabit PHY",
1146 /* PHY_GBIT_FEATURES */
1147 .driver_data = &ksz9021_type,
1148 .probe = kszphy_probe,
1149 .config_init = ksz9131_config_init,
1150 .read_status = ksz9031_read_status,
1151 .ack_interrupt = kszphy_ack_interrupt,
1152 .config_intr = kszphy_config_intr,
1153 .get_sset_count = kszphy_get_sset_count,
1154 .get_strings = kszphy_get_strings,
1155 .get_stats = kszphy_get_stats,
1156 .suspend = genphy_suspend,
1157 .resume = kszphy_resume,
1158}, {
1159 .phy_id = PHY_ID_KSZ8873MLL,
1160 .phy_id_mask = MICREL_PHY_ID_MASK,
1161 .name = "Micrel KSZ8873MLL Switch",
1162 /* PHY_BASIC_FEATURES */
1163 .config_init = kszphy_config_init,
1164 .config_aneg = ksz8873mll_config_aneg,
1165 .read_status = ksz8873mll_read_status,
1166 .suspend = genphy_suspend,
1167 .resume = genphy_resume,
1168}, {
1169 .phy_id = PHY_ID_KSZ886X,
1170 .phy_id_mask = MICREL_PHY_ID_MASK,
1171 .name = "Micrel KSZ886X Switch",
1172 /* PHY_BASIC_FEATURES */
1173 .config_init = kszphy_config_init,
1174 .suspend = genphy_suspend,
1175 .resume = genphy_resume,
1176}, {
1177 .name = "Micrel KSZ87XX Switch",
1178 /* PHY_BASIC_FEATURES */
1179 .config_init = kszphy_config_init,
1180 .config_aneg = ksz8873mll_config_aneg,
1181 .read_status = ksz8873mll_read_status,
1182 .match_phy_device = ksz8795_match_phy_device,
1183 .suspend = genphy_suspend,
1184 .resume = genphy_resume,
1185}, {
1186 .phy_id = PHY_ID_KSZ9477,
1187 .phy_id_mask = MICREL_PHY_ID_MASK,
1188 .name = "Microchip KSZ9477",
1189 /* PHY_GBIT_FEATURES */
1190 .config_init = kszphy_config_init,
1191 .suspend = genphy_suspend,
1192 .resume = genphy_resume,
1193} };
1194
1195module_phy_driver(ksphy_driver);
1196
1197MODULE_DESCRIPTION("Micrel PHY driver");
1198MODULE_AUTHOR("David J. Choi");
1199MODULE_LICENSE("GPL");
1200
1201static struct mdio_device_id __maybe_unused micrel_tbl[] = {
1202 { PHY_ID_KSZ9021, 0x000ffffe },
1203 { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK },
1204 { PHY_ID_KSZ9131, MICREL_PHY_ID_MASK },
1205 { PHY_ID_KSZ8001, 0x00fffffc },
1206 { PHY_ID_KS8737, MICREL_PHY_ID_MASK },
1207 { PHY_ID_KSZ8021, 0x00ffffff },
1208 { PHY_ID_KSZ8031, 0x00ffffff },
1209 { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK },
1210 { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK },
1211 { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK },
1212 { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK },
1213 { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK },
1214 { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK },
1215 { }
1216};
1217
1218MODULE_DEVICE_TABLE(mdio, micrel_tbl);