1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 * Copyright (c) 2020 Synopsys, Inc. and/or its affiliates.
  4 * Synopsys DesignWare XPCS helpers
  5 *
  6 * Author: Jose Abreu <Jose.Abreu@synopsys.com>
  7 */
  8
  9#include <linux/bits.h>
 10#include <linux/pcs/pcs-xpcs.h>
 11
 12/* Vendor regs access */
 13#define DW_VENDOR			BIT(15)
 14
 15/* VR_XS_PCS */
 16#define DW_USXGMII_RST			BIT(10)
 17#define DW_USXGMII_EN			BIT(9)
 18#define DW_VR_XS_PCS_DIG_CTRL1		0x0000
 19#define DW_VR_RST			BIT(15)
 20#define DW_EN_VSMMD1			BIT(13)
 21#define DW_CL37_BP			BIT(12)
 22#define DW_VR_XS_PCS_DIG_STS		0x0010
 23#define DW_RXFIFO_ERR			GENMASK(6, 5)
 24#define DW_PSEQ_ST			GENMASK(4, 2)
 25#define DW_PSEQ_ST_GOOD			FIELD_PREP(GENMASK(4, 2), 0x4)
 26
 27/* SR_MII */
 28#define DW_USXGMII_FULL			BIT(8)
 29#define DW_USXGMII_SS_MASK		(BIT(13) | BIT(6) | BIT(5))
 30#define DW_USXGMII_10000		(BIT(13) | BIT(6))
 31#define DW_USXGMII_5000			(BIT(13) | BIT(5))
 32#define DW_USXGMII_2500			(BIT(5))
 33#define DW_USXGMII_1000			(BIT(6))
 34#define DW_USXGMII_100			(BIT(13))
 35#define DW_USXGMII_10			(0)
 36
 37/* SR_AN */
 38#define DW_SR_AN_ADV1			0x10
 39#define DW_SR_AN_ADV2			0x11
 40#define DW_SR_AN_ADV3			0x12
 41
 42/* Clause 73 Defines */
 43/* AN_LP_ABL1 */
 44#define DW_C73_PAUSE			BIT(10)
 45#define DW_C73_ASYM_PAUSE		BIT(11)
 46#define DW_C73_AN_ADV_SF		0x1
 47/* AN_LP_ABL2 */
 48#define DW_C73_1000KX			BIT(5)
 49#define DW_C73_10000KX4			BIT(6)
 50#define DW_C73_10000KR			BIT(7)
 51/* AN_LP_ABL3 */
 52#define DW_C73_2500KX			BIT(0)
 53#define DW_C73_5000KR			BIT(1)
 54
 55/* Clause 37 Defines */
 56/* VR MII MMD registers offsets */
 57#define DW_VR_MII_DIG_CTRL1		0x8000
 58#define DW_VR_MII_AN_CTRL		0x8001
 59#define DW_VR_MII_AN_INTR_STS		0x8002
 60/* EEE Mode Control Register */
 61#define DW_VR_MII_EEE_MCTRL0		0x8006
 62#define DW_VR_MII_EEE_MCTRL1		0x800b
 63#define DW_VR_MII_DIG_CTRL2		0x80e1
 64
 65/* VR_MII_DIG_CTRL1 */
 66#define DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW		BIT(9)
 67#define DW_VR_MII_DIG_CTRL1_2G5_EN		BIT(2)
 68#define DW_VR_MII_DIG_CTRL1_PHY_MODE_CTRL	BIT(0)
 69
 70/* VR_MII_DIG_CTRL2 */
 71#define DW_VR_MII_DIG_CTRL2_TX_POL_INV		BIT(4)
 72#define DW_VR_MII_DIG_CTRL2_RX_POL_INV		BIT(0)
 73
 74/* VR_MII_AN_CTRL */
 75#define DW_VR_MII_AN_CTRL_8BIT			BIT(8)
 76#define DW_VR_MII_TX_CONFIG_MASK		BIT(3)
 77#define DW_VR_MII_TX_CONFIG_PHY_SIDE_SGMII	0x1
 78#define DW_VR_MII_TX_CONFIG_MAC_SIDE_SGMII	0x0
 79#define DW_VR_MII_PCS_MODE_MASK			GENMASK(2, 1)
 80#define DW_VR_MII_PCS_MODE_C37_1000BASEX	0x0
 81#define DW_VR_MII_PCS_MODE_C37_SGMII		0x2
 82#define DW_VR_MII_AN_INTR_EN			BIT(0)
 83
 84/* VR_MII_AN_INTR_STS */
 85#define DW_VR_MII_AN_STS_C37_ANCMPLT_INTR	BIT(0)
 86#define DW_VR_MII_AN_STS_C37_ANSGM_FD		BIT(1)
 87#define DW_VR_MII_AN_STS_C37_ANSGM_SP		GENMASK(3, 2)
 88#define DW_VR_MII_C37_ANSGM_SP_10		0x0
 89#define DW_VR_MII_C37_ANSGM_SP_100		0x1
 90#define DW_VR_MII_C37_ANSGM_SP_1000		0x2
 91#define DW_VR_MII_C37_ANSGM_SP_LNKSTS		BIT(4)
 92
 93/* VR MII EEE Control 0 defines */
 94#define DW_VR_MII_EEE_LTX_EN			BIT(0)  /* LPI Tx Enable */
 95#define DW_VR_MII_EEE_LRX_EN			BIT(1)  /* LPI Rx Enable */
 96#define DW_VR_MII_EEE_TX_QUIET_EN		BIT(2)  /* Tx Quiet Enable */
 97#define DW_VR_MII_EEE_RX_QUIET_EN		BIT(3)  /* Rx Quiet Enable */
 98#define DW_VR_MII_EEE_TX_EN_CTRL		BIT(4)  /* Tx Control Enable */
 99#define DW_VR_MII_EEE_RX_EN_CTRL		BIT(7)  /* Rx Control Enable */
100
101#define DW_VR_MII_EEE_MULT_FACT_100NS		GENMASK(11, 8)
102
103/* VR MII EEE Control 1 defines */
104#define DW_VR_MII_EEE_TRN_LPI		BIT(0)	/* Transparent Mode Enable */
105
106#define DW_XPCS_INFO_DECLARE(_name, _pcs, _pma)				\
107	static const struct dw_xpcs_info _name = { .pcs = _pcs, .pma = _pma }
108
109struct dw_xpcs_desc;
110
111enum dw_xpcs_clock {
112	DW_XPCS_CORE_CLK,
113	DW_XPCS_PAD_CLK,
114	DW_XPCS_NUM_CLKS,
115};
116
117struct dw_xpcs {
118	struct dw_xpcs_info info;
119	const struct dw_xpcs_desc *desc;
120	struct mdio_device *mdiodev;
121	struct clk_bulk_data clks[DW_XPCS_NUM_CLKS];
122	struct phylink_pcs pcs;
123	phy_interface_t interface;
124	bool need_reset;
125};
126
127int xpcs_read(struct dw_xpcs *xpcs, int dev, u32 reg);
128int xpcs_write(struct dw_xpcs *xpcs, int dev, u32 reg, u16 val);
129int xpcs_modify(struct dw_xpcs *xpcs, int dev, u32 reg, u16 mask, u16 set);
130int xpcs_read_vpcs(struct dw_xpcs *xpcs, int reg);
131int xpcs_write_vpcs(struct dw_xpcs *xpcs, int reg, u16 val);
132int nxp_sja1105_sgmii_pma_config(struct dw_xpcs *xpcs);
133int nxp_sja1110_sgmii_pma_config(struct dw_xpcs *xpcs);
134int nxp_sja1110_2500basex_pma_config(struct dw_xpcs *xpcs);
135int txgbe_xpcs_switch_mode(struct dw_xpcs *xpcs, phy_interface_t interface);