Loading...
1// SPDX-License-Identifier: GPL-2.0-only
2/* Silan SC92031 PCI Fast Ethernet Adapter driver
3 *
4 * Based on vendor drivers:
5 * Silan Fast Ethernet Netcard Driver:
6 * MODULE_AUTHOR ("gaoyonghong");
7 * MODULE_DESCRIPTION ("SILAN Fast Ethernet driver");
8 * MODULE_LICENSE("GPL");
9 * 8139D Fast Ethernet driver:
10 * (C) 2002 by gaoyonghong
11 * MODULE_AUTHOR ("gaoyonghong");
12 * MODULE_DESCRIPTION ("Rsltek 8139D PCI Fast Ethernet Adapter driver");
13 * MODULE_LICENSE("GPL");
14 * Both are almost identical and seem to be based on pci-skeleton.c
15 *
16 * Rewritten for 2.6 by Cesar Eduardo Barros
17 *
18 * A datasheet for this chip can be found at
19 * http://www.silan.com.cn/english/product/pdf/SC92031AY.pdf
20 */
21
22/* Note about set_mac_address: I don't know how to change the hardware
23 * matching, so you need to enable IFF_PROMISC when using it.
24 */
25
26#include <linux/interrupt.h>
27#include <linux/module.h>
28#include <linux/kernel.h>
29#include <linux/delay.h>
30#include <linux/pci.h>
31#include <linux/dma-mapping.h>
32#include <linux/netdevice.h>
33#include <linux/etherdevice.h>
34#include <linux/ethtool.h>
35#include <linux/mii.h>
36#include <linux/crc32.h>
37
38#include <asm/irq.h>
39
40#define SC92031_NAME "sc92031"
41
42/* BAR 0 is MMIO, BAR 1 is PIO */
43#define SC92031_USE_PIO 0
44
45/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). */
46static int multicast_filter_limit = 64;
47module_param(multicast_filter_limit, int, 0);
48MODULE_PARM_DESC(multicast_filter_limit,
49 "Maximum number of filtered multicast addresses");
50
51static int media;
52module_param(media, int, 0);
53MODULE_PARM_DESC(media, "Media type (0x00 = autodetect,"
54 " 0x01 = 10M half, 0x02 = 10M full,"
55 " 0x04 = 100M half, 0x08 = 100M full)");
56
57/* Size of the in-memory receive ring. */
58#define RX_BUF_LEN_IDX 3 /* 0==8K, 1==16K, 2==32K, 3==64K ,4==128K*/
59#define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
60
61/* Number of Tx descriptor registers. */
62#define NUM_TX_DESC 4
63
64/* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
65#define MAX_ETH_FRAME_SIZE 1536
66
67/* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
68#define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
69#define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
70
71/* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
72#define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */
73
74/* Time in jiffies before concluding the transmitter is hung. */
75#define TX_TIMEOUT (4*HZ)
76
77#define SILAN_STATS_NUM 2 /* number of ETHTOOL_GSTATS */
78
79/* media options */
80#define AUTOSELECT 0x00
81#define M10_HALF 0x01
82#define M10_FULL 0x02
83#define M100_HALF 0x04
84#define M100_FULL 0x08
85
86 /* Symbolic offsets to registers. */
87enum silan_registers {
88 Config0 = 0x00, // Config0
89 Config1 = 0x04, // Config1
90 RxBufWPtr = 0x08, // Rx buffer writer poiter
91 IntrStatus = 0x0C, // Interrupt status
92 IntrMask = 0x10, // Interrupt mask
93 RxbufAddr = 0x14, // Rx buffer start address
94 RxBufRPtr = 0x18, // Rx buffer read pointer
95 Txstatusall = 0x1C, // Transmit status of all descriptors
96 TxStatus0 = 0x20, // Transmit status (Four 32bit registers).
97 TxAddr0 = 0x30, // Tx descriptors (also four 32bit).
98 RxConfig = 0x40, // Rx configuration
99 MAC0 = 0x44, // Ethernet hardware address.
100 MAR0 = 0x4C, // Multicast filter.
101 RxStatus0 = 0x54, // Rx status
102 TxConfig = 0x5C, // Tx configuration
103 PhyCtrl = 0x60, // physical control
104 FlowCtrlConfig = 0x64, // flow control
105 Miicmd0 = 0x68, // Mii command0 register
106 Miicmd1 = 0x6C, // Mii command1 register
107 Miistatus = 0x70, // Mii status register
108 Timercnt = 0x74, // Timer counter register
109 TimerIntr = 0x78, // Timer interrupt register
110 PMConfig = 0x7C, // Power Manager configuration
111 CRC0 = 0x80, // Power Manager CRC ( Two 32bit regisers)
112 Wakeup0 = 0x88, // power Manager wakeup( Eight 64bit regiser)
113 LSBCRC0 = 0xC8, // power Manager LSBCRC(Two 32bit regiser)
114 TestD0 = 0xD0,
115 TestD4 = 0xD4,
116 TestD8 = 0xD8,
117};
118
119#define MII_JAB 16
120#define MII_OutputStatus 24
121
122#define PHY_16_JAB_ENB 0x1000
123#define PHY_16_PORT_ENB 0x1
124
125enum IntrStatusBits {
126 LinkFail = 0x80000000,
127 LinkOK = 0x40000000,
128 TimeOut = 0x20000000,
129 RxOverflow = 0x0040,
130 RxOK = 0x0020,
131 TxOK = 0x0001,
132 IntrBits = LinkFail|LinkOK|TimeOut|RxOverflow|RxOK|TxOK,
133};
134
135enum TxStatusBits {
136 TxCarrierLost = 0x20000000,
137 TxAborted = 0x10000000,
138 TxOutOfWindow = 0x08000000,
139 TxNccShift = 22,
140 EarlyTxThresShift = 16,
141 TxStatOK = 0x8000,
142 TxUnderrun = 0x4000,
143 TxOwn = 0x2000,
144};
145
146enum RxStatusBits {
147 RxStatesOK = 0x80000,
148 RxBadAlign = 0x40000,
149 RxHugeFrame = 0x20000,
150 RxSmallFrame = 0x10000,
151 RxCRCOK = 0x8000,
152 RxCrlFrame = 0x4000,
153 Rx_Broadcast = 0x2000,
154 Rx_Multicast = 0x1000,
155 RxAddrMatch = 0x0800,
156 MiiErr = 0x0400,
157};
158
159enum RxConfigBits {
160 RxFullDx = 0x80000000,
161 RxEnb = 0x40000000,
162 RxSmall = 0x20000000,
163 RxHuge = 0x10000000,
164 RxErr = 0x08000000,
165 RxAllphys = 0x04000000,
166 RxMulticast = 0x02000000,
167 RxBroadcast = 0x01000000,
168 RxLoopBack = (1 << 23) | (1 << 22),
169 LowThresholdShift = 12,
170 HighThresholdShift = 2,
171};
172
173enum TxConfigBits {
174 TxFullDx = 0x80000000,
175 TxEnb = 0x40000000,
176 TxEnbPad = 0x20000000,
177 TxEnbHuge = 0x10000000,
178 TxEnbFCS = 0x08000000,
179 TxNoBackOff = 0x04000000,
180 TxEnbPrem = 0x02000000,
181 TxCareLostCrs = 0x1000000,
182 TxExdCollNum = 0xf00000,
183 TxDataRate = 0x80000,
184};
185
186enum PhyCtrlconfigbits {
187 PhyCtrlAne = 0x80000000,
188 PhyCtrlSpd100 = 0x40000000,
189 PhyCtrlSpd10 = 0x20000000,
190 PhyCtrlPhyBaseAddr = 0x1f000000,
191 PhyCtrlDux = 0x800000,
192 PhyCtrlReset = 0x400000,
193};
194
195enum FlowCtrlConfigBits {
196 FlowCtrlFullDX = 0x80000000,
197 FlowCtrlEnb = 0x40000000,
198};
199
200enum Config0Bits {
201 Cfg0_Reset = 0x80000000,
202 Cfg0_Anaoff = 0x40000000,
203 Cfg0_LDPS = 0x20000000,
204};
205
206enum Config1Bits {
207 Cfg1_EarlyRx = 1 << 31,
208 Cfg1_EarlyTx = 1 << 30,
209
210 //rx buffer size
211 Cfg1_Rcv8K = 0x0,
212 Cfg1_Rcv16K = 0x1,
213 Cfg1_Rcv32K = 0x3,
214 Cfg1_Rcv64K = 0x7,
215 Cfg1_Rcv128K = 0xf,
216};
217
218enum MiiCmd0Bits {
219 Mii_Divider = 0x20000000,
220 Mii_WRITE = 0x400000,
221 Mii_READ = 0x200000,
222 Mii_SCAN = 0x100000,
223 Mii_Tamod = 0x80000,
224 Mii_Drvmod = 0x40000,
225 Mii_mdc = 0x20000,
226 Mii_mdoen = 0x10000,
227 Mii_mdo = 0x8000,
228 Mii_mdi = 0x4000,
229};
230
231enum MiiStatusBits {
232 Mii_StatusBusy = 0x80000000,
233};
234
235enum PMConfigBits {
236 PM_Enable = 1 << 31,
237 PM_LongWF = 1 << 30,
238 PM_Magic = 1 << 29,
239 PM_LANWake = 1 << 28,
240 PM_LWPTN = (1 << 27 | 1<< 26),
241 PM_LinkUp = 1 << 25,
242 PM_WakeUp = 1 << 24,
243};
244
245/* Locking rules:
246 * priv->lock protects most of the fields of priv and most of the
247 * hardware registers. It does not have to protect against softirqs
248 * between sc92031_disable_interrupts and sc92031_enable_interrupts;
249 * it also does not need to be used in ->open and ->stop while the
250 * device interrupts are off.
251 * Not having to protect against softirqs is very useful due to heavy
252 * use of mdelay() at _sc92031_reset.
253 * Functions prefixed with _sc92031_ must be called with the lock held;
254 * functions prefixed with sc92031_ must be called without the lock held.
255 */
256
257/* Locking rules for the interrupt:
258 * - the interrupt and the tasklet never run at the same time
259 * - neither run between sc92031_disable_interrupts and
260 * sc92031_enable_interrupt
261 */
262
263struct sc92031_priv {
264 spinlock_t lock;
265 /* iomap.h cookie */
266 void __iomem *port_base;
267 /* pci device structure */
268 struct pci_dev *pdev;
269 /* tasklet */
270 struct tasklet_struct tasklet;
271
272 /* CPU address of rx ring */
273 void *rx_ring;
274 /* PCI address of rx ring */
275 dma_addr_t rx_ring_dma_addr;
276 /* PCI address of rx ring read pointer */
277 dma_addr_t rx_ring_tail;
278
279 /* tx ring write index */
280 unsigned tx_head;
281 /* tx ring read index */
282 unsigned tx_tail;
283 /* CPU address of tx bounce buffer */
284 void *tx_bufs;
285 /* PCI address of tx bounce buffer */
286 dma_addr_t tx_bufs_dma_addr;
287
288 /* copies of some hardware registers */
289 u32 intr_status;
290 atomic_t intr_mask;
291 u32 rx_config;
292 u32 tx_config;
293 u32 pm_config;
294
295 /* copy of some flags from dev->flags */
296 unsigned int mc_flags;
297
298 /* for ETHTOOL_GSTATS */
299 u64 tx_timeouts;
300 u64 rx_loss;
301
302 /* for dev->get_stats */
303 long rx_value;
304 struct net_device *ndev;
305};
306
307/* I don't know which registers can be safely read; however, I can guess
308 * MAC0 is one of them. */
309static inline void _sc92031_dummy_read(void __iomem *port_base)
310{
311 ioread32(port_base + MAC0);
312}
313
314static u32 _sc92031_mii_wait(void __iomem *port_base)
315{
316 u32 mii_status;
317
318 do {
319 udelay(10);
320 mii_status = ioread32(port_base + Miistatus);
321 } while (mii_status & Mii_StatusBusy);
322
323 return mii_status;
324}
325
326static u32 _sc92031_mii_cmd(void __iomem *port_base, u32 cmd0, u32 cmd1)
327{
328 iowrite32(Mii_Divider, port_base + Miicmd0);
329
330 _sc92031_mii_wait(port_base);
331
332 iowrite32(cmd1, port_base + Miicmd1);
333 iowrite32(Mii_Divider | cmd0, port_base + Miicmd0);
334
335 return _sc92031_mii_wait(port_base);
336}
337
338static void _sc92031_mii_scan(void __iomem *port_base)
339{
340 _sc92031_mii_cmd(port_base, Mii_SCAN, 0x1 << 6);
341}
342
343static u16 _sc92031_mii_read(void __iomem *port_base, unsigned reg)
344{
345 return _sc92031_mii_cmd(port_base, Mii_READ, reg << 6) >> 13;
346}
347
348static void _sc92031_mii_write(void __iomem *port_base, unsigned reg, u16 val)
349{
350 _sc92031_mii_cmd(port_base, Mii_WRITE, (reg << 6) | ((u32)val << 11));
351}
352
353static void sc92031_disable_interrupts(struct net_device *dev)
354{
355 struct sc92031_priv *priv = netdev_priv(dev);
356 void __iomem *port_base = priv->port_base;
357
358 /* tell the tasklet/interrupt not to enable interrupts */
359 atomic_set(&priv->intr_mask, 0);
360 wmb();
361
362 /* stop interrupts */
363 iowrite32(0, port_base + IntrMask);
364 _sc92031_dummy_read(port_base);
365
366 /* wait for any concurrent interrupt/tasklet to finish */
367 synchronize_irq(priv->pdev->irq);
368 tasklet_disable(&priv->tasklet);
369}
370
371static void sc92031_enable_interrupts(struct net_device *dev)
372{
373 struct sc92031_priv *priv = netdev_priv(dev);
374 void __iomem *port_base = priv->port_base;
375
376 tasklet_enable(&priv->tasklet);
377
378 atomic_set(&priv->intr_mask, IntrBits);
379 wmb();
380
381 iowrite32(IntrBits, port_base + IntrMask);
382}
383
384static void _sc92031_disable_tx_rx(struct net_device *dev)
385{
386 struct sc92031_priv *priv = netdev_priv(dev);
387 void __iomem *port_base = priv->port_base;
388
389 priv->rx_config &= ~RxEnb;
390 priv->tx_config &= ~TxEnb;
391 iowrite32(priv->rx_config, port_base + RxConfig);
392 iowrite32(priv->tx_config, port_base + TxConfig);
393}
394
395static void _sc92031_enable_tx_rx(struct net_device *dev)
396{
397 struct sc92031_priv *priv = netdev_priv(dev);
398 void __iomem *port_base = priv->port_base;
399
400 priv->rx_config |= RxEnb;
401 priv->tx_config |= TxEnb;
402 iowrite32(priv->rx_config, port_base + RxConfig);
403 iowrite32(priv->tx_config, port_base + TxConfig);
404}
405
406static void _sc92031_tx_clear(struct net_device *dev)
407{
408 struct sc92031_priv *priv = netdev_priv(dev);
409
410 while (priv->tx_head - priv->tx_tail > 0) {
411 priv->tx_tail++;
412 dev->stats.tx_dropped++;
413 }
414 priv->tx_head = priv->tx_tail = 0;
415}
416
417static void _sc92031_set_mar(struct net_device *dev)
418{
419 struct sc92031_priv *priv = netdev_priv(dev);
420 void __iomem *port_base = priv->port_base;
421 u32 mar0 = 0, mar1 = 0;
422
423 if ((dev->flags & IFF_PROMISC) ||
424 netdev_mc_count(dev) > multicast_filter_limit ||
425 (dev->flags & IFF_ALLMULTI))
426 mar0 = mar1 = 0xffffffff;
427 else if (dev->flags & IFF_MULTICAST) {
428 struct netdev_hw_addr *ha;
429
430 netdev_for_each_mc_addr(ha, dev) {
431 u32 crc;
432 unsigned bit = 0;
433
434 crc = ~ether_crc(ETH_ALEN, ha->addr);
435 crc >>= 24;
436
437 if (crc & 0x01) bit |= 0x02;
438 if (crc & 0x02) bit |= 0x01;
439 if (crc & 0x10) bit |= 0x20;
440 if (crc & 0x20) bit |= 0x10;
441 if (crc & 0x40) bit |= 0x08;
442 if (crc & 0x80) bit |= 0x04;
443
444 if (bit > 31)
445 mar0 |= 0x1 << (bit - 32);
446 else
447 mar1 |= 0x1 << bit;
448 }
449 }
450
451 iowrite32(mar0, port_base + MAR0);
452 iowrite32(mar1, port_base + MAR0 + 4);
453}
454
455static void _sc92031_set_rx_config(struct net_device *dev)
456{
457 struct sc92031_priv *priv = netdev_priv(dev);
458 void __iomem *port_base = priv->port_base;
459 unsigned int old_mc_flags;
460 u32 rx_config_bits = 0;
461
462 old_mc_flags = priv->mc_flags;
463
464 if (dev->flags & IFF_PROMISC)
465 rx_config_bits |= RxSmall | RxHuge | RxErr | RxBroadcast
466 | RxMulticast | RxAllphys;
467
468 if (dev->flags & (IFF_ALLMULTI | IFF_MULTICAST))
469 rx_config_bits |= RxMulticast;
470
471 if (dev->flags & IFF_BROADCAST)
472 rx_config_bits |= RxBroadcast;
473
474 priv->rx_config &= ~(RxSmall | RxHuge | RxErr | RxBroadcast
475 | RxMulticast | RxAllphys);
476 priv->rx_config |= rx_config_bits;
477
478 priv->mc_flags = dev->flags & (IFF_PROMISC | IFF_ALLMULTI
479 | IFF_MULTICAST | IFF_BROADCAST);
480
481 if (netif_carrier_ok(dev) && priv->mc_flags != old_mc_flags)
482 iowrite32(priv->rx_config, port_base + RxConfig);
483}
484
485static bool _sc92031_check_media(struct net_device *dev)
486{
487 struct sc92031_priv *priv = netdev_priv(dev);
488 void __iomem *port_base = priv->port_base;
489 u16 bmsr;
490
491 bmsr = _sc92031_mii_read(port_base, MII_BMSR);
492 rmb();
493 if (bmsr & BMSR_LSTATUS) {
494 bool speed_100, duplex_full;
495 u32 flow_ctrl_config = 0;
496 u16 output_status = _sc92031_mii_read(port_base,
497 MII_OutputStatus);
498 _sc92031_mii_scan(port_base);
499
500 speed_100 = output_status & 0x2;
501 duplex_full = output_status & 0x4;
502
503 /* Initial Tx/Rx configuration */
504 priv->rx_config = (0x40 << LowThresholdShift) | (0x1c0 << HighThresholdShift);
505 priv->tx_config = 0x48800000;
506
507 /* NOTE: vendor driver had dead code here to enable tx padding */
508
509 if (!speed_100)
510 priv->tx_config |= 0x80000;
511
512 // configure rx mode
513 _sc92031_set_rx_config(dev);
514
515 if (duplex_full) {
516 priv->rx_config |= RxFullDx;
517 priv->tx_config |= TxFullDx;
518 flow_ctrl_config = FlowCtrlFullDX | FlowCtrlEnb;
519 } else {
520 priv->rx_config &= ~RxFullDx;
521 priv->tx_config &= ~TxFullDx;
522 }
523
524 _sc92031_set_mar(dev);
525 _sc92031_set_rx_config(dev);
526 _sc92031_enable_tx_rx(dev);
527 iowrite32(flow_ctrl_config, port_base + FlowCtrlConfig);
528
529 netif_carrier_on(dev);
530
531 if (printk_ratelimit())
532 printk(KERN_INFO "%s: link up, %sMbps, %s-duplex\n",
533 dev->name,
534 speed_100 ? "100" : "10",
535 duplex_full ? "full" : "half");
536 return true;
537 } else {
538 _sc92031_mii_scan(port_base);
539
540 netif_carrier_off(dev);
541
542 _sc92031_disable_tx_rx(dev);
543
544 if (printk_ratelimit())
545 printk(KERN_INFO "%s: link down\n", dev->name);
546 return false;
547 }
548}
549
550static void _sc92031_phy_reset(struct net_device *dev)
551{
552 struct sc92031_priv *priv = netdev_priv(dev);
553 void __iomem *port_base = priv->port_base;
554 u32 phy_ctrl;
555
556 phy_ctrl = ioread32(port_base + PhyCtrl);
557 phy_ctrl &= ~(PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10);
558 phy_ctrl |= PhyCtrlAne | PhyCtrlReset;
559
560 switch (media) {
561 default:
562 case AUTOSELECT:
563 phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10;
564 break;
565 case M10_HALF:
566 phy_ctrl |= PhyCtrlSpd10;
567 break;
568 case M10_FULL:
569 phy_ctrl |= PhyCtrlDux | PhyCtrlSpd10;
570 break;
571 case M100_HALF:
572 phy_ctrl |= PhyCtrlSpd100;
573 break;
574 case M100_FULL:
575 phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100;
576 break;
577 }
578
579 iowrite32(phy_ctrl, port_base + PhyCtrl);
580 mdelay(10);
581
582 phy_ctrl &= ~PhyCtrlReset;
583 iowrite32(phy_ctrl, port_base + PhyCtrl);
584 mdelay(1);
585
586 _sc92031_mii_write(port_base, MII_JAB,
587 PHY_16_JAB_ENB | PHY_16_PORT_ENB);
588 _sc92031_mii_scan(port_base);
589
590 netif_carrier_off(dev);
591 netif_stop_queue(dev);
592}
593
594static void _sc92031_reset(struct net_device *dev)
595{
596 struct sc92031_priv *priv = netdev_priv(dev);
597 void __iomem *port_base = priv->port_base;
598
599 /* disable PM */
600 iowrite32(0, port_base + PMConfig);
601
602 /* soft reset the chip */
603 iowrite32(Cfg0_Reset, port_base + Config0);
604 mdelay(200);
605
606 iowrite32(0, port_base + Config0);
607 mdelay(10);
608
609 /* disable interrupts */
610 iowrite32(0, port_base + IntrMask);
611
612 /* clear multicast address */
613 iowrite32(0, port_base + MAR0);
614 iowrite32(0, port_base + MAR0 + 4);
615
616 /* init rx ring */
617 iowrite32(priv->rx_ring_dma_addr, port_base + RxbufAddr);
618 priv->rx_ring_tail = priv->rx_ring_dma_addr;
619
620 /* init tx ring */
621 _sc92031_tx_clear(dev);
622
623 /* clear old register values */
624 priv->intr_status = 0;
625 atomic_set(&priv->intr_mask, 0);
626 priv->rx_config = 0;
627 priv->tx_config = 0;
628 priv->mc_flags = 0;
629
630 /* configure rx buffer size */
631 /* NOTE: vendor driver had dead code here to enable early tx/rx */
632 iowrite32(Cfg1_Rcv64K, port_base + Config1);
633
634 _sc92031_phy_reset(dev);
635 _sc92031_check_media(dev);
636
637 /* calculate rx fifo overflow */
638 priv->rx_value = 0;
639
640 /* enable PM */
641 iowrite32(priv->pm_config, port_base + PMConfig);
642
643 /* clear intr register */
644 ioread32(port_base + IntrStatus);
645}
646
647static void _sc92031_tx_tasklet(struct net_device *dev)
648{
649 struct sc92031_priv *priv = netdev_priv(dev);
650 void __iomem *port_base = priv->port_base;
651
652 unsigned old_tx_tail;
653 unsigned entry;
654 u32 tx_status;
655
656 old_tx_tail = priv->tx_tail;
657 while (priv->tx_head - priv->tx_tail > 0) {
658 entry = priv->tx_tail % NUM_TX_DESC;
659 tx_status = ioread32(port_base + TxStatus0 + entry * 4);
660
661 if (!(tx_status & (TxStatOK | TxUnderrun | TxAborted)))
662 break;
663
664 priv->tx_tail++;
665
666 if (tx_status & TxStatOK) {
667 dev->stats.tx_bytes += tx_status & 0x1fff;
668 dev->stats.tx_packets++;
669 /* Note: TxCarrierLost is always asserted at 100mbps. */
670 dev->stats.collisions += (tx_status >> 22) & 0xf;
671 }
672
673 if (tx_status & (TxOutOfWindow | TxAborted)) {
674 dev->stats.tx_errors++;
675
676 if (tx_status & TxAborted)
677 dev->stats.tx_aborted_errors++;
678
679 if (tx_status & TxCarrierLost)
680 dev->stats.tx_carrier_errors++;
681
682 if (tx_status & TxOutOfWindow)
683 dev->stats.tx_window_errors++;
684 }
685
686 if (tx_status & TxUnderrun)
687 dev->stats.tx_fifo_errors++;
688 }
689
690 if (priv->tx_tail != old_tx_tail)
691 if (netif_queue_stopped(dev))
692 netif_wake_queue(dev);
693}
694
695static void _sc92031_rx_tasklet_error(struct net_device *dev,
696 u32 rx_status, unsigned rx_size)
697{
698 if(rx_size > (MAX_ETH_FRAME_SIZE + 4) || rx_size < 16) {
699 dev->stats.rx_errors++;
700 dev->stats.rx_length_errors++;
701 }
702
703 if (!(rx_status & RxStatesOK)) {
704 dev->stats.rx_errors++;
705
706 if (rx_status & (RxHugeFrame | RxSmallFrame))
707 dev->stats.rx_length_errors++;
708
709 if (rx_status & RxBadAlign)
710 dev->stats.rx_frame_errors++;
711
712 if (!(rx_status & RxCRCOK))
713 dev->stats.rx_crc_errors++;
714 } else {
715 struct sc92031_priv *priv = netdev_priv(dev);
716 priv->rx_loss++;
717 }
718}
719
720static void _sc92031_rx_tasklet(struct net_device *dev)
721{
722 struct sc92031_priv *priv = netdev_priv(dev);
723 void __iomem *port_base = priv->port_base;
724
725 dma_addr_t rx_ring_head;
726 unsigned rx_len;
727 unsigned rx_ring_offset;
728 void *rx_ring = priv->rx_ring;
729
730 rx_ring_head = ioread32(port_base + RxBufWPtr);
731 rmb();
732
733 /* rx_ring_head is only 17 bits in the RxBufWPtr register.
734 * we need to change it to 32 bits physical address
735 */
736 rx_ring_head &= (dma_addr_t)(RX_BUF_LEN - 1);
737 rx_ring_head |= priv->rx_ring_dma_addr & ~(dma_addr_t)(RX_BUF_LEN - 1);
738 if (rx_ring_head < priv->rx_ring_dma_addr)
739 rx_ring_head += RX_BUF_LEN;
740
741 if (rx_ring_head >= priv->rx_ring_tail)
742 rx_len = rx_ring_head - priv->rx_ring_tail;
743 else
744 rx_len = RX_BUF_LEN - (priv->rx_ring_tail - rx_ring_head);
745
746 if (!rx_len)
747 return;
748
749 if (unlikely(rx_len > RX_BUF_LEN)) {
750 if (printk_ratelimit())
751 printk(KERN_ERR "%s: rx packets length > rx buffer\n",
752 dev->name);
753 return;
754 }
755
756 rx_ring_offset = (priv->rx_ring_tail - priv->rx_ring_dma_addr) % RX_BUF_LEN;
757
758 while (rx_len) {
759 u32 rx_status;
760 unsigned rx_size, rx_size_align, pkt_size;
761 struct sk_buff *skb;
762
763 rx_status = le32_to_cpup((__le32 *)(rx_ring + rx_ring_offset));
764 rmb();
765
766 rx_size = rx_status >> 20;
767 rx_size_align = (rx_size + 3) & ~3; // for 4 bytes aligned
768 pkt_size = rx_size - 4; // Omit the four octet CRC from the length.
769
770 rx_ring_offset = (rx_ring_offset + 4) % RX_BUF_LEN;
771
772 if (unlikely(rx_status == 0 ||
773 rx_size > (MAX_ETH_FRAME_SIZE + 4) ||
774 rx_size < 16 ||
775 !(rx_status & RxStatesOK))) {
776 _sc92031_rx_tasklet_error(dev, rx_status, rx_size);
777 break;
778 }
779
780 if (unlikely(rx_size_align + 4 > rx_len)) {
781 if (printk_ratelimit())
782 printk(KERN_ERR "%s: rx_len is too small\n", dev->name);
783 break;
784 }
785
786 rx_len -= rx_size_align + 4;
787
788 skb = netdev_alloc_skb_ip_align(dev, pkt_size);
789 if (unlikely(!skb)) {
790 if (printk_ratelimit())
791 printk(KERN_ERR "%s: Couldn't allocate a skb_buff for a packet of size %u\n",
792 dev->name, pkt_size);
793 goto next;
794 }
795
796 if ((rx_ring_offset + pkt_size) > RX_BUF_LEN) {
797 skb_put_data(skb, rx_ring + rx_ring_offset,
798 RX_BUF_LEN - rx_ring_offset);
799 skb_put_data(skb, rx_ring,
800 pkt_size - (RX_BUF_LEN - rx_ring_offset));
801 } else {
802 skb_put_data(skb, rx_ring + rx_ring_offset, pkt_size);
803 }
804
805 skb->protocol = eth_type_trans(skb, dev);
806 netif_rx(skb);
807
808 dev->stats.rx_bytes += pkt_size;
809 dev->stats.rx_packets++;
810
811 if (rx_status & Rx_Multicast)
812 dev->stats.multicast++;
813
814 next:
815 rx_ring_offset = (rx_ring_offset + rx_size_align) % RX_BUF_LEN;
816 }
817 mb();
818
819 priv->rx_ring_tail = rx_ring_head;
820 iowrite32(priv->rx_ring_tail, port_base + RxBufRPtr);
821}
822
823static void _sc92031_link_tasklet(struct net_device *dev)
824{
825 if (_sc92031_check_media(dev))
826 netif_wake_queue(dev);
827 else {
828 netif_stop_queue(dev);
829 dev->stats.tx_carrier_errors++;
830 }
831}
832
833static void sc92031_tasklet(struct tasklet_struct *t)
834{
835 struct sc92031_priv *priv = from_tasklet(priv, t, tasklet);
836 struct net_device *dev = priv->ndev;
837 void __iomem *port_base = priv->port_base;
838 u32 intr_status, intr_mask;
839
840 intr_status = priv->intr_status;
841
842 spin_lock(&priv->lock);
843
844 if (unlikely(!netif_running(dev)))
845 goto out;
846
847 if (intr_status & TxOK)
848 _sc92031_tx_tasklet(dev);
849
850 if (intr_status & RxOK)
851 _sc92031_rx_tasklet(dev);
852
853 if (intr_status & RxOverflow)
854 dev->stats.rx_errors++;
855
856 if (intr_status & TimeOut) {
857 dev->stats.rx_errors++;
858 dev->stats.rx_length_errors++;
859 }
860
861 if (intr_status & (LinkFail | LinkOK))
862 _sc92031_link_tasklet(dev);
863
864out:
865 intr_mask = atomic_read(&priv->intr_mask);
866 rmb();
867
868 iowrite32(intr_mask, port_base + IntrMask);
869
870 spin_unlock(&priv->lock);
871}
872
873static irqreturn_t sc92031_interrupt(int irq, void *dev_id)
874{
875 struct net_device *dev = dev_id;
876 struct sc92031_priv *priv = netdev_priv(dev);
877 void __iomem *port_base = priv->port_base;
878 u32 intr_status, intr_mask;
879
880 /* mask interrupts before clearing IntrStatus */
881 iowrite32(0, port_base + IntrMask);
882 _sc92031_dummy_read(port_base);
883
884 intr_status = ioread32(port_base + IntrStatus);
885 if (unlikely(intr_status == 0xffffffff))
886 return IRQ_NONE; // hardware has gone missing
887
888 intr_status &= IntrBits;
889 if (!intr_status)
890 goto out_none;
891
892 priv->intr_status = intr_status;
893 tasklet_schedule(&priv->tasklet);
894
895 return IRQ_HANDLED;
896
897out_none:
898 intr_mask = atomic_read(&priv->intr_mask);
899 rmb();
900
901 iowrite32(intr_mask, port_base + IntrMask);
902
903 return IRQ_NONE;
904}
905
906static struct net_device_stats *sc92031_get_stats(struct net_device *dev)
907{
908 struct sc92031_priv *priv = netdev_priv(dev);
909 void __iomem *port_base = priv->port_base;
910
911 // FIXME I do not understand what is this trying to do.
912 if (netif_running(dev)) {
913 int temp;
914
915 spin_lock_bh(&priv->lock);
916
917 /* Update the error count. */
918 temp = (ioread32(port_base + RxStatus0) >> 16) & 0xffff;
919
920 if (temp == 0xffff) {
921 priv->rx_value += temp;
922 dev->stats.rx_fifo_errors = priv->rx_value;
923 } else
924 dev->stats.rx_fifo_errors = temp + priv->rx_value;
925
926 spin_unlock_bh(&priv->lock);
927 }
928
929 return &dev->stats;
930}
931
932static netdev_tx_t sc92031_start_xmit(struct sk_buff *skb,
933 struct net_device *dev)
934{
935 struct sc92031_priv *priv = netdev_priv(dev);
936 void __iomem *port_base = priv->port_base;
937 unsigned len;
938 unsigned entry;
939 u32 tx_status;
940
941 if (unlikely(skb->len > TX_BUF_SIZE)) {
942 dev->stats.tx_dropped++;
943 goto out;
944 }
945
946 spin_lock(&priv->lock);
947
948 if (unlikely(!netif_carrier_ok(dev))) {
949 dev->stats.tx_dropped++;
950 goto out_unlock;
951 }
952
953 BUG_ON(priv->tx_head - priv->tx_tail >= NUM_TX_DESC);
954
955 entry = priv->tx_head++ % NUM_TX_DESC;
956
957 skb_copy_and_csum_dev(skb, priv->tx_bufs + entry * TX_BUF_SIZE);
958
959 len = skb->len;
960 if (len < ETH_ZLEN) {
961 memset(priv->tx_bufs + entry * TX_BUF_SIZE + len,
962 0, ETH_ZLEN - len);
963 len = ETH_ZLEN;
964 }
965
966 wmb();
967
968 if (len < 100)
969 tx_status = len;
970 else if (len < 300)
971 tx_status = 0x30000 | len;
972 else
973 tx_status = 0x50000 | len;
974
975 iowrite32(priv->tx_bufs_dma_addr + entry * TX_BUF_SIZE,
976 port_base + TxAddr0 + entry * 4);
977 iowrite32(tx_status, port_base + TxStatus0 + entry * 4);
978
979 if (priv->tx_head - priv->tx_tail >= NUM_TX_DESC)
980 netif_stop_queue(dev);
981
982out_unlock:
983 spin_unlock(&priv->lock);
984
985out:
986 dev_consume_skb_any(skb);
987
988 return NETDEV_TX_OK;
989}
990
991static int sc92031_open(struct net_device *dev)
992{
993 int err;
994 struct sc92031_priv *priv = netdev_priv(dev);
995 struct pci_dev *pdev = priv->pdev;
996
997 priv->rx_ring = dma_alloc_coherent(&pdev->dev, RX_BUF_LEN,
998 &priv->rx_ring_dma_addr, GFP_KERNEL);
999 if (unlikely(!priv->rx_ring)) {
1000 err = -ENOMEM;
1001 goto out_alloc_rx_ring;
1002 }
1003
1004 priv->tx_bufs = dma_alloc_coherent(&pdev->dev, TX_BUF_TOT_LEN,
1005 &priv->tx_bufs_dma_addr, GFP_KERNEL);
1006 if (unlikely(!priv->tx_bufs)) {
1007 err = -ENOMEM;
1008 goto out_alloc_tx_bufs;
1009 }
1010 priv->tx_head = priv->tx_tail = 0;
1011
1012 err = request_irq(pdev->irq, sc92031_interrupt,
1013 IRQF_SHARED, dev->name, dev);
1014 if (unlikely(err < 0))
1015 goto out_request_irq;
1016
1017 priv->pm_config = 0;
1018
1019 /* Interrupts already disabled by sc92031_stop or sc92031_probe */
1020 spin_lock_bh(&priv->lock);
1021
1022 _sc92031_reset(dev);
1023
1024 spin_unlock_bh(&priv->lock);
1025 sc92031_enable_interrupts(dev);
1026
1027 if (netif_carrier_ok(dev))
1028 netif_start_queue(dev);
1029 else
1030 netif_tx_disable(dev);
1031
1032 return 0;
1033
1034out_request_irq:
1035 dma_free_coherent(&pdev->dev, TX_BUF_TOT_LEN, priv->tx_bufs,
1036 priv->tx_bufs_dma_addr);
1037out_alloc_tx_bufs:
1038 dma_free_coherent(&pdev->dev, RX_BUF_LEN, priv->rx_ring,
1039 priv->rx_ring_dma_addr);
1040out_alloc_rx_ring:
1041 return err;
1042}
1043
1044static int sc92031_stop(struct net_device *dev)
1045{
1046 struct sc92031_priv *priv = netdev_priv(dev);
1047 struct pci_dev *pdev = priv->pdev;
1048
1049 netif_tx_disable(dev);
1050
1051 /* Disable interrupts, stop Tx and Rx. */
1052 sc92031_disable_interrupts(dev);
1053
1054 spin_lock_bh(&priv->lock);
1055
1056 _sc92031_disable_tx_rx(dev);
1057 _sc92031_tx_clear(dev);
1058
1059 spin_unlock_bh(&priv->lock);
1060
1061 free_irq(pdev->irq, dev);
1062 dma_free_coherent(&pdev->dev, TX_BUF_TOT_LEN, priv->tx_bufs,
1063 priv->tx_bufs_dma_addr);
1064 dma_free_coherent(&pdev->dev, RX_BUF_LEN, priv->rx_ring,
1065 priv->rx_ring_dma_addr);
1066
1067 return 0;
1068}
1069
1070static void sc92031_set_multicast_list(struct net_device *dev)
1071{
1072 struct sc92031_priv *priv = netdev_priv(dev);
1073
1074 spin_lock_bh(&priv->lock);
1075
1076 _sc92031_set_mar(dev);
1077 _sc92031_set_rx_config(dev);
1078
1079 spin_unlock_bh(&priv->lock);
1080}
1081
1082static void sc92031_tx_timeout(struct net_device *dev, unsigned int txqueue)
1083{
1084 struct sc92031_priv *priv = netdev_priv(dev);
1085
1086 /* Disable interrupts by clearing the interrupt mask.*/
1087 sc92031_disable_interrupts(dev);
1088
1089 spin_lock(&priv->lock);
1090
1091 priv->tx_timeouts++;
1092
1093 _sc92031_reset(dev);
1094
1095 spin_unlock(&priv->lock);
1096
1097 /* enable interrupts */
1098 sc92031_enable_interrupts(dev);
1099
1100 if (netif_carrier_ok(dev))
1101 netif_wake_queue(dev);
1102}
1103
1104#ifdef CONFIG_NET_POLL_CONTROLLER
1105static void sc92031_poll_controller(struct net_device *dev)
1106{
1107 struct sc92031_priv *priv = netdev_priv(dev);
1108 const int irq = priv->pdev->irq;
1109
1110 disable_irq(irq);
1111 if (sc92031_interrupt(irq, dev) != IRQ_NONE)
1112 sc92031_tasklet(&priv->tasklet);
1113 enable_irq(irq);
1114}
1115#endif
1116
1117static int
1118sc92031_ethtool_get_link_ksettings(struct net_device *dev,
1119 struct ethtool_link_ksettings *cmd)
1120{
1121 struct sc92031_priv *priv = netdev_priv(dev);
1122 void __iomem *port_base = priv->port_base;
1123 u8 phy_address;
1124 u32 phy_ctrl;
1125 u16 output_status;
1126 u32 supported, advertising;
1127
1128 spin_lock_bh(&priv->lock);
1129
1130 phy_address = ioread32(port_base + Miicmd1) >> 27;
1131 phy_ctrl = ioread32(port_base + PhyCtrl);
1132
1133 output_status = _sc92031_mii_read(port_base, MII_OutputStatus);
1134 _sc92031_mii_scan(port_base);
1135
1136 spin_unlock_bh(&priv->lock);
1137
1138 supported = SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full
1139 | SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full
1140 | SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII;
1141
1142 advertising = ADVERTISED_TP | ADVERTISED_MII;
1143
1144 if ((phy_ctrl & (PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10))
1145 == (PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10))
1146 advertising |= ADVERTISED_Autoneg;
1147
1148 if ((phy_ctrl & PhyCtrlSpd10) == PhyCtrlSpd10)
1149 advertising |= ADVERTISED_10baseT_Half;
1150
1151 if ((phy_ctrl & (PhyCtrlSpd10 | PhyCtrlDux))
1152 == (PhyCtrlSpd10 | PhyCtrlDux))
1153 advertising |= ADVERTISED_10baseT_Full;
1154
1155 if ((phy_ctrl & PhyCtrlSpd100) == PhyCtrlSpd100)
1156 advertising |= ADVERTISED_100baseT_Half;
1157
1158 if ((phy_ctrl & (PhyCtrlSpd100 | PhyCtrlDux))
1159 == (PhyCtrlSpd100 | PhyCtrlDux))
1160 advertising |= ADVERTISED_100baseT_Full;
1161
1162 if (phy_ctrl & PhyCtrlAne)
1163 advertising |= ADVERTISED_Autoneg;
1164
1165 cmd->base.speed = (output_status & 0x2) ? SPEED_100 : SPEED_10;
1166 cmd->base.duplex = (output_status & 0x4) ? DUPLEX_FULL : DUPLEX_HALF;
1167 cmd->base.port = PORT_MII;
1168 cmd->base.phy_address = phy_address;
1169 cmd->base.autoneg = (phy_ctrl & PhyCtrlAne) ?
1170 AUTONEG_ENABLE : AUTONEG_DISABLE;
1171
1172 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
1173 supported);
1174 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
1175 advertising);
1176
1177 return 0;
1178}
1179
1180static int
1181sc92031_ethtool_set_link_ksettings(struct net_device *dev,
1182 const struct ethtool_link_ksettings *cmd)
1183{
1184 struct sc92031_priv *priv = netdev_priv(dev);
1185 void __iomem *port_base = priv->port_base;
1186 u32 speed = cmd->base.speed;
1187 u32 phy_ctrl;
1188 u32 old_phy_ctrl;
1189 u32 advertising;
1190
1191 ethtool_convert_link_mode_to_legacy_u32(&advertising,
1192 cmd->link_modes.advertising);
1193
1194 if (!(speed == SPEED_10 || speed == SPEED_100))
1195 return -EINVAL;
1196 if (!(cmd->base.duplex == DUPLEX_HALF ||
1197 cmd->base.duplex == DUPLEX_FULL))
1198 return -EINVAL;
1199 if (!(cmd->base.port == PORT_MII))
1200 return -EINVAL;
1201 if (!(cmd->base.phy_address == 0x1f))
1202 return -EINVAL;
1203 if (!(cmd->base.autoneg == AUTONEG_DISABLE ||
1204 cmd->base.autoneg == AUTONEG_ENABLE))
1205 return -EINVAL;
1206
1207 if (cmd->base.autoneg == AUTONEG_ENABLE) {
1208 if (!(advertising & (ADVERTISED_Autoneg
1209 | ADVERTISED_100baseT_Full
1210 | ADVERTISED_100baseT_Half
1211 | ADVERTISED_10baseT_Full
1212 | ADVERTISED_10baseT_Half)))
1213 return -EINVAL;
1214
1215 phy_ctrl = PhyCtrlAne;
1216
1217 // FIXME: I'm not sure what the original code was trying to do
1218 if (advertising & ADVERTISED_Autoneg)
1219 phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10;
1220 if (advertising & ADVERTISED_100baseT_Full)
1221 phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100;
1222 if (advertising & ADVERTISED_100baseT_Half)
1223 phy_ctrl |= PhyCtrlSpd100;
1224 if (advertising & ADVERTISED_10baseT_Full)
1225 phy_ctrl |= PhyCtrlSpd10 | PhyCtrlDux;
1226 if (advertising & ADVERTISED_10baseT_Half)
1227 phy_ctrl |= PhyCtrlSpd10;
1228 } else {
1229 // FIXME: Whole branch guessed
1230 phy_ctrl = 0;
1231
1232 if (speed == SPEED_10)
1233 phy_ctrl |= PhyCtrlSpd10;
1234 else /* cmd->speed == SPEED_100 */
1235 phy_ctrl |= PhyCtrlSpd100;
1236
1237 if (cmd->base.duplex == DUPLEX_FULL)
1238 phy_ctrl |= PhyCtrlDux;
1239 }
1240
1241 spin_lock_bh(&priv->lock);
1242
1243 old_phy_ctrl = ioread32(port_base + PhyCtrl);
1244 phy_ctrl |= old_phy_ctrl & ~(PhyCtrlAne | PhyCtrlDux
1245 | PhyCtrlSpd100 | PhyCtrlSpd10);
1246 if (phy_ctrl != old_phy_ctrl)
1247 iowrite32(phy_ctrl, port_base + PhyCtrl);
1248
1249 spin_unlock_bh(&priv->lock);
1250
1251 return 0;
1252}
1253
1254static void sc92031_ethtool_get_wol(struct net_device *dev,
1255 struct ethtool_wolinfo *wolinfo)
1256{
1257 struct sc92031_priv *priv = netdev_priv(dev);
1258 void __iomem *port_base = priv->port_base;
1259 u32 pm_config;
1260
1261 spin_lock_bh(&priv->lock);
1262 pm_config = ioread32(port_base + PMConfig);
1263 spin_unlock_bh(&priv->lock);
1264
1265 // FIXME: Guessed
1266 wolinfo->supported = WAKE_PHY | WAKE_MAGIC
1267 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
1268 wolinfo->wolopts = 0;
1269
1270 if (pm_config & PM_LinkUp)
1271 wolinfo->wolopts |= WAKE_PHY;
1272
1273 if (pm_config & PM_Magic)
1274 wolinfo->wolopts |= WAKE_MAGIC;
1275
1276 if (pm_config & PM_WakeUp)
1277 // FIXME: Guessed
1278 wolinfo->wolopts |= WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
1279}
1280
1281static int sc92031_ethtool_set_wol(struct net_device *dev,
1282 struct ethtool_wolinfo *wolinfo)
1283{
1284 struct sc92031_priv *priv = netdev_priv(dev);
1285 void __iomem *port_base = priv->port_base;
1286 u32 pm_config;
1287
1288 spin_lock_bh(&priv->lock);
1289
1290 pm_config = ioread32(port_base + PMConfig)
1291 & ~(PM_LinkUp | PM_Magic | PM_WakeUp);
1292
1293 if (wolinfo->wolopts & WAKE_PHY)
1294 pm_config |= PM_LinkUp;
1295
1296 if (wolinfo->wolopts & WAKE_MAGIC)
1297 pm_config |= PM_Magic;
1298
1299 // FIXME: Guessed
1300 if (wolinfo->wolopts & (WAKE_UCAST | WAKE_MCAST | WAKE_BCAST))
1301 pm_config |= PM_WakeUp;
1302
1303 priv->pm_config = pm_config;
1304 iowrite32(pm_config, port_base + PMConfig);
1305
1306 spin_unlock_bh(&priv->lock);
1307
1308 return 0;
1309}
1310
1311static int sc92031_ethtool_nway_reset(struct net_device *dev)
1312{
1313 int err = 0;
1314 struct sc92031_priv *priv = netdev_priv(dev);
1315 void __iomem *port_base = priv->port_base;
1316 u16 bmcr;
1317
1318 spin_lock_bh(&priv->lock);
1319
1320 bmcr = _sc92031_mii_read(port_base, MII_BMCR);
1321 if (!(bmcr & BMCR_ANENABLE)) {
1322 err = -EINVAL;
1323 goto out;
1324 }
1325
1326 _sc92031_mii_write(port_base, MII_BMCR, bmcr | BMCR_ANRESTART);
1327
1328out:
1329 _sc92031_mii_scan(port_base);
1330
1331 spin_unlock_bh(&priv->lock);
1332
1333 return err;
1334}
1335
1336static const char sc92031_ethtool_stats_strings[SILAN_STATS_NUM][ETH_GSTRING_LEN] = {
1337 "tx_timeout",
1338 "rx_loss",
1339};
1340
1341static void sc92031_ethtool_get_strings(struct net_device *dev,
1342 u32 stringset, u8 *data)
1343{
1344 if (stringset == ETH_SS_STATS)
1345 memcpy(data, sc92031_ethtool_stats_strings,
1346 SILAN_STATS_NUM * ETH_GSTRING_LEN);
1347}
1348
1349static int sc92031_ethtool_get_sset_count(struct net_device *dev, int sset)
1350{
1351 switch (sset) {
1352 case ETH_SS_STATS:
1353 return SILAN_STATS_NUM;
1354 default:
1355 return -EOPNOTSUPP;
1356 }
1357}
1358
1359static void sc92031_ethtool_get_ethtool_stats(struct net_device *dev,
1360 struct ethtool_stats *stats, u64 *data)
1361{
1362 struct sc92031_priv *priv = netdev_priv(dev);
1363
1364 spin_lock_bh(&priv->lock);
1365 data[0] = priv->tx_timeouts;
1366 data[1] = priv->rx_loss;
1367 spin_unlock_bh(&priv->lock);
1368}
1369
1370static const struct ethtool_ops sc92031_ethtool_ops = {
1371 .get_wol = sc92031_ethtool_get_wol,
1372 .set_wol = sc92031_ethtool_set_wol,
1373 .nway_reset = sc92031_ethtool_nway_reset,
1374 .get_link = ethtool_op_get_link,
1375 .get_strings = sc92031_ethtool_get_strings,
1376 .get_sset_count = sc92031_ethtool_get_sset_count,
1377 .get_ethtool_stats = sc92031_ethtool_get_ethtool_stats,
1378 .get_link_ksettings = sc92031_ethtool_get_link_ksettings,
1379 .set_link_ksettings = sc92031_ethtool_set_link_ksettings,
1380};
1381
1382
1383static const struct net_device_ops sc92031_netdev_ops = {
1384 .ndo_get_stats = sc92031_get_stats,
1385 .ndo_start_xmit = sc92031_start_xmit,
1386 .ndo_open = sc92031_open,
1387 .ndo_stop = sc92031_stop,
1388 .ndo_set_rx_mode = sc92031_set_multicast_list,
1389 .ndo_validate_addr = eth_validate_addr,
1390 .ndo_set_mac_address = eth_mac_addr,
1391 .ndo_tx_timeout = sc92031_tx_timeout,
1392#ifdef CONFIG_NET_POLL_CONTROLLER
1393 .ndo_poll_controller = sc92031_poll_controller,
1394#endif
1395};
1396
1397static int sc92031_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1398{
1399 int err;
1400 void __iomem* port_base;
1401 struct net_device *dev;
1402 struct sc92031_priv *priv;
1403 u8 addr[ETH_ALEN];
1404 u32 mac0, mac1;
1405
1406 err = pci_enable_device(pdev);
1407 if (unlikely(err < 0))
1408 goto out_enable_device;
1409
1410 pci_set_master(pdev);
1411
1412 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
1413 if (unlikely(err < 0))
1414 goto out_set_dma_mask;
1415
1416 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1417 if (unlikely(err < 0))
1418 goto out_set_dma_mask;
1419
1420 err = pci_request_regions(pdev, SC92031_NAME);
1421 if (unlikely(err < 0))
1422 goto out_request_regions;
1423
1424 port_base = pci_iomap(pdev, SC92031_USE_PIO, 0);
1425 if (unlikely(!port_base)) {
1426 err = -EIO;
1427 goto out_iomap;
1428 }
1429
1430 dev = alloc_etherdev(sizeof(struct sc92031_priv));
1431 if (unlikely(!dev)) {
1432 err = -ENOMEM;
1433 goto out_alloc_etherdev;
1434 }
1435
1436 pci_set_drvdata(pdev, dev);
1437 SET_NETDEV_DEV(dev, &pdev->dev);
1438
1439 /* faked with skb_copy_and_csum_dev */
1440 dev->features = NETIF_F_SG | NETIF_F_HIGHDMA |
1441 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1442
1443 dev->netdev_ops = &sc92031_netdev_ops;
1444 dev->watchdog_timeo = TX_TIMEOUT;
1445 dev->ethtool_ops = &sc92031_ethtool_ops;
1446
1447 priv = netdev_priv(dev);
1448 priv->ndev = dev;
1449 spin_lock_init(&priv->lock);
1450 priv->port_base = port_base;
1451 priv->pdev = pdev;
1452 tasklet_setup(&priv->tasklet, sc92031_tasklet);
1453 /* Fudge tasklet count so the call to sc92031_enable_interrupts at
1454 * sc92031_open will work correctly */
1455 tasklet_disable_nosync(&priv->tasklet);
1456
1457 /* PCI PM Wakeup */
1458 iowrite32((~PM_LongWF & ~PM_LWPTN) | PM_Enable, port_base + PMConfig);
1459
1460 mac0 = ioread32(port_base + MAC0);
1461 mac1 = ioread32(port_base + MAC0 + 4);
1462 addr[0] = mac0 >> 24;
1463 addr[1] = mac0 >> 16;
1464 addr[2] = mac0 >> 8;
1465 addr[3] = mac0;
1466 addr[4] = mac1 >> 8;
1467 addr[5] = mac1;
1468 eth_hw_addr_set(dev, addr);
1469
1470 err = register_netdev(dev);
1471 if (err < 0)
1472 goto out_register_netdev;
1473
1474 printk(KERN_INFO "%s: SC92031 at 0x%lx, %pM, IRQ %d\n", dev->name,
1475 (long)pci_resource_start(pdev, SC92031_USE_PIO), dev->dev_addr,
1476 pdev->irq);
1477
1478 return 0;
1479
1480out_register_netdev:
1481 free_netdev(dev);
1482out_alloc_etherdev:
1483 pci_iounmap(pdev, port_base);
1484out_iomap:
1485 pci_release_regions(pdev);
1486out_request_regions:
1487out_set_dma_mask:
1488 pci_disable_device(pdev);
1489out_enable_device:
1490 return err;
1491}
1492
1493static void sc92031_remove(struct pci_dev *pdev)
1494{
1495 struct net_device *dev = pci_get_drvdata(pdev);
1496 struct sc92031_priv *priv = netdev_priv(dev);
1497 void __iomem* port_base = priv->port_base;
1498
1499 unregister_netdev(dev);
1500 free_netdev(dev);
1501 pci_iounmap(pdev, port_base);
1502 pci_release_regions(pdev);
1503 pci_disable_device(pdev);
1504}
1505
1506static int __maybe_unused sc92031_suspend(struct device *dev_d)
1507{
1508 struct net_device *dev = dev_get_drvdata(dev_d);
1509 struct sc92031_priv *priv = netdev_priv(dev);
1510
1511 if (!netif_running(dev))
1512 return 0;
1513
1514 netif_device_detach(dev);
1515
1516 /* Disable interrupts, stop Tx and Rx. */
1517 sc92031_disable_interrupts(dev);
1518
1519 spin_lock_bh(&priv->lock);
1520
1521 _sc92031_disable_tx_rx(dev);
1522 _sc92031_tx_clear(dev);
1523
1524 spin_unlock_bh(&priv->lock);
1525
1526 return 0;
1527}
1528
1529static int __maybe_unused sc92031_resume(struct device *dev_d)
1530{
1531 struct net_device *dev = dev_get_drvdata(dev_d);
1532 struct sc92031_priv *priv = netdev_priv(dev);
1533
1534 if (!netif_running(dev))
1535 return 0;
1536
1537 /* Interrupts already disabled by sc92031_suspend */
1538 spin_lock_bh(&priv->lock);
1539
1540 _sc92031_reset(dev);
1541
1542 spin_unlock_bh(&priv->lock);
1543 sc92031_enable_interrupts(dev);
1544
1545 netif_device_attach(dev);
1546
1547 if (netif_carrier_ok(dev))
1548 netif_wake_queue(dev);
1549 else
1550 netif_tx_disable(dev);
1551
1552 return 0;
1553}
1554
1555static const struct pci_device_id sc92031_pci_device_id_table[] = {
1556 { PCI_DEVICE(PCI_VENDOR_ID_SILAN, 0x2031) },
1557 { PCI_DEVICE(PCI_VENDOR_ID_SILAN, 0x8139) },
1558 { PCI_DEVICE(0x1088, 0x2031) },
1559 { 0, }
1560};
1561MODULE_DEVICE_TABLE(pci, sc92031_pci_device_id_table);
1562
1563static SIMPLE_DEV_PM_OPS(sc92031_pm_ops, sc92031_suspend, sc92031_resume);
1564
1565static struct pci_driver sc92031_pci_driver = {
1566 .name = SC92031_NAME,
1567 .id_table = sc92031_pci_device_id_table,
1568 .probe = sc92031_probe,
1569 .remove = sc92031_remove,
1570 .driver.pm = &sc92031_pm_ops,
1571};
1572
1573module_pci_driver(sc92031_pci_driver);
1574MODULE_LICENSE("GPL");
1575MODULE_AUTHOR("Cesar Eduardo Barros <cesarb@cesarb.net>");
1576MODULE_DESCRIPTION("Silan SC92031 PCI Fast Ethernet Adapter driver");
1// SPDX-License-Identifier: GPL-2.0-only
2/* Silan SC92031 PCI Fast Ethernet Adapter driver
3 *
4 * Based on vendor drivers:
5 * Silan Fast Ethernet Netcard Driver:
6 * MODULE_AUTHOR ("gaoyonghong");
7 * MODULE_DESCRIPTION ("SILAN Fast Ethernet driver");
8 * MODULE_LICENSE("GPL");
9 * 8139D Fast Ethernet driver:
10 * (C) 2002 by gaoyonghong
11 * MODULE_AUTHOR ("gaoyonghong");
12 * MODULE_DESCRIPTION ("Rsltek 8139D PCI Fast Ethernet Adapter driver");
13 * MODULE_LICENSE("GPL");
14 * Both are almost identical and seem to be based on pci-skeleton.c
15 *
16 * Rewritten for 2.6 by Cesar Eduardo Barros
17 *
18 * A datasheet for this chip can be found at
19 * http://www.silan.com.cn/english/product/pdf/SC92031AY.pdf
20 */
21
22/* Note about set_mac_address: I don't know how to change the hardware
23 * matching, so you need to enable IFF_PROMISC when using it.
24 */
25
26#include <linux/interrupt.h>
27#include <linux/module.h>
28#include <linux/kernel.h>
29#include <linux/delay.h>
30#include <linux/pci.h>
31#include <linux/dma-mapping.h>
32#include <linux/netdevice.h>
33#include <linux/etherdevice.h>
34#include <linux/ethtool.h>
35#include <linux/mii.h>
36#include <linux/crc32.h>
37
38#include <asm/irq.h>
39
40#define SC92031_NAME "sc92031"
41
42/* BAR 0 is MMIO, BAR 1 is PIO */
43#define SC92031_USE_PIO 0
44
45/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). */
46static int multicast_filter_limit = 64;
47module_param(multicast_filter_limit, int, 0);
48MODULE_PARM_DESC(multicast_filter_limit,
49 "Maximum number of filtered multicast addresses");
50
51static int media;
52module_param(media, int, 0);
53MODULE_PARM_DESC(media, "Media type (0x00 = autodetect,"
54 " 0x01 = 10M half, 0x02 = 10M full,"
55 " 0x04 = 100M half, 0x08 = 100M full)");
56
57/* Size of the in-memory receive ring. */
58#define RX_BUF_LEN_IDX 3 /* 0==8K, 1==16K, 2==32K, 3==64K ,4==128K*/
59#define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
60
61/* Number of Tx descriptor registers. */
62#define NUM_TX_DESC 4
63
64/* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
65#define MAX_ETH_FRAME_SIZE 1536
66
67/* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
68#define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
69#define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
70
71/* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
72#define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */
73
74/* Time in jiffies before concluding the transmitter is hung. */
75#define TX_TIMEOUT (4*HZ)
76
77#define SILAN_STATS_NUM 2 /* number of ETHTOOL_GSTATS */
78
79/* media options */
80#define AUTOSELECT 0x00
81#define M10_HALF 0x01
82#define M10_FULL 0x02
83#define M100_HALF 0x04
84#define M100_FULL 0x08
85
86 /* Symbolic offsets to registers. */
87enum silan_registers {
88 Config0 = 0x00, // Config0
89 Config1 = 0x04, // Config1
90 RxBufWPtr = 0x08, // Rx buffer writer poiter
91 IntrStatus = 0x0C, // Interrupt status
92 IntrMask = 0x10, // Interrupt mask
93 RxbufAddr = 0x14, // Rx buffer start address
94 RxBufRPtr = 0x18, // Rx buffer read pointer
95 Txstatusall = 0x1C, // Transmit status of all descriptors
96 TxStatus0 = 0x20, // Transmit status (Four 32bit registers).
97 TxAddr0 = 0x30, // Tx descriptors (also four 32bit).
98 RxConfig = 0x40, // Rx configuration
99 MAC0 = 0x44, // Ethernet hardware address.
100 MAR0 = 0x4C, // Multicast filter.
101 RxStatus0 = 0x54, // Rx status
102 TxConfig = 0x5C, // Tx configuration
103 PhyCtrl = 0x60, // physical control
104 FlowCtrlConfig = 0x64, // flow control
105 Miicmd0 = 0x68, // Mii command0 register
106 Miicmd1 = 0x6C, // Mii command1 register
107 Miistatus = 0x70, // Mii status register
108 Timercnt = 0x74, // Timer counter register
109 TimerIntr = 0x78, // Timer interrupt register
110 PMConfig = 0x7C, // Power Manager configuration
111 CRC0 = 0x80, // Power Manager CRC ( Two 32bit regisers)
112 Wakeup0 = 0x88, // power Manager wakeup( Eight 64bit regiser)
113 LSBCRC0 = 0xC8, // power Manager LSBCRC(Two 32bit regiser)
114 TestD0 = 0xD0,
115 TestD4 = 0xD4,
116 TestD8 = 0xD8,
117};
118
119#define MII_JAB 16
120#define MII_OutputStatus 24
121
122#define PHY_16_JAB_ENB 0x1000
123#define PHY_16_PORT_ENB 0x1
124
125enum IntrStatusBits {
126 LinkFail = 0x80000000,
127 LinkOK = 0x40000000,
128 TimeOut = 0x20000000,
129 RxOverflow = 0x0040,
130 RxOK = 0x0020,
131 TxOK = 0x0001,
132 IntrBits = LinkFail|LinkOK|TimeOut|RxOverflow|RxOK|TxOK,
133};
134
135enum TxStatusBits {
136 TxCarrierLost = 0x20000000,
137 TxAborted = 0x10000000,
138 TxOutOfWindow = 0x08000000,
139 TxNccShift = 22,
140 EarlyTxThresShift = 16,
141 TxStatOK = 0x8000,
142 TxUnderrun = 0x4000,
143 TxOwn = 0x2000,
144};
145
146enum RxStatusBits {
147 RxStatesOK = 0x80000,
148 RxBadAlign = 0x40000,
149 RxHugeFrame = 0x20000,
150 RxSmallFrame = 0x10000,
151 RxCRCOK = 0x8000,
152 RxCrlFrame = 0x4000,
153 Rx_Broadcast = 0x2000,
154 Rx_Multicast = 0x1000,
155 RxAddrMatch = 0x0800,
156 MiiErr = 0x0400,
157};
158
159enum RxConfigBits {
160 RxFullDx = 0x80000000,
161 RxEnb = 0x40000000,
162 RxSmall = 0x20000000,
163 RxHuge = 0x10000000,
164 RxErr = 0x08000000,
165 RxAllphys = 0x04000000,
166 RxMulticast = 0x02000000,
167 RxBroadcast = 0x01000000,
168 RxLoopBack = (1 << 23) | (1 << 22),
169 LowThresholdShift = 12,
170 HighThresholdShift = 2,
171};
172
173enum TxConfigBits {
174 TxFullDx = 0x80000000,
175 TxEnb = 0x40000000,
176 TxEnbPad = 0x20000000,
177 TxEnbHuge = 0x10000000,
178 TxEnbFCS = 0x08000000,
179 TxNoBackOff = 0x04000000,
180 TxEnbPrem = 0x02000000,
181 TxCareLostCrs = 0x1000000,
182 TxExdCollNum = 0xf00000,
183 TxDataRate = 0x80000,
184};
185
186enum PhyCtrlconfigbits {
187 PhyCtrlAne = 0x80000000,
188 PhyCtrlSpd100 = 0x40000000,
189 PhyCtrlSpd10 = 0x20000000,
190 PhyCtrlPhyBaseAddr = 0x1f000000,
191 PhyCtrlDux = 0x800000,
192 PhyCtrlReset = 0x400000,
193};
194
195enum FlowCtrlConfigBits {
196 FlowCtrlFullDX = 0x80000000,
197 FlowCtrlEnb = 0x40000000,
198};
199
200enum Config0Bits {
201 Cfg0_Reset = 0x80000000,
202 Cfg0_Anaoff = 0x40000000,
203 Cfg0_LDPS = 0x20000000,
204};
205
206enum Config1Bits {
207 Cfg1_EarlyRx = 1 << 31,
208 Cfg1_EarlyTx = 1 << 30,
209
210 //rx buffer size
211 Cfg1_Rcv8K = 0x0,
212 Cfg1_Rcv16K = 0x1,
213 Cfg1_Rcv32K = 0x3,
214 Cfg1_Rcv64K = 0x7,
215 Cfg1_Rcv128K = 0xf,
216};
217
218enum MiiCmd0Bits {
219 Mii_Divider = 0x20000000,
220 Mii_WRITE = 0x400000,
221 Mii_READ = 0x200000,
222 Mii_SCAN = 0x100000,
223 Mii_Tamod = 0x80000,
224 Mii_Drvmod = 0x40000,
225 Mii_mdc = 0x20000,
226 Mii_mdoen = 0x10000,
227 Mii_mdo = 0x8000,
228 Mii_mdi = 0x4000,
229};
230
231enum MiiStatusBits {
232 Mii_StatusBusy = 0x80000000,
233};
234
235enum PMConfigBits {
236 PM_Enable = 1 << 31,
237 PM_LongWF = 1 << 30,
238 PM_Magic = 1 << 29,
239 PM_LANWake = 1 << 28,
240 PM_LWPTN = (1 << 27 | 1<< 26),
241 PM_LinkUp = 1 << 25,
242 PM_WakeUp = 1 << 24,
243};
244
245/* Locking rules:
246 * priv->lock protects most of the fields of priv and most of the
247 * hardware registers. It does not have to protect against softirqs
248 * between sc92031_disable_interrupts and sc92031_enable_interrupts;
249 * it also does not need to be used in ->open and ->stop while the
250 * device interrupts are off.
251 * Not having to protect against softirqs is very useful due to heavy
252 * use of mdelay() at _sc92031_reset.
253 * Functions prefixed with _sc92031_ must be called with the lock held;
254 * functions prefixed with sc92031_ must be called without the lock held.
255 */
256
257/* Locking rules for the interrupt:
258 * - the interrupt and the tasklet never run at the same time
259 * - neither run between sc92031_disable_interrupts and
260 * sc92031_enable_interrupt
261 */
262
263struct sc92031_priv {
264 spinlock_t lock;
265 /* iomap.h cookie */
266 void __iomem *port_base;
267 /* pci device structure */
268 struct pci_dev *pdev;
269 /* tasklet */
270 struct tasklet_struct tasklet;
271
272 /* CPU address of rx ring */
273 void *rx_ring;
274 /* PCI address of rx ring */
275 dma_addr_t rx_ring_dma_addr;
276 /* PCI address of rx ring read pointer */
277 dma_addr_t rx_ring_tail;
278
279 /* tx ring write index */
280 unsigned tx_head;
281 /* tx ring read index */
282 unsigned tx_tail;
283 /* CPU address of tx bounce buffer */
284 void *tx_bufs;
285 /* PCI address of tx bounce buffer */
286 dma_addr_t tx_bufs_dma_addr;
287
288 /* copies of some hardware registers */
289 u32 intr_status;
290 atomic_t intr_mask;
291 u32 rx_config;
292 u32 tx_config;
293 u32 pm_config;
294
295 /* copy of some flags from dev->flags */
296 unsigned int mc_flags;
297
298 /* for ETHTOOL_GSTATS */
299 u64 tx_timeouts;
300 u64 rx_loss;
301
302 /* for dev->get_stats */
303 long rx_value;
304};
305
306/* I don't know which registers can be safely read; however, I can guess
307 * MAC0 is one of them. */
308static inline void _sc92031_dummy_read(void __iomem *port_base)
309{
310 ioread32(port_base + MAC0);
311}
312
313static u32 _sc92031_mii_wait(void __iomem *port_base)
314{
315 u32 mii_status;
316
317 do {
318 udelay(10);
319 mii_status = ioread32(port_base + Miistatus);
320 } while (mii_status & Mii_StatusBusy);
321
322 return mii_status;
323}
324
325static u32 _sc92031_mii_cmd(void __iomem *port_base, u32 cmd0, u32 cmd1)
326{
327 iowrite32(Mii_Divider, port_base + Miicmd0);
328
329 _sc92031_mii_wait(port_base);
330
331 iowrite32(cmd1, port_base + Miicmd1);
332 iowrite32(Mii_Divider | cmd0, port_base + Miicmd0);
333
334 return _sc92031_mii_wait(port_base);
335}
336
337static void _sc92031_mii_scan(void __iomem *port_base)
338{
339 _sc92031_mii_cmd(port_base, Mii_SCAN, 0x1 << 6);
340}
341
342static u16 _sc92031_mii_read(void __iomem *port_base, unsigned reg)
343{
344 return _sc92031_mii_cmd(port_base, Mii_READ, reg << 6) >> 13;
345}
346
347static void _sc92031_mii_write(void __iomem *port_base, unsigned reg, u16 val)
348{
349 _sc92031_mii_cmd(port_base, Mii_WRITE, (reg << 6) | ((u32)val << 11));
350}
351
352static void sc92031_disable_interrupts(struct net_device *dev)
353{
354 struct sc92031_priv *priv = netdev_priv(dev);
355 void __iomem *port_base = priv->port_base;
356
357 /* tell the tasklet/interrupt not to enable interrupts */
358 atomic_set(&priv->intr_mask, 0);
359 wmb();
360
361 /* stop interrupts */
362 iowrite32(0, port_base + IntrMask);
363 _sc92031_dummy_read(port_base);
364
365 /* wait for any concurrent interrupt/tasklet to finish */
366 synchronize_irq(priv->pdev->irq);
367 tasklet_disable(&priv->tasklet);
368}
369
370static void sc92031_enable_interrupts(struct net_device *dev)
371{
372 struct sc92031_priv *priv = netdev_priv(dev);
373 void __iomem *port_base = priv->port_base;
374
375 tasklet_enable(&priv->tasklet);
376
377 atomic_set(&priv->intr_mask, IntrBits);
378 wmb();
379
380 iowrite32(IntrBits, port_base + IntrMask);
381}
382
383static void _sc92031_disable_tx_rx(struct net_device *dev)
384{
385 struct sc92031_priv *priv = netdev_priv(dev);
386 void __iomem *port_base = priv->port_base;
387
388 priv->rx_config &= ~RxEnb;
389 priv->tx_config &= ~TxEnb;
390 iowrite32(priv->rx_config, port_base + RxConfig);
391 iowrite32(priv->tx_config, port_base + TxConfig);
392}
393
394static void _sc92031_enable_tx_rx(struct net_device *dev)
395{
396 struct sc92031_priv *priv = netdev_priv(dev);
397 void __iomem *port_base = priv->port_base;
398
399 priv->rx_config |= RxEnb;
400 priv->tx_config |= TxEnb;
401 iowrite32(priv->rx_config, port_base + RxConfig);
402 iowrite32(priv->tx_config, port_base + TxConfig);
403}
404
405static void _sc92031_tx_clear(struct net_device *dev)
406{
407 struct sc92031_priv *priv = netdev_priv(dev);
408
409 while (priv->tx_head - priv->tx_tail > 0) {
410 priv->tx_tail++;
411 dev->stats.tx_dropped++;
412 }
413 priv->tx_head = priv->tx_tail = 0;
414}
415
416static void _sc92031_set_mar(struct net_device *dev)
417{
418 struct sc92031_priv *priv = netdev_priv(dev);
419 void __iomem *port_base = priv->port_base;
420 u32 mar0 = 0, mar1 = 0;
421
422 if ((dev->flags & IFF_PROMISC) ||
423 netdev_mc_count(dev) > multicast_filter_limit ||
424 (dev->flags & IFF_ALLMULTI))
425 mar0 = mar1 = 0xffffffff;
426 else if (dev->flags & IFF_MULTICAST) {
427 struct netdev_hw_addr *ha;
428
429 netdev_for_each_mc_addr(ha, dev) {
430 u32 crc;
431 unsigned bit = 0;
432
433 crc = ~ether_crc(ETH_ALEN, ha->addr);
434 crc >>= 24;
435
436 if (crc & 0x01) bit |= 0x02;
437 if (crc & 0x02) bit |= 0x01;
438 if (crc & 0x10) bit |= 0x20;
439 if (crc & 0x20) bit |= 0x10;
440 if (crc & 0x40) bit |= 0x08;
441 if (crc & 0x80) bit |= 0x04;
442
443 if (bit > 31)
444 mar0 |= 0x1 << (bit - 32);
445 else
446 mar1 |= 0x1 << bit;
447 }
448 }
449
450 iowrite32(mar0, port_base + MAR0);
451 iowrite32(mar1, port_base + MAR0 + 4);
452}
453
454static void _sc92031_set_rx_config(struct net_device *dev)
455{
456 struct sc92031_priv *priv = netdev_priv(dev);
457 void __iomem *port_base = priv->port_base;
458 unsigned int old_mc_flags;
459 u32 rx_config_bits = 0;
460
461 old_mc_flags = priv->mc_flags;
462
463 if (dev->flags & IFF_PROMISC)
464 rx_config_bits |= RxSmall | RxHuge | RxErr | RxBroadcast
465 | RxMulticast | RxAllphys;
466
467 if (dev->flags & (IFF_ALLMULTI | IFF_MULTICAST))
468 rx_config_bits |= RxMulticast;
469
470 if (dev->flags & IFF_BROADCAST)
471 rx_config_bits |= RxBroadcast;
472
473 priv->rx_config &= ~(RxSmall | RxHuge | RxErr | RxBroadcast
474 | RxMulticast | RxAllphys);
475 priv->rx_config |= rx_config_bits;
476
477 priv->mc_flags = dev->flags & (IFF_PROMISC | IFF_ALLMULTI
478 | IFF_MULTICAST | IFF_BROADCAST);
479
480 if (netif_carrier_ok(dev) && priv->mc_flags != old_mc_flags)
481 iowrite32(priv->rx_config, port_base + RxConfig);
482}
483
484static bool _sc92031_check_media(struct net_device *dev)
485{
486 struct sc92031_priv *priv = netdev_priv(dev);
487 void __iomem *port_base = priv->port_base;
488 u16 bmsr;
489
490 bmsr = _sc92031_mii_read(port_base, MII_BMSR);
491 rmb();
492 if (bmsr & BMSR_LSTATUS) {
493 bool speed_100, duplex_full;
494 u32 flow_ctrl_config = 0;
495 u16 output_status = _sc92031_mii_read(port_base,
496 MII_OutputStatus);
497 _sc92031_mii_scan(port_base);
498
499 speed_100 = output_status & 0x2;
500 duplex_full = output_status & 0x4;
501
502 /* Initial Tx/Rx configuration */
503 priv->rx_config = (0x40 << LowThresholdShift) | (0x1c0 << HighThresholdShift);
504 priv->tx_config = 0x48800000;
505
506 /* NOTE: vendor driver had dead code here to enable tx padding */
507
508 if (!speed_100)
509 priv->tx_config |= 0x80000;
510
511 // configure rx mode
512 _sc92031_set_rx_config(dev);
513
514 if (duplex_full) {
515 priv->rx_config |= RxFullDx;
516 priv->tx_config |= TxFullDx;
517 flow_ctrl_config = FlowCtrlFullDX | FlowCtrlEnb;
518 } else {
519 priv->rx_config &= ~RxFullDx;
520 priv->tx_config &= ~TxFullDx;
521 }
522
523 _sc92031_set_mar(dev);
524 _sc92031_set_rx_config(dev);
525 _sc92031_enable_tx_rx(dev);
526 iowrite32(flow_ctrl_config, port_base + FlowCtrlConfig);
527
528 netif_carrier_on(dev);
529
530 if (printk_ratelimit())
531 printk(KERN_INFO "%s: link up, %sMbps, %s-duplex\n",
532 dev->name,
533 speed_100 ? "100" : "10",
534 duplex_full ? "full" : "half");
535 return true;
536 } else {
537 _sc92031_mii_scan(port_base);
538
539 netif_carrier_off(dev);
540
541 _sc92031_disable_tx_rx(dev);
542
543 if (printk_ratelimit())
544 printk(KERN_INFO "%s: link down\n", dev->name);
545 return false;
546 }
547}
548
549static void _sc92031_phy_reset(struct net_device *dev)
550{
551 struct sc92031_priv *priv = netdev_priv(dev);
552 void __iomem *port_base = priv->port_base;
553 u32 phy_ctrl;
554
555 phy_ctrl = ioread32(port_base + PhyCtrl);
556 phy_ctrl &= ~(PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10);
557 phy_ctrl |= PhyCtrlAne | PhyCtrlReset;
558
559 switch (media) {
560 default:
561 case AUTOSELECT:
562 phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10;
563 break;
564 case M10_HALF:
565 phy_ctrl |= PhyCtrlSpd10;
566 break;
567 case M10_FULL:
568 phy_ctrl |= PhyCtrlDux | PhyCtrlSpd10;
569 break;
570 case M100_HALF:
571 phy_ctrl |= PhyCtrlSpd100;
572 break;
573 case M100_FULL:
574 phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100;
575 break;
576 }
577
578 iowrite32(phy_ctrl, port_base + PhyCtrl);
579 mdelay(10);
580
581 phy_ctrl &= ~PhyCtrlReset;
582 iowrite32(phy_ctrl, port_base + PhyCtrl);
583 mdelay(1);
584
585 _sc92031_mii_write(port_base, MII_JAB,
586 PHY_16_JAB_ENB | PHY_16_PORT_ENB);
587 _sc92031_mii_scan(port_base);
588
589 netif_carrier_off(dev);
590 netif_stop_queue(dev);
591}
592
593static void _sc92031_reset(struct net_device *dev)
594{
595 struct sc92031_priv *priv = netdev_priv(dev);
596 void __iomem *port_base = priv->port_base;
597
598 /* disable PM */
599 iowrite32(0, port_base + PMConfig);
600
601 /* soft reset the chip */
602 iowrite32(Cfg0_Reset, port_base + Config0);
603 mdelay(200);
604
605 iowrite32(0, port_base + Config0);
606 mdelay(10);
607
608 /* disable interrupts */
609 iowrite32(0, port_base + IntrMask);
610
611 /* clear multicast address */
612 iowrite32(0, port_base + MAR0);
613 iowrite32(0, port_base + MAR0 + 4);
614
615 /* init rx ring */
616 iowrite32(priv->rx_ring_dma_addr, port_base + RxbufAddr);
617 priv->rx_ring_tail = priv->rx_ring_dma_addr;
618
619 /* init tx ring */
620 _sc92031_tx_clear(dev);
621
622 /* clear old register values */
623 priv->intr_status = 0;
624 atomic_set(&priv->intr_mask, 0);
625 priv->rx_config = 0;
626 priv->tx_config = 0;
627 priv->mc_flags = 0;
628
629 /* configure rx buffer size */
630 /* NOTE: vendor driver had dead code here to enable early tx/rx */
631 iowrite32(Cfg1_Rcv64K, port_base + Config1);
632
633 _sc92031_phy_reset(dev);
634 _sc92031_check_media(dev);
635
636 /* calculate rx fifo overflow */
637 priv->rx_value = 0;
638
639 /* enable PM */
640 iowrite32(priv->pm_config, port_base + PMConfig);
641
642 /* clear intr register */
643 ioread32(port_base + IntrStatus);
644}
645
646static void _sc92031_tx_tasklet(struct net_device *dev)
647{
648 struct sc92031_priv *priv = netdev_priv(dev);
649 void __iomem *port_base = priv->port_base;
650
651 unsigned old_tx_tail;
652 unsigned entry;
653 u32 tx_status;
654
655 old_tx_tail = priv->tx_tail;
656 while (priv->tx_head - priv->tx_tail > 0) {
657 entry = priv->tx_tail % NUM_TX_DESC;
658 tx_status = ioread32(port_base + TxStatus0 + entry * 4);
659
660 if (!(tx_status & (TxStatOK | TxUnderrun | TxAborted)))
661 break;
662
663 priv->tx_tail++;
664
665 if (tx_status & TxStatOK) {
666 dev->stats.tx_bytes += tx_status & 0x1fff;
667 dev->stats.tx_packets++;
668 /* Note: TxCarrierLost is always asserted at 100mbps. */
669 dev->stats.collisions += (tx_status >> 22) & 0xf;
670 }
671
672 if (tx_status & (TxOutOfWindow | TxAborted)) {
673 dev->stats.tx_errors++;
674
675 if (tx_status & TxAborted)
676 dev->stats.tx_aborted_errors++;
677
678 if (tx_status & TxCarrierLost)
679 dev->stats.tx_carrier_errors++;
680
681 if (tx_status & TxOutOfWindow)
682 dev->stats.tx_window_errors++;
683 }
684
685 if (tx_status & TxUnderrun)
686 dev->stats.tx_fifo_errors++;
687 }
688
689 if (priv->tx_tail != old_tx_tail)
690 if (netif_queue_stopped(dev))
691 netif_wake_queue(dev);
692}
693
694static void _sc92031_rx_tasklet_error(struct net_device *dev,
695 u32 rx_status, unsigned rx_size)
696{
697 if(rx_size > (MAX_ETH_FRAME_SIZE + 4) || rx_size < 16) {
698 dev->stats.rx_errors++;
699 dev->stats.rx_length_errors++;
700 }
701
702 if (!(rx_status & RxStatesOK)) {
703 dev->stats.rx_errors++;
704
705 if (rx_status & (RxHugeFrame | RxSmallFrame))
706 dev->stats.rx_length_errors++;
707
708 if (rx_status & RxBadAlign)
709 dev->stats.rx_frame_errors++;
710
711 if (!(rx_status & RxCRCOK))
712 dev->stats.rx_crc_errors++;
713 } else {
714 struct sc92031_priv *priv = netdev_priv(dev);
715 priv->rx_loss++;
716 }
717}
718
719static void _sc92031_rx_tasklet(struct net_device *dev)
720{
721 struct sc92031_priv *priv = netdev_priv(dev);
722 void __iomem *port_base = priv->port_base;
723
724 dma_addr_t rx_ring_head;
725 unsigned rx_len;
726 unsigned rx_ring_offset;
727 void *rx_ring = priv->rx_ring;
728
729 rx_ring_head = ioread32(port_base + RxBufWPtr);
730 rmb();
731
732 /* rx_ring_head is only 17 bits in the RxBufWPtr register.
733 * we need to change it to 32 bits physical address
734 */
735 rx_ring_head &= (dma_addr_t)(RX_BUF_LEN - 1);
736 rx_ring_head |= priv->rx_ring_dma_addr & ~(dma_addr_t)(RX_BUF_LEN - 1);
737 if (rx_ring_head < priv->rx_ring_dma_addr)
738 rx_ring_head += RX_BUF_LEN;
739
740 if (rx_ring_head >= priv->rx_ring_tail)
741 rx_len = rx_ring_head - priv->rx_ring_tail;
742 else
743 rx_len = RX_BUF_LEN - (priv->rx_ring_tail - rx_ring_head);
744
745 if (!rx_len)
746 return;
747
748 if (unlikely(rx_len > RX_BUF_LEN)) {
749 if (printk_ratelimit())
750 printk(KERN_ERR "%s: rx packets length > rx buffer\n",
751 dev->name);
752 return;
753 }
754
755 rx_ring_offset = (priv->rx_ring_tail - priv->rx_ring_dma_addr) % RX_BUF_LEN;
756
757 while (rx_len) {
758 u32 rx_status;
759 unsigned rx_size, rx_size_align, pkt_size;
760 struct sk_buff *skb;
761
762 rx_status = le32_to_cpup((__le32 *)(rx_ring + rx_ring_offset));
763 rmb();
764
765 rx_size = rx_status >> 20;
766 rx_size_align = (rx_size + 3) & ~3; // for 4 bytes aligned
767 pkt_size = rx_size - 4; // Omit the four octet CRC from the length.
768
769 rx_ring_offset = (rx_ring_offset + 4) % RX_BUF_LEN;
770
771 if (unlikely(rx_status == 0 ||
772 rx_size > (MAX_ETH_FRAME_SIZE + 4) ||
773 rx_size < 16 ||
774 !(rx_status & RxStatesOK))) {
775 _sc92031_rx_tasklet_error(dev, rx_status, rx_size);
776 break;
777 }
778
779 if (unlikely(rx_size_align + 4 > rx_len)) {
780 if (printk_ratelimit())
781 printk(KERN_ERR "%s: rx_len is too small\n", dev->name);
782 break;
783 }
784
785 rx_len -= rx_size_align + 4;
786
787 skb = netdev_alloc_skb_ip_align(dev, pkt_size);
788 if (unlikely(!skb)) {
789 if (printk_ratelimit())
790 printk(KERN_ERR "%s: Couldn't allocate a skb_buff for a packet of size %u\n",
791 dev->name, pkt_size);
792 goto next;
793 }
794
795 if ((rx_ring_offset + pkt_size) > RX_BUF_LEN) {
796 skb_put_data(skb, rx_ring + rx_ring_offset,
797 RX_BUF_LEN - rx_ring_offset);
798 skb_put_data(skb, rx_ring,
799 pkt_size - (RX_BUF_LEN - rx_ring_offset));
800 } else {
801 skb_put_data(skb, rx_ring + rx_ring_offset, pkt_size);
802 }
803
804 skb->protocol = eth_type_trans(skb, dev);
805 netif_rx(skb);
806
807 dev->stats.rx_bytes += pkt_size;
808 dev->stats.rx_packets++;
809
810 if (rx_status & Rx_Multicast)
811 dev->stats.multicast++;
812
813 next:
814 rx_ring_offset = (rx_ring_offset + rx_size_align) % RX_BUF_LEN;
815 }
816 mb();
817
818 priv->rx_ring_tail = rx_ring_head;
819 iowrite32(priv->rx_ring_tail, port_base + RxBufRPtr);
820}
821
822static void _sc92031_link_tasklet(struct net_device *dev)
823{
824 if (_sc92031_check_media(dev))
825 netif_wake_queue(dev);
826 else {
827 netif_stop_queue(dev);
828 dev->stats.tx_carrier_errors++;
829 }
830}
831
832static void sc92031_tasklet(unsigned long data)
833{
834 struct net_device *dev = (struct net_device *)data;
835 struct sc92031_priv *priv = netdev_priv(dev);
836 void __iomem *port_base = priv->port_base;
837 u32 intr_status, intr_mask;
838
839 intr_status = priv->intr_status;
840
841 spin_lock(&priv->lock);
842
843 if (unlikely(!netif_running(dev)))
844 goto out;
845
846 if (intr_status & TxOK)
847 _sc92031_tx_tasklet(dev);
848
849 if (intr_status & RxOK)
850 _sc92031_rx_tasklet(dev);
851
852 if (intr_status & RxOverflow)
853 dev->stats.rx_errors++;
854
855 if (intr_status & TimeOut) {
856 dev->stats.rx_errors++;
857 dev->stats.rx_length_errors++;
858 }
859
860 if (intr_status & (LinkFail | LinkOK))
861 _sc92031_link_tasklet(dev);
862
863out:
864 intr_mask = atomic_read(&priv->intr_mask);
865 rmb();
866
867 iowrite32(intr_mask, port_base + IntrMask);
868
869 spin_unlock(&priv->lock);
870}
871
872static irqreturn_t sc92031_interrupt(int irq, void *dev_id)
873{
874 struct net_device *dev = dev_id;
875 struct sc92031_priv *priv = netdev_priv(dev);
876 void __iomem *port_base = priv->port_base;
877 u32 intr_status, intr_mask;
878
879 /* mask interrupts before clearing IntrStatus */
880 iowrite32(0, port_base + IntrMask);
881 _sc92031_dummy_read(port_base);
882
883 intr_status = ioread32(port_base + IntrStatus);
884 if (unlikely(intr_status == 0xffffffff))
885 return IRQ_NONE; // hardware has gone missing
886
887 intr_status &= IntrBits;
888 if (!intr_status)
889 goto out_none;
890
891 priv->intr_status = intr_status;
892 tasklet_schedule(&priv->tasklet);
893
894 return IRQ_HANDLED;
895
896out_none:
897 intr_mask = atomic_read(&priv->intr_mask);
898 rmb();
899
900 iowrite32(intr_mask, port_base + IntrMask);
901
902 return IRQ_NONE;
903}
904
905static struct net_device_stats *sc92031_get_stats(struct net_device *dev)
906{
907 struct sc92031_priv *priv = netdev_priv(dev);
908 void __iomem *port_base = priv->port_base;
909
910 // FIXME I do not understand what is this trying to do.
911 if (netif_running(dev)) {
912 int temp;
913
914 spin_lock_bh(&priv->lock);
915
916 /* Update the error count. */
917 temp = (ioread32(port_base + RxStatus0) >> 16) & 0xffff;
918
919 if (temp == 0xffff) {
920 priv->rx_value += temp;
921 dev->stats.rx_fifo_errors = priv->rx_value;
922 } else
923 dev->stats.rx_fifo_errors = temp + priv->rx_value;
924
925 spin_unlock_bh(&priv->lock);
926 }
927
928 return &dev->stats;
929}
930
931static netdev_tx_t sc92031_start_xmit(struct sk_buff *skb,
932 struct net_device *dev)
933{
934 struct sc92031_priv *priv = netdev_priv(dev);
935 void __iomem *port_base = priv->port_base;
936 unsigned len;
937 unsigned entry;
938 u32 tx_status;
939
940 if (unlikely(skb->len > TX_BUF_SIZE)) {
941 dev->stats.tx_dropped++;
942 goto out;
943 }
944
945 spin_lock(&priv->lock);
946
947 if (unlikely(!netif_carrier_ok(dev))) {
948 dev->stats.tx_dropped++;
949 goto out_unlock;
950 }
951
952 BUG_ON(priv->tx_head - priv->tx_tail >= NUM_TX_DESC);
953
954 entry = priv->tx_head++ % NUM_TX_DESC;
955
956 skb_copy_and_csum_dev(skb, priv->tx_bufs + entry * TX_BUF_SIZE);
957
958 len = skb->len;
959 if (len < ETH_ZLEN) {
960 memset(priv->tx_bufs + entry * TX_BUF_SIZE + len,
961 0, ETH_ZLEN - len);
962 len = ETH_ZLEN;
963 }
964
965 wmb();
966
967 if (len < 100)
968 tx_status = len;
969 else if (len < 300)
970 tx_status = 0x30000 | len;
971 else
972 tx_status = 0x50000 | len;
973
974 iowrite32(priv->tx_bufs_dma_addr + entry * TX_BUF_SIZE,
975 port_base + TxAddr0 + entry * 4);
976 iowrite32(tx_status, port_base + TxStatus0 + entry * 4);
977
978 if (priv->tx_head - priv->tx_tail >= NUM_TX_DESC)
979 netif_stop_queue(dev);
980
981out_unlock:
982 spin_unlock(&priv->lock);
983
984out:
985 dev_consume_skb_any(skb);
986
987 return NETDEV_TX_OK;
988}
989
990static int sc92031_open(struct net_device *dev)
991{
992 int err;
993 struct sc92031_priv *priv = netdev_priv(dev);
994 struct pci_dev *pdev = priv->pdev;
995
996 priv->rx_ring = pci_alloc_consistent(pdev, RX_BUF_LEN,
997 &priv->rx_ring_dma_addr);
998 if (unlikely(!priv->rx_ring)) {
999 err = -ENOMEM;
1000 goto out_alloc_rx_ring;
1001 }
1002
1003 priv->tx_bufs = pci_alloc_consistent(pdev, TX_BUF_TOT_LEN,
1004 &priv->tx_bufs_dma_addr);
1005 if (unlikely(!priv->tx_bufs)) {
1006 err = -ENOMEM;
1007 goto out_alloc_tx_bufs;
1008 }
1009 priv->tx_head = priv->tx_tail = 0;
1010
1011 err = request_irq(pdev->irq, sc92031_interrupt,
1012 IRQF_SHARED, dev->name, dev);
1013 if (unlikely(err < 0))
1014 goto out_request_irq;
1015
1016 priv->pm_config = 0;
1017
1018 /* Interrupts already disabled by sc92031_stop or sc92031_probe */
1019 spin_lock_bh(&priv->lock);
1020
1021 _sc92031_reset(dev);
1022
1023 spin_unlock_bh(&priv->lock);
1024 sc92031_enable_interrupts(dev);
1025
1026 if (netif_carrier_ok(dev))
1027 netif_start_queue(dev);
1028 else
1029 netif_tx_disable(dev);
1030
1031 return 0;
1032
1033out_request_irq:
1034 pci_free_consistent(pdev, TX_BUF_TOT_LEN, priv->tx_bufs,
1035 priv->tx_bufs_dma_addr);
1036out_alloc_tx_bufs:
1037 pci_free_consistent(pdev, RX_BUF_LEN, priv->rx_ring,
1038 priv->rx_ring_dma_addr);
1039out_alloc_rx_ring:
1040 return err;
1041}
1042
1043static int sc92031_stop(struct net_device *dev)
1044{
1045 struct sc92031_priv *priv = netdev_priv(dev);
1046 struct pci_dev *pdev = priv->pdev;
1047
1048 netif_tx_disable(dev);
1049
1050 /* Disable interrupts, stop Tx and Rx. */
1051 sc92031_disable_interrupts(dev);
1052
1053 spin_lock_bh(&priv->lock);
1054
1055 _sc92031_disable_tx_rx(dev);
1056 _sc92031_tx_clear(dev);
1057
1058 spin_unlock_bh(&priv->lock);
1059
1060 free_irq(pdev->irq, dev);
1061 pci_free_consistent(pdev, TX_BUF_TOT_LEN, priv->tx_bufs,
1062 priv->tx_bufs_dma_addr);
1063 pci_free_consistent(pdev, RX_BUF_LEN, priv->rx_ring,
1064 priv->rx_ring_dma_addr);
1065
1066 return 0;
1067}
1068
1069static void sc92031_set_multicast_list(struct net_device *dev)
1070{
1071 struct sc92031_priv *priv = netdev_priv(dev);
1072
1073 spin_lock_bh(&priv->lock);
1074
1075 _sc92031_set_mar(dev);
1076 _sc92031_set_rx_config(dev);
1077
1078 spin_unlock_bh(&priv->lock);
1079}
1080
1081static void sc92031_tx_timeout(struct net_device *dev)
1082{
1083 struct sc92031_priv *priv = netdev_priv(dev);
1084
1085 /* Disable interrupts by clearing the interrupt mask.*/
1086 sc92031_disable_interrupts(dev);
1087
1088 spin_lock(&priv->lock);
1089
1090 priv->tx_timeouts++;
1091
1092 _sc92031_reset(dev);
1093
1094 spin_unlock(&priv->lock);
1095
1096 /* enable interrupts */
1097 sc92031_enable_interrupts(dev);
1098
1099 if (netif_carrier_ok(dev))
1100 netif_wake_queue(dev);
1101}
1102
1103#ifdef CONFIG_NET_POLL_CONTROLLER
1104static void sc92031_poll_controller(struct net_device *dev)
1105{
1106 struct sc92031_priv *priv = netdev_priv(dev);
1107 const int irq = priv->pdev->irq;
1108
1109 disable_irq(irq);
1110 if (sc92031_interrupt(irq, dev) != IRQ_NONE)
1111 sc92031_tasklet((unsigned long)dev);
1112 enable_irq(irq);
1113}
1114#endif
1115
1116static int
1117sc92031_ethtool_get_link_ksettings(struct net_device *dev,
1118 struct ethtool_link_ksettings *cmd)
1119{
1120 struct sc92031_priv *priv = netdev_priv(dev);
1121 void __iomem *port_base = priv->port_base;
1122 u8 phy_address;
1123 u32 phy_ctrl;
1124 u16 output_status;
1125 u32 supported, advertising;
1126
1127 spin_lock_bh(&priv->lock);
1128
1129 phy_address = ioread32(port_base + Miicmd1) >> 27;
1130 phy_ctrl = ioread32(port_base + PhyCtrl);
1131
1132 output_status = _sc92031_mii_read(port_base, MII_OutputStatus);
1133 _sc92031_mii_scan(port_base);
1134
1135 spin_unlock_bh(&priv->lock);
1136
1137 supported = SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full
1138 | SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full
1139 | SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII;
1140
1141 advertising = ADVERTISED_TP | ADVERTISED_MII;
1142
1143 if ((phy_ctrl & (PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10))
1144 == (PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10))
1145 advertising |= ADVERTISED_Autoneg;
1146
1147 if ((phy_ctrl & PhyCtrlSpd10) == PhyCtrlSpd10)
1148 advertising |= ADVERTISED_10baseT_Half;
1149
1150 if ((phy_ctrl & (PhyCtrlSpd10 | PhyCtrlDux))
1151 == (PhyCtrlSpd10 | PhyCtrlDux))
1152 advertising |= ADVERTISED_10baseT_Full;
1153
1154 if ((phy_ctrl & PhyCtrlSpd100) == PhyCtrlSpd100)
1155 advertising |= ADVERTISED_100baseT_Half;
1156
1157 if ((phy_ctrl & (PhyCtrlSpd100 | PhyCtrlDux))
1158 == (PhyCtrlSpd100 | PhyCtrlDux))
1159 advertising |= ADVERTISED_100baseT_Full;
1160
1161 if (phy_ctrl & PhyCtrlAne)
1162 advertising |= ADVERTISED_Autoneg;
1163
1164 cmd->base.speed = (output_status & 0x2) ? SPEED_100 : SPEED_10;
1165 cmd->base.duplex = (output_status & 0x4) ? DUPLEX_FULL : DUPLEX_HALF;
1166 cmd->base.port = PORT_MII;
1167 cmd->base.phy_address = phy_address;
1168 cmd->base.autoneg = (phy_ctrl & PhyCtrlAne) ?
1169 AUTONEG_ENABLE : AUTONEG_DISABLE;
1170
1171 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
1172 supported);
1173 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
1174 advertising);
1175
1176 return 0;
1177}
1178
1179static int
1180sc92031_ethtool_set_link_ksettings(struct net_device *dev,
1181 const struct ethtool_link_ksettings *cmd)
1182{
1183 struct sc92031_priv *priv = netdev_priv(dev);
1184 void __iomem *port_base = priv->port_base;
1185 u32 speed = cmd->base.speed;
1186 u32 phy_ctrl;
1187 u32 old_phy_ctrl;
1188 u32 advertising;
1189
1190 ethtool_convert_link_mode_to_legacy_u32(&advertising,
1191 cmd->link_modes.advertising);
1192
1193 if (!(speed == SPEED_10 || speed == SPEED_100))
1194 return -EINVAL;
1195 if (!(cmd->base.duplex == DUPLEX_HALF ||
1196 cmd->base.duplex == DUPLEX_FULL))
1197 return -EINVAL;
1198 if (!(cmd->base.port == PORT_MII))
1199 return -EINVAL;
1200 if (!(cmd->base.phy_address == 0x1f))
1201 return -EINVAL;
1202 if (!(cmd->base.autoneg == AUTONEG_DISABLE ||
1203 cmd->base.autoneg == AUTONEG_ENABLE))
1204 return -EINVAL;
1205
1206 if (cmd->base.autoneg == AUTONEG_ENABLE) {
1207 if (!(advertising & (ADVERTISED_Autoneg
1208 | ADVERTISED_100baseT_Full
1209 | ADVERTISED_100baseT_Half
1210 | ADVERTISED_10baseT_Full
1211 | ADVERTISED_10baseT_Half)))
1212 return -EINVAL;
1213
1214 phy_ctrl = PhyCtrlAne;
1215
1216 // FIXME: I'm not sure what the original code was trying to do
1217 if (advertising & ADVERTISED_Autoneg)
1218 phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10;
1219 if (advertising & ADVERTISED_100baseT_Full)
1220 phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100;
1221 if (advertising & ADVERTISED_100baseT_Half)
1222 phy_ctrl |= PhyCtrlSpd100;
1223 if (advertising & ADVERTISED_10baseT_Full)
1224 phy_ctrl |= PhyCtrlSpd10 | PhyCtrlDux;
1225 if (advertising & ADVERTISED_10baseT_Half)
1226 phy_ctrl |= PhyCtrlSpd10;
1227 } else {
1228 // FIXME: Whole branch guessed
1229 phy_ctrl = 0;
1230
1231 if (speed == SPEED_10)
1232 phy_ctrl |= PhyCtrlSpd10;
1233 else /* cmd->speed == SPEED_100 */
1234 phy_ctrl |= PhyCtrlSpd100;
1235
1236 if (cmd->base.duplex == DUPLEX_FULL)
1237 phy_ctrl |= PhyCtrlDux;
1238 }
1239
1240 spin_lock_bh(&priv->lock);
1241
1242 old_phy_ctrl = ioread32(port_base + PhyCtrl);
1243 phy_ctrl |= old_phy_ctrl & ~(PhyCtrlAne | PhyCtrlDux
1244 | PhyCtrlSpd100 | PhyCtrlSpd10);
1245 if (phy_ctrl != old_phy_ctrl)
1246 iowrite32(phy_ctrl, port_base + PhyCtrl);
1247
1248 spin_unlock_bh(&priv->lock);
1249
1250 return 0;
1251}
1252
1253static void sc92031_ethtool_get_wol(struct net_device *dev,
1254 struct ethtool_wolinfo *wolinfo)
1255{
1256 struct sc92031_priv *priv = netdev_priv(dev);
1257 void __iomem *port_base = priv->port_base;
1258 u32 pm_config;
1259
1260 spin_lock_bh(&priv->lock);
1261 pm_config = ioread32(port_base + PMConfig);
1262 spin_unlock_bh(&priv->lock);
1263
1264 // FIXME: Guessed
1265 wolinfo->supported = WAKE_PHY | WAKE_MAGIC
1266 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
1267 wolinfo->wolopts = 0;
1268
1269 if (pm_config & PM_LinkUp)
1270 wolinfo->wolopts |= WAKE_PHY;
1271
1272 if (pm_config & PM_Magic)
1273 wolinfo->wolopts |= WAKE_MAGIC;
1274
1275 if (pm_config & PM_WakeUp)
1276 // FIXME: Guessed
1277 wolinfo->wolopts |= WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
1278}
1279
1280static int sc92031_ethtool_set_wol(struct net_device *dev,
1281 struct ethtool_wolinfo *wolinfo)
1282{
1283 struct sc92031_priv *priv = netdev_priv(dev);
1284 void __iomem *port_base = priv->port_base;
1285 u32 pm_config;
1286
1287 spin_lock_bh(&priv->lock);
1288
1289 pm_config = ioread32(port_base + PMConfig)
1290 & ~(PM_LinkUp | PM_Magic | PM_WakeUp);
1291
1292 if (wolinfo->wolopts & WAKE_PHY)
1293 pm_config |= PM_LinkUp;
1294
1295 if (wolinfo->wolopts & WAKE_MAGIC)
1296 pm_config |= PM_Magic;
1297
1298 // FIXME: Guessed
1299 if (wolinfo->wolopts & (WAKE_UCAST | WAKE_MCAST | WAKE_BCAST))
1300 pm_config |= PM_WakeUp;
1301
1302 priv->pm_config = pm_config;
1303 iowrite32(pm_config, port_base + PMConfig);
1304
1305 spin_unlock_bh(&priv->lock);
1306
1307 return 0;
1308}
1309
1310static int sc92031_ethtool_nway_reset(struct net_device *dev)
1311{
1312 int err = 0;
1313 struct sc92031_priv *priv = netdev_priv(dev);
1314 void __iomem *port_base = priv->port_base;
1315 u16 bmcr;
1316
1317 spin_lock_bh(&priv->lock);
1318
1319 bmcr = _sc92031_mii_read(port_base, MII_BMCR);
1320 if (!(bmcr & BMCR_ANENABLE)) {
1321 err = -EINVAL;
1322 goto out;
1323 }
1324
1325 _sc92031_mii_write(port_base, MII_BMCR, bmcr | BMCR_ANRESTART);
1326
1327out:
1328 _sc92031_mii_scan(port_base);
1329
1330 spin_unlock_bh(&priv->lock);
1331
1332 return err;
1333}
1334
1335static const char sc92031_ethtool_stats_strings[SILAN_STATS_NUM][ETH_GSTRING_LEN] = {
1336 "tx_timeout",
1337 "rx_loss",
1338};
1339
1340static void sc92031_ethtool_get_strings(struct net_device *dev,
1341 u32 stringset, u8 *data)
1342{
1343 if (stringset == ETH_SS_STATS)
1344 memcpy(data, sc92031_ethtool_stats_strings,
1345 SILAN_STATS_NUM * ETH_GSTRING_LEN);
1346}
1347
1348static int sc92031_ethtool_get_sset_count(struct net_device *dev, int sset)
1349{
1350 switch (sset) {
1351 case ETH_SS_STATS:
1352 return SILAN_STATS_NUM;
1353 default:
1354 return -EOPNOTSUPP;
1355 }
1356}
1357
1358static void sc92031_ethtool_get_ethtool_stats(struct net_device *dev,
1359 struct ethtool_stats *stats, u64 *data)
1360{
1361 struct sc92031_priv *priv = netdev_priv(dev);
1362
1363 spin_lock_bh(&priv->lock);
1364 data[0] = priv->tx_timeouts;
1365 data[1] = priv->rx_loss;
1366 spin_unlock_bh(&priv->lock);
1367}
1368
1369static const struct ethtool_ops sc92031_ethtool_ops = {
1370 .get_wol = sc92031_ethtool_get_wol,
1371 .set_wol = sc92031_ethtool_set_wol,
1372 .nway_reset = sc92031_ethtool_nway_reset,
1373 .get_link = ethtool_op_get_link,
1374 .get_strings = sc92031_ethtool_get_strings,
1375 .get_sset_count = sc92031_ethtool_get_sset_count,
1376 .get_ethtool_stats = sc92031_ethtool_get_ethtool_stats,
1377 .get_link_ksettings = sc92031_ethtool_get_link_ksettings,
1378 .set_link_ksettings = sc92031_ethtool_set_link_ksettings,
1379};
1380
1381
1382static const struct net_device_ops sc92031_netdev_ops = {
1383 .ndo_get_stats = sc92031_get_stats,
1384 .ndo_start_xmit = sc92031_start_xmit,
1385 .ndo_open = sc92031_open,
1386 .ndo_stop = sc92031_stop,
1387 .ndo_set_rx_mode = sc92031_set_multicast_list,
1388 .ndo_validate_addr = eth_validate_addr,
1389 .ndo_set_mac_address = eth_mac_addr,
1390 .ndo_tx_timeout = sc92031_tx_timeout,
1391#ifdef CONFIG_NET_POLL_CONTROLLER
1392 .ndo_poll_controller = sc92031_poll_controller,
1393#endif
1394};
1395
1396static int sc92031_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1397{
1398 int err;
1399 void __iomem* port_base;
1400 struct net_device *dev;
1401 struct sc92031_priv *priv;
1402 u32 mac0, mac1;
1403
1404 err = pci_enable_device(pdev);
1405 if (unlikely(err < 0))
1406 goto out_enable_device;
1407
1408 pci_set_master(pdev);
1409
1410 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1411 if (unlikely(err < 0))
1412 goto out_set_dma_mask;
1413
1414 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1415 if (unlikely(err < 0))
1416 goto out_set_dma_mask;
1417
1418 err = pci_request_regions(pdev, SC92031_NAME);
1419 if (unlikely(err < 0))
1420 goto out_request_regions;
1421
1422 port_base = pci_iomap(pdev, SC92031_USE_PIO, 0);
1423 if (unlikely(!port_base)) {
1424 err = -EIO;
1425 goto out_iomap;
1426 }
1427
1428 dev = alloc_etherdev(sizeof(struct sc92031_priv));
1429 if (unlikely(!dev)) {
1430 err = -ENOMEM;
1431 goto out_alloc_etherdev;
1432 }
1433
1434 pci_set_drvdata(pdev, dev);
1435 SET_NETDEV_DEV(dev, &pdev->dev);
1436
1437 /* faked with skb_copy_and_csum_dev */
1438 dev->features = NETIF_F_SG | NETIF_F_HIGHDMA |
1439 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1440
1441 dev->netdev_ops = &sc92031_netdev_ops;
1442 dev->watchdog_timeo = TX_TIMEOUT;
1443 dev->ethtool_ops = &sc92031_ethtool_ops;
1444
1445 priv = netdev_priv(dev);
1446 spin_lock_init(&priv->lock);
1447 priv->port_base = port_base;
1448 priv->pdev = pdev;
1449 tasklet_init(&priv->tasklet, sc92031_tasklet, (unsigned long)dev);
1450 /* Fudge tasklet count so the call to sc92031_enable_interrupts at
1451 * sc92031_open will work correctly */
1452 tasklet_disable_nosync(&priv->tasklet);
1453
1454 /* PCI PM Wakeup */
1455 iowrite32((~PM_LongWF & ~PM_LWPTN) | PM_Enable, port_base + PMConfig);
1456
1457 mac0 = ioread32(port_base + MAC0);
1458 mac1 = ioread32(port_base + MAC0 + 4);
1459 dev->dev_addr[0] = mac0 >> 24;
1460 dev->dev_addr[1] = mac0 >> 16;
1461 dev->dev_addr[2] = mac0 >> 8;
1462 dev->dev_addr[3] = mac0;
1463 dev->dev_addr[4] = mac1 >> 8;
1464 dev->dev_addr[5] = mac1;
1465
1466 err = register_netdev(dev);
1467 if (err < 0)
1468 goto out_register_netdev;
1469
1470 printk(KERN_INFO "%s: SC92031 at 0x%lx, %pM, IRQ %d\n", dev->name,
1471 (long)pci_resource_start(pdev, SC92031_USE_PIO), dev->dev_addr,
1472 pdev->irq);
1473
1474 return 0;
1475
1476out_register_netdev:
1477 free_netdev(dev);
1478out_alloc_etherdev:
1479 pci_iounmap(pdev, port_base);
1480out_iomap:
1481 pci_release_regions(pdev);
1482out_request_regions:
1483out_set_dma_mask:
1484 pci_disable_device(pdev);
1485out_enable_device:
1486 return err;
1487}
1488
1489static void sc92031_remove(struct pci_dev *pdev)
1490{
1491 struct net_device *dev = pci_get_drvdata(pdev);
1492 struct sc92031_priv *priv = netdev_priv(dev);
1493 void __iomem* port_base = priv->port_base;
1494
1495 unregister_netdev(dev);
1496 free_netdev(dev);
1497 pci_iounmap(pdev, port_base);
1498 pci_release_regions(pdev);
1499 pci_disable_device(pdev);
1500}
1501
1502static int sc92031_suspend(struct pci_dev *pdev, pm_message_t state)
1503{
1504 struct net_device *dev = pci_get_drvdata(pdev);
1505 struct sc92031_priv *priv = netdev_priv(dev);
1506
1507 pci_save_state(pdev);
1508
1509 if (!netif_running(dev))
1510 goto out;
1511
1512 netif_device_detach(dev);
1513
1514 /* Disable interrupts, stop Tx and Rx. */
1515 sc92031_disable_interrupts(dev);
1516
1517 spin_lock_bh(&priv->lock);
1518
1519 _sc92031_disable_tx_rx(dev);
1520 _sc92031_tx_clear(dev);
1521
1522 spin_unlock_bh(&priv->lock);
1523
1524out:
1525 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1526
1527 return 0;
1528}
1529
1530static int sc92031_resume(struct pci_dev *pdev)
1531{
1532 struct net_device *dev = pci_get_drvdata(pdev);
1533 struct sc92031_priv *priv = netdev_priv(dev);
1534
1535 pci_restore_state(pdev);
1536 pci_set_power_state(pdev, PCI_D0);
1537
1538 if (!netif_running(dev))
1539 goto out;
1540
1541 /* Interrupts already disabled by sc92031_suspend */
1542 spin_lock_bh(&priv->lock);
1543
1544 _sc92031_reset(dev);
1545
1546 spin_unlock_bh(&priv->lock);
1547 sc92031_enable_interrupts(dev);
1548
1549 netif_device_attach(dev);
1550
1551 if (netif_carrier_ok(dev))
1552 netif_wake_queue(dev);
1553 else
1554 netif_tx_disable(dev);
1555
1556out:
1557 return 0;
1558}
1559
1560static const struct pci_device_id sc92031_pci_device_id_table[] = {
1561 { PCI_DEVICE(PCI_VENDOR_ID_SILAN, 0x2031) },
1562 { PCI_DEVICE(PCI_VENDOR_ID_SILAN, 0x8139) },
1563 { PCI_DEVICE(0x1088, 0x2031) },
1564 { 0, }
1565};
1566MODULE_DEVICE_TABLE(pci, sc92031_pci_device_id_table);
1567
1568static struct pci_driver sc92031_pci_driver = {
1569 .name = SC92031_NAME,
1570 .id_table = sc92031_pci_device_id_table,
1571 .probe = sc92031_probe,
1572 .remove = sc92031_remove,
1573 .suspend = sc92031_suspend,
1574 .resume = sc92031_resume,
1575};
1576
1577module_pci_driver(sc92031_pci_driver);
1578MODULE_LICENSE("GPL");
1579MODULE_AUTHOR("Cesar Eduardo Barros <cesarb@cesarb.net>");
1580MODULE_DESCRIPTION("Silan SC92031 PCI Fast Ethernet Adapter driver");