Loading...
Note: File does not exist in v5.4.
1/* SPDX-License-Identifier: GPL-2.0 */
2/* Marvell Octeon EP (EndPoint) Ethernet Driver
3 *
4 * Copyright (C) 2020 Marvell.
5 *
6 */
7
8#ifndef _OCTEP_TX_H_
9#define _OCTEP_TX_H_
10
11#define IQ_SEND_OK 0
12#define IQ_SEND_STOP 1
13#define IQ_SEND_FAILED -1
14
15#define TX_BUFTYPE_NONE 0
16#define TX_BUFTYPE_NET 1
17#define TX_BUFTYPE_NET_SG 2
18#define NUM_TX_BUFTYPES 3
19
20/* Hardware format for Scatter/Gather list
21 *
22 * 63 48|47 32|31 16|15 0
23 * -----------------------------------------
24 * | Len 0 | Len 1 | Len 2 | Len 3 |
25 * -----------------------------------------
26 * | Ptr 0 |
27 * -----------------------------------------
28 * | Ptr 1 |
29 * -----------------------------------------
30 * | Ptr 2 |
31 * -----------------------------------------
32 * | Ptr 3 |
33 * -----------------------------------------
34 */
35struct octep_tx_sglist_desc {
36 u16 len[4];
37 dma_addr_t dma_ptr[4];
38};
39
40static_assert(sizeof(struct octep_tx_sglist_desc) == 40);
41
42/* Each Scatter/Gather entry sent to hardwar hold four pointers.
43 * So, number of entries required is (MAX_SKB_FRAGS + 1)/4, where '+1'
44 * is for main skb which also goes as a gather buffer to Octeon hardware.
45 * To allocate sufficient SGLIST entries for a packet with max fragments,
46 * align by adding 3 before calcuating max SGLIST entries per packet.
47 */
48#define OCTEP_SGLIST_ENTRIES_PER_PKT ((MAX_SKB_FRAGS + 1 + 3) / 4)
49#define OCTEP_SGLIST_SIZE_PER_PKT \
50 (OCTEP_SGLIST_ENTRIES_PER_PKT * sizeof(struct octep_tx_sglist_desc))
51
52struct octep_tx_buffer {
53 struct sk_buff *skb;
54 dma_addr_t dma;
55 struct octep_tx_sglist_desc *sglist;
56 dma_addr_t sglist_dma;
57 u8 gather;
58};
59
60#define OCTEP_IQ_TXBUFF_INFO_SIZE (sizeof(struct octep_tx_buffer))
61
62/* Hardware interface Tx statistics */
63struct octep_iface_tx_stats {
64 /* Total frames sent on the interface */
65 u64 pkts;
66
67 /* Total octets sent on the interface */
68 u64 octs;
69
70 /* Packets sent to a broadcast DMAC */
71 u64 bcst;
72
73 /* Packets sent to the multicast DMAC */
74 u64 mcst;
75
76 /* Packets dropped due to excessive collisions */
77 u64 xscol;
78
79 /* Packets dropped due to excessive deferral */
80 u64 xsdef;
81
82 /* Packets sent that experienced multiple collisions before successful
83 * transmission
84 */
85 u64 mcol;
86
87 /* Packets sent that experienced a single collision before successful
88 * transmission
89 */
90 u64 scol;
91
92 /* Packets sent with an octet count < 64 */
93 u64 hist_lt64;
94
95 /* Packets sent with an octet count == 64 */
96 u64 hist_eq64;
97
98 /* Packets sent with an octet count of 65–127 */
99 u64 hist_65to127;
100
101 /* Packets sent with an octet count of 128–255 */
102 u64 hist_128to255;
103
104 /* Packets sent with an octet count of 256–511 */
105 u64 hist_256to511;
106
107 /* Packets sent with an octet count of 512–1023 */
108 u64 hist_512to1023;
109
110 /* Packets sent with an octet count of 1024-1518 */
111 u64 hist_1024to1518;
112
113 /* Packets sent with an octet count of > 1518 */
114 u64 hist_gt1518;
115
116 /* Packets sent that experienced a transmit underflow and were
117 * truncated
118 */
119 u64 undflw;
120
121 /* Control/PAUSE packets sent */
122 u64 ctl;
123};
124
125/* Input Queue statistics. Each input queue has four stats fields. */
126struct octep_iq_stats {
127 /* Instructions posted to this queue. */
128 u64 instr_posted;
129
130 /* Instructions copied by hardware for processing. */
131 u64 instr_completed;
132
133 /* Instructions that could not be processed. */
134 u64 instr_dropped;
135
136 /* Bytes sent through this queue. */
137 u64 bytes_sent;
138
139 /* Gather entries sent through this queue. */
140 u64 sgentry_sent;
141
142 /* Number of transmit failures due to TX_BUSY */
143 u64 tx_busy;
144
145 /* Number of times the queue is restarted */
146 u64 restart_cnt;
147};
148
149/* The instruction (input) queue.
150 * The input queue is used to post raw (instruction) mode data or packet
151 * data to Octeon device from the host. Each input queue (up to 4) for
152 * a Octeon device has one such structure to represent it.
153 */
154struct octep_iq {
155 u32 q_no;
156
157 struct octep_device *octep_dev;
158 struct net_device *netdev;
159 struct device *dev;
160 struct netdev_queue *netdev_q;
161
162 /* Index in input ring where driver should write the next packet */
163 u16 host_write_index;
164
165 /* Index in input ring where Octeon is expected to read next packet */
166 u16 octep_read_index;
167
168 /* This index aids in finding the window in the queue where Octeon
169 * has read the commands.
170 */
171 u16 flush_index;
172
173 /* Pointer to statistics for this input queue. */
174 struct octep_iq_stats *stats;
175
176 /* Pointer to the Virtual Base addr of the input ring. */
177 struct octep_tx_desc_hw *desc_ring;
178
179 /* DMA mapped base address of the input descriptor ring. */
180 dma_addr_t desc_ring_dma;
181
182 /* Info of Tx buffers pending completion. */
183 struct octep_tx_buffer *buff_info;
184
185 /* Base pointer to Scatter/Gather lists for all ring descriptors. */
186 struct octep_tx_sglist_desc *sglist;
187
188 /* DMA mapped addr of Scatter Gather Lists */
189 dma_addr_t sglist_dma;
190
191 /* Octeon doorbell register for the ring. */
192 u8 __iomem *doorbell_reg;
193
194 /* Octeon instruction count register for this ring. */
195 u8 __iomem *inst_cnt_reg;
196
197 /* interrupt level register for this ring */
198 u8 __iomem *intr_lvl_reg;
199
200 /* Maximum no. of instructions in this queue. */
201 u32 max_count;
202 u32 ring_size_mask;
203
204 u32 pkt_in_done;
205 u32 pkts_processed;
206
207 u32 status;
208
209 /* Number of instructions pending to be posted to Octeon. */
210 u32 fill_cnt;
211
212 /* The max. number of instructions that can be held pending by the
213 * driver before ringing doorbell.
214 */
215 u32 fill_threshold;
216};
217
218/* Hardware Tx Instruction Header */
219struct octep_instr_hdr {
220 /* Data Len */
221 u64 tlen:16;
222
223 /* Reserved */
224 u64 rsvd:20;
225
226 /* PKIND for SDP */
227 u64 pkind:6;
228
229 /* Front Data size */
230 u64 fsz:6;
231
232 /* No. of entries in gather list */
233 u64 gsz:14;
234
235 /* Gather indicator 1=gather*/
236 u64 gather:1;
237
238 /* Reserved3 */
239 u64 reserved3:1;
240};
241
242static_assert(sizeof(struct octep_instr_hdr) == 8);
243
244/* Tx offload flags */
245#define OCTEP_TX_OFFLOAD_VLAN_INSERT BIT(0)
246#define OCTEP_TX_OFFLOAD_IPV4_CKSUM BIT(1)
247#define OCTEP_TX_OFFLOAD_UDP_CKSUM BIT(2)
248#define OCTEP_TX_OFFLOAD_TCP_CKSUM BIT(3)
249#define OCTEP_TX_OFFLOAD_SCTP_CKSUM BIT(4)
250#define OCTEP_TX_OFFLOAD_TCP_TSO BIT(5)
251#define OCTEP_TX_OFFLOAD_UDP_TSO BIT(6)
252
253#define OCTEP_TX_OFFLOAD_CKSUM (OCTEP_TX_OFFLOAD_IPV4_CKSUM | \
254 OCTEP_TX_OFFLOAD_UDP_CKSUM | \
255 OCTEP_TX_OFFLOAD_TCP_CKSUM)
256
257#define OCTEP_TX_OFFLOAD_TSO (OCTEP_TX_OFFLOAD_TCP_TSO | \
258 OCTEP_TX_OFFLOAD_UDP_TSO)
259
260#define OCTEP_TX_IP_CSUM(flags) ((flags) & \
261 (OCTEP_TX_OFFLOAD_IPV4_CKSUM | \
262 OCTEP_TX_OFFLOAD_TCP_CKSUM | \
263 OCTEP_TX_OFFLOAD_UDP_CKSUM))
264
265#define OCTEP_TX_TSO(flags) ((flags) & \
266 (OCTEP_TX_OFFLOAD_TCP_TSO | \
267 OCTEP_TX_OFFLOAD_UDP_TSO))
268
269struct tx_mdata {
270
271 /* offload flags */
272 u16 ol_flags;
273
274 /* gso size */
275 u16 gso_size;
276
277 /* gso flags */
278 u16 gso_segs;
279
280 /* reserved */
281 u16 rsvd1;
282
283 /* reserved */
284 u64 rsvd2;
285};
286
287static_assert(sizeof(struct tx_mdata) == 16);
288
289/* 64-byte Tx instruction format.
290 * Format of instruction for a 64-byte mode input queue.
291 *
292 * only first 16-bytes (dptr and ih) are mandatory; rest are optional
293 * and filled by the driver based on firmware/hardware capabilities.
294 * These optional headers together called Front Data and its size is
295 * described by ih->fsz.
296 */
297struct octep_tx_desc_hw {
298 /* Pointer where the input data is available. */
299 u64 dptr;
300
301 /* Instruction Header. */
302 union {
303 struct octep_instr_hdr ih;
304 u64 ih64;
305 };
306 union {
307 u64 txm64[2];
308 struct tx_mdata txm;
309 };
310 /* Additional headers available in a 64-byte instruction. */
311 u64 exthdr[4];
312};
313
314static_assert(sizeof(struct octep_tx_desc_hw) == 64);
315
316#define OCTEP_IQ_DESC_SIZE (sizeof(struct octep_tx_desc_hw))
317#endif /* _OCTEP_TX_H_ */