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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Huawei HiNIC PCI Express Linux driver
4 * Copyright(c) 2017 Huawei Technologies Co., Ltd
5 */
6
7#ifndef HINIC_PORT_H
8#define HINIC_PORT_H
9
10#include <linux/types.h>
11#include <linux/ethtool.h>
12#include <linux/etherdevice.h>
13#include <linux/bitops.h>
14
15#include "hinic_dev.h"
16
17#define HINIC_RSS_KEY_SIZE 40
18#define HINIC_RSS_INDIR_SIZE 256
19#define HINIC_PORT_STATS_VERSION 0
20#define HINIC_FW_VERSION_NAME 16
21#define HINIC_COMPILE_TIME_LEN 20
22#define HINIC_MGMT_VERSION_MAX_LEN 32
23
24struct hinic_version_info {
25 u8 status;
26 u8 version;
27 u8 rsvd[6];
28
29 u8 ver[HINIC_FW_VERSION_NAME];
30 u8 time[HINIC_COMPILE_TIME_LEN];
31};
32
33enum hinic_rx_mode {
34 HINIC_RX_MODE_UC = BIT(0),
35 HINIC_RX_MODE_MC = BIT(1),
36 HINIC_RX_MODE_BC = BIT(2),
37 HINIC_RX_MODE_MC_ALL = BIT(3),
38 HINIC_RX_MODE_PROMISC = BIT(4),
39};
40
41enum hinic_port_link_state {
42 HINIC_LINK_STATE_DOWN,
43 HINIC_LINK_STATE_UP,
44};
45
46enum hinic_port_state {
47 HINIC_PORT_DISABLE = 0,
48 HINIC_PORT_ENABLE = 3,
49};
50
51enum hinic_func_port_state {
52 HINIC_FUNC_PORT_DISABLE = 0,
53 HINIC_FUNC_PORT_ENABLE = 2,
54};
55
56enum hinic_autoneg_cap {
57 HINIC_AUTONEG_UNSUPPORTED,
58 HINIC_AUTONEG_SUPPORTED,
59};
60
61enum hinic_autoneg_state {
62 HINIC_AUTONEG_DISABLED,
63 HINIC_AUTONEG_ACTIVE,
64};
65
66enum hinic_duplex {
67 HINIC_DUPLEX_HALF,
68 HINIC_DUPLEX_FULL,
69};
70
71enum hinic_speed {
72 HINIC_SPEED_10MB_LINK = 0,
73 HINIC_SPEED_100MB_LINK,
74 HINIC_SPEED_1000MB_LINK,
75 HINIC_SPEED_10GB_LINK,
76 HINIC_SPEED_25GB_LINK,
77 HINIC_SPEED_40GB_LINK,
78 HINIC_SPEED_100GB_LINK,
79
80 HINIC_SPEED_UNKNOWN = 0xFF,
81};
82
83enum hinic_link_mode {
84 HINIC_10GE_BASE_KR = 0,
85 HINIC_40GE_BASE_KR4 = 1,
86 HINIC_40GE_BASE_CR4 = 2,
87 HINIC_100GE_BASE_KR4 = 3,
88 HINIC_100GE_BASE_CR4 = 4,
89 HINIC_25GE_BASE_KR_S = 5,
90 HINIC_25GE_BASE_CR_S = 6,
91 HINIC_25GE_BASE_KR = 7,
92 HINIC_25GE_BASE_CR = 8,
93 HINIC_GE_BASE_KX = 9,
94 HINIC_LINK_MODE_NUMBERS,
95
96 HINIC_SUPPORTED_UNKNOWN = 0xFFFF,
97};
98
99enum hinic_port_type {
100 HINIC_PORT_TP, /* BASET */
101 HINIC_PORT_AUI,
102 HINIC_PORT_MII,
103 HINIC_PORT_FIBRE, /* OPTICAL */
104 HINIC_PORT_BNC,
105 HINIC_PORT_ELEC,
106 HINIC_PORT_COPPER, /* PORT_DA */
107 HINIC_PORT_AOC,
108 HINIC_PORT_BACKPLANE,
109 HINIC_PORT_NONE = 0xEF,
110 HINIC_PORT_OTHER = 0xFF,
111};
112
113enum hinic_valid_link_settings {
114 HILINK_LINK_SET_SPEED = 0x1,
115 HILINK_LINK_SET_AUTONEG = 0x2,
116 HILINK_LINK_SET_FEC = 0x4,
117};
118
119enum hinic_tso_state {
120 HINIC_TSO_DISABLE = 0,
121 HINIC_TSO_ENABLE = 1,
122};
123
124struct hinic_port_mac_cmd {
125 u8 status;
126 u8 version;
127 u8 rsvd0[6];
128
129 u16 func_idx;
130 u16 vlan_id;
131 u16 rsvd1;
132 unsigned char mac[ETH_ALEN];
133};
134
135struct hinic_port_mtu_cmd {
136 u8 status;
137 u8 version;
138 u8 rsvd0[6];
139
140 u16 func_idx;
141 u16 rsvd1;
142 u32 mtu;
143};
144
145struct hinic_port_vlan_cmd {
146 u8 status;
147 u8 version;
148 u8 rsvd0[6];
149
150 u16 func_idx;
151 u16 vlan_id;
152};
153
154struct hinic_port_rx_mode_cmd {
155 u8 status;
156 u8 version;
157 u8 rsvd0[6];
158
159 u16 func_idx;
160 u16 rsvd;
161 u32 rx_mode;
162};
163
164struct hinic_port_link_cmd {
165 u8 status;
166 u8 version;
167 u8 rsvd0[6];
168
169 u16 func_idx;
170 u8 state;
171 u8 rsvd1;
172};
173
174struct hinic_port_state_cmd {
175 u8 status;
176 u8 version;
177 u8 rsvd0[6];
178
179 u8 state;
180 u8 rsvd1[3];
181};
182
183struct hinic_port_link_status {
184 u8 status;
185 u8 version;
186 u8 rsvd0[6];
187
188 u16 func_id;
189 u8 link;
190 u8 port_id;
191};
192
193struct hinic_cable_plug_event {
194 u8 status;
195 u8 version;
196 u8 rsvd0[6];
197
198 u16 func_id;
199 u8 plugged; /* 0: unplugged, 1: plugged */
200 u8 port_id;
201};
202
203enum link_err_type {
204 LINK_ERR_MODULE_UNRECOGENIZED,
205 LINK_ERR_NUM,
206};
207
208struct hinic_link_err_event {
209 u8 status;
210 u8 version;
211 u8 rsvd0[6];
212
213 u16 func_id;
214 u8 err_type;
215 u8 port_id;
216};
217
218struct hinic_port_func_state_cmd {
219 u8 status;
220 u8 version;
221 u8 rsvd0[6];
222
223 u16 func_idx;
224 u16 rsvd1;
225 u8 state;
226 u8 rsvd2[3];
227};
228
229struct hinic_port_cap {
230 u8 status;
231 u8 version;
232 u8 rsvd0[6];
233
234 u16 func_idx;
235 u16 rsvd1;
236 u8 port_type;
237 u8 autoneg_cap;
238 u8 autoneg_state;
239 u8 duplex;
240 u8 speed;
241 u8 rsvd2[3];
242};
243
244struct hinic_link_mode_cmd {
245 u8 status;
246 u8 version;
247 u8 rsvd0[6];
248
249 u16 func_id;
250 u16 rsvd1;
251 u16 supported; /* 0xFFFF represents invalid value */
252 u16 advertised;
253};
254
255struct hinic_speed_cmd {
256 u8 status;
257 u8 version;
258 u8 rsvd0[6];
259
260 u16 func_id;
261 u16 speed;
262};
263
264struct hinic_set_autoneg_cmd {
265 u8 status;
266 u8 version;
267 u8 rsvd0[6];
268
269 u16 func_id;
270 u16 enable; /* 1: enable , 0: disable */
271};
272
273struct hinic_link_ksettings_info {
274 u8 status;
275 u8 version;
276 u8 rsvd0[6];
277
278 u16 func_id;
279 u16 rsvd1;
280
281 u32 valid_bitmap;
282 u32 speed; /* enum nic_speed_level */
283 u8 autoneg; /* 0 - off; 1 - on */
284 u8 fec; /* 0 - RSFEC; 1 - BASEFEC; 2 - NOFEC */
285 u8 rsvd2[18]; /* reserved for duplex, port, etc. */
286};
287
288struct hinic_tso_config {
289 u8 status;
290 u8 version;
291 u8 rsvd0[6];
292
293 u16 func_id;
294 u16 rsvd1;
295 u8 tso_en;
296 u8 resv2[3];
297};
298
299struct hinic_checksum_offload {
300 u8 status;
301 u8 version;
302 u8 rsvd0[6];
303
304 u16 func_id;
305 u16 rsvd1;
306 u32 rx_csum_offload;
307};
308
309struct hinic_rq_num {
310 u8 status;
311 u8 version;
312 u8 rsvd0[6];
313
314 u16 func_id;
315 u16 rsvd1[33];
316 u32 num_rqs;
317 u32 rq_depth;
318};
319
320struct hinic_lro_config {
321 u8 status;
322 u8 version;
323 u8 rsvd0[6];
324
325 u16 func_id;
326 u16 rsvd1;
327 u8 lro_ipv4_en;
328 u8 lro_ipv6_en;
329 u8 lro_max_wqe_num;
330 u8 resv2[13];
331};
332
333struct hinic_lro_timer {
334 u8 status;
335 u8 version;
336 u8 rsvd0[6];
337
338 u8 type; /* 0: set timer value, 1: get timer value */
339 u8 enable; /* when set lro time, enable should be 1 */
340 u16 rsvd1;
341 u32 timer;
342};
343
344struct hinic_vlan_cfg {
345 u8 status;
346 u8 version;
347 u8 rsvd0[6];
348
349 u16 func_id;
350 u8 vlan_rx_offload;
351 u8 rsvd1[5];
352};
353
354struct hinic_vlan_filter {
355 u8 status;
356 u8 version;
357 u8 rsvd0[6];
358
359 u16 func_idx;
360 u8 rsvd1[2];
361 u32 enable;
362};
363
364struct hinic_rss_template_mgmt {
365 u8 status;
366 u8 version;
367 u8 rsvd0[6];
368
369 u16 func_id;
370 u8 cmd;
371 u8 template_id;
372 u8 rsvd1[4];
373};
374
375struct hinic_rss_template_key {
376 u8 status;
377 u8 version;
378 u8 rsvd0[6];
379
380 u16 func_id;
381 u8 template_id;
382 u8 rsvd1;
383 u8 key[HINIC_RSS_KEY_SIZE];
384};
385
386struct hinic_rss_context_tbl {
387 u32 group_index;
388 u32 offset;
389 u32 size;
390 u32 rsvd;
391 u32 ctx;
392};
393
394struct hinic_rss_context_table {
395 u8 status;
396 u8 version;
397 u8 rsvd0[6];
398
399 u16 func_id;
400 u8 template_id;
401 u8 rsvd1;
402 u32 context;
403};
404
405struct hinic_rss_indirect_tbl {
406 u32 group_index;
407 u32 offset;
408 u32 size;
409 u32 rsvd;
410 u8 entry[HINIC_RSS_INDIR_SIZE];
411};
412
413struct hinic_rss_indir_table {
414 u8 status;
415 u8 version;
416 u8 rsvd0[6];
417
418 u16 func_id;
419 u8 template_id;
420 u8 rsvd1;
421 u8 indir[HINIC_RSS_INDIR_SIZE];
422};
423
424struct hinic_rss_key {
425 u8 status;
426 u8 version;
427 u8 rsvd0[6];
428
429 u16 func_id;
430 u8 template_id;
431 u8 rsvd1;
432 u8 key[HINIC_RSS_KEY_SIZE];
433};
434
435struct hinic_rss_engine_type {
436 u8 status;
437 u8 version;
438 u8 rsvd0[6];
439
440 u16 func_id;
441 u8 template_id;
442 u8 hash_engine;
443 u8 rsvd1[4];
444};
445
446struct hinic_rss_config {
447 u8 status;
448 u8 version;
449 u8 rsvd0[6];
450
451 u16 func_id;
452 u8 rss_en;
453 u8 template_id;
454 u8 rq_priority_number;
455 u8 rsvd1[11];
456};
457
458struct hinic_stats {
459 char name[ETH_GSTRING_LEN];
460 u32 size;
461 int offset;
462};
463
464struct hinic_vport_stats {
465 u64 tx_unicast_pkts_vport;
466 u64 tx_unicast_bytes_vport;
467 u64 tx_multicast_pkts_vport;
468 u64 tx_multicast_bytes_vport;
469 u64 tx_broadcast_pkts_vport;
470 u64 tx_broadcast_bytes_vport;
471
472 u64 rx_unicast_pkts_vport;
473 u64 rx_unicast_bytes_vport;
474 u64 rx_multicast_pkts_vport;
475 u64 rx_multicast_bytes_vport;
476 u64 rx_broadcast_pkts_vport;
477 u64 rx_broadcast_bytes_vport;
478
479 u64 tx_discard_vport;
480 u64 rx_discard_vport;
481 u64 tx_err_vport;
482 u64 rx_err_vport;
483};
484
485struct hinic_phy_port_stats {
486 u64 mac_rx_total_pkt_num;
487 u64 mac_rx_total_oct_num;
488 u64 mac_rx_bad_pkt_num;
489 u64 mac_rx_bad_oct_num;
490 u64 mac_rx_good_pkt_num;
491 u64 mac_rx_good_oct_num;
492 u64 mac_rx_uni_pkt_num;
493 u64 mac_rx_multi_pkt_num;
494 u64 mac_rx_broad_pkt_num;
495
496 u64 mac_tx_total_pkt_num;
497 u64 mac_tx_total_oct_num;
498 u64 mac_tx_bad_pkt_num;
499 u64 mac_tx_bad_oct_num;
500 u64 mac_tx_good_pkt_num;
501 u64 mac_tx_good_oct_num;
502 u64 mac_tx_uni_pkt_num;
503 u64 mac_tx_multi_pkt_num;
504 u64 mac_tx_broad_pkt_num;
505
506 u64 mac_rx_fragment_pkt_num;
507 u64 mac_rx_undersize_pkt_num;
508 u64 mac_rx_undermin_pkt_num;
509 u64 mac_rx_64_oct_pkt_num;
510 u64 mac_rx_65_127_oct_pkt_num;
511 u64 mac_rx_128_255_oct_pkt_num;
512 u64 mac_rx_256_511_oct_pkt_num;
513 u64 mac_rx_512_1023_oct_pkt_num;
514 u64 mac_rx_1024_1518_oct_pkt_num;
515 u64 mac_rx_1519_2047_oct_pkt_num;
516 u64 mac_rx_2048_4095_oct_pkt_num;
517 u64 mac_rx_4096_8191_oct_pkt_num;
518 u64 mac_rx_8192_9216_oct_pkt_num;
519 u64 mac_rx_9217_12287_oct_pkt_num;
520 u64 mac_rx_12288_16383_oct_pkt_num;
521 u64 mac_rx_1519_max_bad_pkt_num;
522 u64 mac_rx_1519_max_good_pkt_num;
523 u64 mac_rx_oversize_pkt_num;
524 u64 mac_rx_jabber_pkt_num;
525
526 u64 mac_rx_pause_num;
527 u64 mac_rx_pfc_pkt_num;
528 u64 mac_rx_pfc_pri0_pkt_num;
529 u64 mac_rx_pfc_pri1_pkt_num;
530 u64 mac_rx_pfc_pri2_pkt_num;
531 u64 mac_rx_pfc_pri3_pkt_num;
532 u64 mac_rx_pfc_pri4_pkt_num;
533 u64 mac_rx_pfc_pri5_pkt_num;
534 u64 mac_rx_pfc_pri6_pkt_num;
535 u64 mac_rx_pfc_pri7_pkt_num;
536 u64 mac_rx_control_pkt_num;
537 u64 mac_rx_y1731_pkt_num;
538 u64 mac_rx_sym_err_pkt_num;
539 u64 mac_rx_fcs_err_pkt_num;
540 u64 mac_rx_send_app_good_pkt_num;
541 u64 mac_rx_send_app_bad_pkt_num;
542
543 u64 mac_tx_fragment_pkt_num;
544 u64 mac_tx_undersize_pkt_num;
545 u64 mac_tx_undermin_pkt_num;
546 u64 mac_tx_64_oct_pkt_num;
547 u64 mac_tx_65_127_oct_pkt_num;
548 u64 mac_tx_128_255_oct_pkt_num;
549 u64 mac_tx_256_511_oct_pkt_num;
550 u64 mac_tx_512_1023_oct_pkt_num;
551 u64 mac_tx_1024_1518_oct_pkt_num;
552 u64 mac_tx_1519_2047_oct_pkt_num;
553 u64 mac_tx_2048_4095_oct_pkt_num;
554 u64 mac_tx_4096_8191_oct_pkt_num;
555 u64 mac_tx_8192_9216_oct_pkt_num;
556 u64 mac_tx_9217_12287_oct_pkt_num;
557 u64 mac_tx_12288_16383_oct_pkt_num;
558 u64 mac_tx_1519_max_bad_pkt_num;
559 u64 mac_tx_1519_max_good_pkt_num;
560 u64 mac_tx_oversize_pkt_num;
561 u64 mac_tx_jabber_pkt_num;
562
563 u64 mac_tx_pause_num;
564 u64 mac_tx_pfc_pkt_num;
565 u64 mac_tx_pfc_pri0_pkt_num;
566 u64 mac_tx_pfc_pri1_pkt_num;
567 u64 mac_tx_pfc_pri2_pkt_num;
568 u64 mac_tx_pfc_pri3_pkt_num;
569 u64 mac_tx_pfc_pri4_pkt_num;
570 u64 mac_tx_pfc_pri5_pkt_num;
571 u64 mac_tx_pfc_pri6_pkt_num;
572 u64 mac_tx_pfc_pri7_pkt_num;
573 u64 mac_tx_control_pkt_num;
574 u64 mac_tx_y1731_pkt_num;
575 u64 mac_tx_1588_pkt_num;
576 u64 mac_tx_err_all_pkt_num;
577 u64 mac_tx_from_app_good_pkt_num;
578 u64 mac_tx_from_app_bad_pkt_num;
579
580 u64 mac_rx_higig2_ext_pkt_num;
581 u64 mac_rx_higig2_message_pkt_num;
582 u64 mac_rx_higig2_error_pkt_num;
583 u64 mac_rx_higig2_cpu_ctrl_pkt_num;
584 u64 mac_rx_higig2_unicast_pkt_num;
585 u64 mac_rx_higig2_broadcast_pkt_num;
586 u64 mac_rx_higig2_l2_multicast_pkt_num;
587 u64 mac_rx_higig2_l3_multicast_pkt_num;
588
589 u64 mac_tx_higig2_message_pkt_num;
590 u64 mac_tx_higig2_ext_pkt_num;
591 u64 mac_tx_higig2_cpu_ctrl_pkt_num;
592 u64 mac_tx_higig2_unicast_pkt_num;
593 u64 mac_tx_higig2_broadcast_pkt_num;
594 u64 mac_tx_higig2_l2_multicast_pkt_num;
595 u64 mac_tx_higig2_l3_multicast_pkt_num;
596};
597
598struct hinic_port_stats_info {
599 u8 status;
600 u8 version;
601 u8 rsvd0[6];
602
603 u16 func_id;
604 u16 rsvd1;
605 u32 stats_version;
606 u32 stats_size;
607};
608
609struct hinic_port_stats {
610 u8 status;
611 u8 version;
612 u8 rsvd[6];
613
614 struct hinic_phy_port_stats stats;
615};
616
617struct hinic_cmd_vport_stats {
618 u8 status;
619 u8 version;
620 u8 rsvd0[6];
621
622 struct hinic_vport_stats stats;
623};
624
625struct hinic_tx_rate_cfg_max_min {
626 u8 status;
627 u8 version;
628 u8 rsvd0[6];
629
630 u16 func_id;
631 u16 rsvd1;
632 u32 min_rate;
633 u32 max_rate;
634 u8 rsvd2[8];
635};
636
637struct hinic_tx_rate_cfg {
638 u8 status;
639 u8 version;
640 u8 rsvd0[6];
641
642 u16 func_id;
643 u16 rsvd1;
644 u32 tx_rate;
645};
646
647enum nic_speed_level {
648 LINK_SPEED_10MB = 0,
649 LINK_SPEED_100MB,
650 LINK_SPEED_1GB,
651 LINK_SPEED_10GB,
652 LINK_SPEED_25GB,
653 LINK_SPEED_40GB,
654 LINK_SPEED_100GB,
655 LINK_SPEED_LEVELS,
656};
657
658struct hinic_spoofchk_set {
659 u8 status;
660 u8 version;
661 u8 rsvd0[6];
662
663 u8 state;
664 u8 rsvd1;
665 u16 func_id;
666};
667
668struct hinic_pause_config {
669 u8 status;
670 u8 version;
671 u8 rsvd0[6];
672
673 u16 func_id;
674 u16 rsvd1;
675 u32 auto_neg;
676 u32 rx_pause;
677 u32 tx_pause;
678};
679
680struct hinic_set_pfc {
681 u8 status;
682 u8 version;
683 u8 rsvd0[6];
684
685 u16 func_id;
686 u8 pfc_en;
687 u8 pfc_bitmap;
688 u8 rsvd1[4];
689};
690
691/* get or set loopback mode, need to modify by base API */
692#define HINIC_INTERNAL_LP_MODE 5
693#define LOOP_MODE_MIN 1
694#define LOOP_MODE_MAX 6
695
696struct hinic_port_loopback {
697 u8 status;
698 u8 version;
699 u8 rsvd[6];
700
701 u32 mode;
702 u32 en;
703};
704
705struct hinic_led_info {
706 u8 status;
707 u8 version;
708 u8 rsvd0[6];
709
710 u8 port;
711 u8 type;
712 u8 mode;
713 u8 reset;
714};
715
716#define STD_SFP_INFO_MAX_SIZE 640
717
718struct hinic_cmd_get_light_module_abs {
719 u8 status;
720 u8 version;
721 u8 rsvd0[6];
722
723 u8 port_id;
724 u8 abs_status; /* 0:present, 1:absent */
725 u8 rsv[2];
726};
727
728#define STD_SFP_INFO_MAX_SIZE 640
729
730struct hinic_cmd_get_std_sfp_info {
731 u8 status;
732 u8 version;
733 u8 rsvd0[6];
734
735 u8 port_id;
736 u8 wire_type;
737 u16 eeprom_len;
738 u32 rsvd;
739 u8 sfp_info[STD_SFP_INFO_MAX_SIZE];
740};
741
742struct hinic_cmd_update_fw {
743 u8 status;
744 u8 version;
745 u8 rsvd0[6];
746
747 struct {
748 u32 SL:1;
749 u32 SF:1;
750 u32 flag:1;
751 u32 reserved:13;
752 u32 fragment_len:16;
753 } ctl_info;
754
755 struct {
756 u32 FW_section_CRC;
757 u32 FW_section_type;
758 } section_info;
759
760 u32 total_len;
761 u32 setion_total_len;
762 u32 fw_section_version;
763 u32 section_offset;
764 u32 data[384];
765};
766
767int hinic_port_add_mac(struct hinic_dev *nic_dev, const u8 *addr,
768 u16 vlan_id);
769
770int hinic_port_del_mac(struct hinic_dev *nic_dev, const u8 *addr,
771 u16 vlan_id);
772
773int hinic_port_get_mac(struct hinic_dev *nic_dev, u8 *addr);
774
775int hinic_port_set_mtu(struct hinic_dev *nic_dev, int new_mtu);
776
777int hinic_port_add_vlan(struct hinic_dev *nic_dev, u16 vlan_id);
778
779int hinic_port_del_vlan(struct hinic_dev *nic_dev, u16 vlan_id);
780
781int hinic_port_set_rx_mode(struct hinic_dev *nic_dev, u32 rx_mode);
782
783int hinic_port_link_state(struct hinic_dev *nic_dev,
784 enum hinic_port_link_state *link_state);
785
786int hinic_port_set_state(struct hinic_dev *nic_dev,
787 enum hinic_port_state state);
788
789int hinic_port_set_func_state(struct hinic_dev *nic_dev,
790 enum hinic_func_port_state state);
791
792int hinic_port_get_cap(struct hinic_dev *nic_dev,
793 struct hinic_port_cap *port_cap);
794
795int hinic_set_max_qnum(struct hinic_dev *nic_dev, u8 num_rqs);
796
797int hinic_port_set_tso(struct hinic_dev *nic_dev, enum hinic_tso_state state);
798
799int hinic_set_rx_csum_offload(struct hinic_dev *nic_dev, u32 en);
800
801int hinic_set_rx_lro_state(struct hinic_dev *nic_dev, u8 lro_en,
802 u32 lro_timer, u32 wqe_num);
803
804int hinic_set_rss_type(struct hinic_dev *nic_dev, u32 tmpl_idx,
805 struct hinic_rss_type rss_type);
806
807int hinic_rss_set_indir_tbl(struct hinic_dev *nic_dev, u32 tmpl_idx,
808 const u32 *indir_table);
809
810int hinic_rss_set_template_tbl(struct hinic_dev *nic_dev, u32 template_id,
811 const u8 *temp);
812
813int hinic_rss_set_hash_engine(struct hinic_dev *nic_dev, u8 template_id,
814 u8 type);
815
816int hinic_rss_cfg(struct hinic_dev *nic_dev, u8 rss_en, u8 template_id);
817
818int hinic_rss_template_alloc(struct hinic_dev *nic_dev, u8 *tmpl_idx);
819
820int hinic_rss_template_free(struct hinic_dev *nic_dev, u8 tmpl_idx);
821
822void hinic_set_ethtool_ops(struct net_device *netdev);
823
824int hinic_get_rss_type(struct hinic_dev *nic_dev, u32 tmpl_idx,
825 struct hinic_rss_type *rss_type);
826
827int hinic_rss_get_indir_tbl(struct hinic_dev *nic_dev, u32 tmpl_idx,
828 u32 *indir_table);
829
830int hinic_rss_get_template_tbl(struct hinic_dev *nic_dev, u32 tmpl_idx,
831 u8 *temp);
832
833int hinic_rss_get_hash_engine(struct hinic_dev *nic_dev, u8 tmpl_idx,
834 u8 *type);
835
836int hinic_get_phy_port_stats(struct hinic_dev *nic_dev,
837 struct hinic_phy_port_stats *stats);
838
839int hinic_get_vport_stats(struct hinic_dev *nic_dev,
840 struct hinic_vport_stats *stats);
841
842int hinic_set_rx_vlan_offload(struct hinic_dev *nic_dev, u8 en);
843
844int hinic_set_vlan_fliter(struct hinic_dev *nic_dev, u32 en);
845
846int hinic_get_mgmt_version(struct hinic_dev *nic_dev, u8 *mgmt_ver);
847
848int hinic_set_link_settings(struct hinic_hwdev *hwdev,
849 struct hinic_link_ksettings_info *info);
850
851int hinic_get_link_mode(struct hinic_hwdev *hwdev,
852 struct hinic_link_mode_cmd *link_mode);
853
854int hinic_set_autoneg(struct hinic_hwdev *hwdev, bool enable);
855
856int hinic_set_speed(struct hinic_hwdev *hwdev, enum nic_speed_level speed);
857
858int hinic_get_hw_pause_info(struct hinic_hwdev *hwdev,
859 struct hinic_pause_config *pause_info);
860
861int hinic_set_hw_pause_info(struct hinic_hwdev *hwdev,
862 struct hinic_pause_config *pause_info);
863
864int hinic_dcb_set_pfc(struct hinic_hwdev *hwdev, u8 pfc_en, u8 pfc_bitmap);
865
866int hinic_set_loopback_mode(struct hinic_hwdev *hwdev, u32 mode, u32 enable);
867
868enum hinic_led_mode {
869 HINIC_LED_MODE_ON,
870 HINIC_LED_MODE_OFF,
871 HINIC_LED_MODE_FORCE_1HZ,
872 HINIC_LED_MODE_FORCE_2HZ,
873 HINIC_LED_MODE_FORCE_4HZ,
874 HINIC_LED_MODE_1HZ,
875 HINIC_LED_MODE_2HZ,
876 HINIC_LED_MODE_4HZ,
877 HINIC_LED_MODE_INVALID,
878};
879
880enum hinic_led_type {
881 HINIC_LED_TYPE_LINK,
882 HINIC_LED_TYPE_LOW_SPEED,
883 HINIC_LED_TYPE_HIGH_SPEED,
884 HINIC_LED_TYPE_INVALID,
885};
886
887int hinic_reset_led_status(struct hinic_hwdev *hwdev, u8 port);
888
889int hinic_set_led_status(struct hinic_hwdev *hwdev, u8 port,
890 enum hinic_led_type type, enum hinic_led_mode mode);
891
892int hinic_get_sfp_type(struct hinic_hwdev *hwdev, u8 *data0, u8 *data1);
893
894int hinic_get_sfp_eeprom(struct hinic_hwdev *hwdev, u8 *data, u16 *len);
895
896int hinic_open(struct net_device *netdev);
897
898int hinic_close(struct net_device *netdev);
899
900#endif
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Huawei HiNIC PCI Express Linux driver
4 * Copyright(c) 2017 Huawei Technologies Co., Ltd
5 */
6
7#ifndef HINIC_PORT_H
8#define HINIC_PORT_H
9
10#include <linux/types.h>
11#include <linux/etherdevice.h>
12#include <linux/bitops.h>
13
14#include "hinic_dev.h"
15
16#define HINIC_RSS_KEY_SIZE 40
17#define HINIC_RSS_INDIR_SIZE 256
18#define HINIC_PORT_STATS_VERSION 0
19#define HINIC_FW_VERSION_NAME 16
20#define HINIC_COMPILE_TIME_LEN 20
21#define HINIC_MGMT_VERSION_MAX_LEN 32
22
23struct hinic_version_info {
24 u8 status;
25 u8 version;
26 u8 rsvd[6];
27
28 u8 ver[HINIC_FW_VERSION_NAME];
29 u8 time[HINIC_COMPILE_TIME_LEN];
30};
31
32enum hinic_rx_mode {
33 HINIC_RX_MODE_UC = BIT(0),
34 HINIC_RX_MODE_MC = BIT(1),
35 HINIC_RX_MODE_BC = BIT(2),
36 HINIC_RX_MODE_MC_ALL = BIT(3),
37 HINIC_RX_MODE_PROMISC = BIT(4),
38};
39
40enum hinic_port_link_state {
41 HINIC_LINK_STATE_DOWN,
42 HINIC_LINK_STATE_UP,
43};
44
45enum hinic_port_state {
46 HINIC_PORT_DISABLE = 0,
47 HINIC_PORT_ENABLE = 3,
48};
49
50enum hinic_func_port_state {
51 HINIC_FUNC_PORT_DISABLE = 0,
52 HINIC_FUNC_PORT_ENABLE = 2,
53};
54
55enum hinic_autoneg_cap {
56 HINIC_AUTONEG_UNSUPPORTED,
57 HINIC_AUTONEG_SUPPORTED,
58};
59
60enum hinic_autoneg_state {
61 HINIC_AUTONEG_DISABLED,
62 HINIC_AUTONEG_ACTIVE,
63};
64
65enum hinic_duplex {
66 HINIC_DUPLEX_HALF,
67 HINIC_DUPLEX_FULL,
68};
69
70enum hinic_speed {
71 HINIC_SPEED_10MB_LINK = 0,
72 HINIC_SPEED_100MB_LINK,
73 HINIC_SPEED_1000MB_LINK,
74 HINIC_SPEED_10GB_LINK,
75 HINIC_SPEED_25GB_LINK,
76 HINIC_SPEED_40GB_LINK,
77 HINIC_SPEED_100GB_LINK,
78
79 HINIC_SPEED_UNKNOWN = 0xFF,
80};
81
82enum hinic_tso_state {
83 HINIC_TSO_DISABLE = 0,
84 HINIC_TSO_ENABLE = 1,
85};
86
87struct hinic_port_mac_cmd {
88 u8 status;
89 u8 version;
90 u8 rsvd0[6];
91
92 u16 func_idx;
93 u16 vlan_id;
94 u16 rsvd1;
95 unsigned char mac[ETH_ALEN];
96};
97
98struct hinic_port_mtu_cmd {
99 u8 status;
100 u8 version;
101 u8 rsvd0[6];
102
103 u16 func_idx;
104 u16 rsvd1;
105 u32 mtu;
106};
107
108struct hinic_port_vlan_cmd {
109 u8 status;
110 u8 version;
111 u8 rsvd0[6];
112
113 u16 func_idx;
114 u16 vlan_id;
115};
116
117struct hinic_port_rx_mode_cmd {
118 u8 status;
119 u8 version;
120 u8 rsvd0[6];
121
122 u16 func_idx;
123 u16 rsvd;
124 u32 rx_mode;
125};
126
127struct hinic_port_link_cmd {
128 u8 status;
129 u8 version;
130 u8 rsvd0[6];
131
132 u16 func_idx;
133 u8 state;
134 u8 rsvd1;
135};
136
137struct hinic_port_state_cmd {
138 u8 status;
139 u8 version;
140 u8 rsvd0[6];
141
142 u8 state;
143 u8 rsvd1[3];
144};
145
146struct hinic_port_link_status {
147 u8 status;
148 u8 version;
149 u8 rsvd0[6];
150
151 u16 rsvd1;
152 u8 link;
153 u8 rsvd2;
154};
155
156struct hinic_port_func_state_cmd {
157 u8 status;
158 u8 version;
159 u8 rsvd0[6];
160
161 u16 func_idx;
162 u16 rsvd1;
163 u8 state;
164 u8 rsvd2[3];
165};
166
167struct hinic_port_cap {
168 u8 status;
169 u8 version;
170 u8 rsvd0[6];
171
172 u16 func_idx;
173 u16 rsvd1;
174 u8 port_type;
175 u8 autoneg_cap;
176 u8 autoneg_state;
177 u8 duplex;
178 u8 speed;
179 u8 rsvd2[3];
180};
181
182struct hinic_tso_config {
183 u8 status;
184 u8 version;
185 u8 rsvd0[6];
186
187 u16 func_id;
188 u16 rsvd1;
189 u8 tso_en;
190 u8 resv2[3];
191};
192
193struct hinic_checksum_offload {
194 u8 status;
195 u8 version;
196 u8 rsvd0[6];
197
198 u16 func_id;
199 u16 rsvd1;
200 u32 rx_csum_offload;
201};
202
203struct hinic_rq_num {
204 u8 status;
205 u8 version;
206 u8 rsvd0[6];
207
208 u16 func_id;
209 u16 rsvd1[33];
210 u32 num_rqs;
211 u32 rq_depth;
212};
213
214struct hinic_lro_config {
215 u8 status;
216 u8 version;
217 u8 rsvd0[6];
218
219 u16 func_id;
220 u16 rsvd1;
221 u8 lro_ipv4_en;
222 u8 lro_ipv6_en;
223 u8 lro_max_wqe_num;
224 u8 resv2[13];
225};
226
227struct hinic_lro_timer {
228 u8 status;
229 u8 version;
230 u8 rsvd0[6];
231
232 u8 type; /* 0: set timer value, 1: get timer value */
233 u8 enable; /* when set lro time, enable should be 1 */
234 u16 rsvd1;
235 u32 timer;
236};
237
238struct hinic_vlan_cfg {
239 u8 status;
240 u8 version;
241 u8 rsvd0[6];
242
243 u16 func_id;
244 u8 vlan_rx_offload;
245 u8 rsvd1[5];
246};
247
248struct hinic_rss_template_mgmt {
249 u8 status;
250 u8 version;
251 u8 rsvd0[6];
252
253 u16 func_id;
254 u8 cmd;
255 u8 template_id;
256 u8 rsvd1[4];
257};
258
259struct hinic_rss_template_key {
260 u8 status;
261 u8 version;
262 u8 rsvd0[6];
263
264 u16 func_id;
265 u8 template_id;
266 u8 rsvd1;
267 u8 key[HINIC_RSS_KEY_SIZE];
268};
269
270struct hinic_rss_context_tbl {
271 u32 group_index;
272 u32 offset;
273 u32 size;
274 u32 rsvd;
275 u32 ctx;
276};
277
278struct hinic_rss_context_table {
279 u8 status;
280 u8 version;
281 u8 rsvd0[6];
282
283 u16 func_id;
284 u8 template_id;
285 u8 rsvd1;
286 u32 context;
287};
288
289struct hinic_rss_indirect_tbl {
290 u32 group_index;
291 u32 offset;
292 u32 size;
293 u32 rsvd;
294 u8 entry[HINIC_RSS_INDIR_SIZE];
295};
296
297struct hinic_rss_indir_table {
298 u8 status;
299 u8 version;
300 u8 rsvd0[6];
301
302 u16 func_id;
303 u8 template_id;
304 u8 rsvd1;
305 u8 indir[HINIC_RSS_INDIR_SIZE];
306};
307
308struct hinic_rss_key {
309 u8 status;
310 u8 version;
311 u8 rsvd0[6];
312
313 u16 func_id;
314 u8 template_id;
315 u8 rsvd1;
316 u8 key[HINIC_RSS_KEY_SIZE];
317};
318
319struct hinic_rss_engine_type {
320 u8 status;
321 u8 version;
322 u8 rsvd0[6];
323
324 u16 func_id;
325 u8 template_id;
326 u8 hash_engine;
327 u8 rsvd1[4];
328};
329
330struct hinic_rss_config {
331 u8 status;
332 u8 version;
333 u8 rsvd0[6];
334
335 u16 func_id;
336 u8 rss_en;
337 u8 template_id;
338 u8 rq_priority_number;
339 u8 rsvd1[11];
340};
341
342struct hinic_stats {
343 char name[ETH_GSTRING_LEN];
344 u32 size;
345 int offset;
346};
347
348struct hinic_vport_stats {
349 u64 tx_unicast_pkts_vport;
350 u64 tx_unicast_bytes_vport;
351 u64 tx_multicast_pkts_vport;
352 u64 tx_multicast_bytes_vport;
353 u64 tx_broadcast_pkts_vport;
354 u64 tx_broadcast_bytes_vport;
355
356 u64 rx_unicast_pkts_vport;
357 u64 rx_unicast_bytes_vport;
358 u64 rx_multicast_pkts_vport;
359 u64 rx_multicast_bytes_vport;
360 u64 rx_broadcast_pkts_vport;
361 u64 rx_broadcast_bytes_vport;
362
363 u64 tx_discard_vport;
364 u64 rx_discard_vport;
365 u64 tx_err_vport;
366 u64 rx_err_vport;
367};
368
369struct hinic_phy_port_stats {
370 u64 mac_rx_total_pkt_num;
371 u64 mac_rx_total_oct_num;
372 u64 mac_rx_bad_pkt_num;
373 u64 mac_rx_bad_oct_num;
374 u64 mac_rx_good_pkt_num;
375 u64 mac_rx_good_oct_num;
376 u64 mac_rx_uni_pkt_num;
377 u64 mac_rx_multi_pkt_num;
378 u64 mac_rx_broad_pkt_num;
379
380 u64 mac_tx_total_pkt_num;
381 u64 mac_tx_total_oct_num;
382 u64 mac_tx_bad_pkt_num;
383 u64 mac_tx_bad_oct_num;
384 u64 mac_tx_good_pkt_num;
385 u64 mac_tx_good_oct_num;
386 u64 mac_tx_uni_pkt_num;
387 u64 mac_tx_multi_pkt_num;
388 u64 mac_tx_broad_pkt_num;
389
390 u64 mac_rx_fragment_pkt_num;
391 u64 mac_rx_undersize_pkt_num;
392 u64 mac_rx_undermin_pkt_num;
393 u64 mac_rx_64_oct_pkt_num;
394 u64 mac_rx_65_127_oct_pkt_num;
395 u64 mac_rx_128_255_oct_pkt_num;
396 u64 mac_rx_256_511_oct_pkt_num;
397 u64 mac_rx_512_1023_oct_pkt_num;
398 u64 mac_rx_1024_1518_oct_pkt_num;
399 u64 mac_rx_1519_2047_oct_pkt_num;
400 u64 mac_rx_2048_4095_oct_pkt_num;
401 u64 mac_rx_4096_8191_oct_pkt_num;
402 u64 mac_rx_8192_9216_oct_pkt_num;
403 u64 mac_rx_9217_12287_oct_pkt_num;
404 u64 mac_rx_12288_16383_oct_pkt_num;
405 u64 mac_rx_1519_max_bad_pkt_num;
406 u64 mac_rx_1519_max_good_pkt_num;
407 u64 mac_rx_oversize_pkt_num;
408 u64 mac_rx_jabber_pkt_num;
409
410 u64 mac_rx_pause_num;
411 u64 mac_rx_pfc_pkt_num;
412 u64 mac_rx_pfc_pri0_pkt_num;
413 u64 mac_rx_pfc_pri1_pkt_num;
414 u64 mac_rx_pfc_pri2_pkt_num;
415 u64 mac_rx_pfc_pri3_pkt_num;
416 u64 mac_rx_pfc_pri4_pkt_num;
417 u64 mac_rx_pfc_pri5_pkt_num;
418 u64 mac_rx_pfc_pri6_pkt_num;
419 u64 mac_rx_pfc_pri7_pkt_num;
420 u64 mac_rx_control_pkt_num;
421 u64 mac_rx_y1731_pkt_num;
422 u64 mac_rx_sym_err_pkt_num;
423 u64 mac_rx_fcs_err_pkt_num;
424 u64 mac_rx_send_app_good_pkt_num;
425 u64 mac_rx_send_app_bad_pkt_num;
426
427 u64 mac_tx_fragment_pkt_num;
428 u64 mac_tx_undersize_pkt_num;
429 u64 mac_tx_undermin_pkt_num;
430 u64 mac_tx_64_oct_pkt_num;
431 u64 mac_tx_65_127_oct_pkt_num;
432 u64 mac_tx_128_255_oct_pkt_num;
433 u64 mac_tx_256_511_oct_pkt_num;
434 u64 mac_tx_512_1023_oct_pkt_num;
435 u64 mac_tx_1024_1518_oct_pkt_num;
436 u64 mac_tx_1519_2047_oct_pkt_num;
437 u64 mac_tx_2048_4095_oct_pkt_num;
438 u64 mac_tx_4096_8191_oct_pkt_num;
439 u64 mac_tx_8192_9216_oct_pkt_num;
440 u64 mac_tx_9217_12287_oct_pkt_num;
441 u64 mac_tx_12288_16383_oct_pkt_num;
442 u64 mac_tx_1519_max_bad_pkt_num;
443 u64 mac_tx_1519_max_good_pkt_num;
444 u64 mac_tx_oversize_pkt_num;
445 u64 mac_tx_jabber_pkt_num;
446
447 u64 mac_tx_pause_num;
448 u64 mac_tx_pfc_pkt_num;
449 u64 mac_tx_pfc_pri0_pkt_num;
450 u64 mac_tx_pfc_pri1_pkt_num;
451 u64 mac_tx_pfc_pri2_pkt_num;
452 u64 mac_tx_pfc_pri3_pkt_num;
453 u64 mac_tx_pfc_pri4_pkt_num;
454 u64 mac_tx_pfc_pri5_pkt_num;
455 u64 mac_tx_pfc_pri6_pkt_num;
456 u64 mac_tx_pfc_pri7_pkt_num;
457 u64 mac_tx_control_pkt_num;
458 u64 mac_tx_y1731_pkt_num;
459 u64 mac_tx_1588_pkt_num;
460 u64 mac_tx_err_all_pkt_num;
461 u64 mac_tx_from_app_good_pkt_num;
462 u64 mac_tx_from_app_bad_pkt_num;
463
464 u64 mac_rx_higig2_ext_pkt_num;
465 u64 mac_rx_higig2_message_pkt_num;
466 u64 mac_rx_higig2_error_pkt_num;
467 u64 mac_rx_higig2_cpu_ctrl_pkt_num;
468 u64 mac_rx_higig2_unicast_pkt_num;
469 u64 mac_rx_higig2_broadcast_pkt_num;
470 u64 mac_rx_higig2_l2_multicast_pkt_num;
471 u64 mac_rx_higig2_l3_multicast_pkt_num;
472
473 u64 mac_tx_higig2_message_pkt_num;
474 u64 mac_tx_higig2_ext_pkt_num;
475 u64 mac_tx_higig2_cpu_ctrl_pkt_num;
476 u64 mac_tx_higig2_unicast_pkt_num;
477 u64 mac_tx_higig2_broadcast_pkt_num;
478 u64 mac_tx_higig2_l2_multicast_pkt_num;
479 u64 mac_tx_higig2_l3_multicast_pkt_num;
480};
481
482struct hinic_port_stats_info {
483 u8 status;
484 u8 version;
485 u8 rsvd0[6];
486
487 u16 func_id;
488 u16 rsvd1;
489 u32 stats_version;
490 u32 stats_size;
491};
492
493struct hinic_port_stats {
494 u8 status;
495 u8 version;
496 u8 rsvd[6];
497
498 struct hinic_phy_port_stats stats;
499};
500
501struct hinic_cmd_vport_stats {
502 u8 status;
503 u8 version;
504 u8 rsvd0[6];
505
506 struct hinic_vport_stats stats;
507};
508
509int hinic_port_add_mac(struct hinic_dev *nic_dev, const u8 *addr,
510 u16 vlan_id);
511
512int hinic_port_del_mac(struct hinic_dev *nic_dev, const u8 *addr,
513 u16 vlan_id);
514
515int hinic_port_get_mac(struct hinic_dev *nic_dev, u8 *addr);
516
517int hinic_port_set_mtu(struct hinic_dev *nic_dev, int new_mtu);
518
519int hinic_port_add_vlan(struct hinic_dev *nic_dev, u16 vlan_id);
520
521int hinic_port_del_vlan(struct hinic_dev *nic_dev, u16 vlan_id);
522
523int hinic_port_set_rx_mode(struct hinic_dev *nic_dev, u32 rx_mode);
524
525int hinic_port_link_state(struct hinic_dev *nic_dev,
526 enum hinic_port_link_state *link_state);
527
528int hinic_port_set_state(struct hinic_dev *nic_dev,
529 enum hinic_port_state state);
530
531int hinic_port_set_func_state(struct hinic_dev *nic_dev,
532 enum hinic_func_port_state state);
533
534int hinic_port_get_cap(struct hinic_dev *nic_dev,
535 struct hinic_port_cap *port_cap);
536
537int hinic_set_max_qnum(struct hinic_dev *nic_dev, u8 num_rqs);
538
539int hinic_port_set_tso(struct hinic_dev *nic_dev, enum hinic_tso_state state);
540
541int hinic_set_rx_csum_offload(struct hinic_dev *nic_dev, u32 en);
542
543int hinic_set_rx_lro_state(struct hinic_dev *nic_dev, u8 lro_en,
544 u32 lro_timer, u32 wqe_num);
545
546int hinic_set_rss_type(struct hinic_dev *nic_dev, u32 tmpl_idx,
547 struct hinic_rss_type rss_type);
548
549int hinic_rss_set_indir_tbl(struct hinic_dev *nic_dev, u32 tmpl_idx,
550 const u32 *indir_table);
551
552int hinic_rss_set_template_tbl(struct hinic_dev *nic_dev, u32 template_id,
553 const u8 *temp);
554
555int hinic_rss_set_hash_engine(struct hinic_dev *nic_dev, u8 template_id,
556 u8 type);
557
558int hinic_rss_cfg(struct hinic_dev *nic_dev, u8 rss_en, u8 template_id);
559
560int hinic_rss_template_alloc(struct hinic_dev *nic_dev, u8 *tmpl_idx);
561
562int hinic_rss_template_free(struct hinic_dev *nic_dev, u8 tmpl_idx);
563
564void hinic_set_ethtool_ops(struct net_device *netdev);
565
566int hinic_get_rss_type(struct hinic_dev *nic_dev, u32 tmpl_idx,
567 struct hinic_rss_type *rss_type);
568
569int hinic_rss_get_indir_tbl(struct hinic_dev *nic_dev, u32 tmpl_idx,
570 u32 *indir_table);
571
572int hinic_rss_get_template_tbl(struct hinic_dev *nic_dev, u32 tmpl_idx,
573 u8 *temp);
574
575int hinic_rss_get_hash_engine(struct hinic_dev *nic_dev, u8 tmpl_idx,
576 u8 *type);
577
578int hinic_get_phy_port_stats(struct hinic_dev *nic_dev,
579 struct hinic_phy_port_stats *stats);
580
581int hinic_get_vport_stats(struct hinic_dev *nic_dev,
582 struct hinic_vport_stats *stats);
583
584int hinic_set_rx_vlan_offload(struct hinic_dev *nic_dev, u8 en);
585
586int hinic_get_mgmt_version(struct hinic_dev *nic_dev, u8 *mgmt_ver);
587
588#endif