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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * CAN bus driver for the Freescale MPC5xxx embedded CPU.
4 *
5 * Copyright (C) 2004-2005 Andrey Volkov <avolkov@varma-el.com>,
6 * Varma Electronics Oy
7 * Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com>
8 * Copyright (C) 2009 Wolfram Sang, Pengutronix <kernel@pengutronix.de>
9 */
10
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/interrupt.h>
14#include <linux/platform_device.h>
15#include <linux/property.h>
16#include <linux/netdevice.h>
17#include <linux/can/dev.h>
18#include <linux/of.h>
19#include <linux/of_address.h>
20#include <linux/of_irq.h>
21#include <linux/of_platform.h>
22#include <sysdev/fsl_soc.h>
23#include <linux/clk.h>
24#include <linux/io.h>
25#include <asm/mpc52xx.h>
26
27#include "mscan.h"
28
29#define DRV_NAME "mpc5xxx_can"
30
31struct mpc5xxx_can_data {
32 unsigned int type;
33 u32 (*get_clock)(struct platform_device *ofdev, const char *clock_name,
34 int *mscan_clksrc);
35 void (*put_clock)(struct platform_device *ofdev);
36};
37
38#ifdef CONFIG_PPC_MPC52xx
39static const struct of_device_id mpc52xx_cdm_ids[] = {
40 { .compatible = "fsl,mpc5200-cdm", },
41 {}
42};
43
44static u32 mpc52xx_can_get_clock(struct platform_device *ofdev,
45 const char *clock_name, int *mscan_clksrc)
46{
47 unsigned int pvr;
48 struct mpc52xx_cdm __iomem *cdm;
49 struct device_node *np_cdm;
50 unsigned int freq;
51 u32 val;
52
53 pvr = mfspr(SPRN_PVR);
54
55 /*
56 * Either the oscillator clock (SYS_XTAL_IN) or the IP bus clock
57 * (IP_CLK) can be selected as MSCAN clock source. According to
58 * the MPC5200 user's manual, the oscillator clock is the better
59 * choice as it has less jitter. For this reason, it is selected
60 * by default. Unfortunately, it can not be selected for the old
61 * MPC5200 Rev. A chips due to a hardware bug (check errata).
62 */
63 if (clock_name && strcmp(clock_name, "ip") == 0)
64 *mscan_clksrc = MSCAN_CLKSRC_BUS;
65 else
66 *mscan_clksrc = MSCAN_CLKSRC_XTAL;
67
68 freq = mpc5xxx_get_bus_frequency(&ofdev->dev);
69 if (!freq)
70 return 0;
71
72 if (*mscan_clksrc == MSCAN_CLKSRC_BUS || pvr == 0x80822011)
73 return freq;
74
75 /* Determine SYS_XTAL_IN frequency from the clock domain settings */
76 np_cdm = of_find_matching_node(NULL, mpc52xx_cdm_ids);
77 if (!np_cdm) {
78 dev_err(&ofdev->dev, "can't get clock node!\n");
79 return 0;
80 }
81 cdm = of_iomap(np_cdm, 0);
82 if (!cdm) {
83 of_node_put(np_cdm);
84 dev_err(&ofdev->dev, "can't map clock node!\n");
85 return 0;
86 }
87
88 if (in_8(&cdm->ipb_clk_sel) & 0x1)
89 freq *= 2;
90 val = in_be32(&cdm->rstcfg);
91
92 freq *= (val & (1 << 5)) ? 8 : 4;
93 freq /= (val & (1 << 6)) ? 12 : 16;
94
95 of_node_put(np_cdm);
96 iounmap(cdm);
97
98 return freq;
99}
100#else /* !CONFIG_PPC_MPC52xx */
101static u32 mpc52xx_can_get_clock(struct platform_device *ofdev,
102 const char *clock_name, int *mscan_clksrc)
103{
104 return 0;
105}
106#endif /* CONFIG_PPC_MPC52xx */
107
108#ifdef CONFIG_PPC_MPC512x
109static u32 mpc512x_can_get_clock(struct platform_device *ofdev,
110 const char *clock_source, int *mscan_clksrc)
111{
112 struct device_node *np;
113 u32 clockdiv;
114 enum {
115 CLK_FROM_AUTO,
116 CLK_FROM_IPS,
117 CLK_FROM_SYS,
118 CLK_FROM_REF,
119 } clk_from;
120 struct clk *clk_in, *clk_can;
121 unsigned long freq_calc;
122 struct mscan_priv *priv;
123 struct clk *clk_ipg;
124
125 /* the caller passed in the clock source spec that was read from
126 * the device tree, get the optional clock divider as well
127 */
128 np = ofdev->dev.of_node;
129 clockdiv = 1;
130 of_property_read_u32(np, "fsl,mscan-clock-divider", &clockdiv);
131 dev_dbg(&ofdev->dev, "device tree specs: clk src[%s] div[%d]\n",
132 clock_source ? clock_source : "<NULL>", clockdiv);
133
134 /* when clock-source is 'ip', the CANCTL1[CLKSRC] bit needs to
135 * get set, and the 'ips' clock is the input to the MSCAN
136 * component
137 *
138 * for clock-source values of 'ref' or 'sys' the CANCTL1[CLKSRC]
139 * bit needs to get cleared, an optional clock-divider may have
140 * been specified (the default value is 1), the appropriate
141 * MSCAN related MCLK is the input to the MSCAN component
142 *
143 * in the absence of a clock-source spec, first an optimal clock
144 * gets determined based on the 'sys' clock, if that fails the
145 * 'ref' clock is used
146 */
147 clk_from = CLK_FROM_AUTO;
148 if (clock_source) {
149 /* interpret the device tree's spec for the clock source */
150 if (!strcmp(clock_source, "ip"))
151 clk_from = CLK_FROM_IPS;
152 else if (!strcmp(clock_source, "sys"))
153 clk_from = CLK_FROM_SYS;
154 else if (!strcmp(clock_source, "ref"))
155 clk_from = CLK_FROM_REF;
156 else
157 goto err_invalid;
158 dev_dbg(&ofdev->dev, "got a clk source spec[%d]\n", clk_from);
159 }
160 if (clk_from == CLK_FROM_AUTO) {
161 /* no spec so far, try the 'sys' clock; round to the
162 * next MHz and see if we can get a multiple of 16MHz
163 */
164 dev_dbg(&ofdev->dev, "no clk source spec, trying SYS\n");
165 clk_in = devm_clk_get(&ofdev->dev, "sys");
166 if (IS_ERR(clk_in))
167 goto err_notavail;
168 freq_calc = clk_get_rate(clk_in);
169 freq_calc += 499999;
170 freq_calc /= 1000000;
171 freq_calc *= 1000000;
172 if ((freq_calc % 16000000) == 0) {
173 clk_from = CLK_FROM_SYS;
174 clockdiv = freq_calc / 16000000;
175 dev_dbg(&ofdev->dev,
176 "clk fit, sys[%lu] div[%d] freq[%lu]\n",
177 freq_calc, clockdiv, freq_calc / clockdiv);
178 }
179 }
180 if (clk_from == CLK_FROM_AUTO) {
181 /* no spec so far, use the 'ref' clock */
182 dev_dbg(&ofdev->dev, "no clk source spec, trying REF\n");
183 clk_in = devm_clk_get(&ofdev->dev, "ref");
184 if (IS_ERR(clk_in))
185 goto err_notavail;
186 clk_from = CLK_FROM_REF;
187 freq_calc = clk_get_rate(clk_in);
188 dev_dbg(&ofdev->dev,
189 "clk fit, ref[%lu] (no div) freq[%lu]\n",
190 freq_calc, freq_calc);
191 }
192
193 /* select IPS or MCLK as the MSCAN input (returned to the caller),
194 * setup the MCLK mux source and rate if applicable, apply the
195 * optionally specified or derived above divider, and determine
196 * the actual resulting clock rate to return to the caller
197 */
198 switch (clk_from) {
199 case CLK_FROM_IPS:
200 clk_can = devm_clk_get(&ofdev->dev, "ips");
201 if (IS_ERR(clk_can))
202 goto err_notavail;
203 priv = netdev_priv(dev_get_drvdata(&ofdev->dev));
204 priv->clk_can = clk_can;
205 freq_calc = clk_get_rate(clk_can);
206 *mscan_clksrc = MSCAN_CLKSRC_IPS;
207 dev_dbg(&ofdev->dev, "clk from IPS, clksrc[%d] freq[%lu]\n",
208 *mscan_clksrc, freq_calc);
209 break;
210 case CLK_FROM_SYS:
211 case CLK_FROM_REF:
212 clk_can = devm_clk_get(&ofdev->dev, "mclk");
213 if (IS_ERR(clk_can))
214 goto err_notavail;
215 priv = netdev_priv(dev_get_drvdata(&ofdev->dev));
216 priv->clk_can = clk_can;
217 if (clk_from == CLK_FROM_SYS)
218 clk_in = devm_clk_get(&ofdev->dev, "sys");
219 if (clk_from == CLK_FROM_REF)
220 clk_in = devm_clk_get(&ofdev->dev, "ref");
221 if (IS_ERR(clk_in))
222 goto err_notavail;
223 clk_set_parent(clk_can, clk_in);
224 freq_calc = clk_get_rate(clk_in);
225 freq_calc /= clockdiv;
226 clk_set_rate(clk_can, freq_calc);
227 freq_calc = clk_get_rate(clk_can);
228 *mscan_clksrc = MSCAN_CLKSRC_BUS;
229 dev_dbg(&ofdev->dev, "clk from MCLK, clksrc[%d] freq[%lu]\n",
230 *mscan_clksrc, freq_calc);
231 break;
232 default:
233 goto err_invalid;
234 }
235
236 /* the above clk_can item is used for the bitrate, access to
237 * the peripheral's register set needs the clk_ipg item
238 */
239 clk_ipg = devm_clk_get(&ofdev->dev, "ipg");
240 if (IS_ERR(clk_ipg))
241 goto err_notavail_ipg;
242 if (clk_prepare_enable(clk_ipg))
243 goto err_notavail_ipg;
244 priv = netdev_priv(dev_get_drvdata(&ofdev->dev));
245 priv->clk_ipg = clk_ipg;
246
247 /* return the determined clock source rate */
248 return freq_calc;
249
250err_invalid:
251 dev_err(&ofdev->dev, "invalid clock source specification\n");
252 /* clock source rate could not get determined */
253 return 0;
254
255err_notavail:
256 dev_err(&ofdev->dev, "cannot acquire or setup bitrate clock source\n");
257 /* clock source rate could not get determined */
258 return 0;
259
260err_notavail_ipg:
261 dev_err(&ofdev->dev, "cannot acquire or setup register clock\n");
262 /* clock source rate could not get determined */
263 return 0;
264}
265
266static void mpc512x_can_put_clock(struct platform_device *ofdev)
267{
268 struct mscan_priv *priv;
269
270 priv = netdev_priv(dev_get_drvdata(&ofdev->dev));
271 if (priv->clk_ipg)
272 clk_disable_unprepare(priv->clk_ipg);
273}
274#else /* !CONFIG_PPC_MPC512x */
275static u32 mpc512x_can_get_clock(struct platform_device *ofdev,
276 const char *clock_name, int *mscan_clksrc)
277{
278 return 0;
279}
280#define mpc512x_can_put_clock NULL
281#endif /* CONFIG_PPC_MPC512x */
282
283static const struct of_device_id mpc5xxx_can_table[];
284static int mpc5xxx_can_probe(struct platform_device *ofdev)
285{
286 const struct mpc5xxx_can_data *data;
287 struct device_node *np = ofdev->dev.of_node;
288 struct net_device *dev;
289 struct mscan_priv *priv;
290 void __iomem *base;
291 const char *clock_name = NULL;
292 int irq, mscan_clksrc = 0;
293 int err = -ENOMEM;
294
295 data = device_get_match_data(&ofdev->dev);
296 if (!data)
297 return -EINVAL;
298
299 base = of_iomap(np, 0);
300 if (!base)
301 return dev_err_probe(&ofdev->dev, err, "couldn't ioremap\n");
302
303 irq = irq_of_parse_and_map(np, 0);
304 if (!irq) {
305 dev_err(&ofdev->dev, "no irq found\n");
306 err = -ENODEV;
307 goto exit_unmap_mem;
308 }
309
310 dev = alloc_mscandev();
311 if (!dev)
312 goto exit_dispose_irq;
313 platform_set_drvdata(ofdev, dev);
314 SET_NETDEV_DEV(dev, &ofdev->dev);
315
316 priv = netdev_priv(dev);
317 priv->reg_base = base;
318 dev->irq = irq;
319
320 clock_name = of_get_property(np, "fsl,mscan-clock-source", NULL);
321
322 priv->type = data->type;
323 priv->can.clock.freq = data->get_clock(ofdev, clock_name,
324 &mscan_clksrc);
325 if (!priv->can.clock.freq) {
326 dev_err(&ofdev->dev, "couldn't get MSCAN clock properties\n");
327 goto exit_put_clock;
328 }
329
330 err = register_mscandev(dev, mscan_clksrc);
331 if (err) {
332 dev_err(&ofdev->dev, "registering %s failed (err=%d)\n",
333 DRV_NAME, err);
334 goto exit_put_clock;
335 }
336
337 dev_info(&ofdev->dev, "MSCAN at 0x%p, irq %d, clock %d Hz\n",
338 priv->reg_base, dev->irq, priv->can.clock.freq);
339
340 return 0;
341
342exit_put_clock:
343 if (data->put_clock)
344 data->put_clock(ofdev);
345 free_candev(dev);
346exit_dispose_irq:
347 irq_dispose_mapping(irq);
348exit_unmap_mem:
349 iounmap(base);
350
351 return err;
352}
353
354static void mpc5xxx_can_remove(struct platform_device *ofdev)
355{
356 const struct mpc5xxx_can_data *data;
357 struct net_device *dev = platform_get_drvdata(ofdev);
358 struct mscan_priv *priv = netdev_priv(dev);
359
360 data = device_get_match_data(&ofdev->dev);
361
362 unregister_mscandev(dev);
363 if (data && data->put_clock)
364 data->put_clock(ofdev);
365 iounmap(priv->reg_base);
366 irq_dispose_mapping(dev->irq);
367 free_candev(dev);
368}
369
370#ifdef CONFIG_PM
371static struct mscan_regs saved_regs;
372static int mpc5xxx_can_suspend(struct platform_device *ofdev, pm_message_t state)
373{
374 struct net_device *dev = platform_get_drvdata(ofdev);
375 struct mscan_priv *priv = netdev_priv(dev);
376 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
377
378 _memcpy_fromio(&saved_regs, regs, sizeof(*regs));
379
380 return 0;
381}
382
383static int mpc5xxx_can_resume(struct platform_device *ofdev)
384{
385 struct net_device *dev = platform_get_drvdata(ofdev);
386 struct mscan_priv *priv = netdev_priv(dev);
387 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
388
389 regs->canctl0 |= MSCAN_INITRQ;
390 while (!(regs->canctl1 & MSCAN_INITAK))
391 udelay(10);
392
393 regs->canctl1 = saved_regs.canctl1;
394 regs->canbtr0 = saved_regs.canbtr0;
395 regs->canbtr1 = saved_regs.canbtr1;
396 regs->canidac = saved_regs.canidac;
397
398 /* restore masks, buffers etc. */
399 _memcpy_toio(®s->canidar1_0, (void *)&saved_regs.canidar1_0,
400 sizeof(*regs) - offsetof(struct mscan_regs, canidar1_0));
401
402 regs->canctl0 &= ~MSCAN_INITRQ;
403 regs->cantbsel = saved_regs.cantbsel;
404 regs->canrier = saved_regs.canrier;
405 regs->cantier = saved_regs.cantier;
406 regs->canctl0 = saved_regs.canctl0;
407
408 return 0;
409}
410#endif
411
412static const struct mpc5xxx_can_data mpc5200_can_data = {
413 .type = MSCAN_TYPE_MPC5200,
414 .get_clock = mpc52xx_can_get_clock,
415 /* .put_clock not applicable */
416};
417
418static const struct mpc5xxx_can_data mpc5121_can_data = {
419 .type = MSCAN_TYPE_MPC5121,
420 .get_clock = mpc512x_can_get_clock,
421 .put_clock = mpc512x_can_put_clock,
422};
423
424static const struct of_device_id mpc5xxx_can_table[] = {
425 { .compatible = "fsl,mpc5200-mscan", .data = &mpc5200_can_data, },
426 /* Note that only MPC5121 Rev. 2 (and later) is supported */
427 { .compatible = "fsl,mpc5121-mscan", .data = &mpc5121_can_data, },
428 {},
429};
430MODULE_DEVICE_TABLE(of, mpc5xxx_can_table);
431
432static struct platform_driver mpc5xxx_can_driver = {
433 .driver = {
434 .name = "mpc5xxx_can",
435 .of_match_table = mpc5xxx_can_table,
436 },
437 .probe = mpc5xxx_can_probe,
438 .remove = mpc5xxx_can_remove,
439#ifdef CONFIG_PM
440 .suspend = mpc5xxx_can_suspend,
441 .resume = mpc5xxx_can_resume,
442#endif
443};
444
445module_platform_driver(mpc5xxx_can_driver);
446
447MODULE_AUTHOR("Wolfgang Grandegger <wg@grandegger.com>");
448MODULE_DESCRIPTION("Freescale MPC5xxx CAN driver");
449MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * CAN bus driver for the Freescale MPC5xxx embedded CPU.
4 *
5 * Copyright (C) 2004-2005 Andrey Volkov <avolkov@varma-el.com>,
6 * Varma Electronics Oy
7 * Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com>
8 * Copyright (C) 2009 Wolfram Sang, Pengutronix <w.sang@pengutronix.de>
9 */
10
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/interrupt.h>
14#include <linux/platform_device.h>
15#include <linux/netdevice.h>
16#include <linux/can/dev.h>
17#include <linux/of_platform.h>
18#include <sysdev/fsl_soc.h>
19#include <linux/clk.h>
20#include <linux/io.h>
21#include <asm/mpc52xx.h>
22
23#include "mscan.h"
24
25#define DRV_NAME "mpc5xxx_can"
26
27struct mpc5xxx_can_data {
28 unsigned int type;
29 u32 (*get_clock)(struct platform_device *ofdev, const char *clock_name,
30 int *mscan_clksrc);
31 void (*put_clock)(struct platform_device *ofdev);
32};
33
34#ifdef CONFIG_PPC_MPC52xx
35static const struct of_device_id mpc52xx_cdm_ids[] = {
36 { .compatible = "fsl,mpc5200-cdm", },
37 {}
38};
39
40static u32 mpc52xx_can_get_clock(struct platform_device *ofdev,
41 const char *clock_name, int *mscan_clksrc)
42{
43 unsigned int pvr;
44 struct mpc52xx_cdm __iomem *cdm;
45 struct device_node *np_cdm;
46 unsigned int freq;
47 u32 val;
48
49 pvr = mfspr(SPRN_PVR);
50
51 /*
52 * Either the oscillator clock (SYS_XTAL_IN) or the IP bus clock
53 * (IP_CLK) can be selected as MSCAN clock source. According to
54 * the MPC5200 user's manual, the oscillator clock is the better
55 * choice as it has less jitter. For this reason, it is selected
56 * by default. Unfortunately, it can not be selected for the old
57 * MPC5200 Rev. A chips due to a hardware bug (check errata).
58 */
59 if (clock_name && strcmp(clock_name, "ip") == 0)
60 *mscan_clksrc = MSCAN_CLKSRC_BUS;
61 else
62 *mscan_clksrc = MSCAN_CLKSRC_XTAL;
63
64 freq = mpc5xxx_get_bus_frequency(ofdev->dev.of_node);
65 if (!freq)
66 return 0;
67
68 if (*mscan_clksrc == MSCAN_CLKSRC_BUS || pvr == 0x80822011)
69 return freq;
70
71 /* Determine SYS_XTAL_IN frequency from the clock domain settings */
72 np_cdm = of_find_matching_node(NULL, mpc52xx_cdm_ids);
73 if (!np_cdm) {
74 dev_err(&ofdev->dev, "can't get clock node!\n");
75 return 0;
76 }
77 cdm = of_iomap(np_cdm, 0);
78 if (!cdm) {
79 of_node_put(np_cdm);
80 dev_err(&ofdev->dev, "can't map clock node!\n");
81 return 0;
82 }
83
84 if (in_8(&cdm->ipb_clk_sel) & 0x1)
85 freq *= 2;
86 val = in_be32(&cdm->rstcfg);
87
88 freq *= (val & (1 << 5)) ? 8 : 4;
89 freq /= (val & (1 << 6)) ? 12 : 16;
90
91 of_node_put(np_cdm);
92 iounmap(cdm);
93
94 return freq;
95}
96#else /* !CONFIG_PPC_MPC52xx */
97static u32 mpc52xx_can_get_clock(struct platform_device *ofdev,
98 const char *clock_name, int *mscan_clksrc)
99{
100 return 0;
101}
102#endif /* CONFIG_PPC_MPC52xx */
103
104#ifdef CONFIG_PPC_MPC512x
105static u32 mpc512x_can_get_clock(struct platform_device *ofdev,
106 const char *clock_source, int *mscan_clksrc)
107{
108 struct device_node *np;
109 u32 clockdiv;
110 enum {
111 CLK_FROM_AUTO,
112 CLK_FROM_IPS,
113 CLK_FROM_SYS,
114 CLK_FROM_REF,
115 } clk_from;
116 struct clk *clk_in, *clk_can;
117 unsigned long freq_calc;
118 struct mscan_priv *priv;
119 struct clk *clk_ipg;
120
121 /* the caller passed in the clock source spec that was read from
122 * the device tree, get the optional clock divider as well
123 */
124 np = ofdev->dev.of_node;
125 clockdiv = 1;
126 of_property_read_u32(np, "fsl,mscan-clock-divider", &clockdiv);
127 dev_dbg(&ofdev->dev, "device tree specs: clk src[%s] div[%d]\n",
128 clock_source ? clock_source : "<NULL>", clockdiv);
129
130 /* when clock-source is 'ip', the CANCTL1[CLKSRC] bit needs to
131 * get set, and the 'ips' clock is the input to the MSCAN
132 * component
133 *
134 * for clock-source values of 'ref' or 'sys' the CANCTL1[CLKSRC]
135 * bit needs to get cleared, an optional clock-divider may have
136 * been specified (the default value is 1), the appropriate
137 * MSCAN related MCLK is the input to the MSCAN component
138 *
139 * in the absence of a clock-source spec, first an optimal clock
140 * gets determined based on the 'sys' clock, if that fails the
141 * 'ref' clock is used
142 */
143 clk_from = CLK_FROM_AUTO;
144 if (clock_source) {
145 /* interpret the device tree's spec for the clock source */
146 if (!strcmp(clock_source, "ip"))
147 clk_from = CLK_FROM_IPS;
148 else if (!strcmp(clock_source, "sys"))
149 clk_from = CLK_FROM_SYS;
150 else if (!strcmp(clock_source, "ref"))
151 clk_from = CLK_FROM_REF;
152 else
153 goto err_invalid;
154 dev_dbg(&ofdev->dev, "got a clk source spec[%d]\n", clk_from);
155 }
156 if (clk_from == CLK_FROM_AUTO) {
157 /* no spec so far, try the 'sys' clock; round to the
158 * next MHz and see if we can get a multiple of 16MHz
159 */
160 dev_dbg(&ofdev->dev, "no clk source spec, trying SYS\n");
161 clk_in = devm_clk_get(&ofdev->dev, "sys");
162 if (IS_ERR(clk_in))
163 goto err_notavail;
164 freq_calc = clk_get_rate(clk_in);
165 freq_calc += 499999;
166 freq_calc /= 1000000;
167 freq_calc *= 1000000;
168 if ((freq_calc % 16000000) == 0) {
169 clk_from = CLK_FROM_SYS;
170 clockdiv = freq_calc / 16000000;
171 dev_dbg(&ofdev->dev,
172 "clk fit, sys[%lu] div[%d] freq[%lu]\n",
173 freq_calc, clockdiv, freq_calc / clockdiv);
174 }
175 }
176 if (clk_from == CLK_FROM_AUTO) {
177 /* no spec so far, use the 'ref' clock */
178 dev_dbg(&ofdev->dev, "no clk source spec, trying REF\n");
179 clk_in = devm_clk_get(&ofdev->dev, "ref");
180 if (IS_ERR(clk_in))
181 goto err_notavail;
182 clk_from = CLK_FROM_REF;
183 freq_calc = clk_get_rate(clk_in);
184 dev_dbg(&ofdev->dev,
185 "clk fit, ref[%lu] (no div) freq[%lu]\n",
186 freq_calc, freq_calc);
187 }
188
189 /* select IPS or MCLK as the MSCAN input (returned to the caller),
190 * setup the MCLK mux source and rate if applicable, apply the
191 * optionally specified or derived above divider, and determine
192 * the actual resulting clock rate to return to the caller
193 */
194 switch (clk_from) {
195 case CLK_FROM_IPS:
196 clk_can = devm_clk_get(&ofdev->dev, "ips");
197 if (IS_ERR(clk_can))
198 goto err_notavail;
199 priv = netdev_priv(dev_get_drvdata(&ofdev->dev));
200 priv->clk_can = clk_can;
201 freq_calc = clk_get_rate(clk_can);
202 *mscan_clksrc = MSCAN_CLKSRC_IPS;
203 dev_dbg(&ofdev->dev, "clk from IPS, clksrc[%d] freq[%lu]\n",
204 *mscan_clksrc, freq_calc);
205 break;
206 case CLK_FROM_SYS:
207 case CLK_FROM_REF:
208 clk_can = devm_clk_get(&ofdev->dev, "mclk");
209 if (IS_ERR(clk_can))
210 goto err_notavail;
211 priv = netdev_priv(dev_get_drvdata(&ofdev->dev));
212 priv->clk_can = clk_can;
213 if (clk_from == CLK_FROM_SYS)
214 clk_in = devm_clk_get(&ofdev->dev, "sys");
215 if (clk_from == CLK_FROM_REF)
216 clk_in = devm_clk_get(&ofdev->dev, "ref");
217 if (IS_ERR(clk_in))
218 goto err_notavail;
219 clk_set_parent(clk_can, clk_in);
220 freq_calc = clk_get_rate(clk_in);
221 freq_calc /= clockdiv;
222 clk_set_rate(clk_can, freq_calc);
223 freq_calc = clk_get_rate(clk_can);
224 *mscan_clksrc = MSCAN_CLKSRC_BUS;
225 dev_dbg(&ofdev->dev, "clk from MCLK, clksrc[%d] freq[%lu]\n",
226 *mscan_clksrc, freq_calc);
227 break;
228 default:
229 goto err_invalid;
230 }
231
232 /* the above clk_can item is used for the bitrate, access to
233 * the peripheral's register set needs the clk_ipg item
234 */
235 clk_ipg = devm_clk_get(&ofdev->dev, "ipg");
236 if (IS_ERR(clk_ipg))
237 goto err_notavail_ipg;
238 if (clk_prepare_enable(clk_ipg))
239 goto err_notavail_ipg;
240 priv = netdev_priv(dev_get_drvdata(&ofdev->dev));
241 priv->clk_ipg = clk_ipg;
242
243 /* return the determined clock source rate */
244 return freq_calc;
245
246err_invalid:
247 dev_err(&ofdev->dev, "invalid clock source specification\n");
248 /* clock source rate could not get determined */
249 return 0;
250
251err_notavail:
252 dev_err(&ofdev->dev, "cannot acquire or setup bitrate clock source\n");
253 /* clock source rate could not get determined */
254 return 0;
255
256err_notavail_ipg:
257 dev_err(&ofdev->dev, "cannot acquire or setup register clock\n");
258 /* clock source rate could not get determined */
259 return 0;
260}
261
262static void mpc512x_can_put_clock(struct platform_device *ofdev)
263{
264 struct mscan_priv *priv;
265
266 priv = netdev_priv(dev_get_drvdata(&ofdev->dev));
267 if (priv->clk_ipg)
268 clk_disable_unprepare(priv->clk_ipg);
269}
270#else /* !CONFIG_PPC_MPC512x */
271static u32 mpc512x_can_get_clock(struct platform_device *ofdev,
272 const char *clock_name, int *mscan_clksrc)
273{
274 return 0;
275}
276#define mpc512x_can_put_clock NULL
277#endif /* CONFIG_PPC_MPC512x */
278
279static const struct of_device_id mpc5xxx_can_table[];
280static int mpc5xxx_can_probe(struct platform_device *ofdev)
281{
282 const struct of_device_id *match;
283 const struct mpc5xxx_can_data *data;
284 struct device_node *np = ofdev->dev.of_node;
285 struct net_device *dev;
286 struct mscan_priv *priv;
287 void __iomem *base;
288 const char *clock_name = NULL;
289 int irq, mscan_clksrc = 0;
290 int err = -ENOMEM;
291
292 match = of_match_device(mpc5xxx_can_table, &ofdev->dev);
293 if (!match)
294 return -EINVAL;
295 data = match->data;
296
297 base = of_iomap(np, 0);
298 if (!base) {
299 dev_err(&ofdev->dev, "couldn't ioremap\n");
300 return err;
301 }
302
303 irq = irq_of_parse_and_map(np, 0);
304 if (!irq) {
305 dev_err(&ofdev->dev, "no irq found\n");
306 err = -ENODEV;
307 goto exit_unmap_mem;
308 }
309
310 dev = alloc_mscandev();
311 if (!dev)
312 goto exit_dispose_irq;
313 platform_set_drvdata(ofdev, dev);
314 SET_NETDEV_DEV(dev, &ofdev->dev);
315
316 priv = netdev_priv(dev);
317 priv->reg_base = base;
318 dev->irq = irq;
319
320 clock_name = of_get_property(np, "fsl,mscan-clock-source", NULL);
321
322 BUG_ON(!data);
323 priv->type = data->type;
324 priv->can.clock.freq = data->get_clock(ofdev, clock_name,
325 &mscan_clksrc);
326 if (!priv->can.clock.freq) {
327 dev_err(&ofdev->dev, "couldn't get MSCAN clock properties\n");
328 goto exit_free_mscan;
329 }
330
331 err = register_mscandev(dev, mscan_clksrc);
332 if (err) {
333 dev_err(&ofdev->dev, "registering %s failed (err=%d)\n",
334 DRV_NAME, err);
335 goto exit_free_mscan;
336 }
337
338 dev_info(&ofdev->dev, "MSCAN at 0x%p, irq %d, clock %d Hz\n",
339 priv->reg_base, dev->irq, priv->can.clock.freq);
340
341 return 0;
342
343exit_free_mscan:
344 free_candev(dev);
345exit_dispose_irq:
346 irq_dispose_mapping(irq);
347exit_unmap_mem:
348 iounmap(base);
349
350 return err;
351}
352
353static int mpc5xxx_can_remove(struct platform_device *ofdev)
354{
355 const struct of_device_id *match;
356 const struct mpc5xxx_can_data *data;
357 struct net_device *dev = platform_get_drvdata(ofdev);
358 struct mscan_priv *priv = netdev_priv(dev);
359
360 match = of_match_device(mpc5xxx_can_table, &ofdev->dev);
361 data = match ? match->data : NULL;
362
363 unregister_mscandev(dev);
364 if (data && data->put_clock)
365 data->put_clock(ofdev);
366 iounmap(priv->reg_base);
367 irq_dispose_mapping(dev->irq);
368 free_candev(dev);
369
370 return 0;
371}
372
373#ifdef CONFIG_PM
374static struct mscan_regs saved_regs;
375static int mpc5xxx_can_suspend(struct platform_device *ofdev, pm_message_t state)
376{
377 struct net_device *dev = platform_get_drvdata(ofdev);
378 struct mscan_priv *priv = netdev_priv(dev);
379 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
380
381 _memcpy_fromio(&saved_regs, regs, sizeof(*regs));
382
383 return 0;
384}
385
386static int mpc5xxx_can_resume(struct platform_device *ofdev)
387{
388 struct net_device *dev = platform_get_drvdata(ofdev);
389 struct mscan_priv *priv = netdev_priv(dev);
390 struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
391
392 regs->canctl0 |= MSCAN_INITRQ;
393 while (!(regs->canctl1 & MSCAN_INITAK))
394 udelay(10);
395
396 regs->canctl1 = saved_regs.canctl1;
397 regs->canbtr0 = saved_regs.canbtr0;
398 regs->canbtr1 = saved_regs.canbtr1;
399 regs->canidac = saved_regs.canidac;
400
401 /* restore masks, buffers etc. */
402 _memcpy_toio(®s->canidar1_0, (void *)&saved_regs.canidar1_0,
403 sizeof(*regs) - offsetof(struct mscan_regs, canidar1_0));
404
405 regs->canctl0 &= ~MSCAN_INITRQ;
406 regs->cantbsel = saved_regs.cantbsel;
407 regs->canrier = saved_regs.canrier;
408 regs->cantier = saved_regs.cantier;
409 regs->canctl0 = saved_regs.canctl0;
410
411 return 0;
412}
413#endif
414
415static const struct mpc5xxx_can_data mpc5200_can_data = {
416 .type = MSCAN_TYPE_MPC5200,
417 .get_clock = mpc52xx_can_get_clock,
418 /* .put_clock not applicable */
419};
420
421static const struct mpc5xxx_can_data mpc5121_can_data = {
422 .type = MSCAN_TYPE_MPC5121,
423 .get_clock = mpc512x_can_get_clock,
424 .put_clock = mpc512x_can_put_clock,
425};
426
427static const struct of_device_id mpc5xxx_can_table[] = {
428 { .compatible = "fsl,mpc5200-mscan", .data = &mpc5200_can_data, },
429 /* Note that only MPC5121 Rev. 2 (and later) is supported */
430 { .compatible = "fsl,mpc5121-mscan", .data = &mpc5121_can_data, },
431 {},
432};
433MODULE_DEVICE_TABLE(of, mpc5xxx_can_table);
434
435static struct platform_driver mpc5xxx_can_driver = {
436 .driver = {
437 .name = "mpc5xxx_can",
438 .of_match_table = mpc5xxx_can_table,
439 },
440 .probe = mpc5xxx_can_probe,
441 .remove = mpc5xxx_can_remove,
442#ifdef CONFIG_PM
443 .suspend = mpc5xxx_can_suspend,
444 .resume = mpc5xxx_can_resume,
445#endif
446};
447
448module_platform_driver(mpc5xxx_can_driver);
449
450MODULE_AUTHOR("Wolfgang Grandegger <wg@grandegger.com>");
451MODULE_DESCRIPTION("Freescale MPC5xxx CAN driver");
452MODULE_LICENSE("GPL v2");