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1// SPDX-License-Identifier: GPL-2.0
2// SPI to CAN driver for the Texas Instruments TCAN4x5x
3// Copyright (C) 2018-19 Texas Instruments Incorporated - http://www.ti.com/
4
5#include <linux/regmap.h>
6#include <linux/spi/spi.h>
7
8#include <linux/regulator/consumer.h>
9#include <linux/gpio/consumer.h>
10
11#include "m_can.h"
12
13#define DEVICE_NAME "tcan4x5x"
14#define TCAN4X5X_EXT_CLK_DEF 40000000
15
16#define TCAN4X5X_DEV_ID0 0x00
17#define TCAN4X5X_DEV_ID1 0x04
18#define TCAN4X5X_REV 0x08
19#define TCAN4X5X_STATUS 0x0C
20#define TCAN4X5X_ERROR_STATUS 0x10
21#define TCAN4X5X_CONTROL 0x14
22
23#define TCAN4X5X_CONFIG 0x800
24#define TCAN4X5X_TS_PRESCALE 0x804
25#define TCAN4X5X_TEST_REG 0x808
26#define TCAN4X5X_INT_FLAGS 0x820
27#define TCAN4X5X_MCAN_INT_REG 0x824
28#define TCAN4X5X_INT_EN 0x830
29
30/* Interrupt bits */
31#define TCAN4X5X_CANBUSTERMOPEN_INT_EN BIT(30)
32#define TCAN4X5X_CANHCANL_INT_EN BIT(29)
33#define TCAN4X5X_CANHBAT_INT_EN BIT(28)
34#define TCAN4X5X_CANLGND_INT_EN BIT(27)
35#define TCAN4X5X_CANBUSOPEN_INT_EN BIT(26)
36#define TCAN4X5X_CANBUSGND_INT_EN BIT(25)
37#define TCAN4X5X_CANBUSBAT_INT_EN BIT(24)
38#define TCAN4X5X_UVSUP_INT_EN BIT(22)
39#define TCAN4X5X_UVIO_INT_EN BIT(21)
40#define TCAN4X5X_TSD_INT_EN BIT(19)
41#define TCAN4X5X_ECCERR_INT_EN BIT(16)
42#define TCAN4X5X_CANINT_INT_EN BIT(15)
43#define TCAN4X5X_LWU_INT_EN BIT(14)
44#define TCAN4X5X_CANSLNT_INT_EN BIT(10)
45#define TCAN4X5X_CANDOM_INT_EN BIT(8)
46#define TCAN4X5X_CANBUS_ERR_INT_EN BIT(5)
47#define TCAN4X5X_BUS_FAULT BIT(4)
48#define TCAN4X5X_MCAN_INT BIT(1)
49#define TCAN4X5X_ENABLE_TCAN_INT \
50 (TCAN4X5X_MCAN_INT | TCAN4X5X_BUS_FAULT | \
51 TCAN4X5X_CANBUS_ERR_INT_EN | TCAN4X5X_CANINT_INT_EN)
52
53/* MCAN Interrupt bits */
54#define TCAN4X5X_MCAN_IR_ARA BIT(29)
55#define TCAN4X5X_MCAN_IR_PED BIT(28)
56#define TCAN4X5X_MCAN_IR_PEA BIT(27)
57#define TCAN4X5X_MCAN_IR_WD BIT(26)
58#define TCAN4X5X_MCAN_IR_BO BIT(25)
59#define TCAN4X5X_MCAN_IR_EW BIT(24)
60#define TCAN4X5X_MCAN_IR_EP BIT(23)
61#define TCAN4X5X_MCAN_IR_ELO BIT(22)
62#define TCAN4X5X_MCAN_IR_BEU BIT(21)
63#define TCAN4X5X_MCAN_IR_BEC BIT(20)
64#define TCAN4X5X_MCAN_IR_DRX BIT(19)
65#define TCAN4X5X_MCAN_IR_TOO BIT(18)
66#define TCAN4X5X_MCAN_IR_MRAF BIT(17)
67#define TCAN4X5X_MCAN_IR_TSW BIT(16)
68#define TCAN4X5X_MCAN_IR_TEFL BIT(15)
69#define TCAN4X5X_MCAN_IR_TEFF BIT(14)
70#define TCAN4X5X_MCAN_IR_TEFW BIT(13)
71#define TCAN4X5X_MCAN_IR_TEFN BIT(12)
72#define TCAN4X5X_MCAN_IR_TFE BIT(11)
73#define TCAN4X5X_MCAN_IR_TCF BIT(10)
74#define TCAN4X5X_MCAN_IR_TC BIT(9)
75#define TCAN4X5X_MCAN_IR_HPM BIT(8)
76#define TCAN4X5X_MCAN_IR_RF1L BIT(7)
77#define TCAN4X5X_MCAN_IR_RF1F BIT(6)
78#define TCAN4X5X_MCAN_IR_RF1W BIT(5)
79#define TCAN4X5X_MCAN_IR_RF1N BIT(4)
80#define TCAN4X5X_MCAN_IR_RF0L BIT(3)
81#define TCAN4X5X_MCAN_IR_RF0F BIT(2)
82#define TCAN4X5X_MCAN_IR_RF0W BIT(1)
83#define TCAN4X5X_MCAN_IR_RF0N BIT(0)
84#define TCAN4X5X_ENABLE_MCAN_INT \
85 (TCAN4X5X_MCAN_IR_TC | TCAN4X5X_MCAN_IR_RF0N | \
86 TCAN4X5X_MCAN_IR_RF1N | TCAN4X5X_MCAN_IR_RF0F | \
87 TCAN4X5X_MCAN_IR_RF1F)
88
89#define TCAN4X5X_MRAM_START 0x8000
90#define TCAN4X5X_MCAN_OFFSET 0x1000
91#define TCAN4X5X_MAX_REGISTER 0x8fff
92
93#define TCAN4X5X_CLEAR_ALL_INT 0xffffffff
94#define TCAN4X5X_SET_ALL_INT 0xffffffff
95
96#define TCAN4X5X_WRITE_CMD (0x61 << 24)
97#define TCAN4X5X_READ_CMD (0x41 << 24)
98
99#define TCAN4X5X_MODE_SEL_MASK (BIT(7) | BIT(6))
100#define TCAN4X5X_MODE_SLEEP 0x00
101#define TCAN4X5X_MODE_STANDBY BIT(6)
102#define TCAN4X5X_MODE_NORMAL BIT(7)
103
104#define TCAN4X5X_SW_RESET BIT(2)
105
106#define TCAN4X5X_MCAN_CONFIGURED BIT(5)
107#define TCAN4X5X_WATCHDOG_EN BIT(3)
108#define TCAN4X5X_WD_60_MS_TIMER 0
109#define TCAN4X5X_WD_600_MS_TIMER BIT(28)
110#define TCAN4X5X_WD_3_S_TIMER BIT(29)
111#define TCAN4X5X_WD_6_S_TIMER (BIT(28) | BIT(29))
112
113struct tcan4x5x_priv {
114 struct regmap *regmap;
115 struct spi_device *spi;
116
117 struct m_can_classdev *mcan_dev;
118
119 struct gpio_desc *reset_gpio;
120 struct gpio_desc *device_wake_gpio;
121 struct gpio_desc *device_state_gpio;
122 struct regulator *power;
123
124 /* Register based ip */
125 int mram_start;
126 int reg_offset;
127};
128
129static struct can_bittiming_const tcan4x5x_bittiming_const = {
130 .name = DEVICE_NAME,
131 .tseg1_min = 2,
132 .tseg1_max = 31,
133 .tseg2_min = 2,
134 .tseg2_max = 16,
135 .sjw_max = 16,
136 .brp_min = 1,
137 .brp_max = 32,
138 .brp_inc = 1,
139};
140
141static struct can_bittiming_const tcan4x5x_data_bittiming_const = {
142 .name = DEVICE_NAME,
143 .tseg1_min = 1,
144 .tseg1_max = 32,
145 .tseg2_min = 1,
146 .tseg2_max = 16,
147 .sjw_max = 16,
148 .brp_min = 1,
149 .brp_max = 32,
150 .brp_inc = 1,
151};
152
153static void tcan4x5x_check_wake(struct tcan4x5x_priv *priv)
154{
155 int wake_state = 0;
156
157 if (priv->device_state_gpio)
158 wake_state = gpiod_get_value(priv->device_state_gpio);
159
160 if (priv->device_wake_gpio && wake_state) {
161 gpiod_set_value(priv->device_wake_gpio, 0);
162 usleep_range(5, 50);
163 gpiod_set_value(priv->device_wake_gpio, 1);
164 }
165}
166
167static int regmap_spi_gather_write(void *context, const void *reg,
168 size_t reg_len, const void *val,
169 size_t val_len)
170{
171 struct device *dev = context;
172 struct spi_device *spi = to_spi_device(dev);
173 struct spi_message m;
174 u32 addr;
175 struct spi_transfer t[2] = {
176 { .tx_buf = &addr, .len = reg_len, .cs_change = 0,},
177 { .tx_buf = val, .len = val_len, },
178 };
179
180 addr = TCAN4X5X_WRITE_CMD | (*((u16 *)reg) << 8) | val_len >> 2;
181
182 spi_message_init(&m);
183 spi_message_add_tail(&t[0], &m);
184 spi_message_add_tail(&t[1], &m);
185
186 return spi_sync(spi, &m);
187}
188
189static int tcan4x5x_regmap_write(void *context, const void *data, size_t count)
190{
191 u16 *reg = (u16 *)(data);
192 const u32 *val = data + 4;
193
194 return regmap_spi_gather_write(context, reg, 4, val, count - 4);
195}
196
197static int regmap_spi_async_write(void *context,
198 const void *reg, size_t reg_len,
199 const void *val, size_t val_len,
200 struct regmap_async *a)
201{
202 return -ENOTSUPP;
203}
204
205static struct regmap_async *regmap_spi_async_alloc(void)
206{
207 return NULL;
208}
209
210static int tcan4x5x_regmap_read(void *context,
211 const void *reg, size_t reg_size,
212 void *val, size_t val_size)
213{
214 struct device *dev = context;
215 struct spi_device *spi = to_spi_device(dev);
216
217 u32 addr = TCAN4X5X_READ_CMD | (*((u16 *)reg) << 8) | val_size >> 2;
218
219 return spi_write_then_read(spi, &addr, reg_size, (u32 *)val, val_size);
220}
221
222static struct regmap_bus tcan4x5x_bus = {
223 .write = tcan4x5x_regmap_write,
224 .gather_write = regmap_spi_gather_write,
225 .async_write = regmap_spi_async_write,
226 .async_alloc = regmap_spi_async_alloc,
227 .read = tcan4x5x_regmap_read,
228 .read_flag_mask = 0x00,
229 .reg_format_endian_default = REGMAP_ENDIAN_NATIVE,
230 .val_format_endian_default = REGMAP_ENDIAN_NATIVE,
231};
232
233static u32 tcan4x5x_read_reg(struct m_can_classdev *cdev, int reg)
234{
235 struct tcan4x5x_priv *priv = cdev->device_data;
236 u32 val;
237
238 regmap_read(priv->regmap, priv->reg_offset + reg, &val);
239
240 return val;
241}
242
243static u32 tcan4x5x_read_fifo(struct m_can_classdev *cdev, int addr_offset)
244{
245 struct tcan4x5x_priv *priv = cdev->device_data;
246 u32 val;
247
248 regmap_read(priv->regmap, priv->mram_start + addr_offset, &val);
249
250 return val;
251}
252
253static int tcan4x5x_write_reg(struct m_can_classdev *cdev, int reg, int val)
254{
255 struct tcan4x5x_priv *priv = cdev->device_data;
256
257 return regmap_write(priv->regmap, priv->reg_offset + reg, val);
258}
259
260static int tcan4x5x_write_fifo(struct m_can_classdev *cdev,
261 int addr_offset, int val)
262{
263 struct tcan4x5x_priv *priv = cdev->device_data;
264
265 return regmap_write(priv->regmap, priv->mram_start + addr_offset, val);
266}
267
268static int tcan4x5x_power_enable(struct regulator *reg, int enable)
269{
270 if (IS_ERR_OR_NULL(reg))
271 return 0;
272
273 if (enable)
274 return regulator_enable(reg);
275 else
276 return regulator_disable(reg);
277}
278
279static int tcan4x5x_write_tcan_reg(struct m_can_classdev *cdev,
280 int reg, int val)
281{
282 struct tcan4x5x_priv *priv = cdev->device_data;
283
284 return regmap_write(priv->regmap, reg, val);
285}
286
287static int tcan4x5x_clear_interrupts(struct m_can_classdev *cdev)
288{
289 int ret;
290
291 ret = tcan4x5x_write_tcan_reg(cdev, TCAN4X5X_STATUS,
292 TCAN4X5X_CLEAR_ALL_INT);
293 if (ret)
294 return ret;
295
296 ret = tcan4x5x_write_tcan_reg(cdev, TCAN4X5X_MCAN_INT_REG,
297 TCAN4X5X_ENABLE_MCAN_INT);
298 if (ret)
299 return ret;
300
301 ret = tcan4x5x_write_tcan_reg(cdev, TCAN4X5X_INT_FLAGS,
302 TCAN4X5X_CLEAR_ALL_INT);
303 if (ret)
304 return ret;
305
306 ret = tcan4x5x_write_tcan_reg(cdev, TCAN4X5X_ERROR_STATUS,
307 TCAN4X5X_CLEAR_ALL_INT);
308 if (ret)
309 return ret;
310
311 return ret;
312}
313
314static int tcan4x5x_init(struct m_can_classdev *cdev)
315{
316 struct tcan4x5x_priv *tcan4x5x = cdev->device_data;
317 int ret;
318
319 tcan4x5x_check_wake(tcan4x5x);
320
321 ret = tcan4x5x_clear_interrupts(cdev);
322 if (ret)
323 return ret;
324
325 ret = tcan4x5x_write_tcan_reg(cdev, TCAN4X5X_INT_EN,
326 TCAN4X5X_ENABLE_TCAN_INT);
327 if (ret)
328 return ret;
329
330 ret = regmap_update_bits(tcan4x5x->regmap, TCAN4X5X_CONFIG,
331 TCAN4X5X_MODE_SEL_MASK, TCAN4X5X_MODE_NORMAL);
332 if (ret)
333 return ret;
334
335 /* Zero out the MCAN buffers */
336 m_can_init_ram(cdev);
337
338 return ret;
339}
340
341static int tcan4x5x_parse_config(struct m_can_classdev *cdev)
342{
343 struct tcan4x5x_priv *tcan4x5x = cdev->device_data;
344
345 tcan4x5x->device_wake_gpio = devm_gpiod_get(cdev->dev, "device-wake",
346 GPIOD_OUT_HIGH);
347 if (IS_ERR(tcan4x5x->device_wake_gpio)) {
348 dev_err(cdev->dev, "device-wake gpio not defined\n");
349 return -EINVAL;
350 }
351
352 tcan4x5x->reset_gpio = devm_gpiod_get_optional(cdev->dev, "reset",
353 GPIOD_OUT_LOW);
354 if (IS_ERR(tcan4x5x->reset_gpio))
355 tcan4x5x->reset_gpio = NULL;
356
357 tcan4x5x->device_state_gpio = devm_gpiod_get_optional(cdev->dev,
358 "device-state",
359 GPIOD_IN);
360 if (IS_ERR(tcan4x5x->device_state_gpio))
361 tcan4x5x->device_state_gpio = NULL;
362
363 tcan4x5x->power = devm_regulator_get_optional(cdev->dev,
364 "vsup");
365 if (PTR_ERR(tcan4x5x->power) == -EPROBE_DEFER)
366 return -EPROBE_DEFER;
367
368 return 0;
369}
370
371static const struct regmap_config tcan4x5x_regmap = {
372 .reg_bits = 32,
373 .val_bits = 32,
374 .cache_type = REGCACHE_NONE,
375 .max_register = TCAN4X5X_MAX_REGISTER,
376};
377
378static struct m_can_ops tcan4x5x_ops = {
379 .init = tcan4x5x_init,
380 .read_reg = tcan4x5x_read_reg,
381 .write_reg = tcan4x5x_write_reg,
382 .write_fifo = tcan4x5x_write_fifo,
383 .read_fifo = tcan4x5x_read_fifo,
384 .clear_interrupts = tcan4x5x_clear_interrupts,
385};
386
387static int tcan4x5x_can_probe(struct spi_device *spi)
388{
389 struct tcan4x5x_priv *priv;
390 struct m_can_classdev *mcan_class;
391 int freq, ret;
392
393 mcan_class = m_can_class_allocate_dev(&spi->dev);
394 if (!mcan_class)
395 return -ENOMEM;
396
397 priv = devm_kzalloc(&spi->dev, sizeof(*priv), GFP_KERNEL);
398 if (!priv)
399 return -ENOMEM;
400
401 mcan_class->device_data = priv;
402
403 m_can_class_get_clocks(mcan_class);
404 if (IS_ERR(mcan_class->cclk)) {
405 dev_err(&spi->dev, "no CAN clock source defined\n");
406 freq = TCAN4X5X_EXT_CLK_DEF;
407 } else {
408 freq = clk_get_rate(mcan_class->cclk);
409 }
410
411 /* Sanity check */
412 if (freq < 20000000 || freq > TCAN4X5X_EXT_CLK_DEF)
413 return -ERANGE;
414
415 priv->reg_offset = TCAN4X5X_MCAN_OFFSET;
416 priv->mram_start = TCAN4X5X_MRAM_START;
417 priv->spi = spi;
418 priv->mcan_dev = mcan_class;
419
420 mcan_class->pm_clock_support = 0;
421 mcan_class->can.clock.freq = freq;
422 mcan_class->dev = &spi->dev;
423 mcan_class->ops = &tcan4x5x_ops;
424 mcan_class->is_peripheral = true;
425 mcan_class->bit_timing = &tcan4x5x_bittiming_const;
426 mcan_class->data_timing = &tcan4x5x_data_bittiming_const;
427 mcan_class->net->irq = spi->irq;
428
429 spi_set_drvdata(spi, priv);
430
431 ret = tcan4x5x_parse_config(mcan_class);
432 if (ret)
433 goto out_clk;
434
435 /* Configure the SPI bus */
436 spi->bits_per_word = 32;
437 ret = spi_setup(spi);
438 if (ret)
439 goto out_clk;
440
441 priv->regmap = devm_regmap_init(&spi->dev, &tcan4x5x_bus,
442 &spi->dev, &tcan4x5x_regmap);
443
444 tcan4x5x_power_enable(priv->power, 1);
445
446 ret = m_can_class_register(mcan_class);
447 if (ret)
448 goto out_power;
449
450 netdev_info(mcan_class->net, "TCAN4X5X successfully initialized.\n");
451 return 0;
452
453out_power:
454 tcan4x5x_power_enable(priv->power, 0);
455out_clk:
456 if (!IS_ERR(mcan_class->cclk)) {
457 clk_disable_unprepare(mcan_class->cclk);
458 clk_disable_unprepare(mcan_class->hclk);
459 }
460
461 dev_err(&spi->dev, "Probe failed, err=%d\n", ret);
462 return ret;
463}
464
465static int tcan4x5x_can_remove(struct spi_device *spi)
466{
467 struct tcan4x5x_priv *priv = spi_get_drvdata(spi);
468
469 tcan4x5x_power_enable(priv->power, 0);
470
471 m_can_class_unregister(priv->mcan_dev);
472
473 return 0;
474}
475
476static const struct of_device_id tcan4x5x_of_match[] = {
477 { .compatible = "ti,tcan4x5x", },
478 { }
479};
480MODULE_DEVICE_TABLE(of, tcan4x5x_of_match);
481
482static const struct spi_device_id tcan4x5x_id_table[] = {
483 {
484 .name = "tcan4x5x",
485 .driver_data = 0,
486 },
487 { }
488};
489MODULE_DEVICE_TABLE(spi, tcan4x5x_id_table);
490
491static struct spi_driver tcan4x5x_can_driver = {
492 .driver = {
493 .name = DEVICE_NAME,
494 .of_match_table = tcan4x5x_of_match,
495 .pm = NULL,
496 },
497 .id_table = tcan4x5x_id_table,
498 .probe = tcan4x5x_can_probe,
499 .remove = tcan4x5x_can_remove,
500};
501module_spi_driver(tcan4x5x_can_driver);
502
503MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com>");
504MODULE_DESCRIPTION("Texas Instruments TCAN4x5x CAN driver");
505MODULE_LICENSE("GPL v2");