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1#ifndef __RTS5260_H__
2#define __RTS5260_H__
3
4#define RTS5260_DVCC_CTRL 0xFF73
5#define RTS5260_DVCC_OCP_EN (0x01 << 7)
6#define RTS5260_DVCC_OCP_THD_MASK (0x07 << 4)
7#define RTS5260_DVCC_POWERON (0x01 << 3)
8#define RTS5260_DVCC_OCP_CL_EN (0x01 << 2)
9
10#define RTS5260_DVIO_CTRL 0xFF75
11#define RTS5260_DVIO_OCP_EN (0x01 << 7)
12#define RTS5260_DVIO_OCP_THD_MASK (0x07 << 4)
13#define RTS5260_DVIO_POWERON (0x01 << 3)
14#define RTS5260_DVIO_OCP_CL_EN (0x01 << 2)
15
16#define RTS5260_DV331812_CFG 0xFF71
17#define RTS5260_DV331812_OCP_EN (0x01 << 7)
18#define RTS5260_DV331812_OCP_THD_MASK (0x07 << 4)
19#define RTS5260_DV331812_POWERON (0x01 << 3)
20#define RTS5260_DV331812_SEL (0x01 << 2)
21#define RTS5260_DV331812_VDD1 (0x01 << 2)
22#define RTS5260_DV331812_VDD2 (0x00 << 2)
23
24#define RTS5260_DV331812_OCP_THD_120 (0x00 << 4)
25#define RTS5260_DV331812_OCP_THD_140 (0x01 << 4)
26#define RTS5260_DV331812_OCP_THD_160 (0x02 << 4)
27#define RTS5260_DV331812_OCP_THD_180 (0x03 << 4)
28#define RTS5260_DV331812_OCP_THD_210 (0x04 << 4)
29#define RTS5260_DV331812_OCP_THD_240 (0x05 << 4)
30#define RTS5260_DV331812_OCP_THD_270 (0x06 << 4)
31#define RTS5260_DV331812_OCP_THD_300 (0x07 << 4)
32
33#define RTS5260_DVIO_OCP_THD_250 (0x00 << 4)
34#define RTS5260_DVIO_OCP_THD_300 (0x01 << 4)
35#define RTS5260_DVIO_OCP_THD_350 (0x02 << 4)
36#define RTS5260_DVIO_OCP_THD_400 (0x03 << 4)
37#define RTS5260_DVIO_OCP_THD_450 (0x04 << 4)
38#define RTS5260_DVIO_OCP_THD_500 (0x05 << 4)
39#define RTS5260_DVIO_OCP_THD_550 (0x06 << 4)
40#define RTS5260_DVIO_OCP_THD_600 (0x07 << 4)
41
42#define RTS5260_DVCC_OCP_THD_550 (0x00 << 4)
43#define RTS5260_DVCC_OCP_THD_970 (0x05 << 4)
44
45#endif
1#ifndef __RTS5260_H__
2#define __RTS5260_H__
3
4#define RTS5260_DVCC_CTRL 0xFF73
5#define RTS5260_DVCC_OCP_EN (0x01 << 7)
6#define RTS5260_DVCC_OCP_THD_MASK (0x07 << 4)
7#define RTS5260_DVCC_POWERON (0x01 << 3)
8#define RTS5260_DVCC_OCP_CL_EN (0x01 << 2)
9
10#define RTS5260_DVIO_CTRL 0xFF75
11#define RTS5260_DVIO_OCP_EN (0x01 << 7)
12#define RTS5260_DVIO_OCP_THD_MASK (0x07 << 4)
13#define RTS5260_DVIO_POWERON (0x01 << 3)
14#define RTS5260_DVIO_OCP_CL_EN (0x01 << 2)
15
16#define RTS5260_DV331812_CFG 0xFF71
17#define RTS5260_DV331812_OCP_EN (0x01 << 7)
18#define RTS5260_DV331812_OCP_THD_MASK (0x07 << 4)
19#define RTS5260_DV331812_POWERON (0x01 << 3)
20#define RTS5260_DV331812_SEL (0x01 << 2)
21#define RTS5260_DV331812_VDD1 (0x01 << 2)
22#define RTS5260_DV331812_VDD2 (0x00 << 2)
23
24#define RTS5260_DV331812_OCP_THD_120 (0x00 << 4)
25#define RTS5260_DV331812_OCP_THD_140 (0x01 << 4)
26#define RTS5260_DV331812_OCP_THD_160 (0x02 << 4)
27#define RTS5260_DV331812_OCP_THD_180 (0x03 << 4)
28#define RTS5260_DV331812_OCP_THD_210 (0x04 << 4)
29#define RTS5260_DV331812_OCP_THD_240 (0x05 << 4)
30#define RTS5260_DV331812_OCP_THD_270 (0x06 << 4)
31#define RTS5260_DV331812_OCP_THD_300 (0x07 << 4)
32
33#define RTS5260_DVIO_OCP_THD_250 (0x00 << 4)
34#define RTS5260_DVIO_OCP_THD_300 (0x01 << 4)
35#define RTS5260_DVIO_OCP_THD_350 (0x02 << 4)
36#define RTS5260_DVIO_OCP_THD_400 (0x03 << 4)
37#define RTS5260_DVIO_OCP_THD_450 (0x04 << 4)
38#define RTS5260_DVIO_OCP_THD_500 (0x05 << 4)
39#define RTS5260_DVIO_OCP_THD_550 (0x06 << 4)
40#define RTS5260_DVIO_OCP_THD_600 (0x07 << 4)
41
42#define RTS5260_DVCC_OCP_THD_550 (0x00 << 4)
43#define RTS5260_DVCC_OCP_THD_970 (0x05 << 4)
44
45#endif