Loading...
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
4 */
5
6#ifndef _CORESIGHT_PRIV_H
7#define _CORESIGHT_PRIV_H
8
9#include <linux/amba/bus.h>
10#include <linux/bitops.h>
11#include <linux/io.h>
12#include <linux/coresight.h>
13#include <linux/pm_runtime.h>
14
15extern struct mutex coresight_mutex;
16extern const struct device_type coresight_dev_type[];
17
18/*
19 * Coresight management registers (0xf00-0xfcc)
20 * 0xfa0 - 0xfa4: Management registers in PFTv1.0
21 * Trace registers in PFTv1.1
22 */
23#define CORESIGHT_ITCTRL 0xf00
24#define CORESIGHT_CLAIMSET 0xfa0
25#define CORESIGHT_CLAIMCLR 0xfa4
26#define CORESIGHT_LAR 0xfb0
27#define CORESIGHT_LSR 0xfb4
28#define CORESIGHT_DEVARCH 0xfbc
29#define CORESIGHT_AUTHSTATUS 0xfb8
30#define CORESIGHT_DEVID 0xfc8
31#define CORESIGHT_DEVTYPE 0xfcc
32
33
34/*
35 * Coresight device CLAIM protocol.
36 * See PSCI - ARM DEN 0022D, Section: 6.8.1 Debug and Trace save and restore.
37 */
38#define CORESIGHT_CLAIM_SELF_HOSTED BIT(1)
39
40#define TIMEOUT_US 100
41#define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb)
42
43#define ETM_MODE_EXCL_KERN BIT(30)
44#define ETM_MODE_EXCL_USER BIT(31)
45struct cs_pair_attribute {
46 struct device_attribute attr;
47 u32 lo_off;
48 u32 hi_off;
49};
50
51struct cs_off_attribute {
52 struct device_attribute attr;
53 u32 off;
54};
55
56extern ssize_t coresight_simple_show32(struct device *_dev,
57 struct device_attribute *attr, char *buf);
58extern ssize_t coresight_simple_show_pair(struct device *_dev,
59 struct device_attribute *attr, char *buf);
60
61#define coresight_simple_reg32(name, offset) \
62 (&((struct cs_off_attribute[]) { \
63 { \
64 __ATTR(name, 0444, coresight_simple_show32, NULL), \
65 offset \
66 } \
67 })[0].attr.attr)
68
69#define coresight_simple_reg64(name, lo_off, hi_off) \
70 (&((struct cs_pair_attribute[]) { \
71 { \
72 __ATTR(name, 0444, coresight_simple_show_pair, NULL), \
73 lo_off, hi_off \
74 } \
75 })[0].attr.attr)
76
77extern const u32 coresight_barrier_pkt[4];
78#define CORESIGHT_BARRIER_PKT_SIZE (sizeof(coresight_barrier_pkt))
79
80enum etm_addr_type {
81 ETM_ADDR_TYPE_NONE,
82 ETM_ADDR_TYPE_SINGLE,
83 ETM_ADDR_TYPE_RANGE,
84 ETM_ADDR_TYPE_START,
85 ETM_ADDR_TYPE_STOP,
86};
87
88/**
89 * struct cs_buffer - keep track of a recording session' specifics
90 * @cur: index of the current buffer
91 * @nr_pages: max number of pages granted to us
92 * @pid: PID this cs_buffer belongs to
93 * @offset: offset within the current buffer
94 * @data_size: how much we collected in this run
95 * @snapshot: is this run in snapshot mode
96 * @data_pages: a handle the ring buffer
97 */
98struct cs_buffers {
99 unsigned int cur;
100 unsigned int nr_pages;
101 pid_t pid;
102 unsigned long offset;
103 local_t data_size;
104 bool snapshot;
105 void **data_pages;
106};
107
108static inline void coresight_insert_barrier_packet(void *buf)
109{
110 if (buf)
111 memcpy(buf, coresight_barrier_pkt, CORESIGHT_BARRIER_PKT_SIZE);
112}
113
114static inline void CS_LOCK(void __iomem *addr)
115{
116 do {
117 /* Wait for things to settle */
118 mb();
119 writel_relaxed(0x0, addr + CORESIGHT_LAR);
120 } while (0);
121}
122
123static inline void CS_UNLOCK(void __iomem *addr)
124{
125 do {
126 writel_relaxed(CORESIGHT_UNLOCK, addr + CORESIGHT_LAR);
127 /* Make sure everyone has seen this */
128 mb();
129 } while (0);
130}
131
132void coresight_disable_path(struct list_head *path);
133int coresight_enable_path(struct list_head *path, enum cs_mode mode,
134 void *sink_data);
135struct coresight_device *coresight_get_sink(struct list_head *path);
136struct coresight_device *coresight_get_sink_by_id(u32 id);
137struct coresight_device *
138coresight_find_default_sink(struct coresight_device *csdev);
139struct list_head *coresight_build_path(struct coresight_device *csdev,
140 struct coresight_device *sink);
141void coresight_release_path(struct list_head *path);
142int coresight_add_sysfs_link(struct coresight_sysfs_link *info);
143void coresight_remove_sysfs_link(struct coresight_sysfs_link *info);
144int coresight_create_conns_sysfs_group(struct coresight_device *csdev);
145void coresight_remove_conns_sysfs_group(struct coresight_device *csdev);
146int coresight_make_links(struct coresight_device *orig,
147 struct coresight_connection *conn,
148 struct coresight_device *target);
149void coresight_remove_links(struct coresight_device *orig,
150 struct coresight_connection *conn);
151u32 coresight_get_sink_id(struct coresight_device *csdev);
152
153#if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM3X)
154extern int etm_readl_cp14(u32 off, unsigned int *val);
155extern int etm_writel_cp14(u32 off, u32 val);
156#else
157static inline int etm_readl_cp14(u32 off, unsigned int *val) { return 0; }
158static inline int etm_writel_cp14(u32 off, u32 val) { return 0; }
159#endif
160
161struct cti_assoc_op {
162 void (*add)(struct coresight_device *csdev);
163 void (*remove)(struct coresight_device *csdev);
164};
165
166extern void coresight_set_cti_ops(const struct cti_assoc_op *cti_op);
167extern void coresight_remove_cti_ops(void);
168
169/*
170 * Macros and inline functions to handle CoreSight UCI data and driver
171 * private data in AMBA ID table entries, and extract data values.
172 */
173
174/* coresight AMBA ID, no UCI, no driver data: id table entry */
175#define CS_AMBA_ID(pid) \
176 { \
177 .id = pid, \
178 .mask = 0x000fffff, \
179 }
180
181/* coresight AMBA ID, UCI with driver data only: id table entry. */
182#define CS_AMBA_ID_DATA(pid, dval) \
183 { \
184 .id = pid, \
185 .mask = 0x000fffff, \
186 .data = (void *)&(struct amba_cs_uci_id) \
187 { \
188 .data = (void *)dval, \
189 } \
190 }
191
192/* coresight AMBA ID, full UCI structure: id table entry. */
193#define __CS_AMBA_UCI_ID(pid, m, uci_ptr) \
194 { \
195 .id = pid, \
196 .mask = m, \
197 .data = (void *)uci_ptr \
198 }
199#define CS_AMBA_UCI_ID(pid, uci) __CS_AMBA_UCI_ID(pid, 0x000fffff, uci)
200/*
201 * PIDR2[JEDEC], BIT(3) must be 1 (Read As One) to indicate that rest of the
202 * PIDR1, PIDR2 DES_* fields follow JEDEC encoding for the designer. Use that
203 * as a match value for blanket matching all devices in the given CoreSight
204 * device type and architecture.
205 */
206#define PIDR2_JEDEC BIT(3)
207#define PID_PIDR2_JEDEC (PIDR2_JEDEC << 16)
208/*
209 * Match all PIDs in a given CoreSight device type and architecture, defined
210 * by the uci.
211 */
212#define CS_AMBA_MATCH_ALL_UCI(uci) \
213 __CS_AMBA_UCI_ID(PID_PIDR2_JEDEC, PID_PIDR2_JEDEC, uci)
214
215/* extract the data value from a UCI structure given amba_id pointer. */
216static inline void *coresight_get_uci_data(const struct amba_id *id)
217{
218 struct amba_cs_uci_id *uci_id = id->data;
219
220 if (!uci_id)
221 return NULL;
222
223 return uci_id->data;
224}
225
226static inline void *coresight_get_uci_data_from_amba(const struct amba_id *table, u32 pid)
227{
228 while (table->mask) {
229 if ((pid & table->mask) == table->id)
230 return coresight_get_uci_data(table);
231 table++;
232 };
233 return NULL;
234}
235
236void coresight_release_platform_data(struct coresight_device *csdev,
237 struct device *dev,
238 struct coresight_platform_data *pdata);
239struct coresight_device *
240coresight_find_csdev_by_fwnode(struct fwnode_handle *r_fwnode);
241void coresight_add_helper(struct coresight_device *csdev,
242 struct coresight_device *helper);
243
244void coresight_set_percpu_sink(int cpu, struct coresight_device *csdev);
245struct coresight_device *coresight_get_percpu_sink(int cpu);
246void coresight_disable_source(struct coresight_device *csdev, void *data);
247
248#endif
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
4 */
5
6#ifndef _CORESIGHT_PRIV_H
7#define _CORESIGHT_PRIV_H
8
9#include <linux/amba/bus.h>
10#include <linux/bitops.h>
11#include <linux/io.h>
12#include <linux/coresight.h>
13#include <linux/pm_runtime.h>
14
15/*
16 * Coresight management registers (0xf00-0xfcc)
17 * 0xfa0 - 0xfa4: Management registers in PFTv1.0
18 * Trace registers in PFTv1.1
19 */
20#define CORESIGHT_ITCTRL 0xf00
21#define CORESIGHT_CLAIMSET 0xfa0
22#define CORESIGHT_CLAIMCLR 0xfa4
23#define CORESIGHT_LAR 0xfb0
24#define CORESIGHT_LSR 0xfb4
25#define CORESIGHT_AUTHSTATUS 0xfb8
26#define CORESIGHT_DEVID 0xfc8
27#define CORESIGHT_DEVTYPE 0xfcc
28
29
30/*
31 * Coresight device CLAIM protocol.
32 * See PSCI - ARM DEN 0022D, Section: 6.8.1 Debug and Trace save and restore.
33 */
34#define CORESIGHT_CLAIM_SELF_HOSTED BIT(1)
35
36#define TIMEOUT_US 100
37#define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb)
38
39#define ETM_MODE_EXCL_KERN BIT(30)
40#define ETM_MODE_EXCL_USER BIT(31)
41
42typedef u32 (*coresight_read_fn)(const struct device *, u32 offset);
43#define __coresight_simple_func(type, func, name, lo_off, hi_off) \
44static ssize_t name##_show(struct device *_dev, \
45 struct device_attribute *attr, char *buf) \
46{ \
47 type *drvdata = dev_get_drvdata(_dev->parent); \
48 coresight_read_fn fn = func; \
49 u64 val; \
50 pm_runtime_get_sync(_dev->parent); \
51 if (fn) \
52 val = (u64)fn(_dev->parent, lo_off); \
53 else \
54 val = coresight_read_reg_pair(drvdata->base, \
55 lo_off, hi_off); \
56 pm_runtime_put_sync(_dev->parent); \
57 return scnprintf(buf, PAGE_SIZE, "0x%llx\n", val); \
58} \
59static DEVICE_ATTR_RO(name)
60
61#define coresight_simple_func(type, func, name, offset) \
62 __coresight_simple_func(type, func, name, offset, -1)
63#define coresight_simple_reg32(type, name, offset) \
64 __coresight_simple_func(type, NULL, name, offset, -1)
65#define coresight_simple_reg64(type, name, lo_off, hi_off) \
66 __coresight_simple_func(type, NULL, name, lo_off, hi_off)
67
68extern const u32 barrier_pkt[4];
69#define CORESIGHT_BARRIER_PKT_SIZE (sizeof(barrier_pkt))
70
71enum etm_addr_type {
72 ETM_ADDR_TYPE_NONE,
73 ETM_ADDR_TYPE_SINGLE,
74 ETM_ADDR_TYPE_RANGE,
75 ETM_ADDR_TYPE_START,
76 ETM_ADDR_TYPE_STOP,
77};
78
79enum cs_mode {
80 CS_MODE_DISABLED,
81 CS_MODE_SYSFS,
82 CS_MODE_PERF,
83};
84
85/**
86 * struct cs_buffer - keep track of a recording session' specifics
87 * @cur: index of the current buffer
88 * @nr_pages: max number of pages granted to us
89 * @offset: offset within the current buffer
90 * @data_size: how much we collected in this run
91 * @snapshot: is this run in snapshot mode
92 * @data_pages: a handle the ring buffer
93 */
94struct cs_buffers {
95 unsigned int cur;
96 unsigned int nr_pages;
97 unsigned long offset;
98 local_t data_size;
99 bool snapshot;
100 void **data_pages;
101};
102
103static inline void coresight_insert_barrier_packet(void *buf)
104{
105 if (buf)
106 memcpy(buf, barrier_pkt, CORESIGHT_BARRIER_PKT_SIZE);
107}
108
109
110static inline void CS_LOCK(void __iomem *addr)
111{
112 do {
113 /* Wait for things to settle */
114 mb();
115 writel_relaxed(0x0, addr + CORESIGHT_LAR);
116 } while (0);
117}
118
119static inline void CS_UNLOCK(void __iomem *addr)
120{
121 do {
122 writel_relaxed(CORESIGHT_UNLOCK, addr + CORESIGHT_LAR);
123 /* Make sure everyone has seen this */
124 mb();
125 } while (0);
126}
127
128static inline u64
129coresight_read_reg_pair(void __iomem *addr, s32 lo_offset, s32 hi_offset)
130{
131 u64 val;
132
133 val = readl_relaxed(addr + lo_offset);
134 val |= (hi_offset < 0) ? 0 :
135 (u64)readl_relaxed(addr + hi_offset) << 32;
136 return val;
137}
138
139static inline void coresight_write_reg_pair(void __iomem *addr, u64 val,
140 s32 lo_offset, s32 hi_offset)
141{
142 writel_relaxed((u32)val, addr + lo_offset);
143 if (hi_offset >= 0)
144 writel_relaxed((u32)(val >> 32), addr + hi_offset);
145}
146
147void coresight_disable_path(struct list_head *path);
148int coresight_enable_path(struct list_head *path, u32 mode, void *sink_data);
149struct coresight_device *coresight_get_sink(struct list_head *path);
150struct coresight_device *coresight_get_enabled_sink(bool reset);
151struct coresight_device *coresight_get_sink_by_id(u32 id);
152struct list_head *coresight_build_path(struct coresight_device *csdev,
153 struct coresight_device *sink);
154void coresight_release_path(struct list_head *path);
155
156#ifdef CONFIG_CORESIGHT_SOURCE_ETM3X
157extern int etm_readl_cp14(u32 off, unsigned int *val);
158extern int etm_writel_cp14(u32 off, u32 val);
159#else
160static inline int etm_readl_cp14(u32 off, unsigned int *val) { return 0; }
161static inline int etm_writel_cp14(u32 off, u32 val) { return 0; }
162#endif
163
164/*
165 * Macros and inline functions to handle CoreSight UCI data and driver
166 * private data in AMBA ID table entries, and extract data values.
167 */
168
169/* coresight AMBA ID, no UCI, no driver data: id table entry */
170#define CS_AMBA_ID(pid) \
171 { \
172 .id = pid, \
173 .mask = 0x000fffff, \
174 }
175
176/* coresight AMBA ID, UCI with driver data only: id table entry. */
177#define CS_AMBA_ID_DATA(pid, dval) \
178 { \
179 .id = pid, \
180 .mask = 0x000fffff, \
181 .data = (void *)&(struct amba_cs_uci_id) \
182 { \
183 .data = (void *)dval, \
184 } \
185 }
186
187/* coresight AMBA ID, full UCI structure: id table entry. */
188#define CS_AMBA_UCI_ID(pid, uci_ptr) \
189 { \
190 .id = pid, \
191 .mask = 0x000fffff, \
192 .data = (void *)uci_ptr \
193 }
194
195/* extract the data value from a UCI structure given amba_id pointer. */
196static inline void *coresight_get_uci_data(const struct amba_id *id)
197{
198 if (id->data)
199 return ((struct amba_cs_uci_id *)(id->data))->data;
200 return 0;
201}
202
203void coresight_release_platform_data(struct coresight_platform_data *pdata);
204
205#endif