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v6.13.7
  1/*
  2 * Copyright (C) 2015 Red Hat, Inc.
  3 * All Rights Reserved.
  4 *
  5 * Permission is hereby granted, free of charge, to any person obtaining
  6 * a copy of this software and associated documentation files (the
  7 * "Software"), to deal in the Software without restriction, including
  8 * without limitation the rights to use, copy, modify, merge, publish,
  9 * distribute, sublicense, and/or sell copies of the Software, and to
 10 * permit persons to whom the Software is furnished to do so, subject to
 11 * the following conditions:
 12 *
 13 * The above copyright notice and this permission notice (including the
 14 * next paragraph) shall be included in all copies or substantial
 15 * portions of the Software.
 16 *
 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
 20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
 21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
 22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
 23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 24 */
 25
 26#ifndef VIRTIO_DRV_H
 27#define VIRTIO_DRV_H
 28
 29#include <linux/dma-direction.h>
 30#include <linux/virtio.h>
 31#include <linux/virtio_ids.h>
 32#include <linux/virtio_config.h>
 33#include <linux/virtio_gpu.h>
 34
 35#include <drm/drm_atomic.h>
 36#include <drm/drm_drv.h>
 37#include <drm/drm_encoder.h>
 38#include <drm/drm_fourcc.h>
 39#include <drm/drm_framebuffer.h>
 40#include <drm/drm_gem.h>
 41#include <drm/drm_gem_shmem_helper.h>
 42#include <drm/drm_ioctl.h>
 43#include <drm/drm_probe_helper.h>
 44#include <drm/virtgpu_drm.h>
 
 
 
 45
 46#define DRIVER_NAME "virtio_gpu"
 47#define DRIVER_DESC "virtio GPU"
 48#define DRIVER_DATE "0"
 49
 50#define DRIVER_MAJOR 0
 51#define DRIVER_MINOR 1
 52#define DRIVER_PATCHLEVEL 0
 53
 54#define STATE_INITIALIZING 0
 55#define STATE_OK 1
 56#define STATE_ERR 2
 57
 58#define MAX_CAPSET_ID 63
 59#define MAX_RINGS 64
 60
 61/* See virtio_gpu_ctx_create. One additional character for NULL terminator. */
 62#define DEBUG_NAME_MAX_LEN 65
 63
 64struct virtio_gpu_object_params {
 
 
 
 65	unsigned long size;
 66	bool dumb;
 67	/* 3d */
 68	bool virgl;
 69	bool blob;
 70
 71	/* classic resources only */
 72	uint32_t format;
 73	uint32_t width;
 74	uint32_t height;
 75	uint32_t target;
 76	uint32_t bind;
 77	uint32_t depth;
 78	uint32_t array_size;
 79	uint32_t last_level;
 80	uint32_t nr_samples;
 81	uint32_t flags;
 82
 83	/* blob resources only */
 84	uint32_t ctx_id;
 85	uint32_t blob_mem;
 86	uint32_t blob_flags;
 87	uint64_t blob_id;
 88};
 89
 90struct virtio_gpu_object {
 91	struct drm_gem_shmem_object base;
 92	uint32_t hw_res_handle;
 
 
 
 
 93	bool dumb;
 
 
 
 
 94	bool created;
 95	bool host3d_blob, guest_blob;
 96	uint32_t blob_mem, blob_flags;
 97
 98	int uuid_state;
 99	uuid_t uuid;
100};
101#define gem_to_virtio_gpu_obj(gobj) \
102	container_of((gobj), struct virtio_gpu_object, base.base)
103
104struct virtio_gpu_object_shmem {
105	struct virtio_gpu_object base;
106};
107
108struct virtio_gpu_object_vram {
109	struct virtio_gpu_object base;
110	uint32_t map_state;
111	uint32_t map_info;
112	struct drm_mm_node vram_node;
113};
114
115#define to_virtio_gpu_shmem(virtio_gpu_object) \
116	container_of((virtio_gpu_object), struct virtio_gpu_object_shmem, base)
117
118#define to_virtio_gpu_vram(virtio_gpu_object) \
119	container_of((virtio_gpu_object), struct virtio_gpu_object_vram, base)
120
121struct virtio_gpu_object_array {
122	struct ww_acquire_ctx ticket;
123	struct list_head next;
124	u32 nents, total;
125	struct drm_gem_object *objs[] __counted_by(total);
126};
127
128struct virtio_gpu_vbuffer;
129struct virtio_gpu_device;
130
131typedef void (*virtio_gpu_resp_cb)(struct virtio_gpu_device *vgdev,
132				   struct virtio_gpu_vbuffer *vbuf);
133
134struct virtio_gpu_fence_driver {
135	atomic64_t       last_fence_id;
136	uint64_t         current_fence_id;
137	uint64_t         context;
138	struct list_head fences;
139	spinlock_t       lock;
140};
141
142struct virtio_gpu_fence_event {
143	struct drm_pending_event base;
144	struct drm_event event;
145};
146
147struct virtio_gpu_fence {
148	struct dma_fence f;
149	uint32_t ring_idx;
150	uint64_t fence_id;
151	bool emit_fence_info;
152	struct virtio_gpu_fence_event *e;
153	struct virtio_gpu_fence_driver *drv;
154	struct list_head node;
155};
 
 
156
157struct virtio_gpu_vbuffer {
158	char *buf;
159	int size;
160
161	void *data_buf;
162	uint32_t data_size;
163
164	char *resp_buf;
165	int resp_size;
 
166	virtio_gpu_resp_cb resp_cb;
167	void *resp_cb_data;
168
169	struct virtio_gpu_object_array *objs;
170	struct list_head list;
171
172	uint32_t seqno;
173};
174
175struct virtio_gpu_output {
176	int index;
177	struct drm_crtc crtc;
178	struct drm_connector conn;
179	struct drm_encoder enc;
180	struct virtio_gpu_display_one info;
181	struct virtio_gpu_update_cursor cursor;
182	const struct drm_edid *drm_edid;
183	int cur_x;
184	int cur_y;
185	bool needs_modeset;
186};
187#define drm_crtc_to_virtio_gpu_output(x) \
188	container_of(x, struct virtio_gpu_output, crtc)
 
 
 
 
189
190struct virtio_gpu_framebuffer {
191	struct drm_framebuffer base;
192	struct virtio_gpu_fence *fence;
193};
194#define to_virtio_gpu_framebuffer(x) \
195	container_of(x, struct virtio_gpu_framebuffer, base)
196
197struct virtio_gpu_plane_state {
198	struct drm_plane_state base;
199	struct virtio_gpu_fence *fence;
200};
201#define to_virtio_gpu_plane_state(x) \
202	container_of(x, struct virtio_gpu_plane_state, base)
203
204struct virtio_gpu_queue {
205	struct virtqueue *vq;
206	spinlock_t qlock;
207	wait_queue_head_t ack_queue;
208	struct work_struct dequeue_work;
209	uint32_t seqno;
210};
211
212struct virtio_gpu_drv_capset {
213	uint32_t id;
214	uint32_t max_version;
215	uint32_t max_size;
216};
217
218struct virtio_gpu_drv_cap_cache {
219	struct list_head head;
220	void *caps_cache;
221	uint32_t id;
222	uint32_t version;
223	uint32_t size;
224	atomic_t is_valid;
225};
226
227struct virtio_gpu_device {
 
228	struct drm_device *ddev;
229
230	struct virtio_device *vdev;
231
 
 
232	struct virtio_gpu_output outputs[VIRTIO_GPU_MAX_SCANOUTS];
233	uint32_t num_scanouts;
234
235	struct virtio_gpu_queue ctrlq;
236	struct virtio_gpu_queue cursorq;
237	struct kmem_cache *vbufs;
238
239	atomic_t pending_commands;
240
241	struct ida	resource_ida;
242
243	wait_queue_head_t resp_wq;
244	/* current display info */
245	spinlock_t display_info_lock;
246	bool display_info_pending;
247
248	struct virtio_gpu_fence_driver fence_drv;
249
250	struct ida	ctx_id_ida;
251
252	bool has_virgl_3d;
253	bool has_edid;
254	bool has_indirect;
255	bool has_resource_assign_uuid;
256	bool has_resource_blob;
257	bool has_host_visible;
258	bool has_context_init;
259	struct virtio_shm_region host_visible_region;
260	struct drm_mm host_visible_mm;
261
262	struct work_struct config_changed_work;
263
264	struct work_struct obj_free_work;
265	spinlock_t obj_free_lock;
266	struct list_head obj_free_list;
267
268	struct virtio_gpu_drv_capset *capsets;
269	uint32_t num_capsets;
270	uint64_t capset_id_mask;
271	struct list_head cap_cache;
272
273	/* protects uuid state when exporting */
274	spinlock_t resource_export_lock;
275	/* protects map state and host_visible_mm */
276	spinlock_t host_visible_lock;
277};
278
279struct virtio_gpu_fpriv {
280	uint32_t ctx_id;
281	uint32_t context_init;
282	bool context_created;
283	uint32_t num_rings;
284	uint64_t base_fence_ctx;
285	uint64_t ring_idx_mask;
286	struct mutex context_lock;
287	char debug_name[DEBUG_NAME_MAX_LEN];
288	bool explicit_debug_name;
289};
290
291/* virtgpu_ioctl.c */
292#define DRM_VIRTIO_NUM_IOCTLS 12
293extern struct drm_ioctl_desc virtio_gpu_ioctls[DRM_VIRTIO_NUM_IOCTLS];
294void virtio_gpu_create_context(struct drm_device *dev, struct drm_file *file);
 
 
295
296/* virtgpu_kms.c */
297int virtio_gpu_init(struct virtio_device *vdev, struct drm_device *dev);
298void virtio_gpu_deinit(struct drm_device *dev);
299void virtio_gpu_release(struct drm_device *dev);
300int virtio_gpu_driver_open(struct drm_device *dev, struct drm_file *file);
301void virtio_gpu_driver_postclose(struct drm_device *dev, struct drm_file *file);
302
303/* virtgpu_gem.c */
 
 
 
 
 
 
 
 
304int virtio_gpu_gem_object_open(struct drm_gem_object *obj,
305			       struct drm_file *file);
306void virtio_gpu_gem_object_close(struct drm_gem_object *obj,
307				 struct drm_file *file);
 
 
 
 
308int virtio_gpu_mode_dumb_create(struct drm_file *file_priv,
309				struct drm_device *dev,
310				struct drm_mode_create_dumb *args);
311int virtio_gpu_mode_dumb_mmap(struct drm_file *file_priv,
312			      struct drm_device *dev,
313			      uint32_t handle, uint64_t *offset_p);
314
315struct virtio_gpu_object_array *virtio_gpu_array_alloc(u32 nents);
316struct virtio_gpu_object_array*
317virtio_gpu_array_from_handles(struct drm_file *drm_file, u32 *handles, u32 nents);
318void virtio_gpu_array_add_obj(struct virtio_gpu_object_array *objs,
319			      struct drm_gem_object *obj);
320int virtio_gpu_array_lock_resv(struct virtio_gpu_object_array *objs);
321void virtio_gpu_array_unlock_resv(struct virtio_gpu_object_array *objs);
322void virtio_gpu_array_add_fence(struct virtio_gpu_object_array *objs,
323				struct dma_fence *fence);
324void virtio_gpu_array_put_free(struct virtio_gpu_object_array *objs);
325void virtio_gpu_array_put_free_delayed(struct virtio_gpu_device *vgdev,
326				       struct virtio_gpu_object_array *objs);
327void virtio_gpu_array_put_free_work(struct work_struct *work);
328
329/* virtgpu_vq.c */
330int virtio_gpu_alloc_vbufs(struct virtio_gpu_device *vgdev);
331void virtio_gpu_free_vbufs(struct virtio_gpu_device *vgdev);
332void virtio_gpu_cmd_create_resource(struct virtio_gpu_device *vgdev,
333				    struct virtio_gpu_object *bo,
334				    struct virtio_gpu_object_params *params,
335				    struct virtio_gpu_object_array *objs,
336				    struct virtio_gpu_fence *fence);
337void virtio_gpu_cmd_unref_resource(struct virtio_gpu_device *vgdev,
338				   struct virtio_gpu_object *bo);
339void virtio_gpu_cmd_transfer_to_host_2d(struct virtio_gpu_device *vgdev,
 
340					uint64_t offset,
341					uint32_t width, uint32_t height,
342					uint32_t x, uint32_t y,
343					struct virtio_gpu_object_array *objs,
344					struct virtio_gpu_fence *fence);
345void virtio_gpu_cmd_resource_flush(struct virtio_gpu_device *vgdev,
346				   uint32_t resource_id,
347				   uint32_t x, uint32_t y,
348				   uint32_t width, uint32_t height,
349				   struct virtio_gpu_object_array *objs,
350				   struct virtio_gpu_fence *fence);
351void virtio_gpu_cmd_set_scanout(struct virtio_gpu_device *vgdev,
352				uint32_t scanout_id, uint32_t resource_id,
353				uint32_t width, uint32_t height,
354				uint32_t x, uint32_t y);
355void virtio_gpu_object_attach(struct virtio_gpu_device *vgdev,
356			      struct virtio_gpu_object *obj,
357			      struct virtio_gpu_mem_entry *ents,
358			      unsigned int nents);
 
 
 
359void virtio_gpu_cursor_ping(struct virtio_gpu_device *vgdev,
360			    struct virtio_gpu_output *output);
361int virtio_gpu_cmd_get_display_info(struct virtio_gpu_device *vgdev);
362int virtio_gpu_cmd_get_capset_info(struct virtio_gpu_device *vgdev, int idx);
363int virtio_gpu_cmd_get_capset(struct virtio_gpu_device *vgdev,
364			      int idx, int version,
365			      struct virtio_gpu_drv_cap_cache **cache_p);
366int virtio_gpu_cmd_get_edids(struct virtio_gpu_device *vgdev);
367void virtio_gpu_cmd_context_create(struct virtio_gpu_device *vgdev, uint32_t id,
368				   uint32_t context_init, uint32_t nlen,
369				   const char *name);
370void virtio_gpu_cmd_context_destroy(struct virtio_gpu_device *vgdev,
371				    uint32_t id);
372void virtio_gpu_cmd_context_attach_resource(struct virtio_gpu_device *vgdev,
373					    uint32_t ctx_id,
374					    struct virtio_gpu_object_array *objs);
375void virtio_gpu_cmd_context_detach_resource(struct virtio_gpu_device *vgdev,
376					    uint32_t ctx_id,
377					    struct virtio_gpu_object_array *objs);
378void virtio_gpu_cmd_submit(struct virtio_gpu_device *vgdev,
379			   void *data, uint32_t data_size,
380			   uint32_t ctx_id,
381			   struct virtio_gpu_object_array *objs,
382			   struct virtio_gpu_fence *fence);
383void virtio_gpu_cmd_transfer_from_host_3d(struct virtio_gpu_device *vgdev,
384					  uint32_t ctx_id,
385					  uint64_t offset, uint32_t level,
386					  uint32_t stride,
387					  uint32_t layer_stride,
388					  struct drm_virtgpu_3d_box *box,
389					  struct virtio_gpu_object_array *objs,
390					  struct virtio_gpu_fence *fence);
391void virtio_gpu_cmd_transfer_to_host_3d(struct virtio_gpu_device *vgdev,
 
392					uint32_t ctx_id,
393					uint64_t offset, uint32_t level,
394					uint32_t stride,
395					uint32_t layer_stride,
396					struct drm_virtgpu_3d_box *box,
397					struct virtio_gpu_object_array *objs,
398					struct virtio_gpu_fence *fence);
399void
400virtio_gpu_cmd_resource_create_3d(struct virtio_gpu_device *vgdev,
401				  struct virtio_gpu_object *bo,
402				  struct virtio_gpu_object_params *params,
403				  struct virtio_gpu_object_array *objs,
404				  struct virtio_gpu_fence *fence);
405void virtio_gpu_ctrl_ack(struct virtqueue *vq);
406void virtio_gpu_cursor_ack(struct virtqueue *vq);
 
407void virtio_gpu_dequeue_ctrl_func(struct work_struct *work);
408void virtio_gpu_dequeue_cursor_func(struct work_struct *work);
409void virtio_gpu_notify(struct virtio_gpu_device *vgdev);
410
411int
412virtio_gpu_cmd_resource_assign_uuid(struct virtio_gpu_device *vgdev,
413				    struct virtio_gpu_object_array *objs);
414
415int virtio_gpu_cmd_map(struct virtio_gpu_device *vgdev,
416		       struct virtio_gpu_object_array *objs, uint64_t offset);
417
418void virtio_gpu_cmd_unmap(struct virtio_gpu_device *vgdev,
419			  struct virtio_gpu_object *bo);
420
421void
422virtio_gpu_cmd_resource_create_blob(struct virtio_gpu_device *vgdev,
423				    struct virtio_gpu_object *bo,
424				    struct virtio_gpu_object_params *params,
425				    struct virtio_gpu_mem_entry *ents,
426				    uint32_t nents);
427void
428virtio_gpu_cmd_set_scanout_blob(struct virtio_gpu_device *vgdev,
429				uint32_t scanout_id,
430				struct virtio_gpu_object *bo,
431				struct drm_framebuffer *fb,
432				uint32_t width, uint32_t height,
433				uint32_t x, uint32_t y);
434
435/* virtgpu_display.c */
436int virtio_gpu_modeset_init(struct virtio_gpu_device *vgdev);
437void virtio_gpu_modeset_fini(struct virtio_gpu_device *vgdev);
438
439/* virtgpu_plane.c */
440uint32_t virtio_gpu_translate_format(uint32_t drm_fourcc);
441struct drm_plane *virtio_gpu_plane_init(struct virtio_gpu_device *vgdev,
442					enum drm_plane_type type,
443					int index);
444
445/* virtgpu_fence.c */
446struct virtio_gpu_fence *virtio_gpu_fence_alloc(struct virtio_gpu_device *vgdev,
447						uint64_t base_fence_ctx,
448						uint32_t ring_idx);
 
 
 
 
 
449void virtio_gpu_fence_emit(struct virtio_gpu_device *vgdev,
450			  struct virtio_gpu_ctrl_hdr *cmd_hdr,
451			  struct virtio_gpu_fence *fence);
452void virtio_gpu_fence_event_process(struct virtio_gpu_device *vdev,
453				    u64 fence_id);
454
455/* virtgpu_object.c */
456void virtio_gpu_cleanup_object(struct virtio_gpu_object *bo);
457struct drm_gem_object *virtio_gpu_create_object(struct drm_device *dev,
458						size_t size);
459int virtio_gpu_object_create(struct virtio_gpu_device *vgdev,
460			     struct virtio_gpu_object_params *params,
461			     struct virtio_gpu_object **bo_ptr,
462			     struct virtio_gpu_fence *fence);
 
 
 
 
 
 
463
464bool virtio_gpu_is_shmem(struct virtio_gpu_object *bo);
465
466int virtio_gpu_resource_id_get(struct virtio_gpu_device *vgdev,
467			       uint32_t *resid);
468/* virtgpu_prime.c */
469int virtio_gpu_resource_assign_uuid(struct virtio_gpu_device *vgdev,
470				    struct virtio_gpu_object *bo);
471struct dma_buf *virtgpu_gem_prime_export(struct drm_gem_object *obj,
472					 int flags);
473struct drm_gem_object *virtgpu_gem_prime_import(struct drm_device *dev,
474						struct dma_buf *buf);
475struct drm_gem_object *virtgpu_gem_prime_import_sg_table(
476	struct drm_device *dev, struct dma_buf_attachment *attach,
477	struct sg_table *sgt);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
478
479/* virtgpu_debugfs.c */
480void virtio_gpu_debugfs_init(struct drm_minor *minor);
481
482/* virtgpu_vram.c */
483bool virtio_gpu_is_vram(struct virtio_gpu_object *bo);
484int virtio_gpu_vram_create(struct virtio_gpu_device *vgdev,
485			   struct virtio_gpu_object_params *params,
486			   struct virtio_gpu_object **bo_ptr);
487struct sg_table *virtio_gpu_vram_map_dma_buf(struct virtio_gpu_object *bo,
488					     struct device *dev,
489					     enum dma_data_direction dir);
490void virtio_gpu_vram_unmap_dma_buf(struct device *dev,
491				   struct sg_table *sgt,
492				   enum dma_data_direction dir);
493
494/* virtgpu_submit.c */
495int virtio_gpu_execbuffer_ioctl(struct drm_device *dev, void *data,
496				struct drm_file *file);
497
498#endif
v5.4
  1/*
  2 * Copyright (C) 2015 Red Hat, Inc.
  3 * All Rights Reserved.
  4 *
  5 * Permission is hereby granted, free of charge, to any person obtaining
  6 * a copy of this software and associated documentation files (the
  7 * "Software"), to deal in the Software without restriction, including
  8 * without limitation the rights to use, copy, modify, merge, publish,
  9 * distribute, sublicense, and/or sell copies of the Software, and to
 10 * permit persons to whom the Software is furnished to do so, subject to
 11 * the following conditions:
 12 *
 13 * The above copyright notice and this permission notice (including the
 14 * next paragraph) shall be included in all copies or substantial
 15 * portions of the Software.
 16 *
 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
 20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
 21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
 22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
 23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 24 */
 25
 26#ifndef VIRTIO_DRV_H
 27#define VIRTIO_DRV_H
 28
 
 29#include <linux/virtio.h>
 30#include <linux/virtio_ids.h>
 31#include <linux/virtio_config.h>
 32#include <linux/virtio_gpu.h>
 33
 34#include <drm/drm_atomic.h>
 
 35#include <drm/drm_encoder.h>
 36#include <drm/drm_fb_helper.h>
 
 37#include <drm/drm_gem.h>
 
 38#include <drm/drm_ioctl.h>
 39#include <drm/drm_probe_helper.h>
 40#include <drm/ttm/ttm_bo_api.h>
 41#include <drm/ttm/ttm_bo_driver.h>
 42#include <drm/ttm/ttm_module.h>
 43#include <drm/ttm/ttm_placement.h>
 44
 45#define DRIVER_NAME "virtio_gpu"
 46#define DRIVER_DESC "virtio GPU"
 47#define DRIVER_DATE "0"
 48
 49#define DRIVER_MAJOR 0
 50#define DRIVER_MINOR 1
 51#define DRIVER_PATCHLEVEL 0
 52
 
 
 
 
 
 
 
 
 
 
 53struct virtio_gpu_object_params {
 54	uint32_t format;
 55	uint32_t width;
 56	uint32_t height;
 57	unsigned long size;
 58	bool dumb;
 59	/* 3d */
 60	bool virgl;
 
 
 
 
 
 
 61	uint32_t target;
 62	uint32_t bind;
 63	uint32_t depth;
 64	uint32_t array_size;
 65	uint32_t last_level;
 66	uint32_t nr_samples;
 67	uint32_t flags;
 
 
 
 
 
 
 68};
 69
 70struct virtio_gpu_object {
 71	struct drm_gem_object gem_base;
 72	uint32_t hw_res_handle;
 73
 74	struct sg_table *pages;
 75	uint32_t mapped;
 76	void *vmap;
 77	bool dumb;
 78	struct ttm_place                placement_code;
 79	struct ttm_placement		placement;
 80	struct ttm_buffer_object	tbo;
 81	struct ttm_bo_kmap_obj		kmap;
 82	bool created;
 
 
 
 
 
 83};
 84#define gem_to_virtio_gpu_obj(gobj) \
 85	container_of((gobj), struct virtio_gpu_object, gem_base)
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 86
 87struct virtio_gpu_vbuffer;
 88struct virtio_gpu_device;
 89
 90typedef void (*virtio_gpu_resp_cb)(struct virtio_gpu_device *vgdev,
 91				   struct virtio_gpu_vbuffer *vbuf);
 92
 93struct virtio_gpu_fence_driver {
 94	atomic64_t       last_seq;
 95	uint64_t         sync_seq;
 96	uint64_t         context;
 97	struct list_head fences;
 98	spinlock_t       lock;
 99};
100
 
 
 
 
 
101struct virtio_gpu_fence {
102	struct dma_fence f;
 
 
 
 
103	struct virtio_gpu_fence_driver *drv;
104	struct list_head node;
105};
106#define to_virtio_fence(x) \
107	container_of(x, struct virtio_gpu_fence, f)
108
109struct virtio_gpu_vbuffer {
110	char *buf;
111	int size;
112
113	void *data_buf;
114	uint32_t data_size;
115
116	char *resp_buf;
117	int resp_size;
118
119	virtio_gpu_resp_cb resp_cb;
 
120
 
121	struct list_head list;
 
 
122};
123
124struct virtio_gpu_output {
125	int index;
126	struct drm_crtc crtc;
127	struct drm_connector conn;
128	struct drm_encoder enc;
129	struct virtio_gpu_display_one info;
130	struct virtio_gpu_update_cursor cursor;
131	struct edid *edid;
132	int cur_x;
133	int cur_y;
134	bool enabled;
135};
136#define drm_crtc_to_virtio_gpu_output(x) \
137	container_of(x, struct virtio_gpu_output, crtc)
138#define drm_connector_to_virtio_gpu_output(x) \
139	container_of(x, struct virtio_gpu_output, conn)
140#define drm_encoder_to_virtio_gpu_output(x) \
141	container_of(x, struct virtio_gpu_output, enc)
142
143struct virtio_gpu_framebuffer {
144	struct drm_framebuffer base;
145	struct virtio_gpu_fence *fence;
146};
147#define to_virtio_gpu_framebuffer(x) \
148	container_of(x, struct virtio_gpu_framebuffer, base)
149
150struct virtio_gpu_mman {
151	struct ttm_bo_device		bdev;
 
152};
 
 
153
154struct virtio_gpu_queue {
155	struct virtqueue *vq;
156	spinlock_t qlock;
157	wait_queue_head_t ack_queue;
158	struct work_struct dequeue_work;
 
159};
160
161struct virtio_gpu_drv_capset {
162	uint32_t id;
163	uint32_t max_version;
164	uint32_t max_size;
165};
166
167struct virtio_gpu_drv_cap_cache {
168	struct list_head head;
169	void *caps_cache;
170	uint32_t id;
171	uint32_t version;
172	uint32_t size;
173	atomic_t is_valid;
174};
175
176struct virtio_gpu_device {
177	struct device *dev;
178	struct drm_device *ddev;
179
180	struct virtio_device *vdev;
181
182	struct virtio_gpu_mman mman;
183
184	struct virtio_gpu_output outputs[VIRTIO_GPU_MAX_SCANOUTS];
185	uint32_t num_scanouts;
186
187	struct virtio_gpu_queue ctrlq;
188	struct virtio_gpu_queue cursorq;
189	struct kmem_cache *vbufs;
190	bool vqs_ready;
 
191
192	struct ida	resource_ida;
193
194	wait_queue_head_t resp_wq;
195	/* current display info */
196	spinlock_t display_info_lock;
197	bool display_info_pending;
198
199	struct virtio_gpu_fence_driver fence_drv;
200
201	struct ida	ctx_id_ida;
202
203	bool has_virgl_3d;
204	bool has_edid;
 
 
 
 
 
 
 
205
206	struct work_struct config_changed_work;
207
 
 
 
 
208	struct virtio_gpu_drv_capset *capsets;
209	uint32_t num_capsets;
 
210	struct list_head cap_cache;
 
 
 
 
 
211};
212
213struct virtio_gpu_fpriv {
214	uint32_t ctx_id;
 
 
 
 
 
 
 
 
215};
216
217/* virtio_ioctl.c */
218#define DRM_VIRTIO_NUM_IOCTLS 10
219extern struct drm_ioctl_desc virtio_gpu_ioctls[DRM_VIRTIO_NUM_IOCTLS];
220int virtio_gpu_object_list_validate(struct ww_acquire_ctx *ticket,
221				    struct list_head *head);
222void virtio_gpu_unref_list(struct list_head *head);
223
224/* virtio_kms.c */
225int virtio_gpu_init(struct drm_device *dev);
226void virtio_gpu_deinit(struct drm_device *dev);
 
227int virtio_gpu_driver_open(struct drm_device *dev, struct drm_file *file);
228void virtio_gpu_driver_postclose(struct drm_device *dev, struct drm_file *file);
229
230/* virtio_gem.c */
231void virtio_gpu_gem_free_object(struct drm_gem_object *gem_obj);
232int virtio_gpu_gem_init(struct virtio_gpu_device *vgdev);
233void virtio_gpu_gem_fini(struct virtio_gpu_device *vgdev);
234int virtio_gpu_gem_create(struct drm_file *file,
235			  struct drm_device *dev,
236			  struct virtio_gpu_object_params *params,
237			  struct drm_gem_object **obj_p,
238			  uint32_t *handle_p);
239int virtio_gpu_gem_object_open(struct drm_gem_object *obj,
240			       struct drm_file *file);
241void virtio_gpu_gem_object_close(struct drm_gem_object *obj,
242				 struct drm_file *file);
243struct virtio_gpu_object*
244virtio_gpu_alloc_object(struct drm_device *dev,
245			struct virtio_gpu_object_params *params,
246			struct virtio_gpu_fence *fence);
247int virtio_gpu_mode_dumb_create(struct drm_file *file_priv,
248				struct drm_device *dev,
249				struct drm_mode_create_dumb *args);
250int virtio_gpu_mode_dumb_mmap(struct drm_file *file_priv,
251			      struct drm_device *dev,
252			      uint32_t handle, uint64_t *offset_p);
253
254/* virtio vg */
 
 
 
 
 
 
 
 
 
 
 
 
 
 
255int virtio_gpu_alloc_vbufs(struct virtio_gpu_device *vgdev);
256void virtio_gpu_free_vbufs(struct virtio_gpu_device *vgdev);
257void virtio_gpu_cmd_create_resource(struct virtio_gpu_device *vgdev,
258				    struct virtio_gpu_object *bo,
259				    struct virtio_gpu_object_params *params,
 
260				    struct virtio_gpu_fence *fence);
261void virtio_gpu_cmd_unref_resource(struct virtio_gpu_device *vgdev,
262				   uint32_t resource_id);
263void virtio_gpu_cmd_transfer_to_host_2d(struct virtio_gpu_device *vgdev,
264					struct virtio_gpu_object *bo,
265					uint64_t offset,
266					__le32 width, __le32 height,
267					__le32 x, __le32 y,
 
268					struct virtio_gpu_fence *fence);
269void virtio_gpu_cmd_resource_flush(struct virtio_gpu_device *vgdev,
270				   uint32_t resource_id,
271				   uint32_t x, uint32_t y,
272				   uint32_t width, uint32_t height);
 
 
273void virtio_gpu_cmd_set_scanout(struct virtio_gpu_device *vgdev,
274				uint32_t scanout_id, uint32_t resource_id,
275				uint32_t width, uint32_t height,
276				uint32_t x, uint32_t y);
277int virtio_gpu_object_attach(struct virtio_gpu_device *vgdev,
278			     struct virtio_gpu_object *obj,
279			     struct virtio_gpu_fence *fence);
280void virtio_gpu_object_detach(struct virtio_gpu_device *vgdev,
281			      struct virtio_gpu_object *obj);
282int virtio_gpu_attach_status_page(struct virtio_gpu_device *vgdev);
283int virtio_gpu_detach_status_page(struct virtio_gpu_device *vgdev);
284void virtio_gpu_cursor_ping(struct virtio_gpu_device *vgdev,
285			    struct virtio_gpu_output *output);
286int virtio_gpu_cmd_get_display_info(struct virtio_gpu_device *vgdev);
287int virtio_gpu_cmd_get_capset_info(struct virtio_gpu_device *vgdev, int idx);
288int virtio_gpu_cmd_get_capset(struct virtio_gpu_device *vgdev,
289			      int idx, int version,
290			      struct virtio_gpu_drv_cap_cache **cache_p);
291int virtio_gpu_cmd_get_edids(struct virtio_gpu_device *vgdev);
292void virtio_gpu_cmd_context_create(struct virtio_gpu_device *vgdev, uint32_t id,
293				   uint32_t nlen, const char *name);
 
294void virtio_gpu_cmd_context_destroy(struct virtio_gpu_device *vgdev,
295				    uint32_t id);
296void virtio_gpu_cmd_context_attach_resource(struct virtio_gpu_device *vgdev,
297					    uint32_t ctx_id,
298					    uint32_t resource_id);
299void virtio_gpu_cmd_context_detach_resource(struct virtio_gpu_device *vgdev,
300					    uint32_t ctx_id,
301					    uint32_t resource_id);
302void virtio_gpu_cmd_submit(struct virtio_gpu_device *vgdev,
303			   void *data, uint32_t data_size,
304			   uint32_t ctx_id, struct virtio_gpu_fence *fence);
 
 
305void virtio_gpu_cmd_transfer_from_host_3d(struct virtio_gpu_device *vgdev,
306					  uint32_t resource_id, uint32_t ctx_id,
307					  uint64_t offset, uint32_t level,
308					  struct virtio_gpu_box *box,
 
 
 
309					  struct virtio_gpu_fence *fence);
310void virtio_gpu_cmd_transfer_to_host_3d(struct virtio_gpu_device *vgdev,
311					struct virtio_gpu_object *bo,
312					uint32_t ctx_id,
313					uint64_t offset, uint32_t level,
314					struct virtio_gpu_box *box,
 
 
 
315					struct virtio_gpu_fence *fence);
316void
317virtio_gpu_cmd_resource_create_3d(struct virtio_gpu_device *vgdev,
318				  struct virtio_gpu_object *bo,
319				  struct virtio_gpu_object_params *params,
 
320				  struct virtio_gpu_fence *fence);
321void virtio_gpu_ctrl_ack(struct virtqueue *vq);
322void virtio_gpu_cursor_ack(struct virtqueue *vq);
323void virtio_gpu_fence_ack(struct virtqueue *vq);
324void virtio_gpu_dequeue_ctrl_func(struct work_struct *work);
325void virtio_gpu_dequeue_cursor_func(struct work_struct *work);
326void virtio_gpu_dequeue_fence_func(struct work_struct *work);
 
 
 
 
 
 
 
327
328/* virtio_gpu_display.c */
329int virtio_gpu_framebuffer_init(struct drm_device *dev,
330				struct virtio_gpu_framebuffer *vgfb,
331				const struct drm_mode_fb_cmd2 *mode_cmd,
332				struct drm_gem_object *obj);
333void virtio_gpu_modeset_init(struct virtio_gpu_device *vgdev);
 
 
 
 
 
 
 
 
 
 
 
 
 
334void virtio_gpu_modeset_fini(struct virtio_gpu_device *vgdev);
335
336/* virtio_gpu_plane.c */
337uint32_t virtio_gpu_translate_format(uint32_t drm_fourcc);
338struct drm_plane *virtio_gpu_plane_init(struct virtio_gpu_device *vgdev,
339					enum drm_plane_type type,
340					int index);
341
342/* virtio_gpu_ttm.c */
343int virtio_gpu_ttm_init(struct virtio_gpu_device *vgdev);
344void virtio_gpu_ttm_fini(struct virtio_gpu_device *vgdev);
345int virtio_gpu_mmap(struct file *filp, struct vm_area_struct *vma);
346
347/* virtio_gpu_fence.c */
348bool virtio_fence_signaled(struct dma_fence *f);
349struct virtio_gpu_fence *virtio_gpu_fence_alloc(
350	struct virtio_gpu_device *vgdev);
351void virtio_gpu_fence_emit(struct virtio_gpu_device *vgdev,
352			  struct virtio_gpu_ctrl_hdr *cmd_hdr,
353			  struct virtio_gpu_fence *fence);
354void virtio_gpu_fence_event_process(struct virtio_gpu_device *vdev,
355				    u64 last_seq);
356
357/* virtio_gpu_object */
 
 
 
358int virtio_gpu_object_create(struct virtio_gpu_device *vgdev,
359			     struct virtio_gpu_object_params *params,
360			     struct virtio_gpu_object **bo_ptr,
361			     struct virtio_gpu_fence *fence);
362void virtio_gpu_object_kunmap(struct virtio_gpu_object *bo);
363int virtio_gpu_object_kmap(struct virtio_gpu_object *bo);
364int virtio_gpu_object_get_sg_table(struct virtio_gpu_device *qdev,
365				   struct virtio_gpu_object *bo);
366void virtio_gpu_object_free_sg_table(struct virtio_gpu_object *bo);
367int virtio_gpu_object_wait(struct virtio_gpu_object *bo, bool no_wait);
368
 
 
 
 
369/* virtgpu_prime.c */
370struct sg_table *virtgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
 
 
 
 
 
371struct drm_gem_object *virtgpu_gem_prime_import_sg_table(
372	struct drm_device *dev, struct dma_buf_attachment *attach,
373	struct sg_table *sgt);
374void *virtgpu_gem_prime_vmap(struct drm_gem_object *obj);
375void virtgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
376int virtgpu_gem_prime_mmap(struct drm_gem_object *obj,
377			   struct vm_area_struct *vma);
378
379static inline struct virtio_gpu_object*
380virtio_gpu_object_ref(struct virtio_gpu_object *bo)
381{
382	ttm_bo_get(&bo->tbo);
383	return bo;
384}
385
386static inline void virtio_gpu_object_unref(struct virtio_gpu_object **bo)
387{
388	struct ttm_buffer_object *tbo;
389
390	if ((*bo) == NULL)
391		return;
392	tbo = &((*bo)->tbo);
393	ttm_bo_put(tbo);
394	*bo = NULL;
395}
396
397static inline u64 virtio_gpu_object_mmap_offset(struct virtio_gpu_object *bo)
398{
399	return drm_vma_node_offset_addr(&bo->tbo.base.vma_node);
400}
401
402static inline int virtio_gpu_object_reserve(struct virtio_gpu_object *bo,
403					 bool no_wait)
404{
405	int r;
406
407	r = ttm_bo_reserve(&bo->tbo, true, no_wait, NULL);
408	if (unlikely(r != 0)) {
409		if (r != -ERESTARTSYS) {
410			struct virtio_gpu_device *qdev =
411				bo->gem_base.dev->dev_private;
412			dev_err(qdev->dev, "%p reserve failed\n", bo);
413		}
414		return r;
415	}
416	return 0;
417}
418
419static inline void virtio_gpu_object_unreserve(struct virtio_gpu_object *bo)
420{
421	ttm_bo_unreserve(&bo->tbo);
422}
423
424/* virgl debufs */
425int virtio_gpu_debugfs_init(struct drm_minor *minor);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
426
427#endif