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1/*
2 * Copyright 2009 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26/*
27 * Authors:
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Dave Airlie
30 */
31
32#include <linux/atomic.h>
33#include <linux/debugfs.h>
34#include <linux/firmware.h>
35#include <linux/kref.h>
36#include <linux/sched/signal.h>
37#include <linux/seq_file.h>
38#include <linux/slab.h>
39#include <linux/wait.h>
40
41#include <drm/drm_device.h>
42#include <drm/drm_file.h>
43
44#include "radeon.h"
45#include "radeon_reg.h"
46#include "radeon_trace.h"
47
48/*
49 * Fences mark an event in the GPUs pipeline and are used
50 * for GPU/CPU synchronization. When the fence is written,
51 * it is expected that all buffers associated with that fence
52 * are no longer in use by the associated ring on the GPU and
53 * that the relevant GPU caches have been flushed. Whether
54 * we use a scratch register or memory location depends on the asic
55 * and whether writeback is enabled.
56 */
57
58/**
59 * radeon_fence_write - write a fence value
60 *
61 * @rdev: radeon_device pointer
62 * @seq: sequence number to write
63 * @ring: ring index the fence is associated with
64 *
65 * Writes a fence value to memory or a scratch register (all asics).
66 */
67static void radeon_fence_write(struct radeon_device *rdev, u32 seq, int ring)
68{
69 struct radeon_fence_driver *drv = &rdev->fence_drv[ring];
70
71 if (likely(rdev->wb.enabled || !drv->scratch_reg)) {
72 if (drv->cpu_addr)
73 *drv->cpu_addr = cpu_to_le32(seq);
74 } else {
75 WREG32(drv->scratch_reg, seq);
76 }
77}
78
79/**
80 * radeon_fence_read - read a fence value
81 *
82 * @rdev: radeon_device pointer
83 * @ring: ring index the fence is associated with
84 *
85 * Reads a fence value from memory or a scratch register (all asics).
86 * Returns the value of the fence read from memory or register.
87 */
88static u32 radeon_fence_read(struct radeon_device *rdev, int ring)
89{
90 struct radeon_fence_driver *drv = &rdev->fence_drv[ring];
91 u32 seq = 0;
92
93 if (likely(rdev->wb.enabled || !drv->scratch_reg)) {
94 if (drv->cpu_addr)
95 seq = le32_to_cpu(*drv->cpu_addr);
96 else
97 seq = lower_32_bits(atomic64_read(&drv->last_seq));
98 } else {
99 seq = RREG32(drv->scratch_reg);
100 }
101 return seq;
102}
103
104/**
105 * radeon_fence_schedule_check - schedule lockup check
106 *
107 * @rdev: radeon_device pointer
108 * @ring: ring index we should work with
109 *
110 * Queues a delayed work item to check for lockups.
111 */
112static void radeon_fence_schedule_check(struct radeon_device *rdev, int ring)
113{
114 /*
115 * Do not reset the timer here with mod_delayed_work,
116 * this can livelock in an interaction with TTM delayed destroy.
117 */
118 queue_delayed_work(system_power_efficient_wq,
119 &rdev->fence_drv[ring].lockup_work,
120 RADEON_FENCE_JIFFIES_TIMEOUT);
121}
122
123/**
124 * radeon_fence_emit - emit a fence on the requested ring
125 *
126 * @rdev: radeon_device pointer
127 * @fence: radeon fence object
128 * @ring: ring index the fence is associated with
129 *
130 * Emits a fence command on the requested ring (all asics).
131 * Returns 0 on success, -ENOMEM on failure.
132 */
133int radeon_fence_emit(struct radeon_device *rdev,
134 struct radeon_fence **fence,
135 int ring)
136{
137 u64 seq;
138
139 /* we are protected by the ring emission mutex */
140 *fence = kmalloc(sizeof(struct radeon_fence), GFP_KERNEL);
141 if ((*fence) == NULL)
142 return -ENOMEM;
143
144 (*fence)->rdev = rdev;
145 (*fence)->seq = seq = ++rdev->fence_drv[ring].sync_seq[ring];
146 (*fence)->ring = ring;
147 (*fence)->is_vm_update = false;
148 dma_fence_init(&(*fence)->base, &radeon_fence_ops,
149 &rdev->fence_queue.lock,
150 rdev->fence_context + ring,
151 seq);
152 radeon_fence_ring_emit(rdev, ring, *fence);
153 trace_radeon_fence_emit(rdev_to_drm(rdev), ring, (*fence)->seq);
154 radeon_fence_schedule_check(rdev, ring);
155 return 0;
156}
157
158/*
159 * radeon_fence_check_signaled - callback from fence_queue
160 *
161 * this function is called with fence_queue lock held, which is also used
162 * for the fence locking itself, so unlocked variants are used for
163 * fence_signal, and remove_wait_queue.
164 */
165static int radeon_fence_check_signaled(wait_queue_entry_t *wait,
166 unsigned int mode, int flags, void *key)
167{
168 struct radeon_fence *fence;
169 u64 seq;
170
171 fence = container_of(wait, struct radeon_fence, fence_wake);
172
173 /*
174 * We cannot use radeon_fence_process here because we're already
175 * in the waitqueue, in a call from wake_up_all.
176 */
177 seq = atomic64_read(&fence->rdev->fence_drv[fence->ring].last_seq);
178 if (seq >= fence->seq) {
179 dma_fence_signal_locked(&fence->base);
180 radeon_irq_kms_sw_irq_put(fence->rdev, fence->ring);
181 __remove_wait_queue(&fence->rdev->fence_queue, &fence->fence_wake);
182 dma_fence_put(&fence->base);
183 }
184 return 0;
185}
186
187/**
188 * radeon_fence_activity - check for fence activity
189 *
190 * @rdev: radeon_device pointer
191 * @ring: ring index the fence is associated with
192 *
193 * Checks the current fence value and calculates the last
194 * signalled fence value. Returns true if activity occured
195 * on the ring, and the fence_queue should be waken up.
196 */
197static bool radeon_fence_activity(struct radeon_device *rdev, int ring)
198{
199 uint64_t seq, last_seq, last_emitted;
200 unsigned int count_loop = 0;
201 bool wake = false;
202
203 /* Note there is a scenario here for an infinite loop but it's
204 * very unlikely to happen. For it to happen, the current polling
205 * process need to be interrupted by another process and another
206 * process needs to update the last_seq btw the atomic read and
207 * xchg of the current process.
208 *
209 * More over for this to go in infinite loop there need to be
210 * continuously new fence signaled ie radeon_fence_read needs
211 * to return a different value each time for both the currently
212 * polling process and the other process that xchg the last_seq
213 * btw atomic read and xchg of the current process. And the
214 * value the other process set as last seq must be higher than
215 * the seq value we just read. Which means that current process
216 * need to be interrupted after radeon_fence_read and before
217 * atomic xchg.
218 *
219 * To be even more safe we count the number of time we loop and
220 * we bail after 10 loop just accepting the fact that we might
221 * have temporarly set the last_seq not to the true real last
222 * seq but to an older one.
223 */
224 last_seq = atomic64_read(&rdev->fence_drv[ring].last_seq);
225 do {
226 last_emitted = rdev->fence_drv[ring].sync_seq[ring];
227 seq = radeon_fence_read(rdev, ring);
228 seq |= last_seq & 0xffffffff00000000LL;
229 if (seq < last_seq) {
230 seq &= 0xffffffff;
231 seq |= last_emitted & 0xffffffff00000000LL;
232 }
233
234 if (seq <= last_seq || seq > last_emitted)
235 break;
236
237 /* If we loop over we don't want to return without
238 * checking if a fence is signaled as it means that the
239 * seq we just read is different from the previous on.
240 */
241 wake = true;
242 last_seq = seq;
243 if ((count_loop++) > 10) {
244 /* We looped over too many time leave with the
245 * fact that we might have set an older fence
246 * seq then the current real last seq as signaled
247 * by the hw.
248 */
249 break;
250 }
251 } while (atomic64_xchg(&rdev->fence_drv[ring].last_seq, seq) > seq);
252
253 if (seq < last_emitted)
254 radeon_fence_schedule_check(rdev, ring);
255
256 return wake;
257}
258
259/**
260 * radeon_fence_check_lockup - check for hardware lockup
261 *
262 * @work: delayed work item
263 *
264 * Checks for fence activity and if there is none probe
265 * the hardware if a lockup occured.
266 */
267static void radeon_fence_check_lockup(struct work_struct *work)
268{
269 struct radeon_fence_driver *fence_drv;
270 struct radeon_device *rdev;
271 int ring;
272
273 fence_drv = container_of(work, struct radeon_fence_driver,
274 lockup_work.work);
275 rdev = fence_drv->rdev;
276 ring = fence_drv - &rdev->fence_drv[0];
277
278 if (!down_read_trylock(&rdev->exclusive_lock)) {
279 /* just reschedule the check if a reset is going on */
280 radeon_fence_schedule_check(rdev, ring);
281 return;
282 }
283
284 if (fence_drv->delayed_irq && rdev->irq.installed) {
285 unsigned long irqflags;
286
287 fence_drv->delayed_irq = false;
288 spin_lock_irqsave(&rdev->irq.lock, irqflags);
289 radeon_irq_set(rdev);
290 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
291 }
292
293 if (radeon_fence_activity(rdev, ring))
294 wake_up_all(&rdev->fence_queue);
295
296 else if (radeon_ring_is_lockup(rdev, ring, &rdev->ring[ring])) {
297
298 /* good news we believe it's a lockup */
299 dev_warn(rdev->dev, "GPU lockup (current fence id 0x%016llx last fence id 0x%016llx on ring %d)\n",
300 (uint64_t)atomic64_read(&fence_drv->last_seq),
301 fence_drv->sync_seq[ring], ring);
302
303 /* remember that we need an reset */
304 rdev->needs_reset = true;
305 wake_up_all(&rdev->fence_queue);
306 }
307 up_read(&rdev->exclusive_lock);
308}
309
310/**
311 * radeon_fence_process - process a fence
312 *
313 * @rdev: radeon_device pointer
314 * @ring: ring index the fence is associated with
315 *
316 * Checks the current fence value and wakes the fence queue
317 * if the sequence number has increased (all asics).
318 */
319void radeon_fence_process(struct radeon_device *rdev, int ring)
320{
321 if (radeon_fence_activity(rdev, ring))
322 wake_up_all(&rdev->fence_queue);
323}
324
325/**
326 * radeon_fence_seq_signaled - check if a fence sequence number has signaled
327 *
328 * @rdev: radeon device pointer
329 * @seq: sequence number
330 * @ring: ring index the fence is associated with
331 *
332 * Check if the last signaled fence sequnce number is >= the requested
333 * sequence number (all asics).
334 * Returns true if the fence has signaled (current fence value
335 * is >= requested value) or false if it has not (current fence
336 * value is < the requested value. Helper function for
337 * radeon_fence_signaled().
338 */
339static bool radeon_fence_seq_signaled(struct radeon_device *rdev,
340 u64 seq, unsigned int ring)
341{
342 if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq)
343 return true;
344
345 /* poll new last sequence at least once */
346 radeon_fence_process(rdev, ring);
347 if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq)
348 return true;
349
350 return false;
351}
352
353static bool radeon_fence_is_signaled(struct dma_fence *f)
354{
355 struct radeon_fence *fence = to_radeon_fence(f);
356 struct radeon_device *rdev = fence->rdev;
357 unsigned int ring = fence->ring;
358 u64 seq = fence->seq;
359
360 if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq)
361 return true;
362
363 if (down_read_trylock(&rdev->exclusive_lock)) {
364 radeon_fence_process(rdev, ring);
365 up_read(&rdev->exclusive_lock);
366
367 if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq)
368 return true;
369 }
370 return false;
371}
372
373/**
374 * radeon_fence_enable_signaling - enable signalling on fence
375 * @f: fence
376 *
377 * This function is called with fence_queue lock held, and adds a callback
378 * to fence_queue that checks if this fence is signaled, and if so it
379 * signals the fence and removes itself.
380 */
381static bool radeon_fence_enable_signaling(struct dma_fence *f)
382{
383 struct radeon_fence *fence = to_radeon_fence(f);
384 struct radeon_device *rdev = fence->rdev;
385
386 if (atomic64_read(&rdev->fence_drv[fence->ring].last_seq) >= fence->seq)
387 return false;
388
389 if (down_read_trylock(&rdev->exclusive_lock)) {
390 radeon_irq_kms_sw_irq_get(rdev, fence->ring);
391
392 if (radeon_fence_activity(rdev, fence->ring))
393 wake_up_all_locked(&rdev->fence_queue);
394
395 /* did fence get signaled after we enabled the sw irq? */
396 if (atomic64_read(&rdev->fence_drv[fence->ring].last_seq) >= fence->seq) {
397 radeon_irq_kms_sw_irq_put(rdev, fence->ring);
398 up_read(&rdev->exclusive_lock);
399 return false;
400 }
401
402 up_read(&rdev->exclusive_lock);
403 } else {
404 /* we're probably in a lockup, lets not fiddle too much */
405 if (radeon_irq_kms_sw_irq_get_delayed(rdev, fence->ring))
406 rdev->fence_drv[fence->ring].delayed_irq = true;
407 radeon_fence_schedule_check(rdev, fence->ring);
408 }
409
410 fence->fence_wake.flags = 0;
411 fence->fence_wake.private = NULL;
412 fence->fence_wake.func = radeon_fence_check_signaled;
413 __add_wait_queue(&rdev->fence_queue, &fence->fence_wake);
414 dma_fence_get(f);
415 return true;
416}
417
418/**
419 * radeon_fence_signaled - check if a fence has signaled
420 *
421 * @fence: radeon fence object
422 *
423 * Check if the requested fence has signaled (all asics).
424 * Returns true if the fence has signaled or false if it has not.
425 */
426bool radeon_fence_signaled(struct radeon_fence *fence)
427{
428 if (!fence)
429 return true;
430
431 if (radeon_fence_seq_signaled(fence->rdev, fence->seq, fence->ring)) {
432 dma_fence_signal(&fence->base);
433 return true;
434 }
435 return false;
436}
437
438/**
439 * radeon_fence_any_seq_signaled - check if any sequence number is signaled
440 *
441 * @rdev: radeon device pointer
442 * @seq: sequence numbers
443 *
444 * Check if the last signaled fence sequnce number is >= the requested
445 * sequence number (all asics).
446 * Returns true if any has signaled (current value is >= requested value)
447 * or false if it has not. Helper function for radeon_fence_wait_seq.
448 */
449static bool radeon_fence_any_seq_signaled(struct radeon_device *rdev, u64 *seq)
450{
451 unsigned int i;
452
453 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
454 if (seq[i] && radeon_fence_seq_signaled(rdev, seq[i], i))
455 return true;
456 }
457 return false;
458}
459
460/**
461 * radeon_fence_wait_seq_timeout - wait for a specific sequence numbers
462 *
463 * @rdev: radeon device pointer
464 * @target_seq: sequence number(s) we want to wait for
465 * @intr: use interruptable sleep
466 * @timeout: maximum time to wait, or MAX_SCHEDULE_TIMEOUT for infinite wait
467 *
468 * Wait for the requested sequence number(s) to be written by any ring
469 * (all asics). Sequnce number array is indexed by ring id.
470 * @intr selects whether to use interruptable (true) or non-interruptable
471 * (false) sleep when waiting for the sequence number. Helper function
472 * for radeon_fence_wait_*().
473 * Returns remaining time if the sequence number has passed, 0 when
474 * the wait timeout, or an error for all other cases.
475 * -EDEADLK is returned when a GPU lockup has been detected.
476 */
477static long radeon_fence_wait_seq_timeout(struct radeon_device *rdev,
478 u64 *target_seq, bool intr,
479 long timeout)
480{
481 long r;
482 int i;
483
484 if (radeon_fence_any_seq_signaled(rdev, target_seq))
485 return timeout;
486
487 /* enable IRQs and tracing */
488 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
489 if (!target_seq[i])
490 continue;
491
492 trace_radeon_fence_wait_begin(rdev_to_drm(rdev), i, target_seq[i]);
493 radeon_irq_kms_sw_irq_get(rdev, i);
494 }
495
496 if (intr) {
497 r = wait_event_interruptible_timeout(rdev->fence_queue, (
498 radeon_fence_any_seq_signaled(rdev, target_seq)
499 || rdev->needs_reset), timeout);
500 } else {
501 r = wait_event_timeout(rdev->fence_queue, (
502 radeon_fence_any_seq_signaled(rdev, target_seq)
503 || rdev->needs_reset), timeout);
504 }
505
506 if (rdev->needs_reset)
507 r = -EDEADLK;
508
509 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
510 if (!target_seq[i])
511 continue;
512
513 radeon_irq_kms_sw_irq_put(rdev, i);
514 trace_radeon_fence_wait_end(rdev_to_drm(rdev), i, target_seq[i]);
515 }
516
517 return r;
518}
519
520/**
521 * radeon_fence_wait_timeout - wait for a fence to signal with timeout
522 *
523 * @fence: radeon fence object
524 * @intr: use interruptible sleep
525 *
526 * Wait for the requested fence to signal (all asics).
527 * @intr selects whether to use interruptable (true) or non-interruptable
528 * (false) sleep when waiting for the fence.
529 * @timeout: maximum time to wait, or MAX_SCHEDULE_TIMEOUT for infinite wait
530 * Returns remaining time if the sequence number has passed, 0 when
531 * the wait timeout, or an error for all other cases.
532 */
533long radeon_fence_wait_timeout(struct radeon_fence *fence, bool intr, long timeout)
534{
535 uint64_t seq[RADEON_NUM_RINGS] = {};
536 long r;
537
538 /*
539 * This function should not be called on !radeon fences.
540 * If this is the case, it would mean this function can
541 * also be called on radeon fences belonging to another card.
542 * exclusive_lock is not held in that case.
543 */
544 if (WARN_ON_ONCE(!to_radeon_fence(&fence->base)))
545 return dma_fence_wait(&fence->base, intr);
546
547 seq[fence->ring] = fence->seq;
548 r = radeon_fence_wait_seq_timeout(fence->rdev, seq, intr, timeout);
549 if (r <= 0)
550 return r;
551
552 dma_fence_signal(&fence->base);
553 return r;
554}
555
556/**
557 * radeon_fence_wait - wait for a fence to signal
558 *
559 * @fence: radeon fence object
560 * @intr: use interruptible sleep
561 *
562 * Wait for the requested fence to signal (all asics).
563 * @intr selects whether to use interruptable (true) or non-interruptable
564 * (false) sleep when waiting for the fence.
565 * Returns 0 if the fence has passed, error for all other cases.
566 */
567int radeon_fence_wait(struct radeon_fence *fence, bool intr)
568{
569 long r = radeon_fence_wait_timeout(fence, intr, MAX_SCHEDULE_TIMEOUT);
570
571 if (r > 0)
572 return 0;
573 else
574 return r;
575}
576
577/**
578 * radeon_fence_wait_any - wait for a fence to signal on any ring
579 *
580 * @rdev: radeon device pointer
581 * @fences: radeon fence object(s)
582 * @intr: use interruptable sleep
583 *
584 * Wait for any requested fence to signal (all asics). Fence
585 * array is indexed by ring id. @intr selects whether to use
586 * interruptable (true) or non-interruptable (false) sleep when
587 * waiting for the fences. Used by the suballocator.
588 * Returns 0 if any fence has passed, error for all other cases.
589 */
590int radeon_fence_wait_any(struct radeon_device *rdev,
591 struct radeon_fence **fences,
592 bool intr)
593{
594 uint64_t seq[RADEON_NUM_RINGS];
595 unsigned int i, num_rings = 0;
596 long r;
597
598 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
599 seq[i] = 0;
600
601 if (!fences[i])
602 continue;
603
604 seq[i] = fences[i]->seq;
605 ++num_rings;
606 }
607
608 /* nothing to wait for ? */
609 if (num_rings == 0)
610 return -ENOENT;
611
612 r = radeon_fence_wait_seq_timeout(rdev, seq, intr, MAX_SCHEDULE_TIMEOUT);
613 if (r < 0)
614 return r;
615
616 return 0;
617}
618
619/**
620 * radeon_fence_wait_next - wait for the next fence to signal
621 *
622 * @rdev: radeon device pointer
623 * @ring: ring index the fence is associated with
624 *
625 * Wait for the next fence on the requested ring to signal (all asics).
626 * Returns 0 if the next fence has passed, error for all other cases.
627 * Caller must hold ring lock.
628 */
629int radeon_fence_wait_next(struct radeon_device *rdev, int ring)
630{
631 uint64_t seq[RADEON_NUM_RINGS] = {};
632 long r;
633
634 seq[ring] = atomic64_read(&rdev->fence_drv[ring].last_seq) + 1ULL;
635 if (seq[ring] >= rdev->fence_drv[ring].sync_seq[ring]) {
636 /* nothing to wait for, last_seq is already
637 * the last emited fence
638 */
639 return -ENOENT;
640 }
641
642 r = radeon_fence_wait_seq_timeout(rdev, seq, false, MAX_SCHEDULE_TIMEOUT);
643 if (r < 0)
644 return r;
645
646 return 0;
647}
648
649/**
650 * radeon_fence_wait_empty - wait for all fences to signal
651 *
652 * @rdev: radeon device pointer
653 * @ring: ring index the fence is associated with
654 *
655 * Wait for all fences on the requested ring to signal (all asics).
656 * Returns 0 if the fences have passed, error for all other cases.
657 * Caller must hold ring lock.
658 */
659int radeon_fence_wait_empty(struct radeon_device *rdev, int ring)
660{
661 uint64_t seq[RADEON_NUM_RINGS] = {};
662 long r;
663
664 seq[ring] = rdev->fence_drv[ring].sync_seq[ring];
665 if (!seq[ring])
666 return 0;
667
668 r = radeon_fence_wait_seq_timeout(rdev, seq, false, MAX_SCHEDULE_TIMEOUT);
669 if (r < 0) {
670 if (r == -EDEADLK)
671 return -EDEADLK;
672
673 dev_err(rdev->dev, "error waiting for ring[%d] to become idle (%ld)\n",
674 ring, r);
675 }
676 return 0;
677}
678
679/**
680 * radeon_fence_ref - take a ref on a fence
681 *
682 * @fence: radeon fence object
683 *
684 * Take a reference on a fence (all asics).
685 * Returns the fence.
686 */
687struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence)
688{
689 dma_fence_get(&fence->base);
690 return fence;
691}
692
693/**
694 * radeon_fence_unref - remove a ref on a fence
695 *
696 * @fence: radeon fence object
697 *
698 * Remove a reference on a fence (all asics).
699 */
700void radeon_fence_unref(struct radeon_fence **fence)
701{
702 struct radeon_fence *tmp = *fence;
703
704 *fence = NULL;
705 if (tmp)
706 dma_fence_put(&tmp->base);
707}
708
709/**
710 * radeon_fence_count_emitted - get the count of emitted fences
711 *
712 * @rdev: radeon device pointer
713 * @ring: ring index the fence is associated with
714 *
715 * Get the number of fences emitted on the requested ring (all asics).
716 * Returns the number of emitted fences on the ring. Used by the
717 * dynpm code to ring track activity.
718 */
719unsigned int radeon_fence_count_emitted(struct radeon_device *rdev, int ring)
720{
721 uint64_t emitted;
722
723 /* We are not protected by ring lock when reading the last sequence
724 * but it's ok to report slightly wrong fence count here.
725 */
726 radeon_fence_process(rdev, ring);
727 emitted = rdev->fence_drv[ring].sync_seq[ring]
728 - atomic64_read(&rdev->fence_drv[ring].last_seq);
729 /* to avoid 32bits warp around */
730 if (emitted > 0x10000000)
731 emitted = 0x10000000;
732
733 return (unsigned int)emitted;
734}
735
736/**
737 * radeon_fence_need_sync - do we need a semaphore
738 *
739 * @fence: radeon fence object
740 * @dst_ring: which ring to check against
741 *
742 * Check if the fence needs to be synced against another ring
743 * (all asics). If so, we need to emit a semaphore.
744 * Returns true if we need to sync with another ring, false if
745 * not.
746 */
747bool radeon_fence_need_sync(struct radeon_fence *fence, int dst_ring)
748{
749 struct radeon_fence_driver *fdrv;
750
751 if (!fence)
752 return false;
753
754 if (fence->ring == dst_ring)
755 return false;
756
757 /* we are protected by the ring mutex */
758 fdrv = &fence->rdev->fence_drv[dst_ring];
759 if (fence->seq <= fdrv->sync_seq[fence->ring])
760 return false;
761
762 return true;
763}
764
765/**
766 * radeon_fence_note_sync - record the sync point
767 *
768 * @fence: radeon fence object
769 * @dst_ring: which ring to check against
770 *
771 * Note the sequence number at which point the fence will
772 * be synced with the requested ring (all asics).
773 */
774void radeon_fence_note_sync(struct radeon_fence *fence, int dst_ring)
775{
776 struct radeon_fence_driver *dst, *src;
777 unsigned int i;
778
779 if (!fence)
780 return;
781
782 if (fence->ring == dst_ring)
783 return;
784
785 /* we are protected by the ring mutex */
786 src = &fence->rdev->fence_drv[fence->ring];
787 dst = &fence->rdev->fence_drv[dst_ring];
788 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
789 if (i == dst_ring)
790 continue;
791
792 dst->sync_seq[i] = max(dst->sync_seq[i], src->sync_seq[i]);
793 }
794}
795
796/**
797 * radeon_fence_driver_start_ring - make the fence driver
798 * ready for use on the requested ring.
799 *
800 * @rdev: radeon device pointer
801 * @ring: ring index to start the fence driver on
802 *
803 * Make the fence driver ready for processing (all asics).
804 * Not all asics have all rings, so each asic will only
805 * start the fence driver on the rings it has.
806 * Returns 0 for success, errors for failure.
807 */
808int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring)
809{
810 uint64_t index;
811 int r;
812
813 radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg);
814 if (rdev->wb.use_event || !radeon_ring_supports_scratch_reg(rdev, &rdev->ring[ring])) {
815 rdev->fence_drv[ring].scratch_reg = 0;
816 if (ring != R600_RING_TYPE_UVD_INDEX) {
817 index = R600_WB_EVENT_OFFSET + ring * 4;
818 rdev->fence_drv[ring].cpu_addr = &rdev->wb.wb[index/4];
819 rdev->fence_drv[ring].gpu_addr = rdev->wb.gpu_addr +
820 index;
821
822 } else {
823 /* put fence directly behind firmware */
824 index = ALIGN(rdev->uvd_fw->size, 8);
825 rdev->fence_drv[ring].cpu_addr = rdev->uvd.cpu_addr + index;
826 rdev->fence_drv[ring].gpu_addr = rdev->uvd.gpu_addr + index;
827 }
828
829 } else {
830 r = radeon_scratch_get(rdev, &rdev->fence_drv[ring].scratch_reg);
831 if (r) {
832 dev_err(rdev->dev, "fence failed to get scratch register\n");
833 return r;
834 }
835 index = RADEON_WB_SCRATCH_OFFSET +
836 rdev->fence_drv[ring].scratch_reg -
837 rdev->scratch.reg_base;
838 rdev->fence_drv[ring].cpu_addr = &rdev->wb.wb[index/4];
839 rdev->fence_drv[ring].gpu_addr = rdev->wb.gpu_addr + index;
840 }
841 radeon_fence_write(rdev, atomic64_read(&rdev->fence_drv[ring].last_seq), ring);
842 rdev->fence_drv[ring].initialized = true;
843 dev_info(rdev->dev, "fence driver on ring %d use gpu addr 0x%016llx\n",
844 ring, rdev->fence_drv[ring].gpu_addr);
845 return 0;
846}
847
848/**
849 * radeon_fence_driver_init_ring - init the fence driver
850 * for the requested ring.
851 *
852 * @rdev: radeon device pointer
853 * @ring: ring index to start the fence driver on
854 *
855 * Init the fence driver for the requested ring (all asics).
856 * Helper function for radeon_fence_driver_init().
857 */
858static void radeon_fence_driver_init_ring(struct radeon_device *rdev, int ring)
859{
860 int i;
861
862 rdev->fence_drv[ring].scratch_reg = -1;
863 rdev->fence_drv[ring].cpu_addr = NULL;
864 rdev->fence_drv[ring].gpu_addr = 0;
865 for (i = 0; i < RADEON_NUM_RINGS; ++i)
866 rdev->fence_drv[ring].sync_seq[i] = 0;
867 atomic64_set(&rdev->fence_drv[ring].last_seq, 0);
868 rdev->fence_drv[ring].initialized = false;
869 INIT_DELAYED_WORK(&rdev->fence_drv[ring].lockup_work,
870 radeon_fence_check_lockup);
871 rdev->fence_drv[ring].rdev = rdev;
872}
873
874/**
875 * radeon_fence_driver_init - init the fence driver
876 * for all possible rings.
877 *
878 * @rdev: radeon device pointer
879 *
880 * Init the fence driver for all possible rings (all asics).
881 * Not all asics have all rings, so each asic will only
882 * start the fence driver on the rings it has using
883 * radeon_fence_driver_start_ring().
884 */
885void radeon_fence_driver_init(struct radeon_device *rdev)
886{
887 int ring;
888
889 init_waitqueue_head(&rdev->fence_queue);
890 for (ring = 0; ring < RADEON_NUM_RINGS; ring++)
891 radeon_fence_driver_init_ring(rdev, ring);
892
893 radeon_debugfs_fence_init(rdev);
894}
895
896/**
897 * radeon_fence_driver_fini - tear down the fence driver
898 * for all possible rings.
899 *
900 * @rdev: radeon device pointer
901 *
902 * Tear down the fence driver for all possible rings (all asics).
903 */
904void radeon_fence_driver_fini(struct radeon_device *rdev)
905{
906 int ring, r;
907
908 mutex_lock(&rdev->ring_lock);
909 for (ring = 0; ring < RADEON_NUM_RINGS; ring++) {
910 if (!rdev->fence_drv[ring].initialized)
911 continue;
912 r = radeon_fence_wait_empty(rdev, ring);
913 if (r) {
914 /* no need to trigger GPU reset as we are unloading */
915 radeon_fence_driver_force_completion(rdev, ring);
916 }
917 cancel_delayed_work_sync(&rdev->fence_drv[ring].lockup_work);
918 wake_up_all(&rdev->fence_queue);
919 radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg);
920 rdev->fence_drv[ring].initialized = false;
921 }
922 mutex_unlock(&rdev->ring_lock);
923}
924
925/**
926 * radeon_fence_driver_force_completion - force all fence waiter to complete
927 *
928 * @rdev: radeon device pointer
929 * @ring: the ring to complete
930 *
931 * In case of GPU reset failure make sure no process keep waiting on fence
932 * that will never complete.
933 */
934void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring)
935{
936 if (rdev->fence_drv[ring].initialized) {
937 radeon_fence_write(rdev, rdev->fence_drv[ring].sync_seq[ring], ring);
938 cancel_delayed_work_sync(&rdev->fence_drv[ring].lockup_work);
939 }
940}
941
942
943/*
944 * Fence debugfs
945 */
946#if defined(CONFIG_DEBUG_FS)
947static int radeon_debugfs_fence_info_show(struct seq_file *m, void *data)
948{
949 struct radeon_device *rdev = m->private;
950 int i, j;
951
952 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
953 if (!rdev->fence_drv[i].initialized)
954 continue;
955
956 radeon_fence_process(rdev, i);
957
958 seq_printf(m, "--- ring %d ---\n", i);
959 seq_printf(m, "Last signaled fence 0x%016llx\n",
960 (unsigned long long)atomic64_read(&rdev->fence_drv[i].last_seq));
961 seq_printf(m, "Last emitted 0x%016llx\n",
962 rdev->fence_drv[i].sync_seq[i]);
963
964 for (j = 0; j < RADEON_NUM_RINGS; ++j) {
965 if (i != j && rdev->fence_drv[j].initialized)
966 seq_printf(m, "Last sync to ring %d 0x%016llx\n",
967 j, rdev->fence_drv[i].sync_seq[j]);
968 }
969 }
970 return 0;
971}
972
973/*
974 * radeon_debugfs_gpu_reset - manually trigger a gpu reset
975 *
976 * Manually trigger a gpu reset at the next fence wait.
977 */
978static int radeon_debugfs_gpu_reset(void *data, u64 *val)
979{
980 struct radeon_device *rdev = (struct radeon_device *)data;
981
982 down_read(&rdev->exclusive_lock);
983 *val = rdev->needs_reset;
984 rdev->needs_reset = true;
985 wake_up_all(&rdev->fence_queue);
986 up_read(&rdev->exclusive_lock);
987
988 return 0;
989}
990DEFINE_SHOW_ATTRIBUTE(radeon_debugfs_fence_info);
991DEFINE_DEBUGFS_ATTRIBUTE(radeon_debugfs_gpu_reset_fops,
992 radeon_debugfs_gpu_reset, NULL, "%lld\n");
993#endif
994
995void radeon_debugfs_fence_init(struct radeon_device *rdev)
996{
997#if defined(CONFIG_DEBUG_FS)
998 struct dentry *root = rdev_to_drm(rdev)->primary->debugfs_root;
999
1000 debugfs_create_file("radeon_gpu_reset", 0444, root, rdev,
1001 &radeon_debugfs_gpu_reset_fops);
1002 debugfs_create_file("radeon_fence_info", 0444, root, rdev,
1003 &radeon_debugfs_fence_info_fops);
1004
1005
1006#endif
1007}
1008
1009static const char *radeon_fence_get_driver_name(struct dma_fence *fence)
1010{
1011 return "radeon";
1012}
1013
1014static const char *radeon_fence_get_timeline_name(struct dma_fence *f)
1015{
1016 struct radeon_fence *fence = to_radeon_fence(f);
1017
1018 switch (fence->ring) {
1019 case RADEON_RING_TYPE_GFX_INDEX: return "radeon.gfx";
1020 case CAYMAN_RING_TYPE_CP1_INDEX: return "radeon.cp1";
1021 case CAYMAN_RING_TYPE_CP2_INDEX: return "radeon.cp2";
1022 case R600_RING_TYPE_DMA_INDEX: return "radeon.dma";
1023 case CAYMAN_RING_TYPE_DMA1_INDEX: return "radeon.dma1";
1024 case R600_RING_TYPE_UVD_INDEX: return "radeon.uvd";
1025 case TN_RING_TYPE_VCE1_INDEX: return "radeon.vce1";
1026 case TN_RING_TYPE_VCE2_INDEX: return "radeon.vce2";
1027 default:
1028 WARN_ON_ONCE(1);
1029 return "radeon.unk";
1030 }
1031}
1032
1033static inline bool radeon_test_signaled(struct radeon_fence *fence)
1034{
1035 return test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->base.flags);
1036}
1037
1038struct radeon_wait_cb {
1039 struct dma_fence_cb base;
1040 struct task_struct *task;
1041};
1042
1043static void
1044radeon_fence_wait_cb(struct dma_fence *fence, struct dma_fence_cb *cb)
1045{
1046 struct radeon_wait_cb *wait =
1047 container_of(cb, struct radeon_wait_cb, base);
1048
1049 wake_up_process(wait->task);
1050}
1051
1052static signed long radeon_fence_default_wait(struct dma_fence *f, bool intr,
1053 signed long t)
1054{
1055 struct radeon_fence *fence = to_radeon_fence(f);
1056 struct radeon_device *rdev = fence->rdev;
1057 struct radeon_wait_cb cb;
1058
1059 cb.task = current;
1060
1061 if (dma_fence_add_callback(f, &cb.base, radeon_fence_wait_cb))
1062 return t;
1063
1064 while (t > 0) {
1065 if (intr)
1066 set_current_state(TASK_INTERRUPTIBLE);
1067 else
1068 set_current_state(TASK_UNINTERRUPTIBLE);
1069
1070 /*
1071 * radeon_test_signaled must be called after
1072 * set_current_state to prevent a race with wake_up_process
1073 */
1074 if (radeon_test_signaled(fence))
1075 break;
1076
1077 if (rdev->needs_reset) {
1078 t = -EDEADLK;
1079 break;
1080 }
1081
1082 t = schedule_timeout(t);
1083
1084 if (t > 0 && intr && signal_pending(current))
1085 t = -ERESTARTSYS;
1086 }
1087
1088 __set_current_state(TASK_RUNNING);
1089 dma_fence_remove_callback(f, &cb.base);
1090
1091 return t;
1092}
1093
1094const struct dma_fence_ops radeon_fence_ops = {
1095 .get_driver_name = radeon_fence_get_driver_name,
1096 .get_timeline_name = radeon_fence_get_timeline_name,
1097 .enable_signaling = radeon_fence_enable_signaling,
1098 .signaled = radeon_fence_is_signaled,
1099 .wait = radeon_fence_default_wait,
1100 .release = NULL,
1101};
1/*
2 * Copyright 2009 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26/*
27 * Authors:
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Dave Airlie
30 */
31
32#include <linux/atomic.h>
33#include <linux/firmware.h>
34#include <linux/kref.h>
35#include <linux/sched/signal.h>
36#include <linux/seq_file.h>
37#include <linux/slab.h>
38#include <linux/wait.h>
39
40#include <drm/drm_debugfs.h>
41#include <drm/drm_device.h>
42#include <drm/drm_file.h>
43
44#include "radeon.h"
45#include "radeon_reg.h"
46#include "radeon_trace.h"
47
48/*
49 * Fences
50 * Fences mark an event in the GPUs pipeline and are used
51 * for GPU/CPU synchronization. When the fence is written,
52 * it is expected that all buffers associated with that fence
53 * are no longer in use by the associated ring on the GPU and
54 * that the the relevant GPU caches have been flushed. Whether
55 * we use a scratch register or memory location depends on the asic
56 * and whether writeback is enabled.
57 */
58
59/**
60 * radeon_fence_write - write a fence value
61 *
62 * @rdev: radeon_device pointer
63 * @seq: sequence number to write
64 * @ring: ring index the fence is associated with
65 *
66 * Writes a fence value to memory or a scratch register (all asics).
67 */
68static void radeon_fence_write(struct radeon_device *rdev, u32 seq, int ring)
69{
70 struct radeon_fence_driver *drv = &rdev->fence_drv[ring];
71 if (likely(rdev->wb.enabled || !drv->scratch_reg)) {
72 if (drv->cpu_addr) {
73 *drv->cpu_addr = cpu_to_le32(seq);
74 }
75 } else {
76 WREG32(drv->scratch_reg, seq);
77 }
78}
79
80/**
81 * radeon_fence_read - read a fence value
82 *
83 * @rdev: radeon_device pointer
84 * @ring: ring index the fence is associated with
85 *
86 * Reads a fence value from memory or a scratch register (all asics).
87 * Returns the value of the fence read from memory or register.
88 */
89static u32 radeon_fence_read(struct radeon_device *rdev, int ring)
90{
91 struct radeon_fence_driver *drv = &rdev->fence_drv[ring];
92 u32 seq = 0;
93
94 if (likely(rdev->wb.enabled || !drv->scratch_reg)) {
95 if (drv->cpu_addr) {
96 seq = le32_to_cpu(*drv->cpu_addr);
97 } else {
98 seq = lower_32_bits(atomic64_read(&drv->last_seq));
99 }
100 } else {
101 seq = RREG32(drv->scratch_reg);
102 }
103 return seq;
104}
105
106/**
107 * radeon_fence_schedule_check - schedule lockup check
108 *
109 * @rdev: radeon_device pointer
110 * @ring: ring index we should work with
111 *
112 * Queues a delayed work item to check for lockups.
113 */
114static void radeon_fence_schedule_check(struct radeon_device *rdev, int ring)
115{
116 /*
117 * Do not reset the timer here with mod_delayed_work,
118 * this can livelock in an interaction with TTM delayed destroy.
119 */
120 queue_delayed_work(system_power_efficient_wq,
121 &rdev->fence_drv[ring].lockup_work,
122 RADEON_FENCE_JIFFIES_TIMEOUT);
123}
124
125/**
126 * radeon_fence_emit - emit a fence on the requested ring
127 *
128 * @rdev: radeon_device pointer
129 * @fence: radeon fence object
130 * @ring: ring index the fence is associated with
131 *
132 * Emits a fence command on the requested ring (all asics).
133 * Returns 0 on success, -ENOMEM on failure.
134 */
135int radeon_fence_emit(struct radeon_device *rdev,
136 struct radeon_fence **fence,
137 int ring)
138{
139 u64 seq;
140
141 /* we are protected by the ring emission mutex */
142 *fence = kmalloc(sizeof(struct radeon_fence), GFP_KERNEL);
143 if ((*fence) == NULL) {
144 return -ENOMEM;
145 }
146 (*fence)->rdev = rdev;
147 (*fence)->seq = seq = ++rdev->fence_drv[ring].sync_seq[ring];
148 (*fence)->ring = ring;
149 (*fence)->is_vm_update = false;
150 dma_fence_init(&(*fence)->base, &radeon_fence_ops,
151 &rdev->fence_queue.lock,
152 rdev->fence_context + ring,
153 seq);
154 radeon_fence_ring_emit(rdev, ring, *fence);
155 trace_radeon_fence_emit(rdev->ddev, ring, (*fence)->seq);
156 radeon_fence_schedule_check(rdev, ring);
157 return 0;
158}
159
160/**
161 * radeon_fence_check_signaled - callback from fence_queue
162 *
163 * this function is called with fence_queue lock held, which is also used
164 * for the fence locking itself, so unlocked variants are used for
165 * fence_signal, and remove_wait_queue.
166 */
167static int radeon_fence_check_signaled(wait_queue_entry_t *wait, unsigned mode, int flags, void *key)
168{
169 struct radeon_fence *fence;
170 u64 seq;
171
172 fence = container_of(wait, struct radeon_fence, fence_wake);
173
174 /*
175 * We cannot use radeon_fence_process here because we're already
176 * in the waitqueue, in a call from wake_up_all.
177 */
178 seq = atomic64_read(&fence->rdev->fence_drv[fence->ring].last_seq);
179 if (seq >= fence->seq) {
180 int ret = dma_fence_signal_locked(&fence->base);
181
182 if (!ret)
183 DMA_FENCE_TRACE(&fence->base, "signaled from irq context\n");
184 else
185 DMA_FENCE_TRACE(&fence->base, "was already signaled\n");
186
187 radeon_irq_kms_sw_irq_put(fence->rdev, fence->ring);
188 __remove_wait_queue(&fence->rdev->fence_queue, &fence->fence_wake);
189 dma_fence_put(&fence->base);
190 } else
191 DMA_FENCE_TRACE(&fence->base, "pending\n");
192 return 0;
193}
194
195/**
196 * radeon_fence_activity - check for fence activity
197 *
198 * @rdev: radeon_device pointer
199 * @ring: ring index the fence is associated with
200 *
201 * Checks the current fence value and calculates the last
202 * signalled fence value. Returns true if activity occured
203 * on the ring, and the fence_queue should be waken up.
204 */
205static bool radeon_fence_activity(struct radeon_device *rdev, int ring)
206{
207 uint64_t seq, last_seq, last_emitted;
208 unsigned count_loop = 0;
209 bool wake = false;
210
211 /* Note there is a scenario here for an infinite loop but it's
212 * very unlikely to happen. For it to happen, the current polling
213 * process need to be interrupted by another process and another
214 * process needs to update the last_seq btw the atomic read and
215 * xchg of the current process.
216 *
217 * More over for this to go in infinite loop there need to be
218 * continuously new fence signaled ie radeon_fence_read needs
219 * to return a different value each time for both the currently
220 * polling process and the other process that xchg the last_seq
221 * btw atomic read and xchg of the current process. And the
222 * value the other process set as last seq must be higher than
223 * the seq value we just read. Which means that current process
224 * need to be interrupted after radeon_fence_read and before
225 * atomic xchg.
226 *
227 * To be even more safe we count the number of time we loop and
228 * we bail after 10 loop just accepting the fact that we might
229 * have temporarly set the last_seq not to the true real last
230 * seq but to an older one.
231 */
232 last_seq = atomic64_read(&rdev->fence_drv[ring].last_seq);
233 do {
234 last_emitted = rdev->fence_drv[ring].sync_seq[ring];
235 seq = radeon_fence_read(rdev, ring);
236 seq |= last_seq & 0xffffffff00000000LL;
237 if (seq < last_seq) {
238 seq &= 0xffffffff;
239 seq |= last_emitted & 0xffffffff00000000LL;
240 }
241
242 if (seq <= last_seq || seq > last_emitted) {
243 break;
244 }
245 /* If we loop over we don't want to return without
246 * checking if a fence is signaled as it means that the
247 * seq we just read is different from the previous on.
248 */
249 wake = true;
250 last_seq = seq;
251 if ((count_loop++) > 10) {
252 /* We looped over too many time leave with the
253 * fact that we might have set an older fence
254 * seq then the current real last seq as signaled
255 * by the hw.
256 */
257 break;
258 }
259 } while (atomic64_xchg(&rdev->fence_drv[ring].last_seq, seq) > seq);
260
261 if (seq < last_emitted)
262 radeon_fence_schedule_check(rdev, ring);
263
264 return wake;
265}
266
267/**
268 * radeon_fence_check_lockup - check for hardware lockup
269 *
270 * @work: delayed work item
271 *
272 * Checks for fence activity and if there is none probe
273 * the hardware if a lockup occured.
274 */
275static void radeon_fence_check_lockup(struct work_struct *work)
276{
277 struct radeon_fence_driver *fence_drv;
278 struct radeon_device *rdev;
279 int ring;
280
281 fence_drv = container_of(work, struct radeon_fence_driver,
282 lockup_work.work);
283 rdev = fence_drv->rdev;
284 ring = fence_drv - &rdev->fence_drv[0];
285
286 if (!down_read_trylock(&rdev->exclusive_lock)) {
287 /* just reschedule the check if a reset is going on */
288 radeon_fence_schedule_check(rdev, ring);
289 return;
290 }
291
292 if (fence_drv->delayed_irq && rdev->ddev->irq_enabled) {
293 unsigned long irqflags;
294
295 fence_drv->delayed_irq = false;
296 spin_lock_irqsave(&rdev->irq.lock, irqflags);
297 radeon_irq_set(rdev);
298 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
299 }
300
301 if (radeon_fence_activity(rdev, ring))
302 wake_up_all(&rdev->fence_queue);
303
304 else if (radeon_ring_is_lockup(rdev, ring, &rdev->ring[ring])) {
305
306 /* good news we believe it's a lockup */
307 dev_warn(rdev->dev, "GPU lockup (current fence id "
308 "0x%016llx last fence id 0x%016llx on ring %d)\n",
309 (uint64_t)atomic64_read(&fence_drv->last_seq),
310 fence_drv->sync_seq[ring], ring);
311
312 /* remember that we need an reset */
313 rdev->needs_reset = true;
314 wake_up_all(&rdev->fence_queue);
315 }
316 up_read(&rdev->exclusive_lock);
317}
318
319/**
320 * radeon_fence_process - process a fence
321 *
322 * @rdev: radeon_device pointer
323 * @ring: ring index the fence is associated with
324 *
325 * Checks the current fence value and wakes the fence queue
326 * if the sequence number has increased (all asics).
327 */
328void radeon_fence_process(struct radeon_device *rdev, int ring)
329{
330 if (radeon_fence_activity(rdev, ring))
331 wake_up_all(&rdev->fence_queue);
332}
333
334/**
335 * radeon_fence_seq_signaled - check if a fence sequence number has signaled
336 *
337 * @rdev: radeon device pointer
338 * @seq: sequence number
339 * @ring: ring index the fence is associated with
340 *
341 * Check if the last signaled fence sequnce number is >= the requested
342 * sequence number (all asics).
343 * Returns true if the fence has signaled (current fence value
344 * is >= requested value) or false if it has not (current fence
345 * value is < the requested value. Helper function for
346 * radeon_fence_signaled().
347 */
348static bool radeon_fence_seq_signaled(struct radeon_device *rdev,
349 u64 seq, unsigned ring)
350{
351 if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq) {
352 return true;
353 }
354 /* poll new last sequence at least once */
355 radeon_fence_process(rdev, ring);
356 if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq) {
357 return true;
358 }
359 return false;
360}
361
362static bool radeon_fence_is_signaled(struct dma_fence *f)
363{
364 struct radeon_fence *fence = to_radeon_fence(f);
365 struct radeon_device *rdev = fence->rdev;
366 unsigned ring = fence->ring;
367 u64 seq = fence->seq;
368
369 if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq) {
370 return true;
371 }
372
373 if (down_read_trylock(&rdev->exclusive_lock)) {
374 radeon_fence_process(rdev, ring);
375 up_read(&rdev->exclusive_lock);
376
377 if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq) {
378 return true;
379 }
380 }
381 return false;
382}
383
384/**
385 * radeon_fence_enable_signaling - enable signalling on fence
386 * @fence: fence
387 *
388 * This function is called with fence_queue lock held, and adds a callback
389 * to fence_queue that checks if this fence is signaled, and if so it
390 * signals the fence and removes itself.
391 */
392static bool radeon_fence_enable_signaling(struct dma_fence *f)
393{
394 struct radeon_fence *fence = to_radeon_fence(f);
395 struct radeon_device *rdev = fence->rdev;
396
397 if (atomic64_read(&rdev->fence_drv[fence->ring].last_seq) >= fence->seq)
398 return false;
399
400 if (down_read_trylock(&rdev->exclusive_lock)) {
401 radeon_irq_kms_sw_irq_get(rdev, fence->ring);
402
403 if (radeon_fence_activity(rdev, fence->ring))
404 wake_up_all_locked(&rdev->fence_queue);
405
406 /* did fence get signaled after we enabled the sw irq? */
407 if (atomic64_read(&rdev->fence_drv[fence->ring].last_seq) >= fence->seq) {
408 radeon_irq_kms_sw_irq_put(rdev, fence->ring);
409 up_read(&rdev->exclusive_lock);
410 return false;
411 }
412
413 up_read(&rdev->exclusive_lock);
414 } else {
415 /* we're probably in a lockup, lets not fiddle too much */
416 if (radeon_irq_kms_sw_irq_get_delayed(rdev, fence->ring))
417 rdev->fence_drv[fence->ring].delayed_irq = true;
418 radeon_fence_schedule_check(rdev, fence->ring);
419 }
420
421 fence->fence_wake.flags = 0;
422 fence->fence_wake.private = NULL;
423 fence->fence_wake.func = radeon_fence_check_signaled;
424 __add_wait_queue(&rdev->fence_queue, &fence->fence_wake);
425 dma_fence_get(f);
426
427 DMA_FENCE_TRACE(&fence->base, "armed on ring %i!\n", fence->ring);
428 return true;
429}
430
431/**
432 * radeon_fence_signaled - check if a fence has signaled
433 *
434 * @fence: radeon fence object
435 *
436 * Check if the requested fence has signaled (all asics).
437 * Returns true if the fence has signaled or false if it has not.
438 */
439bool radeon_fence_signaled(struct radeon_fence *fence)
440{
441 if (!fence)
442 return true;
443
444 if (radeon_fence_seq_signaled(fence->rdev, fence->seq, fence->ring)) {
445 int ret;
446
447 ret = dma_fence_signal(&fence->base);
448 if (!ret)
449 DMA_FENCE_TRACE(&fence->base, "signaled from radeon_fence_signaled\n");
450 return true;
451 }
452 return false;
453}
454
455/**
456 * radeon_fence_any_seq_signaled - check if any sequence number is signaled
457 *
458 * @rdev: radeon device pointer
459 * @seq: sequence numbers
460 *
461 * Check if the last signaled fence sequnce number is >= the requested
462 * sequence number (all asics).
463 * Returns true if any has signaled (current value is >= requested value)
464 * or false if it has not. Helper function for radeon_fence_wait_seq.
465 */
466static bool radeon_fence_any_seq_signaled(struct radeon_device *rdev, u64 *seq)
467{
468 unsigned i;
469
470 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
471 if (seq[i] && radeon_fence_seq_signaled(rdev, seq[i], i))
472 return true;
473 }
474 return false;
475}
476
477/**
478 * radeon_fence_wait_seq_timeout - wait for a specific sequence numbers
479 *
480 * @rdev: radeon device pointer
481 * @target_seq: sequence number(s) we want to wait for
482 * @intr: use interruptable sleep
483 * @timeout: maximum time to wait, or MAX_SCHEDULE_TIMEOUT for infinite wait
484 *
485 * Wait for the requested sequence number(s) to be written by any ring
486 * (all asics). Sequnce number array is indexed by ring id.
487 * @intr selects whether to use interruptable (true) or non-interruptable
488 * (false) sleep when waiting for the sequence number. Helper function
489 * for radeon_fence_wait_*().
490 * Returns remaining time if the sequence number has passed, 0 when
491 * the wait timeout, or an error for all other cases.
492 * -EDEADLK is returned when a GPU lockup has been detected.
493 */
494static long radeon_fence_wait_seq_timeout(struct radeon_device *rdev,
495 u64 *target_seq, bool intr,
496 long timeout)
497{
498 long r;
499 int i;
500
501 if (radeon_fence_any_seq_signaled(rdev, target_seq))
502 return timeout;
503
504 /* enable IRQs and tracing */
505 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
506 if (!target_seq[i])
507 continue;
508
509 trace_radeon_fence_wait_begin(rdev->ddev, i, target_seq[i]);
510 radeon_irq_kms_sw_irq_get(rdev, i);
511 }
512
513 if (intr) {
514 r = wait_event_interruptible_timeout(rdev->fence_queue, (
515 radeon_fence_any_seq_signaled(rdev, target_seq)
516 || rdev->needs_reset), timeout);
517 } else {
518 r = wait_event_timeout(rdev->fence_queue, (
519 radeon_fence_any_seq_signaled(rdev, target_seq)
520 || rdev->needs_reset), timeout);
521 }
522
523 if (rdev->needs_reset)
524 r = -EDEADLK;
525
526 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
527 if (!target_seq[i])
528 continue;
529
530 radeon_irq_kms_sw_irq_put(rdev, i);
531 trace_radeon_fence_wait_end(rdev->ddev, i, target_seq[i]);
532 }
533
534 return r;
535}
536
537/**
538 * radeon_fence_wait_timeout - wait for a fence to signal with timeout
539 *
540 * @fence: radeon fence object
541 * @intr: use interruptible sleep
542 *
543 * Wait for the requested fence to signal (all asics).
544 * @intr selects whether to use interruptable (true) or non-interruptable
545 * (false) sleep when waiting for the fence.
546 * @timeout: maximum time to wait, or MAX_SCHEDULE_TIMEOUT for infinite wait
547 * Returns remaining time if the sequence number has passed, 0 when
548 * the wait timeout, or an error for all other cases.
549 */
550long radeon_fence_wait_timeout(struct radeon_fence *fence, bool intr, long timeout)
551{
552 uint64_t seq[RADEON_NUM_RINGS] = {};
553 long r;
554 int r_sig;
555
556 /*
557 * This function should not be called on !radeon fences.
558 * If this is the case, it would mean this function can
559 * also be called on radeon fences belonging to another card.
560 * exclusive_lock is not held in that case.
561 */
562 if (WARN_ON_ONCE(!to_radeon_fence(&fence->base)))
563 return dma_fence_wait(&fence->base, intr);
564
565 seq[fence->ring] = fence->seq;
566 r = radeon_fence_wait_seq_timeout(fence->rdev, seq, intr, timeout);
567 if (r <= 0) {
568 return r;
569 }
570
571 r_sig = dma_fence_signal(&fence->base);
572 if (!r_sig)
573 DMA_FENCE_TRACE(&fence->base, "signaled from fence_wait\n");
574 return r;
575}
576
577/**
578 * radeon_fence_wait - wait for a fence to signal
579 *
580 * @fence: radeon fence object
581 * @intr: use interruptible sleep
582 *
583 * Wait for the requested fence to signal (all asics).
584 * @intr selects whether to use interruptable (true) or non-interruptable
585 * (false) sleep when waiting for the fence.
586 * Returns 0 if the fence has passed, error for all other cases.
587 */
588int radeon_fence_wait(struct radeon_fence *fence, bool intr)
589{
590 long r = radeon_fence_wait_timeout(fence, intr, MAX_SCHEDULE_TIMEOUT);
591 if (r > 0) {
592 return 0;
593 } else {
594 return r;
595 }
596}
597
598/**
599 * radeon_fence_wait_any - wait for a fence to signal on any ring
600 *
601 * @rdev: radeon device pointer
602 * @fences: radeon fence object(s)
603 * @intr: use interruptable sleep
604 *
605 * Wait for any requested fence to signal (all asics). Fence
606 * array is indexed by ring id. @intr selects whether to use
607 * interruptable (true) or non-interruptable (false) sleep when
608 * waiting for the fences. Used by the suballocator.
609 * Returns 0 if any fence has passed, error for all other cases.
610 */
611int radeon_fence_wait_any(struct radeon_device *rdev,
612 struct radeon_fence **fences,
613 bool intr)
614{
615 uint64_t seq[RADEON_NUM_RINGS];
616 unsigned i, num_rings = 0;
617 long r;
618
619 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
620 seq[i] = 0;
621
622 if (!fences[i]) {
623 continue;
624 }
625
626 seq[i] = fences[i]->seq;
627 ++num_rings;
628 }
629
630 /* nothing to wait for ? */
631 if (num_rings == 0)
632 return -ENOENT;
633
634 r = radeon_fence_wait_seq_timeout(rdev, seq, intr, MAX_SCHEDULE_TIMEOUT);
635 if (r < 0) {
636 return r;
637 }
638 return 0;
639}
640
641/**
642 * radeon_fence_wait_next - wait for the next fence to signal
643 *
644 * @rdev: radeon device pointer
645 * @ring: ring index the fence is associated with
646 *
647 * Wait for the next fence on the requested ring to signal (all asics).
648 * Returns 0 if the next fence has passed, error for all other cases.
649 * Caller must hold ring lock.
650 */
651int radeon_fence_wait_next(struct radeon_device *rdev, int ring)
652{
653 uint64_t seq[RADEON_NUM_RINGS] = {};
654 long r;
655
656 seq[ring] = atomic64_read(&rdev->fence_drv[ring].last_seq) + 1ULL;
657 if (seq[ring] >= rdev->fence_drv[ring].sync_seq[ring]) {
658 /* nothing to wait for, last_seq is
659 already the last emited fence */
660 return -ENOENT;
661 }
662 r = radeon_fence_wait_seq_timeout(rdev, seq, false, MAX_SCHEDULE_TIMEOUT);
663 if (r < 0)
664 return r;
665 return 0;
666}
667
668/**
669 * radeon_fence_wait_empty - wait for all fences to signal
670 *
671 * @rdev: radeon device pointer
672 * @ring: ring index the fence is associated with
673 *
674 * Wait for all fences on the requested ring to signal (all asics).
675 * Returns 0 if the fences have passed, error for all other cases.
676 * Caller must hold ring lock.
677 */
678int radeon_fence_wait_empty(struct radeon_device *rdev, int ring)
679{
680 uint64_t seq[RADEON_NUM_RINGS] = {};
681 long r;
682
683 seq[ring] = rdev->fence_drv[ring].sync_seq[ring];
684 if (!seq[ring])
685 return 0;
686
687 r = radeon_fence_wait_seq_timeout(rdev, seq, false, MAX_SCHEDULE_TIMEOUT);
688 if (r < 0) {
689 if (r == -EDEADLK)
690 return -EDEADLK;
691
692 dev_err(rdev->dev, "error waiting for ring[%d] to become idle (%ld)\n",
693 ring, r);
694 }
695 return 0;
696}
697
698/**
699 * radeon_fence_ref - take a ref on a fence
700 *
701 * @fence: radeon fence object
702 *
703 * Take a reference on a fence (all asics).
704 * Returns the fence.
705 */
706struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence)
707{
708 dma_fence_get(&fence->base);
709 return fence;
710}
711
712/**
713 * radeon_fence_unref - remove a ref on a fence
714 *
715 * @fence: radeon fence object
716 *
717 * Remove a reference on a fence (all asics).
718 */
719void radeon_fence_unref(struct radeon_fence **fence)
720{
721 struct radeon_fence *tmp = *fence;
722
723 *fence = NULL;
724 if (tmp) {
725 dma_fence_put(&tmp->base);
726 }
727}
728
729/**
730 * radeon_fence_count_emitted - get the count of emitted fences
731 *
732 * @rdev: radeon device pointer
733 * @ring: ring index the fence is associated with
734 *
735 * Get the number of fences emitted on the requested ring (all asics).
736 * Returns the number of emitted fences on the ring. Used by the
737 * dynpm code to ring track activity.
738 */
739unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring)
740{
741 uint64_t emitted;
742
743 /* We are not protected by ring lock when reading the last sequence
744 * but it's ok to report slightly wrong fence count here.
745 */
746 radeon_fence_process(rdev, ring);
747 emitted = rdev->fence_drv[ring].sync_seq[ring]
748 - atomic64_read(&rdev->fence_drv[ring].last_seq);
749 /* to avoid 32bits warp around */
750 if (emitted > 0x10000000) {
751 emitted = 0x10000000;
752 }
753 return (unsigned)emitted;
754}
755
756/**
757 * radeon_fence_need_sync - do we need a semaphore
758 *
759 * @fence: radeon fence object
760 * @dst_ring: which ring to check against
761 *
762 * Check if the fence needs to be synced against another ring
763 * (all asics). If so, we need to emit a semaphore.
764 * Returns true if we need to sync with another ring, false if
765 * not.
766 */
767bool radeon_fence_need_sync(struct radeon_fence *fence, int dst_ring)
768{
769 struct radeon_fence_driver *fdrv;
770
771 if (!fence) {
772 return false;
773 }
774
775 if (fence->ring == dst_ring) {
776 return false;
777 }
778
779 /* we are protected by the ring mutex */
780 fdrv = &fence->rdev->fence_drv[dst_ring];
781 if (fence->seq <= fdrv->sync_seq[fence->ring]) {
782 return false;
783 }
784
785 return true;
786}
787
788/**
789 * radeon_fence_note_sync - record the sync point
790 *
791 * @fence: radeon fence object
792 * @dst_ring: which ring to check against
793 *
794 * Note the sequence number at which point the fence will
795 * be synced with the requested ring (all asics).
796 */
797void radeon_fence_note_sync(struct radeon_fence *fence, int dst_ring)
798{
799 struct radeon_fence_driver *dst, *src;
800 unsigned i;
801
802 if (!fence) {
803 return;
804 }
805
806 if (fence->ring == dst_ring) {
807 return;
808 }
809
810 /* we are protected by the ring mutex */
811 src = &fence->rdev->fence_drv[fence->ring];
812 dst = &fence->rdev->fence_drv[dst_ring];
813 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
814 if (i == dst_ring) {
815 continue;
816 }
817 dst->sync_seq[i] = max(dst->sync_seq[i], src->sync_seq[i]);
818 }
819}
820
821/**
822 * radeon_fence_driver_start_ring - make the fence driver
823 * ready for use on the requested ring.
824 *
825 * @rdev: radeon device pointer
826 * @ring: ring index to start the fence driver on
827 *
828 * Make the fence driver ready for processing (all asics).
829 * Not all asics have all rings, so each asic will only
830 * start the fence driver on the rings it has.
831 * Returns 0 for success, errors for failure.
832 */
833int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring)
834{
835 uint64_t index;
836 int r;
837
838 radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg);
839 if (rdev->wb.use_event || !radeon_ring_supports_scratch_reg(rdev, &rdev->ring[ring])) {
840 rdev->fence_drv[ring].scratch_reg = 0;
841 if (ring != R600_RING_TYPE_UVD_INDEX) {
842 index = R600_WB_EVENT_OFFSET + ring * 4;
843 rdev->fence_drv[ring].cpu_addr = &rdev->wb.wb[index/4];
844 rdev->fence_drv[ring].gpu_addr = rdev->wb.gpu_addr +
845 index;
846
847 } else {
848 /* put fence directly behind firmware */
849 index = ALIGN(rdev->uvd_fw->size, 8);
850 rdev->fence_drv[ring].cpu_addr = rdev->uvd.cpu_addr + index;
851 rdev->fence_drv[ring].gpu_addr = rdev->uvd.gpu_addr + index;
852 }
853
854 } else {
855 r = radeon_scratch_get(rdev, &rdev->fence_drv[ring].scratch_reg);
856 if (r) {
857 dev_err(rdev->dev, "fence failed to get scratch register\n");
858 return r;
859 }
860 index = RADEON_WB_SCRATCH_OFFSET +
861 rdev->fence_drv[ring].scratch_reg -
862 rdev->scratch.reg_base;
863 rdev->fence_drv[ring].cpu_addr = &rdev->wb.wb[index/4];
864 rdev->fence_drv[ring].gpu_addr = rdev->wb.gpu_addr + index;
865 }
866 radeon_fence_write(rdev, atomic64_read(&rdev->fence_drv[ring].last_seq), ring);
867 rdev->fence_drv[ring].initialized = true;
868 dev_info(rdev->dev, "fence driver on ring %d use gpu addr 0x%016llx and cpu addr 0x%p\n",
869 ring, rdev->fence_drv[ring].gpu_addr, rdev->fence_drv[ring].cpu_addr);
870 return 0;
871}
872
873/**
874 * radeon_fence_driver_init_ring - init the fence driver
875 * for the requested ring.
876 *
877 * @rdev: radeon device pointer
878 * @ring: ring index to start the fence driver on
879 *
880 * Init the fence driver for the requested ring (all asics).
881 * Helper function for radeon_fence_driver_init().
882 */
883static void radeon_fence_driver_init_ring(struct radeon_device *rdev, int ring)
884{
885 int i;
886
887 rdev->fence_drv[ring].scratch_reg = -1;
888 rdev->fence_drv[ring].cpu_addr = NULL;
889 rdev->fence_drv[ring].gpu_addr = 0;
890 for (i = 0; i < RADEON_NUM_RINGS; ++i)
891 rdev->fence_drv[ring].sync_seq[i] = 0;
892 atomic64_set(&rdev->fence_drv[ring].last_seq, 0);
893 rdev->fence_drv[ring].initialized = false;
894 INIT_DELAYED_WORK(&rdev->fence_drv[ring].lockup_work,
895 radeon_fence_check_lockup);
896 rdev->fence_drv[ring].rdev = rdev;
897}
898
899/**
900 * radeon_fence_driver_init - init the fence driver
901 * for all possible rings.
902 *
903 * @rdev: radeon device pointer
904 *
905 * Init the fence driver for all possible rings (all asics).
906 * Not all asics have all rings, so each asic will only
907 * start the fence driver on the rings it has using
908 * radeon_fence_driver_start_ring().
909 * Returns 0 for success.
910 */
911int radeon_fence_driver_init(struct radeon_device *rdev)
912{
913 int ring;
914
915 init_waitqueue_head(&rdev->fence_queue);
916 for (ring = 0; ring < RADEON_NUM_RINGS; ring++) {
917 radeon_fence_driver_init_ring(rdev, ring);
918 }
919 if (radeon_debugfs_fence_init(rdev)) {
920 dev_err(rdev->dev, "fence debugfs file creation failed\n");
921 }
922 return 0;
923}
924
925/**
926 * radeon_fence_driver_fini - tear down the fence driver
927 * for all possible rings.
928 *
929 * @rdev: radeon device pointer
930 *
931 * Tear down the fence driver for all possible rings (all asics).
932 */
933void radeon_fence_driver_fini(struct radeon_device *rdev)
934{
935 int ring, r;
936
937 mutex_lock(&rdev->ring_lock);
938 for (ring = 0; ring < RADEON_NUM_RINGS; ring++) {
939 if (!rdev->fence_drv[ring].initialized)
940 continue;
941 r = radeon_fence_wait_empty(rdev, ring);
942 if (r) {
943 /* no need to trigger GPU reset as we are unloading */
944 radeon_fence_driver_force_completion(rdev, ring);
945 }
946 cancel_delayed_work_sync(&rdev->fence_drv[ring].lockup_work);
947 wake_up_all(&rdev->fence_queue);
948 radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg);
949 rdev->fence_drv[ring].initialized = false;
950 }
951 mutex_unlock(&rdev->ring_lock);
952}
953
954/**
955 * radeon_fence_driver_force_completion - force all fence waiter to complete
956 *
957 * @rdev: radeon device pointer
958 * @ring: the ring to complete
959 *
960 * In case of GPU reset failure make sure no process keep waiting on fence
961 * that will never complete.
962 */
963void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring)
964{
965 if (rdev->fence_drv[ring].initialized) {
966 radeon_fence_write(rdev, rdev->fence_drv[ring].sync_seq[ring], ring);
967 cancel_delayed_work_sync(&rdev->fence_drv[ring].lockup_work);
968 }
969}
970
971
972/*
973 * Fence debugfs
974 */
975#if defined(CONFIG_DEBUG_FS)
976static int radeon_debugfs_fence_info(struct seq_file *m, void *data)
977{
978 struct drm_info_node *node = (struct drm_info_node *)m->private;
979 struct drm_device *dev = node->minor->dev;
980 struct radeon_device *rdev = dev->dev_private;
981 int i, j;
982
983 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
984 if (!rdev->fence_drv[i].initialized)
985 continue;
986
987 radeon_fence_process(rdev, i);
988
989 seq_printf(m, "--- ring %d ---\n", i);
990 seq_printf(m, "Last signaled fence 0x%016llx\n",
991 (unsigned long long)atomic64_read(&rdev->fence_drv[i].last_seq));
992 seq_printf(m, "Last emitted 0x%016llx\n",
993 rdev->fence_drv[i].sync_seq[i]);
994
995 for (j = 0; j < RADEON_NUM_RINGS; ++j) {
996 if (i != j && rdev->fence_drv[j].initialized)
997 seq_printf(m, "Last sync to ring %d 0x%016llx\n",
998 j, rdev->fence_drv[i].sync_seq[j]);
999 }
1000 }
1001 return 0;
1002}
1003
1004/**
1005 * radeon_debugfs_gpu_reset - manually trigger a gpu reset
1006 *
1007 * Manually trigger a gpu reset at the next fence wait.
1008 */
1009static int radeon_debugfs_gpu_reset(struct seq_file *m, void *data)
1010{
1011 struct drm_info_node *node = (struct drm_info_node *) m->private;
1012 struct drm_device *dev = node->minor->dev;
1013 struct radeon_device *rdev = dev->dev_private;
1014
1015 down_read(&rdev->exclusive_lock);
1016 seq_printf(m, "%d\n", rdev->needs_reset);
1017 rdev->needs_reset = true;
1018 wake_up_all(&rdev->fence_queue);
1019 up_read(&rdev->exclusive_lock);
1020
1021 return 0;
1022}
1023
1024static struct drm_info_list radeon_debugfs_fence_list[] = {
1025 {"radeon_fence_info", &radeon_debugfs_fence_info, 0, NULL},
1026 {"radeon_gpu_reset", &radeon_debugfs_gpu_reset, 0, NULL}
1027};
1028#endif
1029
1030int radeon_debugfs_fence_init(struct radeon_device *rdev)
1031{
1032#if defined(CONFIG_DEBUG_FS)
1033 return radeon_debugfs_add_files(rdev, radeon_debugfs_fence_list, 2);
1034#else
1035 return 0;
1036#endif
1037}
1038
1039static const char *radeon_fence_get_driver_name(struct dma_fence *fence)
1040{
1041 return "radeon";
1042}
1043
1044static const char *radeon_fence_get_timeline_name(struct dma_fence *f)
1045{
1046 struct radeon_fence *fence = to_radeon_fence(f);
1047 switch (fence->ring) {
1048 case RADEON_RING_TYPE_GFX_INDEX: return "radeon.gfx";
1049 case CAYMAN_RING_TYPE_CP1_INDEX: return "radeon.cp1";
1050 case CAYMAN_RING_TYPE_CP2_INDEX: return "radeon.cp2";
1051 case R600_RING_TYPE_DMA_INDEX: return "radeon.dma";
1052 case CAYMAN_RING_TYPE_DMA1_INDEX: return "radeon.dma1";
1053 case R600_RING_TYPE_UVD_INDEX: return "radeon.uvd";
1054 case TN_RING_TYPE_VCE1_INDEX: return "radeon.vce1";
1055 case TN_RING_TYPE_VCE2_INDEX: return "radeon.vce2";
1056 default: WARN_ON_ONCE(1); return "radeon.unk";
1057 }
1058}
1059
1060static inline bool radeon_test_signaled(struct radeon_fence *fence)
1061{
1062 return test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->base.flags);
1063}
1064
1065struct radeon_wait_cb {
1066 struct dma_fence_cb base;
1067 struct task_struct *task;
1068};
1069
1070static void
1071radeon_fence_wait_cb(struct dma_fence *fence, struct dma_fence_cb *cb)
1072{
1073 struct radeon_wait_cb *wait =
1074 container_of(cb, struct radeon_wait_cb, base);
1075
1076 wake_up_process(wait->task);
1077}
1078
1079static signed long radeon_fence_default_wait(struct dma_fence *f, bool intr,
1080 signed long t)
1081{
1082 struct radeon_fence *fence = to_radeon_fence(f);
1083 struct radeon_device *rdev = fence->rdev;
1084 struct radeon_wait_cb cb;
1085
1086 cb.task = current;
1087
1088 if (dma_fence_add_callback(f, &cb.base, radeon_fence_wait_cb))
1089 return t;
1090
1091 while (t > 0) {
1092 if (intr)
1093 set_current_state(TASK_INTERRUPTIBLE);
1094 else
1095 set_current_state(TASK_UNINTERRUPTIBLE);
1096
1097 /*
1098 * radeon_test_signaled must be called after
1099 * set_current_state to prevent a race with wake_up_process
1100 */
1101 if (radeon_test_signaled(fence))
1102 break;
1103
1104 if (rdev->needs_reset) {
1105 t = -EDEADLK;
1106 break;
1107 }
1108
1109 t = schedule_timeout(t);
1110
1111 if (t > 0 && intr && signal_pending(current))
1112 t = -ERESTARTSYS;
1113 }
1114
1115 __set_current_state(TASK_RUNNING);
1116 dma_fence_remove_callback(f, &cb.base);
1117
1118 return t;
1119}
1120
1121const struct dma_fence_ops radeon_fence_ops = {
1122 .get_driver_name = radeon_fence_get_driver_name,
1123 .get_timeline_name = radeon_fence_get_timeline_name,
1124 .enable_signaling = radeon_fence_enable_signaling,
1125 .signaled = radeon_fence_is_signaled,
1126 .wait = radeon_fence_default_wait,
1127 .release = NULL,
1128};