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1/* r128_cce.c -- ATI Rage 128 driver -*- linux-c -*-
2 * Created: Wed Apr 5 19:24:19 2000 by kevin@precisioninsight.com
3 */
4/*
5 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
6 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
7 * All Rights Reserved.
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
18 * Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
27 *
28 * Authors:
29 * Gareth Hughes <gareth@valinux.com>
30 */
31
32#include <linux/delay.h>
33#include <linux/dma-mapping.h>
34#include <linux/firmware.h>
35#include <linux/module.h>
36#include <linux/platform_device.h>
37#include <linux/slab.h>
38#include <linux/uaccess.h>
39
40#include <drm/drm_agpsupport.h>
41#include <drm/drm_device.h>
42#include <drm/drm_file.h>
43#include <drm/drm_irq.h>
44#include <drm/drm_print.h>
45#include <drm/r128_drm.h>
46
47#include "r128_drv.h"
48
49#define R128_FIFO_DEBUG 0
50
51#define FIRMWARE_NAME "r128/r128_cce.bin"
52
53MODULE_FIRMWARE(FIRMWARE_NAME);
54
55static int R128_READ_PLL(struct drm_device *dev, int addr)
56{
57 drm_r128_private_t *dev_priv = dev->dev_private;
58
59 R128_WRITE8(R128_CLOCK_CNTL_INDEX, addr & 0x1f);
60 return R128_READ(R128_CLOCK_CNTL_DATA);
61}
62
63#if R128_FIFO_DEBUG
64static void r128_status(drm_r128_private_t *dev_priv)
65{
66 printk("GUI_STAT = 0x%08x\n",
67 (unsigned int)R128_READ(R128_GUI_STAT));
68 printk("PM4_STAT = 0x%08x\n",
69 (unsigned int)R128_READ(R128_PM4_STAT));
70 printk("PM4_BUFFER_DL_WPTR = 0x%08x\n",
71 (unsigned int)R128_READ(R128_PM4_BUFFER_DL_WPTR));
72 printk("PM4_BUFFER_DL_RPTR = 0x%08x\n",
73 (unsigned int)R128_READ(R128_PM4_BUFFER_DL_RPTR));
74 printk("PM4_MICRO_CNTL = 0x%08x\n",
75 (unsigned int)R128_READ(R128_PM4_MICRO_CNTL));
76 printk("PM4_BUFFER_CNTL = 0x%08x\n",
77 (unsigned int)R128_READ(R128_PM4_BUFFER_CNTL));
78}
79#endif
80
81/* ================================================================
82 * Engine, FIFO control
83 */
84
85static int r128_do_pixcache_flush(drm_r128_private_t *dev_priv)
86{
87 u32 tmp;
88 int i;
89
90 tmp = R128_READ(R128_PC_NGUI_CTLSTAT) | R128_PC_FLUSH_ALL;
91 R128_WRITE(R128_PC_NGUI_CTLSTAT, tmp);
92
93 for (i = 0; i < dev_priv->usec_timeout; i++) {
94 if (!(R128_READ(R128_PC_NGUI_CTLSTAT) & R128_PC_BUSY))
95 return 0;
96 udelay(1);
97 }
98
99#if R128_FIFO_DEBUG
100 DRM_ERROR("failed!\n");
101#endif
102 return -EBUSY;
103}
104
105static int r128_do_wait_for_fifo(drm_r128_private_t *dev_priv, int entries)
106{
107 int i;
108
109 for (i = 0; i < dev_priv->usec_timeout; i++) {
110 int slots = R128_READ(R128_GUI_STAT) & R128_GUI_FIFOCNT_MASK;
111 if (slots >= entries)
112 return 0;
113 udelay(1);
114 }
115
116#if R128_FIFO_DEBUG
117 DRM_ERROR("failed!\n");
118#endif
119 return -EBUSY;
120}
121
122static int r128_do_wait_for_idle(drm_r128_private_t *dev_priv)
123{
124 int i, ret;
125
126 ret = r128_do_wait_for_fifo(dev_priv, 64);
127 if (ret)
128 return ret;
129
130 for (i = 0; i < dev_priv->usec_timeout; i++) {
131 if (!(R128_READ(R128_GUI_STAT) & R128_GUI_ACTIVE)) {
132 r128_do_pixcache_flush(dev_priv);
133 return 0;
134 }
135 udelay(1);
136 }
137
138#if R128_FIFO_DEBUG
139 DRM_ERROR("failed!\n");
140#endif
141 return -EBUSY;
142}
143
144/* ================================================================
145 * CCE control, initialization
146 */
147
148/* Load the microcode for the CCE */
149static int r128_cce_load_microcode(drm_r128_private_t *dev_priv)
150{
151 struct platform_device *pdev;
152 const struct firmware *fw;
153 const __be32 *fw_data;
154 int rc, i;
155
156 DRM_DEBUG("\n");
157
158 pdev = platform_device_register_simple("r128_cce", 0, NULL, 0);
159 if (IS_ERR(pdev)) {
160 pr_err("r128_cce: Failed to register firmware\n");
161 return PTR_ERR(pdev);
162 }
163 rc = request_firmware(&fw, FIRMWARE_NAME, &pdev->dev);
164 platform_device_unregister(pdev);
165 if (rc) {
166 pr_err("r128_cce: Failed to load firmware \"%s\"\n",
167 FIRMWARE_NAME);
168 return rc;
169 }
170
171 if (fw->size != 256 * 8) {
172 pr_err("r128_cce: Bogus length %zu in firmware \"%s\"\n",
173 fw->size, FIRMWARE_NAME);
174 rc = -EINVAL;
175 goto out_release;
176 }
177
178 r128_do_wait_for_idle(dev_priv);
179
180 fw_data = (const __be32 *)fw->data;
181 R128_WRITE(R128_PM4_MICROCODE_ADDR, 0);
182 for (i = 0; i < 256; i++) {
183 R128_WRITE(R128_PM4_MICROCODE_DATAH,
184 be32_to_cpup(&fw_data[i * 2]));
185 R128_WRITE(R128_PM4_MICROCODE_DATAL,
186 be32_to_cpup(&fw_data[i * 2 + 1]));
187 }
188
189out_release:
190 release_firmware(fw);
191 return rc;
192}
193
194/* Flush any pending commands to the CCE. This should only be used just
195 * prior to a wait for idle, as it informs the engine that the command
196 * stream is ending.
197 */
198static void r128_do_cce_flush(drm_r128_private_t *dev_priv)
199{
200 u32 tmp;
201
202 tmp = R128_READ(R128_PM4_BUFFER_DL_WPTR) | R128_PM4_BUFFER_DL_DONE;
203 R128_WRITE(R128_PM4_BUFFER_DL_WPTR, tmp);
204}
205
206/* Wait for the CCE to go idle.
207 */
208int r128_do_cce_idle(drm_r128_private_t *dev_priv)
209{
210 int i;
211
212 for (i = 0; i < dev_priv->usec_timeout; i++) {
213 if (GET_RING_HEAD(dev_priv) == dev_priv->ring.tail) {
214 int pm4stat = R128_READ(R128_PM4_STAT);
215 if (((pm4stat & R128_PM4_FIFOCNT_MASK) >=
216 dev_priv->cce_fifo_size) &&
217 !(pm4stat & (R128_PM4_BUSY |
218 R128_PM4_GUI_ACTIVE))) {
219 return r128_do_pixcache_flush(dev_priv);
220 }
221 }
222 udelay(1);
223 }
224
225#if R128_FIFO_DEBUG
226 DRM_ERROR("failed!\n");
227 r128_status(dev_priv);
228#endif
229 return -EBUSY;
230}
231
232/* Start the Concurrent Command Engine.
233 */
234static void r128_do_cce_start(drm_r128_private_t *dev_priv)
235{
236 r128_do_wait_for_idle(dev_priv);
237
238 R128_WRITE(R128_PM4_BUFFER_CNTL,
239 dev_priv->cce_mode | dev_priv->ring.size_l2qw
240 | R128_PM4_BUFFER_CNTL_NOUPDATE);
241 R128_READ(R128_PM4_BUFFER_ADDR); /* as per the sample code */
242 R128_WRITE(R128_PM4_MICRO_CNTL, R128_PM4_MICRO_FREERUN);
243
244 dev_priv->cce_running = 1;
245}
246
247/* Reset the Concurrent Command Engine. This will not flush any pending
248 * commands, so you must wait for the CCE command stream to complete
249 * before calling this routine.
250 */
251static void r128_do_cce_reset(drm_r128_private_t *dev_priv)
252{
253 R128_WRITE(R128_PM4_BUFFER_DL_WPTR, 0);
254 R128_WRITE(R128_PM4_BUFFER_DL_RPTR, 0);
255 dev_priv->ring.tail = 0;
256}
257
258/* Stop the Concurrent Command Engine. This will not flush any pending
259 * commands, so you must flush the command stream and wait for the CCE
260 * to go idle before calling this routine.
261 */
262static void r128_do_cce_stop(drm_r128_private_t *dev_priv)
263{
264 R128_WRITE(R128_PM4_MICRO_CNTL, 0);
265 R128_WRITE(R128_PM4_BUFFER_CNTL,
266 R128_PM4_NONPM4 | R128_PM4_BUFFER_CNTL_NOUPDATE);
267
268 dev_priv->cce_running = 0;
269}
270
271/* Reset the engine. This will stop the CCE if it is running.
272 */
273static int r128_do_engine_reset(struct drm_device *dev)
274{
275 drm_r128_private_t *dev_priv = dev->dev_private;
276 u32 clock_cntl_index, mclk_cntl, gen_reset_cntl;
277
278 r128_do_pixcache_flush(dev_priv);
279
280 clock_cntl_index = R128_READ(R128_CLOCK_CNTL_INDEX);
281 mclk_cntl = R128_READ_PLL(dev, R128_MCLK_CNTL);
282
283 R128_WRITE_PLL(R128_MCLK_CNTL,
284 mclk_cntl | R128_FORCE_GCP | R128_FORCE_PIPE3D_CP);
285
286 gen_reset_cntl = R128_READ(R128_GEN_RESET_CNTL);
287
288 /* Taken from the sample code - do not change */
289 R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl | R128_SOFT_RESET_GUI);
290 R128_READ(R128_GEN_RESET_CNTL);
291 R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl & ~R128_SOFT_RESET_GUI);
292 R128_READ(R128_GEN_RESET_CNTL);
293
294 R128_WRITE_PLL(R128_MCLK_CNTL, mclk_cntl);
295 R128_WRITE(R128_CLOCK_CNTL_INDEX, clock_cntl_index);
296 R128_WRITE(R128_GEN_RESET_CNTL, gen_reset_cntl);
297
298 /* Reset the CCE ring */
299 r128_do_cce_reset(dev_priv);
300
301 /* The CCE is no longer running after an engine reset */
302 dev_priv->cce_running = 0;
303
304 /* Reset any pending vertex, indirect buffers */
305 r128_freelist_reset(dev);
306
307 return 0;
308}
309
310static void r128_cce_init_ring_buffer(struct drm_device *dev,
311 drm_r128_private_t *dev_priv)
312{
313 u32 ring_start;
314 u32 tmp;
315
316 DRM_DEBUG("\n");
317
318 /* The manual (p. 2) says this address is in "VM space". This
319 * means it's an offset from the start of AGP space.
320 */
321#if IS_ENABLED(CONFIG_AGP)
322 if (!dev_priv->is_pci)
323 ring_start = dev_priv->cce_ring->offset - dev->agp->base;
324 else
325#endif
326 ring_start = dev_priv->cce_ring->offset -
327 (unsigned long)dev->sg->virtual;
328
329 R128_WRITE(R128_PM4_BUFFER_OFFSET, ring_start | R128_AGP_OFFSET);
330
331 R128_WRITE(R128_PM4_BUFFER_DL_WPTR, 0);
332 R128_WRITE(R128_PM4_BUFFER_DL_RPTR, 0);
333
334 /* Set watermark control */
335 R128_WRITE(R128_PM4_BUFFER_WM_CNTL,
336 ((R128_WATERMARK_L / 4) << R128_WMA_SHIFT)
337 | ((R128_WATERMARK_M / 4) << R128_WMB_SHIFT)
338 | ((R128_WATERMARK_N / 4) << R128_WMC_SHIFT)
339 | ((R128_WATERMARK_K / 64) << R128_WB_WM_SHIFT));
340
341 /* Force read. Why? Because it's in the examples... */
342 R128_READ(R128_PM4_BUFFER_ADDR);
343
344 /* Turn on bus mastering */
345 tmp = R128_READ(R128_BUS_CNTL) & ~R128_BUS_MASTER_DIS;
346 R128_WRITE(R128_BUS_CNTL, tmp);
347}
348
349static int r128_do_init_cce(struct drm_device *dev, drm_r128_init_t *init)
350{
351 drm_r128_private_t *dev_priv;
352 int rc;
353
354 DRM_DEBUG("\n");
355
356 if (dev->dev_private) {
357 DRM_DEBUG("called when already initialized\n");
358 return -EINVAL;
359 }
360
361 dev_priv = kzalloc(sizeof(drm_r128_private_t), GFP_KERNEL);
362 if (dev_priv == NULL)
363 return -ENOMEM;
364
365 dev_priv->is_pci = init->is_pci;
366
367 if (dev_priv->is_pci && !dev->sg) {
368 DRM_ERROR("PCI GART memory not allocated!\n");
369 dev->dev_private = (void *)dev_priv;
370 r128_do_cleanup_cce(dev);
371 return -EINVAL;
372 }
373
374 dev_priv->usec_timeout = init->usec_timeout;
375 if (dev_priv->usec_timeout < 1 ||
376 dev_priv->usec_timeout > R128_MAX_USEC_TIMEOUT) {
377 DRM_DEBUG("TIMEOUT problem!\n");
378 dev->dev_private = (void *)dev_priv;
379 r128_do_cleanup_cce(dev);
380 return -EINVAL;
381 }
382
383 dev_priv->cce_mode = init->cce_mode;
384
385 /* GH: Simple idle check.
386 */
387 atomic_set(&dev_priv->idle_count, 0);
388
389 /* We don't support anything other than bus-mastering ring mode,
390 * but the ring can be in either AGP or PCI space for the ring
391 * read pointer.
392 */
393 if ((init->cce_mode != R128_PM4_192BM) &&
394 (init->cce_mode != R128_PM4_128BM_64INDBM) &&
395 (init->cce_mode != R128_PM4_64BM_128INDBM) &&
396 (init->cce_mode != R128_PM4_64BM_64VCBM_64INDBM)) {
397 DRM_DEBUG("Bad cce_mode!\n");
398 dev->dev_private = (void *)dev_priv;
399 r128_do_cleanup_cce(dev);
400 return -EINVAL;
401 }
402
403 switch (init->cce_mode) {
404 case R128_PM4_NONPM4:
405 dev_priv->cce_fifo_size = 0;
406 break;
407 case R128_PM4_192PIO:
408 case R128_PM4_192BM:
409 dev_priv->cce_fifo_size = 192;
410 break;
411 case R128_PM4_128PIO_64INDBM:
412 case R128_PM4_128BM_64INDBM:
413 dev_priv->cce_fifo_size = 128;
414 break;
415 case R128_PM4_64PIO_128INDBM:
416 case R128_PM4_64BM_128INDBM:
417 case R128_PM4_64PIO_64VCBM_64INDBM:
418 case R128_PM4_64BM_64VCBM_64INDBM:
419 case R128_PM4_64PIO_64VCPIO_64INDPIO:
420 dev_priv->cce_fifo_size = 64;
421 break;
422 }
423
424 switch (init->fb_bpp) {
425 case 16:
426 dev_priv->color_fmt = R128_DATATYPE_RGB565;
427 break;
428 case 32:
429 default:
430 dev_priv->color_fmt = R128_DATATYPE_ARGB8888;
431 break;
432 }
433 dev_priv->front_offset = init->front_offset;
434 dev_priv->front_pitch = init->front_pitch;
435 dev_priv->back_offset = init->back_offset;
436 dev_priv->back_pitch = init->back_pitch;
437
438 switch (init->depth_bpp) {
439 case 16:
440 dev_priv->depth_fmt = R128_DATATYPE_RGB565;
441 break;
442 case 24:
443 case 32:
444 default:
445 dev_priv->depth_fmt = R128_DATATYPE_ARGB8888;
446 break;
447 }
448 dev_priv->depth_offset = init->depth_offset;
449 dev_priv->depth_pitch = init->depth_pitch;
450 dev_priv->span_offset = init->span_offset;
451
452 dev_priv->front_pitch_offset_c = (((dev_priv->front_pitch / 8) << 21) |
453 (dev_priv->front_offset >> 5));
454 dev_priv->back_pitch_offset_c = (((dev_priv->back_pitch / 8) << 21) |
455 (dev_priv->back_offset >> 5));
456 dev_priv->depth_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) |
457 (dev_priv->depth_offset >> 5) |
458 R128_DST_TILE);
459 dev_priv->span_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) |
460 (dev_priv->span_offset >> 5));
461
462 dev_priv->sarea = drm_legacy_getsarea(dev);
463 if (!dev_priv->sarea) {
464 DRM_ERROR("could not find sarea!\n");
465 dev->dev_private = (void *)dev_priv;
466 r128_do_cleanup_cce(dev);
467 return -EINVAL;
468 }
469
470 dev_priv->mmio = drm_legacy_findmap(dev, init->mmio_offset);
471 if (!dev_priv->mmio) {
472 DRM_ERROR("could not find mmio region!\n");
473 dev->dev_private = (void *)dev_priv;
474 r128_do_cleanup_cce(dev);
475 return -EINVAL;
476 }
477 dev_priv->cce_ring = drm_legacy_findmap(dev, init->ring_offset);
478 if (!dev_priv->cce_ring) {
479 DRM_ERROR("could not find cce ring region!\n");
480 dev->dev_private = (void *)dev_priv;
481 r128_do_cleanup_cce(dev);
482 return -EINVAL;
483 }
484 dev_priv->ring_rptr = drm_legacy_findmap(dev, init->ring_rptr_offset);
485 if (!dev_priv->ring_rptr) {
486 DRM_ERROR("could not find ring read pointer!\n");
487 dev->dev_private = (void *)dev_priv;
488 r128_do_cleanup_cce(dev);
489 return -EINVAL;
490 }
491 dev->agp_buffer_token = init->buffers_offset;
492 dev->agp_buffer_map = drm_legacy_findmap(dev, init->buffers_offset);
493 if (!dev->agp_buffer_map) {
494 DRM_ERROR("could not find dma buffer region!\n");
495 dev->dev_private = (void *)dev_priv;
496 r128_do_cleanup_cce(dev);
497 return -EINVAL;
498 }
499
500 if (!dev_priv->is_pci) {
501 dev_priv->agp_textures =
502 drm_legacy_findmap(dev, init->agp_textures_offset);
503 if (!dev_priv->agp_textures) {
504 DRM_ERROR("could not find agp texture region!\n");
505 dev->dev_private = (void *)dev_priv;
506 r128_do_cleanup_cce(dev);
507 return -EINVAL;
508 }
509 }
510
511 dev_priv->sarea_priv =
512 (drm_r128_sarea_t *) ((u8 *) dev_priv->sarea->handle +
513 init->sarea_priv_offset);
514
515#if IS_ENABLED(CONFIG_AGP)
516 if (!dev_priv->is_pci) {
517 drm_legacy_ioremap_wc(dev_priv->cce_ring, dev);
518 drm_legacy_ioremap_wc(dev_priv->ring_rptr, dev);
519 drm_legacy_ioremap_wc(dev->agp_buffer_map, dev);
520 if (!dev_priv->cce_ring->handle ||
521 !dev_priv->ring_rptr->handle ||
522 !dev->agp_buffer_map->handle) {
523 DRM_ERROR("Could not ioremap agp regions!\n");
524 dev->dev_private = (void *)dev_priv;
525 r128_do_cleanup_cce(dev);
526 return -ENOMEM;
527 }
528 } else
529#endif
530 {
531 dev_priv->cce_ring->handle =
532 (void *)(unsigned long)dev_priv->cce_ring->offset;
533 dev_priv->ring_rptr->handle =
534 (void *)(unsigned long)dev_priv->ring_rptr->offset;
535 dev->agp_buffer_map->handle =
536 (void *)(unsigned long)dev->agp_buffer_map->offset;
537 }
538
539#if IS_ENABLED(CONFIG_AGP)
540 if (!dev_priv->is_pci)
541 dev_priv->cce_buffers_offset = dev->agp->base;
542 else
543#endif
544 dev_priv->cce_buffers_offset = (unsigned long)dev->sg->virtual;
545
546 dev_priv->ring.start = (u32 *) dev_priv->cce_ring->handle;
547 dev_priv->ring.end = ((u32 *) dev_priv->cce_ring->handle
548 + init->ring_size / sizeof(u32));
549 dev_priv->ring.size = init->ring_size;
550 dev_priv->ring.size_l2qw = order_base_2(init->ring_size / 8);
551
552 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
553
554 dev_priv->ring.high_mark = 128;
555
556 dev_priv->sarea_priv->last_frame = 0;
557 R128_WRITE(R128_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
558
559 dev_priv->sarea_priv->last_dispatch = 0;
560 R128_WRITE(R128_LAST_DISPATCH_REG, dev_priv->sarea_priv->last_dispatch);
561
562#if IS_ENABLED(CONFIG_AGP)
563 if (dev_priv->is_pci) {
564#endif
565 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
566 dev_priv->gart_info.gart_table_location = DRM_ATI_GART_MAIN;
567 dev_priv->gart_info.table_size = R128_PCIGART_TABLE_SIZE;
568 dev_priv->gart_info.addr = NULL;
569 dev_priv->gart_info.bus_addr = 0;
570 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
571 rc = drm_ati_pcigart_init(dev, &dev_priv->gart_info);
572 if (rc) {
573 DRM_ERROR("failed to init PCI GART!\n");
574 dev->dev_private = (void *)dev_priv;
575 r128_do_cleanup_cce(dev);
576 return rc;
577 }
578 R128_WRITE(R128_PCI_GART_PAGE, dev_priv->gart_info.bus_addr);
579#if IS_ENABLED(CONFIG_AGP)
580 }
581#endif
582
583 r128_cce_init_ring_buffer(dev, dev_priv);
584 rc = r128_cce_load_microcode(dev_priv);
585
586 dev->dev_private = (void *)dev_priv;
587
588 r128_do_engine_reset(dev);
589
590 if (rc) {
591 DRM_ERROR("Failed to load firmware!\n");
592 r128_do_cleanup_cce(dev);
593 }
594
595 return rc;
596}
597
598int r128_do_cleanup_cce(struct drm_device *dev)
599{
600
601 /* Make sure interrupts are disabled here because the uninstall ioctl
602 * may not have been called from userspace and after dev_private
603 * is freed, it's too late.
604 */
605 if (dev->irq_enabled)
606 drm_irq_uninstall(dev);
607
608 if (dev->dev_private) {
609 drm_r128_private_t *dev_priv = dev->dev_private;
610
611#if IS_ENABLED(CONFIG_AGP)
612 if (!dev_priv->is_pci) {
613 if (dev_priv->cce_ring != NULL)
614 drm_legacy_ioremapfree(dev_priv->cce_ring, dev);
615 if (dev_priv->ring_rptr != NULL)
616 drm_legacy_ioremapfree(dev_priv->ring_rptr, dev);
617 if (dev->agp_buffer_map != NULL) {
618 drm_legacy_ioremapfree(dev->agp_buffer_map, dev);
619 dev->agp_buffer_map = NULL;
620 }
621 } else
622#endif
623 {
624 if (dev_priv->gart_info.bus_addr)
625 if (!drm_ati_pcigart_cleanup(dev,
626 &dev_priv->gart_info))
627 DRM_ERROR
628 ("failed to cleanup PCI GART!\n");
629 }
630
631 kfree(dev->dev_private);
632 dev->dev_private = NULL;
633 }
634
635 return 0;
636}
637
638int r128_cce_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
639{
640 drm_r128_init_t *init = data;
641
642 DRM_DEBUG("\n");
643
644 LOCK_TEST_WITH_RETURN(dev, file_priv);
645
646 switch (init->func) {
647 case R128_INIT_CCE:
648 return r128_do_init_cce(dev, init);
649 case R128_CLEANUP_CCE:
650 return r128_do_cleanup_cce(dev);
651 }
652
653 return -EINVAL;
654}
655
656int r128_cce_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
657{
658 drm_r128_private_t *dev_priv = dev->dev_private;
659 DRM_DEBUG("\n");
660
661 LOCK_TEST_WITH_RETURN(dev, file_priv);
662
663 DEV_INIT_TEST_WITH_RETURN(dev_priv);
664
665 if (dev_priv->cce_running || dev_priv->cce_mode == R128_PM4_NONPM4) {
666 DRM_DEBUG("while CCE running\n");
667 return 0;
668 }
669
670 r128_do_cce_start(dev_priv);
671
672 return 0;
673}
674
675/* Stop the CCE. The engine must have been idled before calling this
676 * routine.
677 */
678int r128_cce_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
679{
680 drm_r128_private_t *dev_priv = dev->dev_private;
681 drm_r128_cce_stop_t *stop = data;
682 int ret;
683 DRM_DEBUG("\n");
684
685 LOCK_TEST_WITH_RETURN(dev, file_priv);
686
687 DEV_INIT_TEST_WITH_RETURN(dev_priv);
688
689 /* Flush any pending CCE commands. This ensures any outstanding
690 * commands are exectuted by the engine before we turn it off.
691 */
692 if (stop->flush)
693 r128_do_cce_flush(dev_priv);
694
695 /* If we fail to make the engine go idle, we return an error
696 * code so that the DRM ioctl wrapper can try again.
697 */
698 if (stop->idle) {
699 ret = r128_do_cce_idle(dev_priv);
700 if (ret)
701 return ret;
702 }
703
704 /* Finally, we can turn off the CCE. If the engine isn't idle,
705 * we will get some dropped triangles as they won't be fully
706 * rendered before the CCE is shut down.
707 */
708 r128_do_cce_stop(dev_priv);
709
710 /* Reset the engine */
711 r128_do_engine_reset(dev);
712
713 return 0;
714}
715
716/* Just reset the CCE ring. Called as part of an X Server engine reset.
717 */
718int r128_cce_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
719{
720 drm_r128_private_t *dev_priv = dev->dev_private;
721 DRM_DEBUG("\n");
722
723 LOCK_TEST_WITH_RETURN(dev, file_priv);
724
725 DEV_INIT_TEST_WITH_RETURN(dev_priv);
726
727 r128_do_cce_reset(dev_priv);
728
729 /* The CCE is no longer running after an engine reset */
730 dev_priv->cce_running = 0;
731
732 return 0;
733}
734
735int r128_cce_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
736{
737 drm_r128_private_t *dev_priv = dev->dev_private;
738 DRM_DEBUG("\n");
739
740 LOCK_TEST_WITH_RETURN(dev, file_priv);
741
742 DEV_INIT_TEST_WITH_RETURN(dev_priv);
743
744 if (dev_priv->cce_running)
745 r128_do_cce_flush(dev_priv);
746
747 return r128_do_cce_idle(dev_priv);
748}
749
750int r128_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
751{
752 DRM_DEBUG("\n");
753
754 LOCK_TEST_WITH_RETURN(dev, file_priv);
755
756 DEV_INIT_TEST_WITH_RETURN(dev->dev_private);
757
758 return r128_do_engine_reset(dev);
759}
760
761int r128_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
762{
763 return -EINVAL;
764}
765
766/* ================================================================
767 * Freelist management
768 */
769#define R128_BUFFER_USED 0xffffffff
770#define R128_BUFFER_FREE 0
771
772#if 0
773static int r128_freelist_init(struct drm_device *dev)
774{
775 struct drm_device_dma *dma = dev->dma;
776 drm_r128_private_t *dev_priv = dev->dev_private;
777 struct drm_buf *buf;
778 drm_r128_buf_priv_t *buf_priv;
779 drm_r128_freelist_t *entry;
780 int i;
781
782 dev_priv->head = kzalloc(sizeof(drm_r128_freelist_t), GFP_KERNEL);
783 if (dev_priv->head == NULL)
784 return -ENOMEM;
785
786 dev_priv->head->age = R128_BUFFER_USED;
787
788 for (i = 0; i < dma->buf_count; i++) {
789 buf = dma->buflist[i];
790 buf_priv = buf->dev_private;
791
792 entry = kmalloc(sizeof(drm_r128_freelist_t), GFP_KERNEL);
793 if (!entry)
794 return -ENOMEM;
795
796 entry->age = R128_BUFFER_FREE;
797 entry->buf = buf;
798 entry->prev = dev_priv->head;
799 entry->next = dev_priv->head->next;
800 if (!entry->next)
801 dev_priv->tail = entry;
802
803 buf_priv->discard = 0;
804 buf_priv->dispatched = 0;
805 buf_priv->list_entry = entry;
806
807 dev_priv->head->next = entry;
808
809 if (dev_priv->head->next)
810 dev_priv->head->next->prev = entry;
811 }
812
813 return 0;
814
815}
816#endif
817
818static struct drm_buf *r128_freelist_get(struct drm_device * dev)
819{
820 struct drm_device_dma *dma = dev->dma;
821 drm_r128_private_t *dev_priv = dev->dev_private;
822 drm_r128_buf_priv_t *buf_priv;
823 struct drm_buf *buf;
824 int i, t;
825
826 /* FIXME: Optimize -- use freelist code */
827
828 for (i = 0; i < dma->buf_count; i++) {
829 buf = dma->buflist[i];
830 buf_priv = buf->dev_private;
831 if (!buf->file_priv)
832 return buf;
833 }
834
835 for (t = 0; t < dev_priv->usec_timeout; t++) {
836 u32 done_age = R128_READ(R128_LAST_DISPATCH_REG);
837
838 for (i = 0; i < dma->buf_count; i++) {
839 buf = dma->buflist[i];
840 buf_priv = buf->dev_private;
841 if (buf->pending && buf_priv->age <= done_age) {
842 /* The buffer has been processed, so it
843 * can now be used.
844 */
845 buf->pending = 0;
846 return buf;
847 }
848 }
849 udelay(1);
850 }
851
852 DRM_DEBUG("returning NULL!\n");
853 return NULL;
854}
855
856void r128_freelist_reset(struct drm_device *dev)
857{
858 struct drm_device_dma *dma = dev->dma;
859 int i;
860
861 for (i = 0; i < dma->buf_count; i++) {
862 struct drm_buf *buf = dma->buflist[i];
863 drm_r128_buf_priv_t *buf_priv = buf->dev_private;
864 buf_priv->age = 0;
865 }
866}
867
868/* ================================================================
869 * CCE command submission
870 */
871
872int r128_wait_ring(drm_r128_private_t *dev_priv, int n)
873{
874 drm_r128_ring_buffer_t *ring = &dev_priv->ring;
875 int i;
876
877 for (i = 0; i < dev_priv->usec_timeout; i++) {
878 r128_update_ring_snapshot(dev_priv);
879 if (ring->space >= n)
880 return 0;
881 udelay(1);
882 }
883
884 /* FIXME: This is being ignored... */
885 DRM_ERROR("failed!\n");
886 return -EBUSY;
887}
888
889static int r128_cce_get_buffers(struct drm_device *dev,
890 struct drm_file *file_priv,
891 struct drm_dma *d)
892{
893 int i;
894 struct drm_buf *buf;
895
896 for (i = d->granted_count; i < d->request_count; i++) {
897 buf = r128_freelist_get(dev);
898 if (!buf)
899 return -EAGAIN;
900
901 buf->file_priv = file_priv;
902
903 if (copy_to_user(&d->request_indices[i], &buf->idx,
904 sizeof(buf->idx)))
905 return -EFAULT;
906 if (copy_to_user(&d->request_sizes[i], &buf->total,
907 sizeof(buf->total)))
908 return -EFAULT;
909
910 d->granted_count++;
911 }
912 return 0;
913}
914
915int r128_cce_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
916{
917 struct drm_device_dma *dma = dev->dma;
918 int ret = 0;
919 struct drm_dma *d = data;
920
921 LOCK_TEST_WITH_RETURN(dev, file_priv);
922
923 /* Please don't send us buffers.
924 */
925 if (d->send_count != 0) {
926 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
927 task_pid_nr(current), d->send_count);
928 return -EINVAL;
929 }
930
931 /* We'll send you buffers.
932 */
933 if (d->request_count < 0 || d->request_count > dma->buf_count) {
934 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
935 task_pid_nr(current), d->request_count, dma->buf_count);
936 return -EINVAL;
937 }
938
939 d->granted_count = 0;
940
941 if (d->request_count)
942 ret = r128_cce_get_buffers(dev, file_priv, d);
943
944 return ret;
945}