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1/*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30#include <linux/log2.h>
31
32#include <drm/i915_drm.h>
33
34#include "gem/i915_gem_context.h"
35
36#include "i915_drv.h"
37#include "i915_trace.h"
38#include "intel_context.h"
39#include "intel_gt.h"
40#include "intel_gt_irq.h"
41#include "intel_gt_pm_irq.h"
42#include "intel_reset.h"
43#include "intel_workarounds.h"
44
45/* Rough estimate of the typical request size, performing a flush,
46 * set-context and then emitting the batch.
47 */
48#define LEGACY_REQUEST_SIZE 200
49
50unsigned int intel_ring_update_space(struct intel_ring *ring)
51{
52 unsigned int space;
53
54 space = __intel_ring_space(ring->head, ring->emit, ring->size);
55
56 ring->space = space;
57 return space;
58}
59
60static int
61gen2_render_ring_flush(struct i915_request *rq, u32 mode)
62{
63 unsigned int num_store_dw;
64 u32 cmd, *cs;
65
66 cmd = MI_FLUSH;
67 num_store_dw = 0;
68 if (mode & EMIT_INVALIDATE)
69 cmd |= MI_READ_FLUSH;
70 if (mode & EMIT_FLUSH)
71 num_store_dw = 4;
72
73 cs = intel_ring_begin(rq, 2 + 3 * num_store_dw);
74 if (IS_ERR(cs))
75 return PTR_ERR(cs);
76
77 *cs++ = cmd;
78 while (num_store_dw--) {
79 *cs++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
80 *cs++ = intel_gt_scratch_offset(rq->engine->gt,
81 INTEL_GT_SCRATCH_FIELD_DEFAULT);
82 *cs++ = 0;
83 }
84 *cs++ = MI_FLUSH | MI_NO_WRITE_FLUSH;
85
86 intel_ring_advance(rq, cs);
87
88 return 0;
89}
90
91static int
92gen4_render_ring_flush(struct i915_request *rq, u32 mode)
93{
94 u32 cmd, *cs;
95 int i;
96
97 /*
98 * read/write caches:
99 *
100 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
101 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
102 * also flushed at 2d versus 3d pipeline switches.
103 *
104 * read-only caches:
105 *
106 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
107 * MI_READ_FLUSH is set, and is always flushed on 965.
108 *
109 * I915_GEM_DOMAIN_COMMAND may not exist?
110 *
111 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
112 * invalidated when MI_EXE_FLUSH is set.
113 *
114 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
115 * invalidated with every MI_FLUSH.
116 *
117 * TLBs:
118 *
119 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
120 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
121 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
122 * are flushed at any MI_FLUSH.
123 */
124
125 cmd = MI_FLUSH;
126 if (mode & EMIT_INVALIDATE) {
127 cmd |= MI_EXE_FLUSH;
128 if (IS_G4X(rq->i915) || IS_GEN(rq->i915, 5))
129 cmd |= MI_INVALIDATE_ISP;
130 }
131
132 i = 2;
133 if (mode & EMIT_INVALIDATE)
134 i += 20;
135
136 cs = intel_ring_begin(rq, i);
137 if (IS_ERR(cs))
138 return PTR_ERR(cs);
139
140 *cs++ = cmd;
141
142 /*
143 * A random delay to let the CS invalidate take effect? Without this
144 * delay, the GPU relocation path fails as the CS does not see
145 * the updated contents. Just as important, if we apply the flushes
146 * to the EMIT_FLUSH branch (i.e. immediately after the relocation
147 * write and before the invalidate on the next batch), the relocations
148 * still fail. This implies that is a delay following invalidation
149 * that is required to reset the caches as opposed to a delay to
150 * ensure the memory is written.
151 */
152 if (mode & EMIT_INVALIDATE) {
153 *cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE;
154 *cs++ = intel_gt_scratch_offset(rq->engine->gt,
155 INTEL_GT_SCRATCH_FIELD_DEFAULT) |
156 PIPE_CONTROL_GLOBAL_GTT;
157 *cs++ = 0;
158 *cs++ = 0;
159
160 for (i = 0; i < 12; i++)
161 *cs++ = MI_FLUSH;
162
163 *cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE;
164 *cs++ = intel_gt_scratch_offset(rq->engine->gt,
165 INTEL_GT_SCRATCH_FIELD_DEFAULT) |
166 PIPE_CONTROL_GLOBAL_GTT;
167 *cs++ = 0;
168 *cs++ = 0;
169 }
170
171 *cs++ = cmd;
172
173 intel_ring_advance(rq, cs);
174
175 return 0;
176}
177
178/*
179 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
180 * implementing two workarounds on gen6. From section 1.4.7.1
181 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
182 *
183 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
184 * produced by non-pipelined state commands), software needs to first
185 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
186 * 0.
187 *
188 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
189 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
190 *
191 * And the workaround for these two requires this workaround first:
192 *
193 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
194 * BEFORE the pipe-control with a post-sync op and no write-cache
195 * flushes.
196 *
197 * And this last workaround is tricky because of the requirements on
198 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
199 * volume 2 part 1:
200 *
201 * "1 of the following must also be set:
202 * - Render Target Cache Flush Enable ([12] of DW1)
203 * - Depth Cache Flush Enable ([0] of DW1)
204 * - Stall at Pixel Scoreboard ([1] of DW1)
205 * - Depth Stall ([13] of DW1)
206 * - Post-Sync Operation ([13] of DW1)
207 * - Notify Enable ([8] of DW1)"
208 *
209 * The cache flushes require the workaround flush that triggered this
210 * one, so we can't use it. Depth stall would trigger the same.
211 * Post-sync nonzero is what triggered this second workaround, so we
212 * can't use that one either. Notify enable is IRQs, which aren't
213 * really our business. That leaves only stall at scoreboard.
214 */
215static int
216gen6_emit_post_sync_nonzero_flush(struct i915_request *rq)
217{
218 u32 scratch_addr =
219 intel_gt_scratch_offset(rq->engine->gt,
220 INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH);
221 u32 *cs;
222
223 cs = intel_ring_begin(rq, 6);
224 if (IS_ERR(cs))
225 return PTR_ERR(cs);
226
227 *cs++ = GFX_OP_PIPE_CONTROL(5);
228 *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD;
229 *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT;
230 *cs++ = 0; /* low dword */
231 *cs++ = 0; /* high dword */
232 *cs++ = MI_NOOP;
233 intel_ring_advance(rq, cs);
234
235 cs = intel_ring_begin(rq, 6);
236 if (IS_ERR(cs))
237 return PTR_ERR(cs);
238
239 *cs++ = GFX_OP_PIPE_CONTROL(5);
240 *cs++ = PIPE_CONTROL_QW_WRITE;
241 *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT;
242 *cs++ = 0;
243 *cs++ = 0;
244 *cs++ = MI_NOOP;
245 intel_ring_advance(rq, cs);
246
247 return 0;
248}
249
250static int
251gen6_render_ring_flush(struct i915_request *rq, u32 mode)
252{
253 u32 scratch_addr =
254 intel_gt_scratch_offset(rq->engine->gt,
255 INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH);
256 u32 *cs, flags = 0;
257 int ret;
258
259 /* Force SNB workarounds for PIPE_CONTROL flushes */
260 ret = gen6_emit_post_sync_nonzero_flush(rq);
261 if (ret)
262 return ret;
263
264 /* Just flush everything. Experiments have shown that reducing the
265 * number of bits based on the write domains has little performance
266 * impact.
267 */
268 if (mode & EMIT_FLUSH) {
269 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
270 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
271 /*
272 * Ensure that any following seqno writes only happen
273 * when the render cache is indeed flushed.
274 */
275 flags |= PIPE_CONTROL_CS_STALL;
276 }
277 if (mode & EMIT_INVALIDATE) {
278 flags |= PIPE_CONTROL_TLB_INVALIDATE;
279 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
280 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
281 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
282 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
283 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
284 /*
285 * TLB invalidate requires a post-sync write.
286 */
287 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
288 }
289
290 cs = intel_ring_begin(rq, 4);
291 if (IS_ERR(cs))
292 return PTR_ERR(cs);
293
294 *cs++ = GFX_OP_PIPE_CONTROL(4);
295 *cs++ = flags;
296 *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT;
297 *cs++ = 0;
298 intel_ring_advance(rq, cs);
299
300 return 0;
301}
302
303static u32 *gen6_rcs_emit_breadcrumb(struct i915_request *rq, u32 *cs)
304{
305 /* First we do the gen6_emit_post_sync_nonzero_flush w/a */
306 *cs++ = GFX_OP_PIPE_CONTROL(4);
307 *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD;
308 *cs++ = 0;
309 *cs++ = 0;
310
311 *cs++ = GFX_OP_PIPE_CONTROL(4);
312 *cs++ = PIPE_CONTROL_QW_WRITE;
313 *cs++ = intel_gt_scratch_offset(rq->engine->gt,
314 INTEL_GT_SCRATCH_FIELD_DEFAULT) |
315 PIPE_CONTROL_GLOBAL_GTT;
316 *cs++ = 0;
317
318 /* Finally we can flush and with it emit the breadcrumb */
319 *cs++ = GFX_OP_PIPE_CONTROL(4);
320 *cs++ = (PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
321 PIPE_CONTROL_DEPTH_CACHE_FLUSH |
322 PIPE_CONTROL_DC_FLUSH_ENABLE |
323 PIPE_CONTROL_QW_WRITE |
324 PIPE_CONTROL_CS_STALL);
325 *cs++ = rq->timeline->hwsp_offset | PIPE_CONTROL_GLOBAL_GTT;
326 *cs++ = rq->fence.seqno;
327
328 *cs++ = MI_USER_INTERRUPT;
329 *cs++ = MI_NOOP;
330
331 rq->tail = intel_ring_offset(rq, cs);
332 assert_ring_tail_valid(rq->ring, rq->tail);
333
334 return cs;
335}
336
337static int
338gen7_render_ring_cs_stall_wa(struct i915_request *rq)
339{
340 u32 *cs;
341
342 cs = intel_ring_begin(rq, 4);
343 if (IS_ERR(cs))
344 return PTR_ERR(cs);
345
346 *cs++ = GFX_OP_PIPE_CONTROL(4);
347 *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD;
348 *cs++ = 0;
349 *cs++ = 0;
350 intel_ring_advance(rq, cs);
351
352 return 0;
353}
354
355static int
356gen7_render_ring_flush(struct i915_request *rq, u32 mode)
357{
358 u32 scratch_addr =
359 intel_gt_scratch_offset(rq->engine->gt,
360 INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH);
361 u32 *cs, flags = 0;
362
363 /*
364 * Ensure that any following seqno writes only happen when the render
365 * cache is indeed flushed.
366 *
367 * Workaround: 4th PIPE_CONTROL command (except the ones with only
368 * read-cache invalidate bits set) must have the CS_STALL bit set. We
369 * don't try to be clever and just set it unconditionally.
370 */
371 flags |= PIPE_CONTROL_CS_STALL;
372
373 /* Just flush everything. Experiments have shown that reducing the
374 * number of bits based on the write domains has little performance
375 * impact.
376 */
377 if (mode & EMIT_FLUSH) {
378 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
379 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
380 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
381 flags |= PIPE_CONTROL_FLUSH_ENABLE;
382 }
383 if (mode & EMIT_INVALIDATE) {
384 flags |= PIPE_CONTROL_TLB_INVALIDATE;
385 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
386 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
387 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
388 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
389 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
390 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
391 /*
392 * TLB invalidate requires a post-sync write.
393 */
394 flags |= PIPE_CONTROL_QW_WRITE;
395 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
396
397 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
398
399 /* Workaround: we must issue a pipe_control with CS-stall bit
400 * set before a pipe_control command that has the state cache
401 * invalidate bit set. */
402 gen7_render_ring_cs_stall_wa(rq);
403 }
404
405 cs = intel_ring_begin(rq, 4);
406 if (IS_ERR(cs))
407 return PTR_ERR(cs);
408
409 *cs++ = GFX_OP_PIPE_CONTROL(4);
410 *cs++ = flags;
411 *cs++ = scratch_addr;
412 *cs++ = 0;
413 intel_ring_advance(rq, cs);
414
415 return 0;
416}
417
418static u32 *gen7_rcs_emit_breadcrumb(struct i915_request *rq, u32 *cs)
419{
420 *cs++ = GFX_OP_PIPE_CONTROL(4);
421 *cs++ = (PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
422 PIPE_CONTROL_DEPTH_CACHE_FLUSH |
423 PIPE_CONTROL_DC_FLUSH_ENABLE |
424 PIPE_CONTROL_FLUSH_ENABLE |
425 PIPE_CONTROL_QW_WRITE |
426 PIPE_CONTROL_GLOBAL_GTT_IVB |
427 PIPE_CONTROL_CS_STALL);
428 *cs++ = rq->timeline->hwsp_offset;
429 *cs++ = rq->fence.seqno;
430
431 *cs++ = MI_USER_INTERRUPT;
432 *cs++ = MI_NOOP;
433
434 rq->tail = intel_ring_offset(rq, cs);
435 assert_ring_tail_valid(rq->ring, rq->tail);
436
437 return cs;
438}
439
440static u32 *gen6_xcs_emit_breadcrumb(struct i915_request *rq, u32 *cs)
441{
442 GEM_BUG_ON(rq->timeline->hwsp_ggtt != rq->engine->status_page.vma);
443 GEM_BUG_ON(offset_in_page(rq->timeline->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR);
444
445 *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX;
446 *cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT;
447 *cs++ = rq->fence.seqno;
448
449 *cs++ = MI_USER_INTERRUPT;
450
451 rq->tail = intel_ring_offset(rq, cs);
452 assert_ring_tail_valid(rq->ring, rq->tail);
453
454 return cs;
455}
456
457#define GEN7_XCS_WA 32
458static u32 *gen7_xcs_emit_breadcrumb(struct i915_request *rq, u32 *cs)
459{
460 int i;
461
462 GEM_BUG_ON(rq->timeline->hwsp_ggtt != rq->engine->status_page.vma);
463 GEM_BUG_ON(offset_in_page(rq->timeline->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR);
464
465 *cs++ = MI_FLUSH_DW | MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_STORE_INDEX;
466 *cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT;
467 *cs++ = rq->fence.seqno;
468
469 for (i = 0; i < GEN7_XCS_WA; i++) {
470 *cs++ = MI_STORE_DWORD_INDEX;
471 *cs++ = I915_GEM_HWS_SEQNO_ADDR;
472 *cs++ = rq->fence.seqno;
473 }
474
475 *cs++ = MI_FLUSH_DW;
476 *cs++ = 0;
477 *cs++ = 0;
478
479 *cs++ = MI_USER_INTERRUPT;
480 *cs++ = MI_NOOP;
481
482 rq->tail = intel_ring_offset(rq, cs);
483 assert_ring_tail_valid(rq->ring, rq->tail);
484
485 return cs;
486}
487#undef GEN7_XCS_WA
488
489static void set_hwstam(struct intel_engine_cs *engine, u32 mask)
490{
491 /*
492 * Keep the render interrupt unmasked as this papers over
493 * lost interrupts following a reset.
494 */
495 if (engine->class == RENDER_CLASS) {
496 if (INTEL_GEN(engine->i915) >= 6)
497 mask &= ~BIT(0);
498 else
499 mask &= ~I915_USER_INTERRUPT;
500 }
501
502 intel_engine_set_hwsp_writemask(engine, mask);
503}
504
505static void set_hws_pga(struct intel_engine_cs *engine, phys_addr_t phys)
506{
507 struct drm_i915_private *dev_priv = engine->i915;
508 u32 addr;
509
510 addr = lower_32_bits(phys);
511 if (INTEL_GEN(dev_priv) >= 4)
512 addr |= (phys >> 28) & 0xf0;
513
514 I915_WRITE(HWS_PGA, addr);
515}
516
517static struct page *status_page(struct intel_engine_cs *engine)
518{
519 struct drm_i915_gem_object *obj = engine->status_page.vma->obj;
520
521 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
522 return sg_page(obj->mm.pages->sgl);
523}
524
525static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
526{
527 set_hws_pga(engine, PFN_PHYS(page_to_pfn(status_page(engine))));
528 set_hwstam(engine, ~0u);
529}
530
531static void set_hwsp(struct intel_engine_cs *engine, u32 offset)
532{
533 struct drm_i915_private *dev_priv = engine->i915;
534 i915_reg_t hwsp;
535
536 /*
537 * The ring status page addresses are no longer next to the rest of
538 * the ring registers as of gen7.
539 */
540 if (IS_GEN(dev_priv, 7)) {
541 switch (engine->id) {
542 /*
543 * No more rings exist on Gen7. Default case is only to shut up
544 * gcc switch check warning.
545 */
546 default:
547 GEM_BUG_ON(engine->id);
548 /* fallthrough */
549 case RCS0:
550 hwsp = RENDER_HWS_PGA_GEN7;
551 break;
552 case BCS0:
553 hwsp = BLT_HWS_PGA_GEN7;
554 break;
555 case VCS0:
556 hwsp = BSD_HWS_PGA_GEN7;
557 break;
558 case VECS0:
559 hwsp = VEBOX_HWS_PGA_GEN7;
560 break;
561 }
562 } else if (IS_GEN(dev_priv, 6)) {
563 hwsp = RING_HWS_PGA_GEN6(engine->mmio_base);
564 } else {
565 hwsp = RING_HWS_PGA(engine->mmio_base);
566 }
567
568 I915_WRITE(hwsp, offset);
569 POSTING_READ(hwsp);
570}
571
572static void flush_cs_tlb(struct intel_engine_cs *engine)
573{
574 struct drm_i915_private *dev_priv = engine->i915;
575
576 if (!IS_GEN_RANGE(dev_priv, 6, 7))
577 return;
578
579 /* ring should be idle before issuing a sync flush*/
580 WARN_ON((ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0);
581
582 ENGINE_WRITE(engine, RING_INSTPM,
583 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
584 INSTPM_SYNC_FLUSH));
585 if (intel_wait_for_register(engine->uncore,
586 RING_INSTPM(engine->mmio_base),
587 INSTPM_SYNC_FLUSH, 0,
588 1000))
589 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
590 engine->name);
591}
592
593static void ring_setup_status_page(struct intel_engine_cs *engine)
594{
595 set_hwsp(engine, i915_ggtt_offset(engine->status_page.vma));
596 set_hwstam(engine, ~0u);
597
598 flush_cs_tlb(engine);
599}
600
601static bool stop_ring(struct intel_engine_cs *engine)
602{
603 struct drm_i915_private *dev_priv = engine->i915;
604
605 if (INTEL_GEN(dev_priv) > 2) {
606 ENGINE_WRITE(engine,
607 RING_MI_MODE, _MASKED_BIT_ENABLE(STOP_RING));
608 if (intel_wait_for_register(engine->uncore,
609 RING_MI_MODE(engine->mmio_base),
610 MODE_IDLE,
611 MODE_IDLE,
612 1000)) {
613 DRM_ERROR("%s : timed out trying to stop ring\n",
614 engine->name);
615
616 /*
617 * Sometimes we observe that the idle flag is not
618 * set even though the ring is empty. So double
619 * check before giving up.
620 */
621 if (ENGINE_READ(engine, RING_HEAD) !=
622 ENGINE_READ(engine, RING_TAIL))
623 return false;
624 }
625 }
626
627 ENGINE_WRITE(engine, RING_HEAD, ENGINE_READ(engine, RING_TAIL));
628
629 ENGINE_WRITE(engine, RING_HEAD, 0);
630 ENGINE_WRITE(engine, RING_TAIL, 0);
631
632 /* The ring must be empty before it is disabled */
633 ENGINE_WRITE(engine, RING_CTL, 0);
634
635 return (ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR) == 0;
636}
637
638static int xcs_resume(struct intel_engine_cs *engine)
639{
640 struct drm_i915_private *dev_priv = engine->i915;
641 struct intel_ring *ring = engine->legacy.ring;
642 int ret = 0;
643
644 GEM_TRACE("%s: ring:{HEAD:%04x, TAIL:%04x}\n",
645 engine->name, ring->head, ring->tail);
646
647 intel_uncore_forcewake_get(engine->uncore, FORCEWAKE_ALL);
648
649 /* WaClearRingBufHeadRegAtInit:ctg,elk */
650 if (!stop_ring(engine)) {
651 /* G45 ring initialization often fails to reset head to zero */
652 DRM_DEBUG_DRIVER("%s head not reset to zero "
653 "ctl %08x head %08x tail %08x start %08x\n",
654 engine->name,
655 ENGINE_READ(engine, RING_CTL),
656 ENGINE_READ(engine, RING_HEAD),
657 ENGINE_READ(engine, RING_TAIL),
658 ENGINE_READ(engine, RING_START));
659
660 if (!stop_ring(engine)) {
661 DRM_ERROR("failed to set %s head to zero "
662 "ctl %08x head %08x tail %08x start %08x\n",
663 engine->name,
664 ENGINE_READ(engine, RING_CTL),
665 ENGINE_READ(engine, RING_HEAD),
666 ENGINE_READ(engine, RING_TAIL),
667 ENGINE_READ(engine, RING_START));
668 ret = -EIO;
669 goto out;
670 }
671 }
672
673 if (HWS_NEEDS_PHYSICAL(dev_priv))
674 ring_setup_phys_status_page(engine);
675 else
676 ring_setup_status_page(engine);
677
678 intel_engine_reset_breadcrumbs(engine);
679
680 /* Enforce ordering by reading HEAD register back */
681 ENGINE_POSTING_READ(engine, RING_HEAD);
682
683 /*
684 * Initialize the ring. This must happen _after_ we've cleared the ring
685 * registers with the above sequence (the readback of the HEAD registers
686 * also enforces ordering), otherwise the hw might lose the new ring
687 * register values.
688 */
689 ENGINE_WRITE(engine, RING_START, i915_ggtt_offset(ring->vma));
690
691 /* Check that the ring offsets point within the ring! */
692 GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->head));
693 GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->tail));
694 intel_ring_update_space(ring);
695
696 /* First wake the ring up to an empty/idle ring */
697 ENGINE_WRITE(engine, RING_HEAD, ring->head);
698 ENGINE_WRITE(engine, RING_TAIL, ring->head);
699 ENGINE_POSTING_READ(engine, RING_TAIL);
700
701 ENGINE_WRITE(engine, RING_CTL, RING_CTL_SIZE(ring->size) | RING_VALID);
702
703 /* If the head is still not zero, the ring is dead */
704 if (intel_wait_for_register(engine->uncore,
705 RING_CTL(engine->mmio_base),
706 RING_VALID, RING_VALID,
707 50)) {
708 DRM_ERROR("%s initialization failed "
709 "ctl %08x (valid? %d) head %08x [%08x] tail %08x [%08x] start %08x [expected %08x]\n",
710 engine->name,
711 ENGINE_READ(engine, RING_CTL),
712 ENGINE_READ(engine, RING_CTL) & RING_VALID,
713 ENGINE_READ(engine, RING_HEAD), ring->head,
714 ENGINE_READ(engine, RING_TAIL), ring->tail,
715 ENGINE_READ(engine, RING_START),
716 i915_ggtt_offset(ring->vma));
717 ret = -EIO;
718 goto out;
719 }
720
721 if (INTEL_GEN(dev_priv) > 2)
722 ENGINE_WRITE(engine,
723 RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
724
725 /* Now awake, let it get started */
726 if (ring->tail != ring->head) {
727 ENGINE_WRITE(engine, RING_TAIL, ring->tail);
728 ENGINE_POSTING_READ(engine, RING_TAIL);
729 }
730
731 /* Papering over lost _interrupts_ immediately following the restart */
732 intel_engine_queue_breadcrumbs(engine);
733out:
734 intel_uncore_forcewake_put(engine->uncore, FORCEWAKE_ALL);
735
736 return ret;
737}
738
739static void reset_prepare(struct intel_engine_cs *engine)
740{
741 struct intel_uncore *uncore = engine->uncore;
742 const u32 base = engine->mmio_base;
743
744 /*
745 * We stop engines, otherwise we might get failed reset and a
746 * dead gpu (on elk). Also as modern gpu as kbl can suffer
747 * from system hang if batchbuffer is progressing when
748 * the reset is issued, regardless of READY_TO_RESET ack.
749 * Thus assume it is best to stop engines on all gens
750 * where we have a gpu reset.
751 *
752 * WaKBLVECSSemaphoreWaitPoll:kbl (on ALL_ENGINES)
753 *
754 * WaMediaResetMainRingCleanup:ctg,elk (presumably)
755 *
756 * FIXME: Wa for more modern gens needs to be validated
757 */
758 GEM_TRACE("%s\n", engine->name);
759
760 if (intel_engine_stop_cs(engine))
761 GEM_TRACE("%s: timed out on STOP_RING\n", engine->name);
762
763 intel_uncore_write_fw(uncore,
764 RING_HEAD(base),
765 intel_uncore_read_fw(uncore, RING_TAIL(base)));
766 intel_uncore_posting_read_fw(uncore, RING_HEAD(base)); /* paranoia */
767
768 intel_uncore_write_fw(uncore, RING_HEAD(base), 0);
769 intel_uncore_write_fw(uncore, RING_TAIL(base), 0);
770 intel_uncore_posting_read_fw(uncore, RING_TAIL(base));
771
772 /* The ring must be empty before it is disabled */
773 intel_uncore_write_fw(uncore, RING_CTL(base), 0);
774
775 /* Check acts as a post */
776 if (intel_uncore_read_fw(uncore, RING_HEAD(base)))
777 GEM_TRACE("%s: ring head [%x] not parked\n",
778 engine->name,
779 intel_uncore_read_fw(uncore, RING_HEAD(base)));
780}
781
782static void reset_ring(struct intel_engine_cs *engine, bool stalled)
783{
784 struct i915_request *pos, *rq;
785 unsigned long flags;
786 u32 head;
787
788 rq = NULL;
789 spin_lock_irqsave(&engine->active.lock, flags);
790 list_for_each_entry(pos, &engine->active.requests, sched.link) {
791 if (!i915_request_completed(pos)) {
792 rq = pos;
793 break;
794 }
795 }
796
797 /*
798 * The guilty request will get skipped on a hung engine.
799 *
800 * Users of client default contexts do not rely on logical
801 * state preserved between batches so it is safe to execute
802 * queued requests following the hang. Non default contexts
803 * rely on preserved state, so skipping a batch loses the
804 * evolution of the state and it needs to be considered corrupted.
805 * Executing more queued batches on top of corrupted state is
806 * risky. But we take the risk by trying to advance through
807 * the queued requests in order to make the client behaviour
808 * more predictable around resets, by not throwing away random
809 * amount of batches it has prepared for execution. Sophisticated
810 * clients can use gem_reset_stats_ioctl and dma fence status
811 * (exported via sync_file info ioctl on explicit fences) to observe
812 * when it loses the context state and should rebuild accordingly.
813 *
814 * The context ban, and ultimately the client ban, mechanism are safety
815 * valves if client submission ends up resulting in nothing more than
816 * subsequent hangs.
817 */
818
819 if (rq) {
820 /*
821 * Try to restore the logical GPU state to match the
822 * continuation of the request queue. If we skip the
823 * context/PD restore, then the next request may try to execute
824 * assuming that its context is valid and loaded on the GPU and
825 * so may try to access invalid memory, prompting repeated GPU
826 * hangs.
827 *
828 * If the request was guilty, we still restore the logical
829 * state in case the next request requires it (e.g. the
830 * aliasing ppgtt), but skip over the hung batch.
831 *
832 * If the request was innocent, we try to replay the request
833 * with the restored context.
834 */
835 __i915_request_reset(rq, stalled);
836
837 GEM_BUG_ON(rq->ring != engine->legacy.ring);
838 head = rq->head;
839 } else {
840 head = engine->legacy.ring->tail;
841 }
842 engine->legacy.ring->head = intel_ring_wrap(engine->legacy.ring, head);
843
844 spin_unlock_irqrestore(&engine->active.lock, flags);
845}
846
847static void reset_finish(struct intel_engine_cs *engine)
848{
849}
850
851static int rcs_resume(struct intel_engine_cs *engine)
852{
853 struct drm_i915_private *dev_priv = engine->i915;
854
855 /*
856 * Disable CONSTANT_BUFFER before it is loaded from the context
857 * image. For as it is loaded, it is executed and the stored
858 * address may no longer be valid, leading to a GPU hang.
859 *
860 * This imposes the requirement that userspace reload their
861 * CONSTANT_BUFFER on every batch, fortunately a requirement
862 * they are already accustomed to from before contexts were
863 * enabled.
864 */
865 if (IS_GEN(dev_priv, 4))
866 I915_WRITE(ECOSKPD,
867 _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE));
868
869 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
870 if (IS_GEN_RANGE(dev_priv, 4, 6))
871 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
872
873 /* We need to disable the AsyncFlip performance optimisations in order
874 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
875 * programmed to '1' on all products.
876 *
877 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
878 */
879 if (IS_GEN_RANGE(dev_priv, 6, 7))
880 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
881
882 /* Required for the hardware to program scanline values for waiting */
883 /* WaEnableFlushTlbInvalidationMode:snb */
884 if (IS_GEN(dev_priv, 6))
885 I915_WRITE(GFX_MODE,
886 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
887
888 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
889 if (IS_GEN(dev_priv, 7))
890 I915_WRITE(GFX_MODE_GEN7,
891 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
892 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
893
894 if (IS_GEN(dev_priv, 6)) {
895 /* From the Sandybridge PRM, volume 1 part 3, page 24:
896 * "If this bit is set, STCunit will have LRA as replacement
897 * policy. [...] This bit must be reset. LRA replacement
898 * policy is not supported."
899 */
900 I915_WRITE(CACHE_MODE_0,
901 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
902 }
903
904 if (IS_GEN_RANGE(dev_priv, 6, 7))
905 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
906
907 return xcs_resume(engine);
908}
909
910static void cancel_requests(struct intel_engine_cs *engine)
911{
912 struct i915_request *request;
913 unsigned long flags;
914
915 spin_lock_irqsave(&engine->active.lock, flags);
916
917 /* Mark all submitted requests as skipped. */
918 list_for_each_entry(request, &engine->active.requests, sched.link) {
919 if (!i915_request_signaled(request))
920 dma_fence_set_error(&request->fence, -EIO);
921
922 i915_request_mark_complete(request);
923 }
924
925 /* Remaining _unready_ requests will be nop'ed when submitted */
926
927 spin_unlock_irqrestore(&engine->active.lock, flags);
928}
929
930static void i9xx_submit_request(struct i915_request *request)
931{
932 i915_request_submit(request);
933
934 ENGINE_WRITE(request->engine, RING_TAIL,
935 intel_ring_set_tail(request->ring, request->tail));
936}
937
938static u32 *i9xx_emit_breadcrumb(struct i915_request *rq, u32 *cs)
939{
940 GEM_BUG_ON(rq->timeline->hwsp_ggtt != rq->engine->status_page.vma);
941 GEM_BUG_ON(offset_in_page(rq->timeline->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR);
942
943 *cs++ = MI_FLUSH;
944
945 *cs++ = MI_STORE_DWORD_INDEX;
946 *cs++ = I915_GEM_HWS_SEQNO_ADDR;
947 *cs++ = rq->fence.seqno;
948
949 *cs++ = MI_USER_INTERRUPT;
950 *cs++ = MI_NOOP;
951
952 rq->tail = intel_ring_offset(rq, cs);
953 assert_ring_tail_valid(rq->ring, rq->tail);
954
955 return cs;
956}
957
958#define GEN5_WA_STORES 8 /* must be at least 1! */
959static u32 *gen5_emit_breadcrumb(struct i915_request *rq, u32 *cs)
960{
961 int i;
962
963 GEM_BUG_ON(rq->timeline->hwsp_ggtt != rq->engine->status_page.vma);
964 GEM_BUG_ON(offset_in_page(rq->timeline->hwsp_offset) != I915_GEM_HWS_SEQNO_ADDR);
965
966 *cs++ = MI_FLUSH;
967
968 BUILD_BUG_ON(GEN5_WA_STORES < 1);
969 for (i = 0; i < GEN5_WA_STORES; i++) {
970 *cs++ = MI_STORE_DWORD_INDEX;
971 *cs++ = I915_GEM_HWS_SEQNO_ADDR;
972 *cs++ = rq->fence.seqno;
973 }
974
975 *cs++ = MI_USER_INTERRUPT;
976
977 rq->tail = intel_ring_offset(rq, cs);
978 assert_ring_tail_valid(rq->ring, rq->tail);
979
980 return cs;
981}
982#undef GEN5_WA_STORES
983
984static void
985gen5_irq_enable(struct intel_engine_cs *engine)
986{
987 gen5_gt_enable_irq(engine->gt, engine->irq_enable_mask);
988}
989
990static void
991gen5_irq_disable(struct intel_engine_cs *engine)
992{
993 gen5_gt_disable_irq(engine->gt, engine->irq_enable_mask);
994}
995
996static void
997i9xx_irq_enable(struct intel_engine_cs *engine)
998{
999 engine->i915->irq_mask &= ~engine->irq_enable_mask;
1000 intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->irq_mask);
1001 intel_uncore_posting_read_fw(engine->uncore, GEN2_IMR);
1002}
1003
1004static void
1005i9xx_irq_disable(struct intel_engine_cs *engine)
1006{
1007 engine->i915->irq_mask |= engine->irq_enable_mask;
1008 intel_uncore_write(engine->uncore, GEN2_IMR, engine->i915->irq_mask);
1009}
1010
1011static void
1012i8xx_irq_enable(struct intel_engine_cs *engine)
1013{
1014 struct drm_i915_private *i915 = engine->i915;
1015
1016 i915->irq_mask &= ~engine->irq_enable_mask;
1017 intel_uncore_write16(&i915->uncore, GEN2_IMR, i915->irq_mask);
1018 ENGINE_POSTING_READ16(engine, RING_IMR);
1019}
1020
1021static void
1022i8xx_irq_disable(struct intel_engine_cs *engine)
1023{
1024 struct drm_i915_private *i915 = engine->i915;
1025
1026 i915->irq_mask |= engine->irq_enable_mask;
1027 intel_uncore_write16(&i915->uncore, GEN2_IMR, i915->irq_mask);
1028}
1029
1030static int
1031bsd_ring_flush(struct i915_request *rq, u32 mode)
1032{
1033 u32 *cs;
1034
1035 cs = intel_ring_begin(rq, 2);
1036 if (IS_ERR(cs))
1037 return PTR_ERR(cs);
1038
1039 *cs++ = MI_FLUSH;
1040 *cs++ = MI_NOOP;
1041 intel_ring_advance(rq, cs);
1042 return 0;
1043}
1044
1045static void
1046gen6_irq_enable(struct intel_engine_cs *engine)
1047{
1048 ENGINE_WRITE(engine, RING_IMR,
1049 ~(engine->irq_enable_mask | engine->irq_keep_mask));
1050
1051 /* Flush/delay to ensure the RING_IMR is active before the GT IMR */
1052 ENGINE_POSTING_READ(engine, RING_IMR);
1053
1054 gen5_gt_enable_irq(engine->gt, engine->irq_enable_mask);
1055}
1056
1057static void
1058gen6_irq_disable(struct intel_engine_cs *engine)
1059{
1060 ENGINE_WRITE(engine, RING_IMR, ~engine->irq_keep_mask);
1061 gen5_gt_disable_irq(engine->gt, engine->irq_enable_mask);
1062}
1063
1064static void
1065hsw_vebox_irq_enable(struct intel_engine_cs *engine)
1066{
1067 ENGINE_WRITE(engine, RING_IMR, ~engine->irq_enable_mask);
1068
1069 /* Flush/delay to ensure the RING_IMR is active before the GT IMR */
1070 ENGINE_POSTING_READ(engine, RING_IMR);
1071
1072 gen6_gt_pm_unmask_irq(engine->gt, engine->irq_enable_mask);
1073}
1074
1075static void
1076hsw_vebox_irq_disable(struct intel_engine_cs *engine)
1077{
1078 ENGINE_WRITE(engine, RING_IMR, ~0);
1079 gen6_gt_pm_mask_irq(engine->gt, engine->irq_enable_mask);
1080}
1081
1082static int
1083i965_emit_bb_start(struct i915_request *rq,
1084 u64 offset, u32 length,
1085 unsigned int dispatch_flags)
1086{
1087 u32 *cs;
1088
1089 cs = intel_ring_begin(rq, 2);
1090 if (IS_ERR(cs))
1091 return PTR_ERR(cs);
1092
1093 *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT | (dispatch_flags &
1094 I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965);
1095 *cs++ = offset;
1096 intel_ring_advance(rq, cs);
1097
1098 return 0;
1099}
1100
1101/* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1102#define I830_BATCH_LIMIT SZ_256K
1103#define I830_TLB_ENTRIES (2)
1104#define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
1105static int
1106i830_emit_bb_start(struct i915_request *rq,
1107 u64 offset, u32 len,
1108 unsigned int dispatch_flags)
1109{
1110 u32 *cs, cs_offset =
1111 intel_gt_scratch_offset(rq->engine->gt,
1112 INTEL_GT_SCRATCH_FIELD_DEFAULT);
1113
1114 GEM_BUG_ON(rq->engine->gt->scratch->size < I830_WA_SIZE);
1115
1116 cs = intel_ring_begin(rq, 6);
1117 if (IS_ERR(cs))
1118 return PTR_ERR(cs);
1119
1120 /* Evict the invalid PTE TLBs */
1121 *cs++ = COLOR_BLT_CMD | BLT_WRITE_RGBA;
1122 *cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096;
1123 *cs++ = I830_TLB_ENTRIES << 16 | 4; /* load each page */
1124 *cs++ = cs_offset;
1125 *cs++ = 0xdeadbeef;
1126 *cs++ = MI_NOOP;
1127 intel_ring_advance(rq, cs);
1128
1129 if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
1130 if (len > I830_BATCH_LIMIT)
1131 return -ENOSPC;
1132
1133 cs = intel_ring_begin(rq, 6 + 2);
1134 if (IS_ERR(cs))
1135 return PTR_ERR(cs);
1136
1137 /* Blit the batch (which has now all relocs applied) to the
1138 * stable batch scratch bo area (so that the CS never
1139 * stumbles over its tlb invalidation bug) ...
1140 */
1141 *cs++ = SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (6 - 2);
1142 *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096;
1143 *cs++ = DIV_ROUND_UP(len, 4096) << 16 | 4096;
1144 *cs++ = cs_offset;
1145 *cs++ = 4096;
1146 *cs++ = offset;
1147
1148 *cs++ = MI_FLUSH;
1149 *cs++ = MI_NOOP;
1150 intel_ring_advance(rq, cs);
1151
1152 /* ... and execute it. */
1153 offset = cs_offset;
1154 }
1155
1156 cs = intel_ring_begin(rq, 2);
1157 if (IS_ERR(cs))
1158 return PTR_ERR(cs);
1159
1160 *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
1161 *cs++ = offset | (dispatch_flags & I915_DISPATCH_SECURE ? 0 :
1162 MI_BATCH_NON_SECURE);
1163 intel_ring_advance(rq, cs);
1164
1165 return 0;
1166}
1167
1168static int
1169i915_emit_bb_start(struct i915_request *rq,
1170 u64 offset, u32 len,
1171 unsigned int dispatch_flags)
1172{
1173 u32 *cs;
1174
1175 cs = intel_ring_begin(rq, 2);
1176 if (IS_ERR(cs))
1177 return PTR_ERR(cs);
1178
1179 *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
1180 *cs++ = offset | (dispatch_flags & I915_DISPATCH_SECURE ? 0 :
1181 MI_BATCH_NON_SECURE);
1182 intel_ring_advance(rq, cs);
1183
1184 return 0;
1185}
1186
1187int intel_ring_pin(struct intel_ring *ring)
1188{
1189 struct i915_vma *vma = ring->vma;
1190 unsigned int flags;
1191 void *addr;
1192 int ret;
1193
1194 if (atomic_fetch_inc(&ring->pin_count))
1195 return 0;
1196
1197 flags = PIN_GLOBAL;
1198
1199 /* Ring wraparound at offset 0 sometimes hangs. No idea why. */
1200 flags |= PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma);
1201
1202 if (vma->obj->stolen)
1203 flags |= PIN_MAPPABLE;
1204 else
1205 flags |= PIN_HIGH;
1206
1207 ret = i915_vma_pin(vma, 0, 0, flags);
1208 if (unlikely(ret))
1209 goto err_unpin;
1210
1211 if (i915_vma_is_map_and_fenceable(vma))
1212 addr = (void __force *)i915_vma_pin_iomap(vma);
1213 else
1214 addr = i915_gem_object_pin_map(vma->obj,
1215 i915_coherent_map_type(vma->vm->i915));
1216 if (IS_ERR(addr)) {
1217 ret = PTR_ERR(addr);
1218 goto err_ring;
1219 }
1220
1221 i915_vma_make_unshrinkable(vma);
1222
1223 GEM_BUG_ON(ring->vaddr);
1224 ring->vaddr = addr;
1225
1226 return 0;
1227
1228err_ring:
1229 i915_vma_unpin(vma);
1230err_unpin:
1231 atomic_dec(&ring->pin_count);
1232 return ret;
1233}
1234
1235void intel_ring_reset(struct intel_ring *ring, u32 tail)
1236{
1237 tail = intel_ring_wrap(ring, tail);
1238 ring->tail = tail;
1239 ring->head = tail;
1240 ring->emit = tail;
1241 intel_ring_update_space(ring);
1242}
1243
1244void intel_ring_unpin(struct intel_ring *ring)
1245{
1246 struct i915_vma *vma = ring->vma;
1247
1248 if (!atomic_dec_and_test(&ring->pin_count))
1249 return;
1250
1251 /* Discard any unused bytes beyond that submitted to hw. */
1252 intel_ring_reset(ring, ring->emit);
1253
1254 i915_vma_unset_ggtt_write(vma);
1255 if (i915_vma_is_map_and_fenceable(vma))
1256 i915_vma_unpin_iomap(vma);
1257 else
1258 i915_gem_object_unpin_map(vma->obj);
1259
1260 GEM_BUG_ON(!ring->vaddr);
1261 ring->vaddr = NULL;
1262
1263 i915_vma_unpin(vma);
1264 i915_vma_make_purgeable(vma);
1265}
1266
1267static struct i915_vma *create_ring_vma(struct i915_ggtt *ggtt, int size)
1268{
1269 struct i915_address_space *vm = &ggtt->vm;
1270 struct drm_i915_private *i915 = vm->i915;
1271 struct drm_i915_gem_object *obj;
1272 struct i915_vma *vma;
1273
1274 obj = i915_gem_object_create_stolen(i915, size);
1275 if (!obj)
1276 obj = i915_gem_object_create_internal(i915, size);
1277 if (IS_ERR(obj))
1278 return ERR_CAST(obj);
1279
1280 /*
1281 * Mark ring buffers as read-only from GPU side (so no stray overwrites)
1282 * if supported by the platform's GGTT.
1283 */
1284 if (vm->has_read_only)
1285 i915_gem_object_set_readonly(obj);
1286
1287 vma = i915_vma_instance(obj, vm, NULL);
1288 if (IS_ERR(vma))
1289 goto err;
1290
1291 return vma;
1292
1293err:
1294 i915_gem_object_put(obj);
1295 return vma;
1296}
1297
1298struct intel_ring *
1299intel_engine_create_ring(struct intel_engine_cs *engine, int size)
1300{
1301 struct drm_i915_private *i915 = engine->i915;
1302 struct intel_ring *ring;
1303 struct i915_vma *vma;
1304
1305 GEM_BUG_ON(!is_power_of_2(size));
1306 GEM_BUG_ON(RING_CTL_SIZE(size) & ~RING_NR_PAGES);
1307
1308 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
1309 if (!ring)
1310 return ERR_PTR(-ENOMEM);
1311
1312 kref_init(&ring->ref);
1313
1314 ring->size = size;
1315 /* Workaround an erratum on the i830 which causes a hang if
1316 * the TAIL pointer points to within the last 2 cachelines
1317 * of the buffer.
1318 */
1319 ring->effective_size = size;
1320 if (IS_I830(i915) || IS_I845G(i915))
1321 ring->effective_size -= 2 * CACHELINE_BYTES;
1322
1323 intel_ring_update_space(ring);
1324
1325 vma = create_ring_vma(engine->gt->ggtt, size);
1326 if (IS_ERR(vma)) {
1327 kfree(ring);
1328 return ERR_CAST(vma);
1329 }
1330 ring->vma = vma;
1331
1332 return ring;
1333}
1334
1335void intel_ring_free(struct kref *ref)
1336{
1337 struct intel_ring *ring = container_of(ref, typeof(*ring), ref);
1338
1339 i915_vma_close(ring->vma);
1340 i915_vma_put(ring->vma);
1341
1342 kfree(ring);
1343}
1344
1345static void __ring_context_fini(struct intel_context *ce)
1346{
1347 i915_gem_object_put(ce->state->obj);
1348}
1349
1350static void ring_context_destroy(struct kref *ref)
1351{
1352 struct intel_context *ce = container_of(ref, typeof(*ce), ref);
1353
1354 GEM_BUG_ON(intel_context_is_pinned(ce));
1355
1356 if (ce->state)
1357 __ring_context_fini(ce);
1358
1359 intel_context_fini(ce);
1360 intel_context_free(ce);
1361}
1362
1363static struct i915_address_space *vm_alias(struct intel_context *ce)
1364{
1365 struct i915_address_space *vm;
1366
1367 vm = ce->vm;
1368 if (i915_is_ggtt(vm))
1369 vm = &i915_vm_to_ggtt(vm)->alias->vm;
1370
1371 return vm;
1372}
1373
1374static int __context_pin_ppgtt(struct intel_context *ce)
1375{
1376 struct i915_address_space *vm;
1377 int err = 0;
1378
1379 vm = vm_alias(ce);
1380 if (vm)
1381 err = gen6_ppgtt_pin(i915_vm_to_ppgtt((vm)));
1382
1383 return err;
1384}
1385
1386static void __context_unpin_ppgtt(struct intel_context *ce)
1387{
1388 struct i915_address_space *vm;
1389
1390 vm = vm_alias(ce);
1391 if (vm)
1392 gen6_ppgtt_unpin(i915_vm_to_ppgtt(vm));
1393}
1394
1395static void ring_context_unpin(struct intel_context *ce)
1396{
1397 __context_unpin_ppgtt(ce);
1398}
1399
1400static struct i915_vma *
1401alloc_context_vma(struct intel_engine_cs *engine)
1402{
1403 struct drm_i915_private *i915 = engine->i915;
1404 struct drm_i915_gem_object *obj;
1405 struct i915_vma *vma;
1406 int err;
1407
1408 obj = i915_gem_object_create_shmem(i915, engine->context_size);
1409 if (IS_ERR(obj))
1410 return ERR_CAST(obj);
1411
1412 /*
1413 * Try to make the context utilize L3 as well as LLC.
1414 *
1415 * On VLV we don't have L3 controls in the PTEs so we
1416 * shouldn't touch the cache level, especially as that
1417 * would make the object snooped which might have a
1418 * negative performance impact.
1419 *
1420 * Snooping is required on non-llc platforms in execlist
1421 * mode, but since all GGTT accesses use PAT entry 0 we
1422 * get snooping anyway regardless of cache_level.
1423 *
1424 * This is only applicable for Ivy Bridge devices since
1425 * later platforms don't have L3 control bits in the PTE.
1426 */
1427 if (IS_IVYBRIDGE(i915))
1428 i915_gem_object_set_cache_coherency(obj, I915_CACHE_L3_LLC);
1429
1430 if (engine->default_state) {
1431 void *defaults, *vaddr;
1432
1433 vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
1434 if (IS_ERR(vaddr)) {
1435 err = PTR_ERR(vaddr);
1436 goto err_obj;
1437 }
1438
1439 defaults = i915_gem_object_pin_map(engine->default_state,
1440 I915_MAP_WB);
1441 if (IS_ERR(defaults)) {
1442 err = PTR_ERR(defaults);
1443 goto err_map;
1444 }
1445
1446 memcpy(vaddr, defaults, engine->context_size);
1447 i915_gem_object_unpin_map(engine->default_state);
1448
1449 i915_gem_object_flush_map(obj);
1450 i915_gem_object_unpin_map(obj);
1451 }
1452
1453 vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);
1454 if (IS_ERR(vma)) {
1455 err = PTR_ERR(vma);
1456 goto err_obj;
1457 }
1458
1459 return vma;
1460
1461err_map:
1462 i915_gem_object_unpin_map(obj);
1463err_obj:
1464 i915_gem_object_put(obj);
1465 return ERR_PTR(err);
1466}
1467
1468static int ring_context_alloc(struct intel_context *ce)
1469{
1470 struct intel_engine_cs *engine = ce->engine;
1471
1472 /* One ringbuffer to rule them all */
1473 GEM_BUG_ON(!engine->legacy.ring);
1474 ce->ring = engine->legacy.ring;
1475 ce->timeline = intel_timeline_get(engine->legacy.timeline);
1476
1477 GEM_BUG_ON(ce->state);
1478 if (engine->context_size) {
1479 struct i915_vma *vma;
1480
1481 vma = alloc_context_vma(engine);
1482 if (IS_ERR(vma))
1483 return PTR_ERR(vma);
1484
1485 ce->state = vma;
1486 }
1487
1488 return 0;
1489}
1490
1491static int ring_context_pin(struct intel_context *ce)
1492{
1493 int err;
1494
1495 err = intel_context_active_acquire(ce);
1496 if (err)
1497 return err;
1498
1499 err = __context_pin_ppgtt(ce);
1500 if (err)
1501 goto err_active;
1502
1503 return 0;
1504
1505err_active:
1506 intel_context_active_release(ce);
1507 return err;
1508}
1509
1510static void ring_context_reset(struct intel_context *ce)
1511{
1512 intel_ring_reset(ce->ring, 0);
1513}
1514
1515static const struct intel_context_ops ring_context_ops = {
1516 .alloc = ring_context_alloc,
1517
1518 .pin = ring_context_pin,
1519 .unpin = ring_context_unpin,
1520
1521 .enter = intel_context_enter_engine,
1522 .exit = intel_context_exit_engine,
1523
1524 .reset = ring_context_reset,
1525 .destroy = ring_context_destroy,
1526};
1527
1528static int load_pd_dir(struct i915_request *rq, const struct i915_ppgtt *ppgtt)
1529{
1530 const struct intel_engine_cs * const engine = rq->engine;
1531 u32 *cs;
1532
1533 cs = intel_ring_begin(rq, 6);
1534 if (IS_ERR(cs))
1535 return PTR_ERR(cs);
1536
1537 *cs++ = MI_LOAD_REGISTER_IMM(1);
1538 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine->mmio_base));
1539 *cs++ = PP_DIR_DCLV_2G;
1540
1541 *cs++ = MI_LOAD_REGISTER_IMM(1);
1542 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));
1543 *cs++ = px_base(ppgtt->pd)->ggtt_offset << 10;
1544
1545 intel_ring_advance(rq, cs);
1546
1547 return 0;
1548}
1549
1550static int flush_pd_dir(struct i915_request *rq)
1551{
1552 const struct intel_engine_cs * const engine = rq->engine;
1553 u32 *cs;
1554
1555 cs = intel_ring_begin(rq, 4);
1556 if (IS_ERR(cs))
1557 return PTR_ERR(cs);
1558
1559 /* Stall until the page table load is complete */
1560 *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
1561 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));
1562 *cs++ = intel_gt_scratch_offset(rq->engine->gt,
1563 INTEL_GT_SCRATCH_FIELD_DEFAULT);
1564 *cs++ = MI_NOOP;
1565
1566 intel_ring_advance(rq, cs);
1567 return 0;
1568}
1569
1570static inline int mi_set_context(struct i915_request *rq, u32 flags)
1571{
1572 struct drm_i915_private *i915 = rq->i915;
1573 struct intel_engine_cs *engine = rq->engine;
1574 enum intel_engine_id id;
1575 const int num_engines =
1576 IS_HASWELL(i915) ? RUNTIME_INFO(i915)->num_engines - 1 : 0;
1577 bool force_restore = false;
1578 int len;
1579 u32 *cs;
1580
1581 flags |= MI_MM_SPACE_GTT;
1582 if (IS_HASWELL(i915))
1583 /* These flags are for resource streamer on HSW+ */
1584 flags |= HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN;
1585 else
1586 /* We need to save the extended state for powersaving modes */
1587 flags |= MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN;
1588
1589 len = 4;
1590 if (IS_GEN(i915, 7))
1591 len += 2 + (num_engines ? 4 * num_engines + 6 : 0);
1592 else if (IS_GEN(i915, 5))
1593 len += 2;
1594 if (flags & MI_FORCE_RESTORE) {
1595 GEM_BUG_ON(flags & MI_RESTORE_INHIBIT);
1596 flags &= ~MI_FORCE_RESTORE;
1597 force_restore = true;
1598 len += 2;
1599 }
1600
1601 cs = intel_ring_begin(rq, len);
1602 if (IS_ERR(cs))
1603 return PTR_ERR(cs);
1604
1605 /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
1606 if (IS_GEN(i915, 7)) {
1607 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
1608 if (num_engines) {
1609 struct intel_engine_cs *signaller;
1610
1611 *cs++ = MI_LOAD_REGISTER_IMM(num_engines);
1612 for_each_engine(signaller, i915, id) {
1613 if (signaller == engine)
1614 continue;
1615
1616 *cs++ = i915_mmio_reg_offset(
1617 RING_PSMI_CTL(signaller->mmio_base));
1618 *cs++ = _MASKED_BIT_ENABLE(
1619 GEN6_PSMI_SLEEP_MSG_DISABLE);
1620 }
1621 }
1622 } else if (IS_GEN(i915, 5)) {
1623 /*
1624 * This w/a is only listed for pre-production ilk a/b steppings,
1625 * but is also mentioned for programming the powerctx. To be
1626 * safe, just apply the workaround; we do not use SyncFlush so
1627 * this should never take effect and so be a no-op!
1628 */
1629 *cs++ = MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN;
1630 }
1631
1632 if (force_restore) {
1633 /*
1634 * The HW doesn't handle being told to restore the current
1635 * context very well. Quite often it likes goes to go off and
1636 * sulk, especially when it is meant to be reloading PP_DIR.
1637 * A very simple fix to force the reload is to simply switch
1638 * away from the current context and back again.
1639 *
1640 * Note that the kernel_context will contain random state
1641 * following the INHIBIT_RESTORE. We accept this since we
1642 * never use the kernel_context state; it is merely a
1643 * placeholder we use to flush other contexts.
1644 */
1645 *cs++ = MI_SET_CONTEXT;
1646 *cs++ = i915_ggtt_offset(engine->kernel_context->state) |
1647 MI_MM_SPACE_GTT |
1648 MI_RESTORE_INHIBIT;
1649 }
1650
1651 *cs++ = MI_NOOP;
1652 *cs++ = MI_SET_CONTEXT;
1653 *cs++ = i915_ggtt_offset(rq->hw_context->state) | flags;
1654 /*
1655 * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
1656 * WaMiSetContext_Hang:snb,ivb,vlv
1657 */
1658 *cs++ = MI_NOOP;
1659
1660 if (IS_GEN(i915, 7)) {
1661 if (num_engines) {
1662 struct intel_engine_cs *signaller;
1663 i915_reg_t last_reg = {}; /* keep gcc quiet */
1664
1665 *cs++ = MI_LOAD_REGISTER_IMM(num_engines);
1666 for_each_engine(signaller, i915, id) {
1667 if (signaller == engine)
1668 continue;
1669
1670 last_reg = RING_PSMI_CTL(signaller->mmio_base);
1671 *cs++ = i915_mmio_reg_offset(last_reg);
1672 *cs++ = _MASKED_BIT_DISABLE(
1673 GEN6_PSMI_SLEEP_MSG_DISABLE);
1674 }
1675
1676 /* Insert a delay before the next switch! */
1677 *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
1678 *cs++ = i915_mmio_reg_offset(last_reg);
1679 *cs++ = intel_gt_scratch_offset(rq->engine->gt,
1680 INTEL_GT_SCRATCH_FIELD_DEFAULT);
1681 *cs++ = MI_NOOP;
1682 }
1683 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
1684 } else if (IS_GEN(i915, 5)) {
1685 *cs++ = MI_SUSPEND_FLUSH;
1686 }
1687
1688 intel_ring_advance(rq, cs);
1689
1690 return 0;
1691}
1692
1693static int remap_l3_slice(struct i915_request *rq, int slice)
1694{
1695 u32 *cs, *remap_info = rq->i915->l3_parity.remap_info[slice];
1696 int i;
1697
1698 if (!remap_info)
1699 return 0;
1700
1701 cs = intel_ring_begin(rq, GEN7_L3LOG_SIZE/4 * 2 + 2);
1702 if (IS_ERR(cs))
1703 return PTR_ERR(cs);
1704
1705 /*
1706 * Note: We do not worry about the concurrent register cacheline hang
1707 * here because no other code should access these registers other than
1708 * at initialization time.
1709 */
1710 *cs++ = MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4);
1711 for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) {
1712 *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i));
1713 *cs++ = remap_info[i];
1714 }
1715 *cs++ = MI_NOOP;
1716 intel_ring_advance(rq, cs);
1717
1718 return 0;
1719}
1720
1721static int remap_l3(struct i915_request *rq)
1722{
1723 struct i915_gem_context *ctx = rq->gem_context;
1724 int i, err;
1725
1726 if (!ctx->remap_slice)
1727 return 0;
1728
1729 for (i = 0; i < MAX_L3_SLICES; i++) {
1730 if (!(ctx->remap_slice & BIT(i)))
1731 continue;
1732
1733 err = remap_l3_slice(rq, i);
1734 if (err)
1735 return err;
1736 }
1737
1738 ctx->remap_slice = 0;
1739 return 0;
1740}
1741
1742static int switch_context(struct i915_request *rq)
1743{
1744 struct intel_engine_cs *engine = rq->engine;
1745 struct i915_address_space *vm = vm_alias(rq->hw_context);
1746 unsigned int unwind_mm = 0;
1747 u32 hw_flags = 0;
1748 int ret;
1749
1750 GEM_BUG_ON(HAS_EXECLISTS(rq->i915));
1751
1752 if (vm) {
1753 struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
1754 int loops;
1755
1756 /*
1757 * Baytail takes a little more convincing that it really needs
1758 * to reload the PD between contexts. It is not just a little
1759 * longer, as adding more stalls after the load_pd_dir (i.e.
1760 * adding a long loop around flush_pd_dir) is not as effective
1761 * as reloading the PD umpteen times. 32 is derived from
1762 * experimentation (gem_exec_parallel/fds) and has no good
1763 * explanation.
1764 */
1765 loops = 1;
1766 if (engine->id == BCS0 && IS_VALLEYVIEW(engine->i915))
1767 loops = 32;
1768
1769 do {
1770 ret = load_pd_dir(rq, ppgtt);
1771 if (ret)
1772 goto err;
1773 } while (--loops);
1774
1775 if (ppgtt->pd_dirty_engines & engine->mask) {
1776 unwind_mm = engine->mask;
1777 ppgtt->pd_dirty_engines &= ~unwind_mm;
1778 hw_flags = MI_FORCE_RESTORE;
1779 }
1780 }
1781
1782 if (rq->hw_context->state) {
1783 GEM_BUG_ON(engine->id != RCS0);
1784
1785 /*
1786 * The kernel context(s) is treated as pure scratch and is not
1787 * expected to retain any state (as we sacrifice it during
1788 * suspend and on resume it may be corrupted). This is ok,
1789 * as nothing actually executes using the kernel context; it
1790 * is purely used for flushing user contexts.
1791 */
1792 if (i915_gem_context_is_kernel(rq->gem_context))
1793 hw_flags = MI_RESTORE_INHIBIT;
1794
1795 ret = mi_set_context(rq, hw_flags);
1796 if (ret)
1797 goto err_mm;
1798 }
1799
1800 if (vm) {
1801 ret = engine->emit_flush(rq, EMIT_INVALIDATE);
1802 if (ret)
1803 goto err_mm;
1804
1805 ret = flush_pd_dir(rq);
1806 if (ret)
1807 goto err_mm;
1808
1809 /*
1810 * Not only do we need a full barrier (post-sync write) after
1811 * invalidating the TLBs, but we need to wait a little bit
1812 * longer. Whether this is merely delaying us, or the
1813 * subsequent flush is a key part of serialising with the
1814 * post-sync op, this extra pass appears vital before a
1815 * mm switch!
1816 */
1817 ret = engine->emit_flush(rq, EMIT_INVALIDATE);
1818 if (ret)
1819 goto err_mm;
1820
1821 ret = engine->emit_flush(rq, EMIT_FLUSH);
1822 if (ret)
1823 goto err_mm;
1824 }
1825
1826 ret = remap_l3(rq);
1827 if (ret)
1828 goto err_mm;
1829
1830 return 0;
1831
1832err_mm:
1833 if (unwind_mm)
1834 i915_vm_to_ppgtt(vm)->pd_dirty_engines |= unwind_mm;
1835err:
1836 return ret;
1837}
1838
1839static int ring_request_alloc(struct i915_request *request)
1840{
1841 int ret;
1842
1843 GEM_BUG_ON(!intel_context_is_pinned(request->hw_context));
1844 GEM_BUG_ON(request->timeline->has_initial_breadcrumb);
1845
1846 /*
1847 * Flush enough space to reduce the likelihood of waiting after
1848 * we start building the request - in which case we will just
1849 * have to repeat work.
1850 */
1851 request->reserved_space += LEGACY_REQUEST_SIZE;
1852
1853 /* Unconditionally invalidate GPU caches and TLBs. */
1854 ret = request->engine->emit_flush(request, EMIT_INVALIDATE);
1855 if (ret)
1856 return ret;
1857
1858 ret = switch_context(request);
1859 if (ret)
1860 return ret;
1861
1862 request->reserved_space -= LEGACY_REQUEST_SIZE;
1863 return 0;
1864}
1865
1866static noinline int
1867wait_for_space(struct intel_ring *ring,
1868 struct intel_timeline *tl,
1869 unsigned int bytes)
1870{
1871 struct i915_request *target;
1872 long timeout;
1873
1874 if (intel_ring_update_space(ring) >= bytes)
1875 return 0;
1876
1877 GEM_BUG_ON(list_empty(&tl->requests));
1878 list_for_each_entry(target, &tl->requests, link) {
1879 if (target->ring != ring)
1880 continue;
1881
1882 /* Would completion of this request free enough space? */
1883 if (bytes <= __intel_ring_space(target->postfix,
1884 ring->emit, ring->size))
1885 break;
1886 }
1887
1888 if (GEM_WARN_ON(&target->link == &tl->requests))
1889 return -ENOSPC;
1890
1891 timeout = i915_request_wait(target,
1892 I915_WAIT_INTERRUPTIBLE,
1893 MAX_SCHEDULE_TIMEOUT);
1894 if (timeout < 0)
1895 return timeout;
1896
1897 i915_request_retire_upto(target);
1898
1899 intel_ring_update_space(ring);
1900 GEM_BUG_ON(ring->space < bytes);
1901 return 0;
1902}
1903
1904u32 *intel_ring_begin(struct i915_request *rq, unsigned int num_dwords)
1905{
1906 struct intel_ring *ring = rq->ring;
1907 const unsigned int remain_usable = ring->effective_size - ring->emit;
1908 const unsigned int bytes = num_dwords * sizeof(u32);
1909 unsigned int need_wrap = 0;
1910 unsigned int total_bytes;
1911 u32 *cs;
1912
1913 /* Packets must be qword aligned. */
1914 GEM_BUG_ON(num_dwords & 1);
1915
1916 total_bytes = bytes + rq->reserved_space;
1917 GEM_BUG_ON(total_bytes > ring->effective_size);
1918
1919 if (unlikely(total_bytes > remain_usable)) {
1920 const int remain_actual = ring->size - ring->emit;
1921
1922 if (bytes > remain_usable) {
1923 /*
1924 * Not enough space for the basic request. So need to
1925 * flush out the remainder and then wait for
1926 * base + reserved.
1927 */
1928 total_bytes += remain_actual;
1929 need_wrap = remain_actual | 1;
1930 } else {
1931 /*
1932 * The base request will fit but the reserved space
1933 * falls off the end. So we don't need an immediate
1934 * wrap and only need to effectively wait for the
1935 * reserved size from the start of ringbuffer.
1936 */
1937 total_bytes = rq->reserved_space + remain_actual;
1938 }
1939 }
1940
1941 if (unlikely(total_bytes > ring->space)) {
1942 int ret;
1943
1944 /*
1945 * Space is reserved in the ringbuffer for finalising the
1946 * request, as that cannot be allowed to fail. During request
1947 * finalisation, reserved_space is set to 0 to stop the
1948 * overallocation and the assumption is that then we never need
1949 * to wait (which has the risk of failing with EINTR).
1950 *
1951 * See also i915_request_alloc() and i915_request_add().
1952 */
1953 GEM_BUG_ON(!rq->reserved_space);
1954
1955 ret = wait_for_space(ring, rq->timeline, total_bytes);
1956 if (unlikely(ret))
1957 return ERR_PTR(ret);
1958 }
1959
1960 if (unlikely(need_wrap)) {
1961 need_wrap &= ~1;
1962 GEM_BUG_ON(need_wrap > ring->space);
1963 GEM_BUG_ON(ring->emit + need_wrap > ring->size);
1964 GEM_BUG_ON(!IS_ALIGNED(need_wrap, sizeof(u64)));
1965
1966 /* Fill the tail with MI_NOOP */
1967 memset64(ring->vaddr + ring->emit, 0, need_wrap / sizeof(u64));
1968 ring->space -= need_wrap;
1969 ring->emit = 0;
1970 }
1971
1972 GEM_BUG_ON(ring->emit > ring->size - bytes);
1973 GEM_BUG_ON(ring->space < bytes);
1974 cs = ring->vaddr + ring->emit;
1975 GEM_DEBUG_EXEC(memset32(cs, POISON_INUSE, bytes / sizeof(*cs)));
1976 ring->emit += bytes;
1977 ring->space -= bytes;
1978
1979 return cs;
1980}
1981
1982/* Align the ring tail to a cacheline boundary */
1983int intel_ring_cacheline_align(struct i915_request *rq)
1984{
1985 int num_dwords;
1986 void *cs;
1987
1988 num_dwords = (rq->ring->emit & (CACHELINE_BYTES - 1)) / sizeof(u32);
1989 if (num_dwords == 0)
1990 return 0;
1991
1992 num_dwords = CACHELINE_DWORDS - num_dwords;
1993 GEM_BUG_ON(num_dwords & 1);
1994
1995 cs = intel_ring_begin(rq, num_dwords);
1996 if (IS_ERR(cs))
1997 return PTR_ERR(cs);
1998
1999 memset64(cs, (u64)MI_NOOP << 32 | MI_NOOP, num_dwords / 2);
2000 intel_ring_advance(rq, cs);
2001
2002 GEM_BUG_ON(rq->ring->emit & (CACHELINE_BYTES - 1));
2003 return 0;
2004}
2005
2006static void gen6_bsd_submit_request(struct i915_request *request)
2007{
2008 struct intel_uncore *uncore = request->engine->uncore;
2009
2010 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
2011
2012 /* Every tail move must follow the sequence below */
2013
2014 /* Disable notification that the ring is IDLE. The GT
2015 * will then assume that it is busy and bring it out of rc6.
2016 */
2017 intel_uncore_write_fw(uncore, GEN6_BSD_SLEEP_PSMI_CONTROL,
2018 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2019
2020 /* Clear the context id. Here be magic! */
2021 intel_uncore_write64_fw(uncore, GEN6_BSD_RNCID, 0x0);
2022
2023 /* Wait for the ring not to be idle, i.e. for it to wake up. */
2024 if (__intel_wait_for_register_fw(uncore,
2025 GEN6_BSD_SLEEP_PSMI_CONTROL,
2026 GEN6_BSD_SLEEP_INDICATOR,
2027 0,
2028 1000, 0, NULL))
2029 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
2030
2031 /* Now that the ring is fully powered up, update the tail */
2032 i9xx_submit_request(request);
2033
2034 /* Let the ring send IDLE messages to the GT again,
2035 * and so let it sleep to conserve power when idle.
2036 */
2037 intel_uncore_write_fw(uncore, GEN6_BSD_SLEEP_PSMI_CONTROL,
2038 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2039
2040 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
2041}
2042
2043static int mi_flush_dw(struct i915_request *rq, u32 flags)
2044{
2045 u32 cmd, *cs;
2046
2047 cs = intel_ring_begin(rq, 4);
2048 if (IS_ERR(cs))
2049 return PTR_ERR(cs);
2050
2051 cmd = MI_FLUSH_DW;
2052
2053 /*
2054 * We always require a command barrier so that subsequent
2055 * commands, such as breadcrumb interrupts, are strictly ordered
2056 * wrt the contents of the write cache being flushed to memory
2057 * (and thus being coherent from the CPU).
2058 */
2059 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2060
2061 /*
2062 * Bspec vol 1c.3 - blitter engine command streamer:
2063 * "If ENABLED, all TLBs will be invalidated once the flush
2064 * operation is complete. This bit is only valid when the
2065 * Post-Sync Operation field is a value of 1h or 3h."
2066 */
2067 cmd |= flags;
2068
2069 *cs++ = cmd;
2070 *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT;
2071 *cs++ = 0;
2072 *cs++ = MI_NOOP;
2073
2074 intel_ring_advance(rq, cs);
2075
2076 return 0;
2077}
2078
2079static int gen6_flush_dw(struct i915_request *rq, u32 mode, u32 invflags)
2080{
2081 return mi_flush_dw(rq, mode & EMIT_INVALIDATE ? invflags : 0);
2082}
2083
2084static int gen6_bsd_ring_flush(struct i915_request *rq, u32 mode)
2085{
2086 return gen6_flush_dw(rq, mode, MI_INVALIDATE_TLB | MI_INVALIDATE_BSD);
2087}
2088
2089static int
2090hsw_emit_bb_start(struct i915_request *rq,
2091 u64 offset, u32 len,
2092 unsigned int dispatch_flags)
2093{
2094 u32 *cs;
2095
2096 cs = intel_ring_begin(rq, 2);
2097 if (IS_ERR(cs))
2098 return PTR_ERR(cs);
2099
2100 *cs++ = MI_BATCH_BUFFER_START | (dispatch_flags & I915_DISPATCH_SECURE ?
2101 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW);
2102 /* bit0-7 is the length on GEN6+ */
2103 *cs++ = offset;
2104 intel_ring_advance(rq, cs);
2105
2106 return 0;
2107}
2108
2109static int
2110gen6_emit_bb_start(struct i915_request *rq,
2111 u64 offset, u32 len,
2112 unsigned int dispatch_flags)
2113{
2114 u32 *cs;
2115
2116 cs = intel_ring_begin(rq, 2);
2117 if (IS_ERR(cs))
2118 return PTR_ERR(cs);
2119
2120 *cs++ = MI_BATCH_BUFFER_START | (dispatch_flags & I915_DISPATCH_SECURE ?
2121 0 : MI_BATCH_NON_SECURE_I965);
2122 /* bit0-7 is the length on GEN6+ */
2123 *cs++ = offset;
2124 intel_ring_advance(rq, cs);
2125
2126 return 0;
2127}
2128
2129/* Blitter support (SandyBridge+) */
2130
2131static int gen6_ring_flush(struct i915_request *rq, u32 mode)
2132{
2133 return gen6_flush_dw(rq, mode, MI_INVALIDATE_TLB);
2134}
2135
2136static void i9xx_set_default_submission(struct intel_engine_cs *engine)
2137{
2138 engine->submit_request = i9xx_submit_request;
2139 engine->cancel_requests = cancel_requests;
2140
2141 engine->park = NULL;
2142 engine->unpark = NULL;
2143}
2144
2145static void gen6_bsd_set_default_submission(struct intel_engine_cs *engine)
2146{
2147 i9xx_set_default_submission(engine);
2148 engine->submit_request = gen6_bsd_submit_request;
2149}
2150
2151static void ring_destroy(struct intel_engine_cs *engine)
2152{
2153 struct drm_i915_private *dev_priv = engine->i915;
2154
2155 WARN_ON(INTEL_GEN(dev_priv) > 2 &&
2156 (ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0);
2157
2158 intel_engine_cleanup_common(engine);
2159
2160 intel_ring_unpin(engine->legacy.ring);
2161 intel_ring_put(engine->legacy.ring);
2162
2163 intel_timeline_unpin(engine->legacy.timeline);
2164 intel_timeline_put(engine->legacy.timeline);
2165
2166 kfree(engine);
2167}
2168
2169static void setup_irq(struct intel_engine_cs *engine)
2170{
2171 struct drm_i915_private *i915 = engine->i915;
2172
2173 if (INTEL_GEN(i915) >= 6) {
2174 engine->irq_enable = gen6_irq_enable;
2175 engine->irq_disable = gen6_irq_disable;
2176 } else if (INTEL_GEN(i915) >= 5) {
2177 engine->irq_enable = gen5_irq_enable;
2178 engine->irq_disable = gen5_irq_disable;
2179 } else if (INTEL_GEN(i915) >= 3) {
2180 engine->irq_enable = i9xx_irq_enable;
2181 engine->irq_disable = i9xx_irq_disable;
2182 } else {
2183 engine->irq_enable = i8xx_irq_enable;
2184 engine->irq_disable = i8xx_irq_disable;
2185 }
2186}
2187
2188static void setup_common(struct intel_engine_cs *engine)
2189{
2190 struct drm_i915_private *i915 = engine->i915;
2191
2192 /* gen8+ are only supported with execlists */
2193 GEM_BUG_ON(INTEL_GEN(i915) >= 8);
2194
2195 setup_irq(engine);
2196
2197 engine->destroy = ring_destroy;
2198
2199 engine->resume = xcs_resume;
2200 engine->reset.prepare = reset_prepare;
2201 engine->reset.reset = reset_ring;
2202 engine->reset.finish = reset_finish;
2203
2204 engine->cops = &ring_context_ops;
2205 engine->request_alloc = ring_request_alloc;
2206
2207 /*
2208 * Using a global execution timeline; the previous final breadcrumb is
2209 * equivalent to our next initial bread so we can elide
2210 * engine->emit_init_breadcrumb().
2211 */
2212 engine->emit_fini_breadcrumb = i9xx_emit_breadcrumb;
2213 if (IS_GEN(i915, 5))
2214 engine->emit_fini_breadcrumb = gen5_emit_breadcrumb;
2215
2216 engine->set_default_submission = i9xx_set_default_submission;
2217
2218 if (INTEL_GEN(i915) >= 6)
2219 engine->emit_bb_start = gen6_emit_bb_start;
2220 else if (INTEL_GEN(i915) >= 4)
2221 engine->emit_bb_start = i965_emit_bb_start;
2222 else if (IS_I830(i915) || IS_I845G(i915))
2223 engine->emit_bb_start = i830_emit_bb_start;
2224 else
2225 engine->emit_bb_start = i915_emit_bb_start;
2226}
2227
2228static void setup_rcs(struct intel_engine_cs *engine)
2229{
2230 struct drm_i915_private *i915 = engine->i915;
2231
2232 if (HAS_L3_DPF(i915))
2233 engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
2234
2235 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2236
2237 if (INTEL_GEN(i915) >= 7) {
2238 engine->emit_flush = gen7_render_ring_flush;
2239 engine->emit_fini_breadcrumb = gen7_rcs_emit_breadcrumb;
2240 } else if (IS_GEN(i915, 6)) {
2241 engine->emit_flush = gen6_render_ring_flush;
2242 engine->emit_fini_breadcrumb = gen6_rcs_emit_breadcrumb;
2243 } else if (IS_GEN(i915, 5)) {
2244 engine->emit_flush = gen4_render_ring_flush;
2245 } else {
2246 if (INTEL_GEN(i915) < 4)
2247 engine->emit_flush = gen2_render_ring_flush;
2248 else
2249 engine->emit_flush = gen4_render_ring_flush;
2250 engine->irq_enable_mask = I915_USER_INTERRUPT;
2251 }
2252
2253 if (IS_HASWELL(i915))
2254 engine->emit_bb_start = hsw_emit_bb_start;
2255
2256 engine->resume = rcs_resume;
2257}
2258
2259static void setup_vcs(struct intel_engine_cs *engine)
2260{
2261 struct drm_i915_private *i915 = engine->i915;
2262
2263 if (INTEL_GEN(i915) >= 6) {
2264 /* gen6 bsd needs a special wa for tail updates */
2265 if (IS_GEN(i915, 6))
2266 engine->set_default_submission = gen6_bsd_set_default_submission;
2267 engine->emit_flush = gen6_bsd_ring_flush;
2268 engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2269
2270 if (IS_GEN(i915, 6))
2271 engine->emit_fini_breadcrumb = gen6_xcs_emit_breadcrumb;
2272 else
2273 engine->emit_fini_breadcrumb = gen7_xcs_emit_breadcrumb;
2274 } else {
2275 engine->emit_flush = bsd_ring_flush;
2276 if (IS_GEN(i915, 5))
2277 engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2278 else
2279 engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2280 }
2281}
2282
2283static void setup_bcs(struct intel_engine_cs *engine)
2284{
2285 struct drm_i915_private *i915 = engine->i915;
2286
2287 engine->emit_flush = gen6_ring_flush;
2288 engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2289
2290 if (IS_GEN(i915, 6))
2291 engine->emit_fini_breadcrumb = gen6_xcs_emit_breadcrumb;
2292 else
2293 engine->emit_fini_breadcrumb = gen7_xcs_emit_breadcrumb;
2294}
2295
2296static void setup_vecs(struct intel_engine_cs *engine)
2297{
2298 struct drm_i915_private *i915 = engine->i915;
2299
2300 GEM_BUG_ON(INTEL_GEN(i915) < 7);
2301
2302 engine->emit_flush = gen6_ring_flush;
2303 engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2304 engine->irq_enable = hsw_vebox_irq_enable;
2305 engine->irq_disable = hsw_vebox_irq_disable;
2306
2307 engine->emit_fini_breadcrumb = gen7_xcs_emit_breadcrumb;
2308}
2309
2310int intel_ring_submission_setup(struct intel_engine_cs *engine)
2311{
2312 setup_common(engine);
2313
2314 switch (engine->class) {
2315 case RENDER_CLASS:
2316 setup_rcs(engine);
2317 break;
2318 case VIDEO_DECODE_CLASS:
2319 setup_vcs(engine);
2320 break;
2321 case COPY_ENGINE_CLASS:
2322 setup_bcs(engine);
2323 break;
2324 case VIDEO_ENHANCEMENT_CLASS:
2325 setup_vecs(engine);
2326 break;
2327 default:
2328 MISSING_CASE(engine->class);
2329 return -ENODEV;
2330 }
2331
2332 return 0;
2333}
2334
2335int intel_ring_submission_init(struct intel_engine_cs *engine)
2336{
2337 struct intel_timeline *timeline;
2338 struct intel_ring *ring;
2339 int err;
2340
2341 timeline = intel_timeline_create(engine->gt, engine->status_page.vma);
2342 if (IS_ERR(timeline)) {
2343 err = PTR_ERR(timeline);
2344 goto err;
2345 }
2346 GEM_BUG_ON(timeline->has_initial_breadcrumb);
2347
2348 err = intel_timeline_pin(timeline);
2349 if (err)
2350 goto err_timeline;
2351
2352 ring = intel_engine_create_ring(engine, SZ_16K);
2353 if (IS_ERR(ring)) {
2354 err = PTR_ERR(ring);
2355 goto err_timeline_unpin;
2356 }
2357
2358 err = intel_ring_pin(ring);
2359 if (err)
2360 goto err_ring;
2361
2362 GEM_BUG_ON(engine->legacy.ring);
2363 engine->legacy.ring = ring;
2364 engine->legacy.timeline = timeline;
2365
2366 err = intel_engine_init_common(engine);
2367 if (err)
2368 goto err_ring_unpin;
2369
2370 GEM_BUG_ON(timeline->hwsp_ggtt != engine->status_page.vma);
2371
2372 return 0;
2373
2374err_ring_unpin:
2375 intel_ring_unpin(ring);
2376err_ring:
2377 intel_ring_put(ring);
2378err_timeline_unpin:
2379 intel_timeline_unpin(timeline);
2380err_timeline:
2381 intel_timeline_put(timeline);
2382err:
2383 intel_engine_cleanup_common(engine);
2384 return err;
2385}