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1/*
2 * Copyright © 2006-2007 Intel Corporation
3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Dave Airlie <airlied@linux.ie>
27 * Jesse Barnes <jesse.barnes@intel.com>
28 */
29
30#include <acpi/button.h>
31#include <linux/acpi.h>
32#include <linux/dmi.h>
33#include <linux/i2c.h>
34#include <linux/slab.h>
35#include <linux/vga_switcheroo.h>
36
37#include <drm/drm_atomic_helper.h>
38#include <drm/drm_crtc.h>
39#include <drm/drm_edid.h>
40#include <drm/drm_probe_helper.h>
41
42#include "i915_drv.h"
43#include "i915_reg.h"
44#include "intel_atomic.h"
45#include "intel_backlight.h"
46#include "intel_connector.h"
47#include "intel_de.h"
48#include "intel_display_types.h"
49#include "intel_dpll.h"
50#include "intel_fdi.h"
51#include "intel_gmbus.h"
52#include "intel_lvds.h"
53#include "intel_lvds_regs.h"
54#include "intel_panel.h"
55#include "intel_pfit.h"
56#include "intel_pps_regs.h"
57
58/* Private structure for the integrated LVDS support */
59struct intel_lvds_pps {
60 /* 100us units */
61 int t1_t2;
62 int t3;
63 int t4;
64 int t5;
65 int tx;
66
67 int divider;
68
69 int port;
70 bool powerdown_on_reset;
71};
72
73struct intel_lvds_encoder {
74 struct intel_encoder base;
75
76 bool is_dual_link;
77 i915_reg_t reg;
78 u32 a3_power;
79
80 struct intel_lvds_pps init_pps;
81 u32 init_lvds_val;
82
83 struct intel_connector *attached_connector;
84};
85
86static struct intel_lvds_encoder *to_lvds_encoder(struct intel_encoder *encoder)
87{
88 return container_of(encoder, struct intel_lvds_encoder, base);
89}
90
91bool intel_lvds_port_enabled(struct drm_i915_private *i915,
92 i915_reg_t lvds_reg, enum pipe *pipe)
93{
94 u32 val;
95
96 val = intel_de_read(i915, lvds_reg);
97
98 /* asserts want to know the pipe even if the port is disabled */
99 if (HAS_PCH_CPT(i915))
100 *pipe = REG_FIELD_GET(LVDS_PIPE_SEL_MASK_CPT, val);
101 else
102 *pipe = REG_FIELD_GET(LVDS_PIPE_SEL_MASK, val);
103
104 return val & LVDS_PORT_EN;
105}
106
107static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
108 enum pipe *pipe)
109{
110 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
111 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
112 intel_wakeref_t wakeref;
113 bool ret;
114
115 wakeref = intel_display_power_get_if_enabled(i915, encoder->power_domain);
116 if (!wakeref)
117 return false;
118
119 ret = intel_lvds_port_enabled(i915, lvds_encoder->reg, pipe);
120
121 intel_display_power_put(i915, encoder->power_domain, wakeref);
122
123 return ret;
124}
125
126static void intel_lvds_get_config(struct intel_encoder *encoder,
127 struct intel_crtc_state *crtc_state)
128{
129 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
130 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
131 u32 tmp, flags = 0;
132
133 crtc_state->output_types |= BIT(INTEL_OUTPUT_LVDS);
134
135 tmp = intel_de_read(dev_priv, lvds_encoder->reg);
136 if (tmp & LVDS_HSYNC_POLARITY)
137 flags |= DRM_MODE_FLAG_NHSYNC;
138 else
139 flags |= DRM_MODE_FLAG_PHSYNC;
140 if (tmp & LVDS_VSYNC_POLARITY)
141 flags |= DRM_MODE_FLAG_NVSYNC;
142 else
143 flags |= DRM_MODE_FLAG_PVSYNC;
144
145 crtc_state->hw.adjusted_mode.flags |= flags;
146
147 if (DISPLAY_VER(dev_priv) < 5)
148 crtc_state->gmch_pfit.lvds_border_bits =
149 tmp & LVDS_BORDER_ENABLE;
150
151 /* gen2/3 store dither state in pfit control, needs to match */
152 if (DISPLAY_VER(dev_priv) < 4) {
153 tmp = intel_de_read(dev_priv, PFIT_CONTROL(dev_priv));
154
155 crtc_state->gmch_pfit.control |= tmp & PFIT_PANEL_8TO6_DITHER_ENABLE;
156 }
157
158 crtc_state->hw.adjusted_mode.crtc_clock = crtc_state->port_clock;
159}
160
161static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv,
162 struct intel_lvds_pps *pps)
163{
164 u32 val;
165
166 pps->powerdown_on_reset = intel_de_read(dev_priv,
167 PP_CONTROL(dev_priv, 0)) & PANEL_POWER_RESET;
168
169 val = intel_de_read(dev_priv, PP_ON_DELAYS(dev_priv, 0));
170 pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val);
171 pps->t1_t2 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val);
172 pps->t5 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val);
173
174 val = intel_de_read(dev_priv, PP_OFF_DELAYS(dev_priv, 0));
175 pps->t3 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val);
176 pps->tx = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val);
177
178 val = intel_de_read(dev_priv, PP_DIVISOR(dev_priv, 0));
179 pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val);
180 val = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, val);
181 /*
182 * Remove the BSpec specified +1 (100ms) offset that accounts for a
183 * too short power-cycle delay due to the asynchronous programming of
184 * the register.
185 */
186 if (val)
187 val--;
188 /* Convert from 100ms to 100us units */
189 pps->t4 = val * 1000;
190
191 if (DISPLAY_VER(dev_priv) < 5 &&
192 pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) {
193 drm_dbg_kms(&dev_priv->drm,
194 "Panel power timings uninitialized, "
195 "setting defaults\n");
196 /* Set T2 to 40ms and T5 to 200ms in 100 usec units */
197 pps->t1_t2 = 40 * 10;
198 pps->t5 = 200 * 10;
199 /* Set T3 to 35ms and Tx to 200ms in 100 usec units */
200 pps->t3 = 35 * 10;
201 pps->tx = 200 * 10;
202 }
203
204 drm_dbg(&dev_priv->drm, "LVDS PPS:t1+t2 %d t3 %d t4 %d t5 %d tx %d "
205 "divider %d port %d powerdown_on_reset %d\n",
206 pps->t1_t2, pps->t3, pps->t4, pps->t5, pps->tx,
207 pps->divider, pps->port, pps->powerdown_on_reset);
208}
209
210static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv,
211 struct intel_lvds_pps *pps)
212{
213 u32 val;
214
215 val = intel_de_read(dev_priv, PP_CONTROL(dev_priv, 0));
216 drm_WARN_ON(&dev_priv->drm,
217 (val & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS);
218 if (pps->powerdown_on_reset)
219 val |= PANEL_POWER_RESET;
220 intel_de_write(dev_priv, PP_CONTROL(dev_priv, 0), val);
221
222 intel_de_write(dev_priv, PP_ON_DELAYS(dev_priv, 0),
223 REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, pps->port) |
224 REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, pps->t1_t2) |
225 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, pps->t5));
226
227 intel_de_write(dev_priv, PP_OFF_DELAYS(dev_priv, 0),
228 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, pps->t3) |
229 REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, pps->tx));
230
231 intel_de_write(dev_priv, PP_DIVISOR(dev_priv, 0),
232 REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) |
233 REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(pps->t4, 1000) + 1));
234}
235
236static void intel_pre_enable_lvds(struct intel_atomic_state *state,
237 struct intel_encoder *encoder,
238 const struct intel_crtc_state *crtc_state,
239 const struct drm_connector_state *conn_state)
240{
241 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
242 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
243 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
244 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
245 enum pipe pipe = crtc->pipe;
246 u32 temp;
247
248 if (HAS_PCH_SPLIT(i915)) {
249 assert_fdi_rx_pll_disabled(i915, pipe);
250 assert_shared_dpll_disabled(i915, crtc_state->shared_dpll);
251 } else {
252 assert_pll_disabled(i915, pipe);
253 }
254
255 intel_lvds_pps_init_hw(i915, &lvds_encoder->init_pps);
256
257 temp = lvds_encoder->init_lvds_val;
258 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
259
260 if (HAS_PCH_CPT(i915)) {
261 temp &= ~LVDS_PIPE_SEL_MASK_CPT;
262 temp |= LVDS_PIPE_SEL_CPT(pipe);
263 } else {
264 temp &= ~LVDS_PIPE_SEL_MASK;
265 temp |= LVDS_PIPE_SEL(pipe);
266 }
267
268 /* set the corresponding LVDS_BORDER bit */
269 temp &= ~LVDS_BORDER_ENABLE;
270 temp |= crtc_state->gmch_pfit.lvds_border_bits;
271
272 /*
273 * Set the B0-B3 data pairs corresponding to whether we're going to
274 * set the DPLLs for dual-channel mode or not.
275 */
276 if (lvds_encoder->is_dual_link)
277 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
278 else
279 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
280
281 /*
282 * It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
283 * appropriately here, but we need to look more thoroughly into how
284 * panels behave in the two modes. For now, let's just maintain the
285 * value we got from the BIOS.
286 */
287 temp &= ~LVDS_A3_POWER_MASK;
288 temp |= lvds_encoder->a3_power;
289
290 /*
291 * Set the dithering flag on LVDS as needed, note that there is no
292 * special lvds dither control bit on pch-split platforms, dithering is
293 * only controlled through the TRANSCONF reg.
294 */
295 if (DISPLAY_VER(i915) == 4) {
296 /*
297 * Bspec wording suggests that LVDS port dithering only exists
298 * for 18bpp panels.
299 */
300 if (crtc_state->dither && crtc_state->pipe_bpp == 18)
301 temp |= LVDS_ENABLE_DITHER;
302 else
303 temp &= ~LVDS_ENABLE_DITHER;
304 }
305 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
306 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
307 temp |= LVDS_HSYNC_POLARITY;
308 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
309 temp |= LVDS_VSYNC_POLARITY;
310
311 intel_de_write(i915, lvds_encoder->reg, temp);
312}
313
314/*
315 * Sets the power state for the panel.
316 */
317static void intel_enable_lvds(struct intel_atomic_state *state,
318 struct intel_encoder *encoder,
319 const struct intel_crtc_state *crtc_state,
320 const struct drm_connector_state *conn_state)
321{
322 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
323 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
324
325 intel_de_rmw(dev_priv, lvds_encoder->reg, 0, LVDS_PORT_EN);
326
327 intel_de_rmw(dev_priv, PP_CONTROL(dev_priv, 0), 0, PANEL_POWER_ON);
328 intel_de_posting_read(dev_priv, lvds_encoder->reg);
329
330 if (intel_de_wait_for_set(dev_priv, PP_STATUS(dev_priv, 0), PP_ON, 5000))
331 drm_err(&dev_priv->drm,
332 "timed out waiting for panel to power on\n");
333
334 intel_backlight_enable(crtc_state, conn_state);
335}
336
337static void intel_disable_lvds(struct intel_atomic_state *state,
338 struct intel_encoder *encoder,
339 const struct intel_crtc_state *old_crtc_state,
340 const struct drm_connector_state *old_conn_state)
341{
342 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
343 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
344
345 intel_de_rmw(dev_priv, PP_CONTROL(dev_priv, 0), PANEL_POWER_ON, 0);
346 if (intel_de_wait_for_clear(dev_priv, PP_STATUS(dev_priv, 0), PP_ON, 1000))
347 drm_err(&dev_priv->drm,
348 "timed out waiting for panel to power off\n");
349
350 intel_de_rmw(dev_priv, lvds_encoder->reg, LVDS_PORT_EN, 0);
351 intel_de_posting_read(dev_priv, lvds_encoder->reg);
352}
353
354static void gmch_disable_lvds(struct intel_atomic_state *state,
355 struct intel_encoder *encoder,
356 const struct intel_crtc_state *old_crtc_state,
357 const struct drm_connector_state *old_conn_state)
358
359{
360 intel_backlight_disable(old_conn_state);
361
362 intel_disable_lvds(state, encoder, old_crtc_state, old_conn_state);
363}
364
365static void pch_disable_lvds(struct intel_atomic_state *state,
366 struct intel_encoder *encoder,
367 const struct intel_crtc_state *old_crtc_state,
368 const struct drm_connector_state *old_conn_state)
369{
370 intel_backlight_disable(old_conn_state);
371}
372
373static void pch_post_disable_lvds(struct intel_atomic_state *state,
374 struct intel_encoder *encoder,
375 const struct intel_crtc_state *old_crtc_state,
376 const struct drm_connector_state *old_conn_state)
377{
378 intel_disable_lvds(state, encoder, old_crtc_state, old_conn_state);
379}
380
381static void intel_lvds_shutdown(struct intel_encoder *encoder)
382{
383 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
384
385 if (intel_de_wait_for_clear(dev_priv, PP_STATUS(dev_priv, 0), PP_CYCLE_DELAY_ACTIVE, 5000))
386 drm_err(&dev_priv->drm,
387 "timed out waiting for panel power cycle delay\n");
388}
389
390static enum drm_mode_status
391intel_lvds_mode_valid(struct drm_connector *_connector,
392 struct drm_display_mode *mode)
393{
394 struct intel_connector *connector = to_intel_connector(_connector);
395 struct drm_i915_private *i915 = to_i915(connector->base.dev);
396 const struct drm_display_mode *fixed_mode =
397 intel_panel_fixed_mode(connector, mode);
398 int max_pixclk = to_i915(connector->base.dev)->display.cdclk.max_dotclk_freq;
399 enum drm_mode_status status;
400
401 status = intel_cpu_transcoder_mode_valid(i915, mode);
402 if (status != MODE_OK)
403 return status;
404
405 status = intel_panel_mode_valid(connector, mode);
406 if (status != MODE_OK)
407 return status;
408
409 if (fixed_mode->clock > max_pixclk)
410 return MODE_CLOCK_HIGH;
411
412 return MODE_OK;
413}
414
415static int intel_lvds_compute_config(struct intel_encoder *encoder,
416 struct intel_crtc_state *crtc_state,
417 struct drm_connector_state *conn_state)
418{
419 struct drm_i915_private *i915 = to_i915(encoder->base.dev);
420 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
421 struct intel_connector *connector = lvds_encoder->attached_connector;
422 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
423 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
424 unsigned int lvds_bpp;
425 int ret;
426
427 /* Should never happen!! */
428 if (DISPLAY_VER(i915) < 4 && crtc->pipe == 0) {
429 drm_err(&i915->drm, "Can't support LVDS on pipe A\n");
430 return -EINVAL;
431 }
432
433 if (HAS_PCH_SPLIT(i915)) {
434 crtc_state->has_pch_encoder = true;
435 if (!intel_fdi_compute_pipe_bpp(crtc_state))
436 return -EINVAL;
437 }
438
439 if (lvds_encoder->a3_power == LVDS_A3_POWER_UP)
440 lvds_bpp = 8*3;
441 else
442 lvds_bpp = 6*3;
443
444 /* TODO: Check crtc_state->max_link_bpp_x16 instead of bw_constrained */
445 if (lvds_bpp != crtc_state->pipe_bpp && !crtc_state->bw_constrained) {
446 drm_dbg_kms(&i915->drm,
447 "forcing display bpp (was %d) to LVDS (%d)\n",
448 crtc_state->pipe_bpp, lvds_bpp);
449 crtc_state->pipe_bpp = lvds_bpp;
450 }
451
452 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
453 crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB;
454
455 /*
456 * We have timings from the BIOS for the panel, put them in
457 * to the adjusted mode. The CRTC will be set up for this mode,
458 * with the panel scaling set up to source from the H/VDisplay
459 * of the original mode.
460 */
461 ret = intel_panel_compute_config(connector, adjusted_mode);
462 if (ret)
463 return ret;
464
465 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
466 return -EINVAL;
467
468 ret = intel_panel_fitting(crtc_state, conn_state);
469 if (ret)
470 return ret;
471
472 /*
473 * XXX: It would be nice to support lower refresh rates on the
474 * panels to reduce power consumption, and perhaps match the
475 * user's requested refresh rate.
476 */
477
478 return 0;
479}
480
481/*
482 * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
483 */
484static int intel_lvds_get_modes(struct drm_connector *_connector)
485{
486 struct intel_connector *connector = to_intel_connector(_connector);
487 const struct drm_edid *fixed_edid = connector->panel.fixed_edid;
488
489 /* Use panel fixed edid if we have one */
490 if (!IS_ERR_OR_NULL(fixed_edid)) {
491 drm_edid_connector_update(&connector->base, fixed_edid);
492
493 return drm_edid_connector_add_modes(&connector->base);
494 }
495
496 return intel_panel_get_modes(connector);
497}
498
499static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
500 .get_modes = intel_lvds_get_modes,
501 .mode_valid = intel_lvds_mode_valid,
502 .atomic_check = intel_digital_connector_atomic_check,
503};
504
505static const struct drm_connector_funcs intel_lvds_connector_funcs = {
506 .detect = intel_panel_detect,
507 .fill_modes = drm_helper_probe_single_connector_modes,
508 .atomic_get_property = intel_digital_connector_atomic_get_property,
509 .atomic_set_property = intel_digital_connector_atomic_set_property,
510 .late_register = intel_connector_register,
511 .early_unregister = intel_connector_unregister,
512 .destroy = intel_connector_destroy,
513 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
514 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
515};
516
517static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
518 .destroy = intel_encoder_destroy,
519};
520
521static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
522{
523 DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
524 return 1;
525}
526
527/* These systems claim to have LVDS, but really don't */
528static const struct dmi_system_id intel_no_lvds[] = {
529 {
530 .callback = intel_no_lvds_dmi_callback,
531 .ident = "Apple Mac Mini (Core series)",
532 .matches = {
533 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
534 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
535 },
536 },
537 {
538 .callback = intel_no_lvds_dmi_callback,
539 .ident = "Apple Mac Mini (Core 2 series)",
540 .matches = {
541 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
542 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
543 },
544 },
545 {
546 .callback = intel_no_lvds_dmi_callback,
547 .ident = "MSI IM-945GSE-A",
548 .matches = {
549 DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
550 DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
551 },
552 },
553 {
554 .callback = intel_no_lvds_dmi_callback,
555 .ident = "Dell Studio Hybrid",
556 .matches = {
557 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
558 DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
559 },
560 },
561 {
562 .callback = intel_no_lvds_dmi_callback,
563 .ident = "Dell OptiPlex FX170",
564 .matches = {
565 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
566 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
567 },
568 },
569 {
570 .callback = intel_no_lvds_dmi_callback,
571 .ident = "AOpen Mini PC",
572 .matches = {
573 DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
574 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
575 },
576 },
577 {
578 .callback = intel_no_lvds_dmi_callback,
579 .ident = "AOpen Mini PC MP915",
580 .matches = {
581 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
582 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
583 },
584 },
585 {
586 .callback = intel_no_lvds_dmi_callback,
587 .ident = "AOpen i915GMm-HFS",
588 .matches = {
589 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
590 DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
591 },
592 },
593 {
594 .callback = intel_no_lvds_dmi_callback,
595 .ident = "AOpen i45GMx-I",
596 .matches = {
597 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
598 DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
599 },
600 },
601 {
602 .callback = intel_no_lvds_dmi_callback,
603 .ident = "Aopen i945GTt-VFA",
604 .matches = {
605 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
606 },
607 },
608 {
609 .callback = intel_no_lvds_dmi_callback,
610 .ident = "Clientron U800",
611 .matches = {
612 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
613 DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
614 },
615 },
616 {
617 .callback = intel_no_lvds_dmi_callback,
618 .ident = "Clientron E830",
619 .matches = {
620 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
621 DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
622 },
623 },
624 {
625 .callback = intel_no_lvds_dmi_callback,
626 .ident = "Asus EeeBox PC EB1007",
627 .matches = {
628 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."),
629 DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"),
630 },
631 },
632 {
633 .callback = intel_no_lvds_dmi_callback,
634 .ident = "Asus AT5NM10T-I",
635 .matches = {
636 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
637 DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
638 },
639 },
640 {
641 .callback = intel_no_lvds_dmi_callback,
642 .ident = "Hewlett-Packard HP t5740",
643 .matches = {
644 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
645 DMI_MATCH(DMI_PRODUCT_NAME, " t5740"),
646 },
647 },
648 {
649 .callback = intel_no_lvds_dmi_callback,
650 .ident = "Hewlett-Packard t5745",
651 .matches = {
652 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
653 DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"),
654 },
655 },
656 {
657 .callback = intel_no_lvds_dmi_callback,
658 .ident = "Hewlett-Packard st5747",
659 .matches = {
660 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
661 DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"),
662 },
663 },
664 {
665 .callback = intel_no_lvds_dmi_callback,
666 .ident = "MSI Wind Box DC500",
667 .matches = {
668 DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
669 DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
670 },
671 },
672 {
673 .callback = intel_no_lvds_dmi_callback,
674 .ident = "Gigabyte GA-D525TUD",
675 .matches = {
676 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
677 DMI_MATCH(DMI_BOARD_NAME, "D525TUD"),
678 },
679 },
680 {
681 .callback = intel_no_lvds_dmi_callback,
682 .ident = "Supermicro X7SPA-H",
683 .matches = {
684 DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"),
685 DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"),
686 },
687 },
688 {
689 .callback = intel_no_lvds_dmi_callback,
690 .ident = "Fujitsu Esprimo Q900",
691 .matches = {
692 DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"),
693 DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"),
694 },
695 },
696 {
697 .callback = intel_no_lvds_dmi_callback,
698 .ident = "Intel D410PT",
699 .matches = {
700 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
701 DMI_MATCH(DMI_BOARD_NAME, "D410PT"),
702 },
703 },
704 {
705 .callback = intel_no_lvds_dmi_callback,
706 .ident = "Intel D425KT",
707 .matches = {
708 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
709 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"),
710 },
711 },
712 {
713 .callback = intel_no_lvds_dmi_callback,
714 .ident = "Intel D510MO",
715 .matches = {
716 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
717 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"),
718 },
719 },
720 {
721 .callback = intel_no_lvds_dmi_callback,
722 .ident = "Intel D525MW",
723 .matches = {
724 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
725 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"),
726 },
727 },
728 {
729 .callback = intel_no_lvds_dmi_callback,
730 .ident = "Radiant P845",
731 .matches = {
732 DMI_MATCH(DMI_SYS_VENDOR, "Radiant Systems Inc"),
733 DMI_MATCH(DMI_PRODUCT_NAME, "P845"),
734 },
735 },
736
737 { } /* terminating entry */
738};
739
740static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
741{
742 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
743 return 1;
744}
745
746static const struct dmi_system_id intel_dual_link_lvds[] = {
747 {
748 .callback = intel_dual_link_lvds_callback,
749 .ident = "Apple MacBook Pro 15\" (2010)",
750 .matches = {
751 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
752 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro6,2"),
753 },
754 },
755 {
756 .callback = intel_dual_link_lvds_callback,
757 .ident = "Apple MacBook Pro 15\" (2011)",
758 .matches = {
759 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
760 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
761 },
762 },
763 {
764 .callback = intel_dual_link_lvds_callback,
765 .ident = "Apple MacBook Pro 15\" (2012)",
766 .matches = {
767 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
768 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro9,1"),
769 },
770 },
771 { } /* terminating entry */
772};
773
774struct intel_encoder *intel_get_lvds_encoder(struct drm_i915_private *i915)
775{
776 struct intel_encoder *encoder;
777
778 for_each_intel_encoder(&i915->drm, encoder) {
779 if (encoder->type == INTEL_OUTPUT_LVDS)
780 return encoder;
781 }
782
783 return NULL;
784}
785
786bool intel_is_dual_link_lvds(struct drm_i915_private *i915)
787{
788 struct intel_encoder *encoder = intel_get_lvds_encoder(i915);
789
790 return encoder && to_lvds_encoder(encoder)->is_dual_link;
791}
792
793static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
794{
795 struct drm_i915_private *i915 = to_i915(lvds_encoder->base.base.dev);
796 struct intel_connector *connector = lvds_encoder->attached_connector;
797 const struct drm_display_mode *fixed_mode =
798 intel_panel_preferred_fixed_mode(connector);
799 unsigned int val;
800
801 /* use the module option value if specified */
802 if (i915->display.params.lvds_channel_mode > 0)
803 return i915->display.params.lvds_channel_mode == 2;
804
805 /* single channel LVDS is limited to 112 MHz */
806 if (fixed_mode->clock > 112999)
807 return true;
808
809 if (dmi_check_system(intel_dual_link_lvds))
810 return true;
811
812 /*
813 * BIOS should set the proper LVDS register value at boot, but
814 * in reality, it doesn't set the value when the lid is closed;
815 * we need to check "the value to be set" in VBT when LVDS
816 * register is uninitialized.
817 */
818 val = intel_de_read(i915, lvds_encoder->reg);
819 if (HAS_PCH_CPT(i915))
820 val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK_CPT);
821 else
822 val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK);
823 if (val == 0)
824 val = connector->panel.vbt.bios_lvds_val;
825
826 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
827}
828
829static void intel_lvds_add_properties(struct drm_connector *connector)
830{
831 intel_attach_scaling_mode_property(connector);
832}
833
834/**
835 * intel_lvds_init - setup LVDS connectors on this device
836 * @i915: i915 device
837 *
838 * Create the connector, register the LVDS DDC bus, and try to figure out what
839 * modes we can display on the LVDS panel (if present).
840 */
841void intel_lvds_init(struct drm_i915_private *i915)
842{
843 struct intel_display *display = &i915->display;
844 struct intel_lvds_encoder *lvds_encoder;
845 struct intel_connector *connector;
846 const struct drm_edid *drm_edid;
847 struct intel_encoder *encoder;
848 i915_reg_t lvds_reg;
849 u32 lvds;
850 u8 ddc_pin;
851
852 /* Skip init on machines we know falsely report LVDS */
853 if (dmi_check_system(intel_no_lvds)) {
854 drm_WARN(&i915->drm, !i915->display.vbt.int_lvds_support,
855 "Useless DMI match. Internal LVDS support disabled by VBT\n");
856 return;
857 }
858
859 if (!i915->display.vbt.int_lvds_support) {
860 drm_dbg_kms(&i915->drm,
861 "Internal LVDS support disabled by VBT\n");
862 return;
863 }
864
865 if (HAS_PCH_SPLIT(i915))
866 lvds_reg = PCH_LVDS;
867 else
868 lvds_reg = LVDS;
869
870 lvds = intel_de_read(i915, lvds_reg);
871
872 if (HAS_PCH_SPLIT(i915)) {
873 if ((lvds & LVDS_DETECTED) == 0)
874 return;
875 }
876
877 ddc_pin = GMBUS_PIN_PANEL;
878 if (!intel_bios_is_lvds_present(display, &ddc_pin)) {
879 if ((lvds & LVDS_PORT_EN) == 0) {
880 drm_dbg_kms(&i915->drm,
881 "LVDS is not present in VBT\n");
882 return;
883 }
884 drm_dbg_kms(&i915->drm,
885 "LVDS is not present in VBT, but enabled anyway\n");
886 }
887
888 lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL);
889 if (!lvds_encoder)
890 return;
891
892 connector = intel_connector_alloc();
893 if (!connector) {
894 kfree(lvds_encoder);
895 return;
896 }
897
898 lvds_encoder->attached_connector = connector;
899 encoder = &lvds_encoder->base;
900
901 drm_connector_init_with_ddc(&i915->drm, &connector->base,
902 &intel_lvds_connector_funcs,
903 DRM_MODE_CONNECTOR_LVDS,
904 intel_gmbus_get_adapter(display, ddc_pin));
905
906 drm_encoder_init(&i915->drm, &encoder->base, &intel_lvds_enc_funcs,
907 DRM_MODE_ENCODER_LVDS, "LVDS");
908
909 encoder->enable = intel_enable_lvds;
910 encoder->pre_enable = intel_pre_enable_lvds;
911 encoder->compute_config = intel_lvds_compute_config;
912 if (HAS_PCH_SPLIT(i915)) {
913 encoder->disable = pch_disable_lvds;
914 encoder->post_disable = pch_post_disable_lvds;
915 } else {
916 encoder->disable = gmch_disable_lvds;
917 }
918 encoder->get_hw_state = intel_lvds_get_hw_state;
919 encoder->get_config = intel_lvds_get_config;
920 encoder->update_pipe = intel_backlight_update;
921 encoder->shutdown = intel_lvds_shutdown;
922 connector->get_hw_state = intel_connector_get_hw_state;
923
924 intel_connector_attach_encoder(connector, encoder);
925
926 encoder->type = INTEL_OUTPUT_LVDS;
927 encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
928 encoder->port = PORT_NONE;
929 encoder->cloneable = 0;
930 if (DISPLAY_VER(i915) < 4)
931 encoder->pipe_mask = BIT(PIPE_B);
932 else
933 encoder->pipe_mask = ~0;
934
935 drm_connector_helper_add(&connector->base, &intel_lvds_connector_helper_funcs);
936 connector->base.display_info.subpixel_order = SubPixelHorizontalRGB;
937
938 lvds_encoder->reg = lvds_reg;
939
940 intel_lvds_add_properties(&connector->base);
941
942 intel_lvds_pps_get_hw_state(i915, &lvds_encoder->init_pps);
943 lvds_encoder->init_lvds_val = lvds;
944
945 /*
946 * LVDS discovery:
947 * 1) check for EDID on DDC
948 * 2) check for VBT data
949 * 3) check to see if LVDS is already on
950 * if none of the above, no panel
951 */
952
953 /*
954 * Attempt to get the fixed panel mode from DDC. Assume that the
955 * preferred mode is the right one.
956 */
957 mutex_lock(&i915->drm.mode_config.mutex);
958 if (vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC)
959 drm_edid = drm_edid_read_switcheroo(&connector->base, connector->base.ddc);
960 else
961 drm_edid = drm_edid_read_ddc(&connector->base, connector->base.ddc);
962 if (drm_edid) {
963 if (drm_edid_connector_update(&connector->base, drm_edid) ||
964 !drm_edid_connector_add_modes(&connector->base)) {
965 drm_edid_connector_update(&connector->base, NULL);
966 drm_edid_free(drm_edid);
967 drm_edid = ERR_PTR(-EINVAL);
968 }
969 } else {
970 drm_edid = ERR_PTR(-ENOENT);
971 }
972 intel_bios_init_panel_late(display, &connector->panel, NULL,
973 IS_ERR(drm_edid) ? NULL : drm_edid);
974
975 /* Try EDID first */
976 intel_panel_add_edid_fixed_modes(connector, true);
977
978 /* Failed to get EDID, what about VBT? */
979 if (!intel_panel_preferred_fixed_mode(connector))
980 intel_panel_add_vbt_lfp_fixed_mode(connector);
981
982 /*
983 * If we didn't get a fixed mode from EDID or VBT, try checking
984 * if the panel is already turned on. If so, assume that
985 * whatever is currently programmed is the correct mode.
986 */
987 if (!intel_panel_preferred_fixed_mode(connector))
988 intel_panel_add_encoder_fixed_mode(connector, encoder);
989
990 mutex_unlock(&i915->drm.mode_config.mutex);
991
992 /* If we still don't have a mode after all that, give up. */
993 if (!intel_panel_preferred_fixed_mode(connector))
994 goto failed;
995
996 intel_panel_init(connector, drm_edid);
997
998 intel_backlight_setup(connector, INVALID_PIPE);
999
1000 lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder);
1001 drm_dbg_kms(&i915->drm, "detected %s-link lvds configuration\n",
1002 lvds_encoder->is_dual_link ? "dual" : "single");
1003
1004 lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK;
1005
1006 return;
1007
1008failed:
1009 drm_dbg_kms(&i915->drm, "No LVDS modes found, disabling.\n");
1010 drm_connector_cleanup(&connector->base);
1011 drm_encoder_cleanup(&encoder->base);
1012 kfree(lvds_encoder);
1013 intel_connector_free(connector);
1014 return;
1015}
1/*
2 * Copyright © 2006-2007 Intel Corporation
3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Dave Airlie <airlied@linux.ie>
27 * Jesse Barnes <jesse.barnes@intel.com>
28 */
29
30#include <acpi/button.h>
31#include <linux/acpi.h>
32#include <linux/dmi.h>
33#include <linux/i2c.h>
34#include <linux/slab.h>
35#include <linux/vga_switcheroo.h>
36
37#include <drm/drm_atomic_helper.h>
38#include <drm/drm_crtc.h>
39#include <drm/drm_edid.h>
40#include <drm/i915_drm.h>
41
42#include "i915_drv.h"
43#include "intel_atomic.h"
44#include "intel_connector.h"
45#include "intel_display_types.h"
46#include "intel_gmbus.h"
47#include "intel_lvds.h"
48#include "intel_panel.h"
49
50/* Private structure for the integrated LVDS support */
51struct intel_lvds_pps {
52 /* 100us units */
53 int t1_t2;
54 int t3;
55 int t4;
56 int t5;
57 int tx;
58
59 int divider;
60
61 int port;
62 bool powerdown_on_reset;
63};
64
65struct intel_lvds_encoder {
66 struct intel_encoder base;
67
68 bool is_dual_link;
69 i915_reg_t reg;
70 u32 a3_power;
71
72 struct intel_lvds_pps init_pps;
73 u32 init_lvds_val;
74
75 struct intel_connector *attached_connector;
76};
77
78static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder)
79{
80 return container_of(encoder, struct intel_lvds_encoder, base.base);
81}
82
83bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv,
84 i915_reg_t lvds_reg, enum pipe *pipe)
85{
86 u32 val;
87
88 val = I915_READ(lvds_reg);
89
90 /* asserts want to know the pipe even if the port is disabled */
91 if (HAS_PCH_CPT(dev_priv))
92 *pipe = (val & LVDS_PIPE_SEL_MASK_CPT) >> LVDS_PIPE_SEL_SHIFT_CPT;
93 else
94 *pipe = (val & LVDS_PIPE_SEL_MASK) >> LVDS_PIPE_SEL_SHIFT;
95
96 return val & LVDS_PORT_EN;
97}
98
99static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
100 enum pipe *pipe)
101{
102 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
103 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
104 intel_wakeref_t wakeref;
105 bool ret;
106
107 wakeref = intel_display_power_get_if_enabled(dev_priv,
108 encoder->power_domain);
109 if (!wakeref)
110 return false;
111
112 ret = intel_lvds_port_enabled(dev_priv, lvds_encoder->reg, pipe);
113
114 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
115
116 return ret;
117}
118
119static void intel_lvds_get_config(struct intel_encoder *encoder,
120 struct intel_crtc_state *pipe_config)
121{
122 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
123 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
124 u32 tmp, flags = 0;
125
126 pipe_config->output_types |= BIT(INTEL_OUTPUT_LVDS);
127
128 tmp = I915_READ(lvds_encoder->reg);
129 if (tmp & LVDS_HSYNC_POLARITY)
130 flags |= DRM_MODE_FLAG_NHSYNC;
131 else
132 flags |= DRM_MODE_FLAG_PHSYNC;
133 if (tmp & LVDS_VSYNC_POLARITY)
134 flags |= DRM_MODE_FLAG_NVSYNC;
135 else
136 flags |= DRM_MODE_FLAG_PVSYNC;
137
138 pipe_config->base.adjusted_mode.flags |= flags;
139
140 if (INTEL_GEN(dev_priv) < 5)
141 pipe_config->gmch_pfit.lvds_border_bits =
142 tmp & LVDS_BORDER_ENABLE;
143
144 /* gen2/3 store dither state in pfit control, needs to match */
145 if (INTEL_GEN(dev_priv) < 4) {
146 tmp = I915_READ(PFIT_CONTROL);
147
148 pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
149 }
150
151 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
152}
153
154static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv,
155 struct intel_lvds_pps *pps)
156{
157 u32 val;
158
159 pps->powerdown_on_reset = I915_READ(PP_CONTROL(0)) & PANEL_POWER_RESET;
160
161 val = I915_READ(PP_ON_DELAYS(0));
162 pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val);
163 pps->t1_t2 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val);
164 pps->t5 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val);
165
166 val = I915_READ(PP_OFF_DELAYS(0));
167 pps->t3 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val);
168 pps->tx = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val);
169
170 val = I915_READ(PP_DIVISOR(0));
171 pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val);
172 val = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, val);
173 /*
174 * Remove the BSpec specified +1 (100ms) offset that accounts for a
175 * too short power-cycle delay due to the asynchronous programming of
176 * the register.
177 */
178 if (val)
179 val--;
180 /* Convert from 100ms to 100us units */
181 pps->t4 = val * 1000;
182
183 if (INTEL_GEN(dev_priv) <= 4 &&
184 pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) {
185 DRM_DEBUG_KMS("Panel power timings uninitialized, "
186 "setting defaults\n");
187 /* Set T2 to 40ms and T5 to 200ms in 100 usec units */
188 pps->t1_t2 = 40 * 10;
189 pps->t5 = 200 * 10;
190 /* Set T3 to 35ms and Tx to 200ms in 100 usec units */
191 pps->t3 = 35 * 10;
192 pps->tx = 200 * 10;
193 }
194
195 DRM_DEBUG_DRIVER("LVDS PPS:t1+t2 %d t3 %d t4 %d t5 %d tx %d "
196 "divider %d port %d powerdown_on_reset %d\n",
197 pps->t1_t2, pps->t3, pps->t4, pps->t5, pps->tx,
198 pps->divider, pps->port, pps->powerdown_on_reset);
199}
200
201static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv,
202 struct intel_lvds_pps *pps)
203{
204 u32 val;
205
206 val = I915_READ(PP_CONTROL(0));
207 WARN_ON((val & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS);
208 if (pps->powerdown_on_reset)
209 val |= PANEL_POWER_RESET;
210 I915_WRITE(PP_CONTROL(0), val);
211
212 I915_WRITE(PP_ON_DELAYS(0),
213 REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, pps->port) |
214 REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, pps->t1_t2) |
215 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, pps->t5));
216
217 I915_WRITE(PP_OFF_DELAYS(0),
218 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, pps->t3) |
219 REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, pps->tx));
220
221 I915_WRITE(PP_DIVISOR(0),
222 REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) |
223 REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK,
224 DIV_ROUND_UP(pps->t4, 1000) + 1));
225}
226
227static void intel_pre_enable_lvds(struct intel_encoder *encoder,
228 const struct intel_crtc_state *pipe_config,
229 const struct drm_connector_state *conn_state)
230{
231 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
232 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
233 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
234 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
235 int pipe = crtc->pipe;
236 u32 temp;
237
238 if (HAS_PCH_SPLIT(dev_priv)) {
239 assert_fdi_rx_pll_disabled(dev_priv, pipe);
240 assert_shared_dpll_disabled(dev_priv,
241 pipe_config->shared_dpll);
242 } else {
243 assert_pll_disabled(dev_priv, pipe);
244 }
245
246 intel_lvds_pps_init_hw(dev_priv, &lvds_encoder->init_pps);
247
248 temp = lvds_encoder->init_lvds_val;
249 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
250
251 if (HAS_PCH_CPT(dev_priv)) {
252 temp &= ~LVDS_PIPE_SEL_MASK_CPT;
253 temp |= LVDS_PIPE_SEL_CPT(pipe);
254 } else {
255 temp &= ~LVDS_PIPE_SEL_MASK;
256 temp |= LVDS_PIPE_SEL(pipe);
257 }
258
259 /* set the corresponsding LVDS_BORDER bit */
260 temp &= ~LVDS_BORDER_ENABLE;
261 temp |= pipe_config->gmch_pfit.lvds_border_bits;
262
263 /*
264 * Set the B0-B3 data pairs corresponding to whether we're going to
265 * set the DPLLs for dual-channel mode or not.
266 */
267 if (lvds_encoder->is_dual_link)
268 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
269 else
270 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
271
272 /*
273 * It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
274 * appropriately here, but we need to look more thoroughly into how
275 * panels behave in the two modes. For now, let's just maintain the
276 * value we got from the BIOS.
277 */
278 temp &= ~LVDS_A3_POWER_MASK;
279 temp |= lvds_encoder->a3_power;
280
281 /*
282 * Set the dithering flag on LVDS as needed, note that there is no
283 * special lvds dither control bit on pch-split platforms, dithering is
284 * only controlled through the PIPECONF reg.
285 */
286 if (IS_GEN(dev_priv, 4)) {
287 /*
288 * Bspec wording suggests that LVDS port dithering only exists
289 * for 18bpp panels.
290 */
291 if (pipe_config->dither && pipe_config->pipe_bpp == 18)
292 temp |= LVDS_ENABLE_DITHER;
293 else
294 temp &= ~LVDS_ENABLE_DITHER;
295 }
296 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
297 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
298 temp |= LVDS_HSYNC_POLARITY;
299 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
300 temp |= LVDS_VSYNC_POLARITY;
301
302 I915_WRITE(lvds_encoder->reg, temp);
303}
304
305/*
306 * Sets the power state for the panel.
307 */
308static void intel_enable_lvds(struct intel_encoder *encoder,
309 const struct intel_crtc_state *pipe_config,
310 const struct drm_connector_state *conn_state)
311{
312 struct drm_device *dev = encoder->base.dev;
313 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
314 struct drm_i915_private *dev_priv = to_i915(dev);
315
316 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN);
317
318 I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) | PANEL_POWER_ON);
319 POSTING_READ(lvds_encoder->reg);
320
321 if (intel_de_wait_for_set(dev_priv, PP_STATUS(0), PP_ON, 5000))
322 DRM_ERROR("timed out waiting for panel to power on\n");
323
324 intel_panel_enable_backlight(pipe_config, conn_state);
325}
326
327static void intel_disable_lvds(struct intel_encoder *encoder,
328 const struct intel_crtc_state *old_crtc_state,
329 const struct drm_connector_state *old_conn_state)
330{
331 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
332 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
333
334 I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) & ~PANEL_POWER_ON);
335 if (intel_de_wait_for_clear(dev_priv, PP_STATUS(0), PP_ON, 1000))
336 DRM_ERROR("timed out waiting for panel to power off\n");
337
338 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN);
339 POSTING_READ(lvds_encoder->reg);
340}
341
342static void gmch_disable_lvds(struct intel_encoder *encoder,
343 const struct intel_crtc_state *old_crtc_state,
344 const struct drm_connector_state *old_conn_state)
345
346{
347 intel_panel_disable_backlight(old_conn_state);
348
349 intel_disable_lvds(encoder, old_crtc_state, old_conn_state);
350}
351
352static void pch_disable_lvds(struct intel_encoder *encoder,
353 const struct intel_crtc_state *old_crtc_state,
354 const struct drm_connector_state *old_conn_state)
355{
356 intel_panel_disable_backlight(old_conn_state);
357}
358
359static void pch_post_disable_lvds(struct intel_encoder *encoder,
360 const struct intel_crtc_state *old_crtc_state,
361 const struct drm_connector_state *old_conn_state)
362{
363 intel_disable_lvds(encoder, old_crtc_state, old_conn_state);
364}
365
366static enum drm_mode_status
367intel_lvds_mode_valid(struct drm_connector *connector,
368 struct drm_display_mode *mode)
369{
370 struct intel_connector *intel_connector = to_intel_connector(connector);
371 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
372 int max_pixclk = to_i915(connector->dev)->max_dotclk_freq;
373
374 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
375 return MODE_NO_DBLESCAN;
376 if (mode->hdisplay > fixed_mode->hdisplay)
377 return MODE_PANEL;
378 if (mode->vdisplay > fixed_mode->vdisplay)
379 return MODE_PANEL;
380 if (fixed_mode->clock > max_pixclk)
381 return MODE_CLOCK_HIGH;
382
383 return MODE_OK;
384}
385
386static int intel_lvds_compute_config(struct intel_encoder *intel_encoder,
387 struct intel_crtc_state *pipe_config,
388 struct drm_connector_state *conn_state)
389{
390 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
391 struct intel_lvds_encoder *lvds_encoder =
392 to_lvds_encoder(&intel_encoder->base);
393 struct intel_connector *intel_connector =
394 lvds_encoder->attached_connector;
395 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
396 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
397 unsigned int lvds_bpp;
398
399 /* Should never happen!! */
400 if (INTEL_GEN(dev_priv) < 4 && intel_crtc->pipe == 0) {
401 DRM_ERROR("Can't support LVDS on pipe A\n");
402 return -EINVAL;
403 }
404
405 if (lvds_encoder->a3_power == LVDS_A3_POWER_UP)
406 lvds_bpp = 8*3;
407 else
408 lvds_bpp = 6*3;
409
410 if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) {
411 DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n",
412 pipe_config->pipe_bpp, lvds_bpp);
413 pipe_config->pipe_bpp = lvds_bpp;
414 }
415
416 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
417
418 /*
419 * We have timings from the BIOS for the panel, put them in
420 * to the adjusted mode. The CRTC will be set up for this mode,
421 * with the panel scaling set up to source from the H/VDisplay
422 * of the original mode.
423 */
424 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
425 adjusted_mode);
426
427 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
428 return -EINVAL;
429
430 if (HAS_PCH_SPLIT(dev_priv)) {
431 pipe_config->has_pch_encoder = true;
432
433 intel_pch_panel_fitting(intel_crtc, pipe_config,
434 conn_state->scaling_mode);
435 } else {
436 intel_gmch_panel_fitting(intel_crtc, pipe_config,
437 conn_state->scaling_mode);
438
439 }
440
441 /*
442 * XXX: It would be nice to support lower refresh rates on the
443 * panels to reduce power consumption, and perhaps match the
444 * user's requested refresh rate.
445 */
446
447 return 0;
448}
449
450static enum drm_connector_status
451intel_lvds_detect(struct drm_connector *connector, bool force)
452{
453 return connector_status_connected;
454}
455
456/*
457 * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
458 */
459static int intel_lvds_get_modes(struct drm_connector *connector)
460{
461 struct intel_connector *intel_connector = to_intel_connector(connector);
462 struct drm_device *dev = connector->dev;
463 struct drm_display_mode *mode;
464
465 /* use cached edid if we have one */
466 if (!IS_ERR_OR_NULL(intel_connector->edid))
467 return drm_add_edid_modes(connector, intel_connector->edid);
468
469 mode = drm_mode_duplicate(dev, intel_connector->panel.fixed_mode);
470 if (mode == NULL)
471 return 0;
472
473 drm_mode_probed_add(connector, mode);
474 return 1;
475}
476
477static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
478 .get_modes = intel_lvds_get_modes,
479 .mode_valid = intel_lvds_mode_valid,
480 .atomic_check = intel_digital_connector_atomic_check,
481};
482
483static const struct drm_connector_funcs intel_lvds_connector_funcs = {
484 .detect = intel_lvds_detect,
485 .fill_modes = drm_helper_probe_single_connector_modes,
486 .atomic_get_property = intel_digital_connector_atomic_get_property,
487 .atomic_set_property = intel_digital_connector_atomic_set_property,
488 .late_register = intel_connector_register,
489 .early_unregister = intel_connector_unregister,
490 .destroy = intel_connector_destroy,
491 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
492 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
493};
494
495static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
496 .destroy = intel_encoder_destroy,
497};
498
499static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
500{
501 DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
502 return 1;
503}
504
505/* These systems claim to have LVDS, but really don't */
506static const struct dmi_system_id intel_no_lvds[] = {
507 {
508 .callback = intel_no_lvds_dmi_callback,
509 .ident = "Apple Mac Mini (Core series)",
510 .matches = {
511 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
512 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
513 },
514 },
515 {
516 .callback = intel_no_lvds_dmi_callback,
517 .ident = "Apple Mac Mini (Core 2 series)",
518 .matches = {
519 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
520 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
521 },
522 },
523 {
524 .callback = intel_no_lvds_dmi_callback,
525 .ident = "MSI IM-945GSE-A",
526 .matches = {
527 DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
528 DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
529 },
530 },
531 {
532 .callback = intel_no_lvds_dmi_callback,
533 .ident = "Dell Studio Hybrid",
534 .matches = {
535 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
536 DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
537 },
538 },
539 {
540 .callback = intel_no_lvds_dmi_callback,
541 .ident = "Dell OptiPlex FX170",
542 .matches = {
543 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
544 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
545 },
546 },
547 {
548 .callback = intel_no_lvds_dmi_callback,
549 .ident = "AOpen Mini PC",
550 .matches = {
551 DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
552 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
553 },
554 },
555 {
556 .callback = intel_no_lvds_dmi_callback,
557 .ident = "AOpen Mini PC MP915",
558 .matches = {
559 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
560 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
561 },
562 },
563 {
564 .callback = intel_no_lvds_dmi_callback,
565 .ident = "AOpen i915GMm-HFS",
566 .matches = {
567 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
568 DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
569 },
570 },
571 {
572 .callback = intel_no_lvds_dmi_callback,
573 .ident = "AOpen i45GMx-I",
574 .matches = {
575 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
576 DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
577 },
578 },
579 {
580 .callback = intel_no_lvds_dmi_callback,
581 .ident = "Aopen i945GTt-VFA",
582 .matches = {
583 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
584 },
585 },
586 {
587 .callback = intel_no_lvds_dmi_callback,
588 .ident = "Clientron U800",
589 .matches = {
590 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
591 DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
592 },
593 },
594 {
595 .callback = intel_no_lvds_dmi_callback,
596 .ident = "Clientron E830",
597 .matches = {
598 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
599 DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
600 },
601 },
602 {
603 .callback = intel_no_lvds_dmi_callback,
604 .ident = "Asus EeeBox PC EB1007",
605 .matches = {
606 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."),
607 DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"),
608 },
609 },
610 {
611 .callback = intel_no_lvds_dmi_callback,
612 .ident = "Asus AT5NM10T-I",
613 .matches = {
614 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
615 DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
616 },
617 },
618 {
619 .callback = intel_no_lvds_dmi_callback,
620 .ident = "Hewlett-Packard HP t5740",
621 .matches = {
622 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
623 DMI_MATCH(DMI_PRODUCT_NAME, " t5740"),
624 },
625 },
626 {
627 .callback = intel_no_lvds_dmi_callback,
628 .ident = "Hewlett-Packard t5745",
629 .matches = {
630 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
631 DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"),
632 },
633 },
634 {
635 .callback = intel_no_lvds_dmi_callback,
636 .ident = "Hewlett-Packard st5747",
637 .matches = {
638 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
639 DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"),
640 },
641 },
642 {
643 .callback = intel_no_lvds_dmi_callback,
644 .ident = "MSI Wind Box DC500",
645 .matches = {
646 DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
647 DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
648 },
649 },
650 {
651 .callback = intel_no_lvds_dmi_callback,
652 .ident = "Gigabyte GA-D525TUD",
653 .matches = {
654 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
655 DMI_MATCH(DMI_BOARD_NAME, "D525TUD"),
656 },
657 },
658 {
659 .callback = intel_no_lvds_dmi_callback,
660 .ident = "Supermicro X7SPA-H",
661 .matches = {
662 DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"),
663 DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"),
664 },
665 },
666 {
667 .callback = intel_no_lvds_dmi_callback,
668 .ident = "Fujitsu Esprimo Q900",
669 .matches = {
670 DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"),
671 DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"),
672 },
673 },
674 {
675 .callback = intel_no_lvds_dmi_callback,
676 .ident = "Intel D410PT",
677 .matches = {
678 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
679 DMI_MATCH(DMI_BOARD_NAME, "D410PT"),
680 },
681 },
682 {
683 .callback = intel_no_lvds_dmi_callback,
684 .ident = "Intel D425KT",
685 .matches = {
686 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
687 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"),
688 },
689 },
690 {
691 .callback = intel_no_lvds_dmi_callback,
692 .ident = "Intel D510MO",
693 .matches = {
694 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
695 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"),
696 },
697 },
698 {
699 .callback = intel_no_lvds_dmi_callback,
700 .ident = "Intel D525MW",
701 .matches = {
702 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
703 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"),
704 },
705 },
706 {
707 .callback = intel_no_lvds_dmi_callback,
708 .ident = "Radiant P845",
709 .matches = {
710 DMI_MATCH(DMI_SYS_VENDOR, "Radiant Systems Inc"),
711 DMI_MATCH(DMI_PRODUCT_NAME, "P845"),
712 },
713 },
714
715 { } /* terminating entry */
716};
717
718static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
719{
720 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
721 return 1;
722}
723
724static const struct dmi_system_id intel_dual_link_lvds[] = {
725 {
726 .callback = intel_dual_link_lvds_callback,
727 .ident = "Apple MacBook Pro 15\" (2010)",
728 .matches = {
729 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
730 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro6,2"),
731 },
732 },
733 {
734 .callback = intel_dual_link_lvds_callback,
735 .ident = "Apple MacBook Pro 15\" (2011)",
736 .matches = {
737 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
738 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
739 },
740 },
741 {
742 .callback = intel_dual_link_lvds_callback,
743 .ident = "Apple MacBook Pro 15\" (2012)",
744 .matches = {
745 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
746 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro9,1"),
747 },
748 },
749 { } /* terminating entry */
750};
751
752struct intel_encoder *intel_get_lvds_encoder(struct drm_i915_private *dev_priv)
753{
754 struct intel_encoder *encoder;
755
756 for_each_intel_encoder(&dev_priv->drm, encoder) {
757 if (encoder->type == INTEL_OUTPUT_LVDS)
758 return encoder;
759 }
760
761 return NULL;
762}
763
764bool intel_is_dual_link_lvds(struct drm_i915_private *dev_priv)
765{
766 struct intel_encoder *encoder = intel_get_lvds_encoder(dev_priv);
767
768 return encoder && to_lvds_encoder(&encoder->base)->is_dual_link;
769}
770
771static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
772{
773 struct drm_device *dev = lvds_encoder->base.base.dev;
774 unsigned int val;
775 struct drm_i915_private *dev_priv = to_i915(dev);
776
777 /* use the module option value if specified */
778 if (i915_modparams.lvds_channel_mode > 0)
779 return i915_modparams.lvds_channel_mode == 2;
780
781 /* single channel LVDS is limited to 112 MHz */
782 if (lvds_encoder->attached_connector->panel.fixed_mode->clock > 112999)
783 return true;
784
785 if (dmi_check_system(intel_dual_link_lvds))
786 return true;
787
788 /*
789 * BIOS should set the proper LVDS register value at boot, but
790 * in reality, it doesn't set the value when the lid is closed;
791 * we need to check "the value to be set" in VBT when LVDS
792 * register is uninitialized.
793 */
794 val = I915_READ(lvds_encoder->reg);
795 if (HAS_PCH_CPT(dev_priv))
796 val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK_CPT);
797 else
798 val &= ~(LVDS_DETECTED | LVDS_PIPE_SEL_MASK);
799 if (val == 0)
800 val = dev_priv->vbt.bios_lvds_val;
801
802 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
803}
804
805/**
806 * intel_lvds_init - setup LVDS connectors on this device
807 * @dev_priv: i915 device
808 *
809 * Create the connector, register the LVDS DDC bus, and try to figure out what
810 * modes we can display on the LVDS panel (if present).
811 */
812void intel_lvds_init(struct drm_i915_private *dev_priv)
813{
814 struct drm_device *dev = &dev_priv->drm;
815 struct intel_lvds_encoder *lvds_encoder;
816 struct intel_encoder *intel_encoder;
817 struct intel_connector *intel_connector;
818 struct drm_connector *connector;
819 struct drm_encoder *encoder;
820 struct drm_display_mode *fixed_mode = NULL;
821 struct drm_display_mode *downclock_mode = NULL;
822 struct edid *edid;
823 i915_reg_t lvds_reg;
824 u32 lvds;
825 u8 pin;
826 u32 allowed_scalers;
827
828 /* Skip init on machines we know falsely report LVDS */
829 if (dmi_check_system(intel_no_lvds)) {
830 WARN(!dev_priv->vbt.int_lvds_support,
831 "Useless DMI match. Internal LVDS support disabled by VBT\n");
832 return;
833 }
834
835 if (!dev_priv->vbt.int_lvds_support) {
836 DRM_DEBUG_KMS("Internal LVDS support disabled by VBT\n");
837 return;
838 }
839
840 if (HAS_PCH_SPLIT(dev_priv))
841 lvds_reg = PCH_LVDS;
842 else
843 lvds_reg = LVDS;
844
845 lvds = I915_READ(lvds_reg);
846
847 if (HAS_PCH_SPLIT(dev_priv)) {
848 if ((lvds & LVDS_DETECTED) == 0)
849 return;
850 }
851
852 pin = GMBUS_PIN_PANEL;
853 if (!intel_bios_is_lvds_present(dev_priv, &pin)) {
854 if ((lvds & LVDS_PORT_EN) == 0) {
855 DRM_DEBUG_KMS("LVDS is not present in VBT\n");
856 return;
857 }
858 DRM_DEBUG_KMS("LVDS is not present in VBT, but enabled anyway\n");
859 }
860
861 lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL);
862 if (!lvds_encoder)
863 return;
864
865 intel_connector = intel_connector_alloc();
866 if (!intel_connector) {
867 kfree(lvds_encoder);
868 return;
869 }
870
871 lvds_encoder->attached_connector = intel_connector;
872
873 intel_encoder = &lvds_encoder->base;
874 encoder = &intel_encoder->base;
875 connector = &intel_connector->base;
876 drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs,
877 DRM_MODE_CONNECTOR_LVDS);
878
879 drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs,
880 DRM_MODE_ENCODER_LVDS, "LVDS");
881
882 intel_encoder->enable = intel_enable_lvds;
883 intel_encoder->pre_enable = intel_pre_enable_lvds;
884 intel_encoder->compute_config = intel_lvds_compute_config;
885 if (HAS_PCH_SPLIT(dev_priv)) {
886 intel_encoder->disable = pch_disable_lvds;
887 intel_encoder->post_disable = pch_post_disable_lvds;
888 } else {
889 intel_encoder->disable = gmch_disable_lvds;
890 }
891 intel_encoder->get_hw_state = intel_lvds_get_hw_state;
892 intel_encoder->get_config = intel_lvds_get_config;
893 intel_encoder->update_pipe = intel_panel_update_backlight;
894 intel_connector->get_hw_state = intel_connector_get_hw_state;
895
896 intel_connector_attach_encoder(intel_connector, intel_encoder);
897
898 intel_encoder->type = INTEL_OUTPUT_LVDS;
899 intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
900 intel_encoder->port = PORT_NONE;
901 intel_encoder->cloneable = 0;
902 if (HAS_PCH_SPLIT(dev_priv))
903 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
904 else if (IS_GEN(dev_priv, 4))
905 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
906 else
907 intel_encoder->crtc_mask = (1 << 1);
908
909 drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
910 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
911 connector->interlace_allowed = false;
912 connector->doublescan_allowed = false;
913
914 lvds_encoder->reg = lvds_reg;
915
916 /* create the scaling mode property */
917 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT);
918 allowed_scalers |= BIT(DRM_MODE_SCALE_FULLSCREEN);
919 allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
920 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
921 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
922
923 intel_lvds_pps_get_hw_state(dev_priv, &lvds_encoder->init_pps);
924 lvds_encoder->init_lvds_val = lvds;
925
926 /*
927 * LVDS discovery:
928 * 1) check for EDID on DDC
929 * 2) check for VBT data
930 * 3) check to see if LVDS is already on
931 * if none of the above, no panel
932 */
933
934 /*
935 * Attempt to get the fixed panel mode from DDC. Assume that the
936 * preferred mode is the right one.
937 */
938 mutex_lock(&dev->mode_config.mutex);
939 if (vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC)
940 edid = drm_get_edid_switcheroo(connector,
941 intel_gmbus_get_adapter(dev_priv, pin));
942 else
943 edid = drm_get_edid(connector,
944 intel_gmbus_get_adapter(dev_priv, pin));
945 if (edid) {
946 if (drm_add_edid_modes(connector, edid)) {
947 drm_connector_update_edid_property(connector,
948 edid);
949 } else {
950 kfree(edid);
951 edid = ERR_PTR(-EINVAL);
952 }
953 } else {
954 edid = ERR_PTR(-ENOENT);
955 }
956 intel_connector->edid = edid;
957
958 fixed_mode = intel_panel_edid_fixed_mode(intel_connector);
959 if (fixed_mode)
960 goto out;
961
962 /* Failed to get EDID, what about VBT? */
963 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector);
964 if (fixed_mode)
965 goto out;
966
967 /*
968 * If we didn't get EDID, try checking if the panel is already turned
969 * on. If so, assume that whatever is currently programmed is the
970 * correct mode.
971 */
972 fixed_mode = intel_encoder_current_mode(intel_encoder);
973 if (fixed_mode) {
974 DRM_DEBUG_KMS("using current (BIOS) mode: ");
975 drm_mode_debug_printmodeline(fixed_mode);
976 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
977 }
978
979 /* If we still don't have a mode after all that, give up. */
980 if (!fixed_mode)
981 goto failed;
982
983out:
984 mutex_unlock(&dev->mode_config.mutex);
985
986 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
987 intel_panel_setup_backlight(connector, INVALID_PIPE);
988
989 lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder);
990 DRM_DEBUG_KMS("detected %s-link lvds configuration\n",
991 lvds_encoder->is_dual_link ? "dual" : "single");
992
993 lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK;
994
995 return;
996
997failed:
998 mutex_unlock(&dev->mode_config.mutex);
999
1000 DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
1001 drm_connector_cleanup(connector);
1002 drm_encoder_cleanup(encoder);
1003 kfree(lvds_encoder);
1004 intel_connector_free(intel_connector);
1005 return;
1006}