Loading...
Note: File does not exist in v6.13.7.
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright(c) 2016, Analogix Semiconductor. All rights reserved.
4 */
5
6#ifndef __ANX78xx_H
7#define __ANX78xx_H
8
9#define TX_P0 0x70
10#define TX_P1 0x7a
11#define TX_P2 0x72
12
13#define RX_P0 0x7e
14#define RX_P1 0x80
15
16/***************************************************************/
17/* Register definition of device address 0x7e */
18/***************************************************************/
19
20/*
21 * System Control and Status
22 */
23
24/* Software Reset Register 1 */
25#define SP_SOFTWARE_RESET1_REG 0x11
26#define SP_VIDEO_RST BIT(4)
27#define SP_HDCP_MAN_RST BIT(2)
28#define SP_TMDS_RST BIT(1)
29#define SP_SW_MAN_RST BIT(0)
30
31/* System Status Register */
32#define SP_SYSTEM_STATUS_REG 0x14
33#define SP_TMDS_CLOCK_DET BIT(1)
34#define SP_TMDS_DE_DET BIT(0)
35
36/* HDMI Status Register */
37#define SP_HDMI_STATUS_REG 0x15
38#define SP_HDMI_AUD_LAYOUT BIT(3)
39#define SP_HDMI_DET BIT(0)
40# define SP_DVI_MODE 0
41# define SP_HDMI_MODE 1
42
43/* HDMI Mute Control Register */
44#define SP_HDMI_MUTE_CTRL_REG 0x16
45#define SP_AUD_MUTE BIT(1)
46#define SP_VID_MUTE BIT(0)
47
48/* System Power Down Register 1 */
49#define SP_SYSTEM_POWER_DOWN1_REG 0x18
50#define SP_PWDN_CTRL BIT(0)
51
52/*
53 * Audio and Video Auto Control
54 */
55
56/* Auto Audio and Video Control register */
57#define SP_AUDVID_CTRL_REG 0x20
58#define SP_AVC_OE BIT(7)
59#define SP_AAC_OE BIT(6)
60#define SP_AVC_EN BIT(1)
61#define SP_AAC_EN BIT(0)
62
63/* Audio Exception Enable Registers */
64#define SP_AUD_EXCEPTION_ENABLE_BASE (0x24 - 1)
65/* Bits for Audio Exception Enable Register 3 */
66#define SP_AEC_EN21 BIT(5)
67
68/*
69 * Interrupt
70 */
71
72/* Interrupt Status Register 1 */
73#define SP_INT_STATUS1_REG 0x31
74/* Bits for Interrupt Status Register 1 */
75#define SP_HDMI_DVI BIT(7)
76#define SP_CKDT_CHG BIT(6)
77#define SP_SCDT_CHG BIT(5)
78#define SP_PCLK_CHG BIT(4)
79#define SP_PLL_UNLOCK BIT(3)
80#define SP_CABLE_PLUG_CHG BIT(2)
81#define SP_SET_MUTE BIT(1)
82#define SP_SW_INTR BIT(0)
83/* Bits for Interrupt Status Register 2 */
84#define SP_HDCP_ERR BIT(5)
85#define SP_AUDIO_SAMPLE_CHG BIT(0) /* undocumented */
86/* Bits for Interrupt Status Register 3 */
87#define SP_AUD_MODE_CHG BIT(0)
88/* Bits for Interrupt Status Register 5 */
89#define SP_AUDIO_RCV BIT(0)
90/* Bits for Interrupt Status Register 6 */
91#define SP_INT_STATUS6_REG 0x36
92#define SP_CTS_RCV BIT(7)
93#define SP_NEW_AUD_PKT BIT(4)
94#define SP_NEW_AVI_PKT BIT(1)
95#define SP_NEW_CP_PKT BIT(0)
96/* Bits for Interrupt Status Register 7 */
97#define SP_NO_VSI BIT(7)
98#define SP_NEW_VS BIT(4)
99
100/* Interrupt Mask 1 Status Registers */
101#define SP_INT_MASK1_REG 0x41
102
103/* HDMI US TIMER Control Register */
104#define SP_HDMI_US_TIMER_CTRL_REG 0x49
105#define SP_MS_TIMER_MARGIN_10_8_MASK 0x07
106
107/*
108 * TMDS Control
109 */
110
111/* TMDS Control Registers */
112#define SP_TMDS_CTRL_BASE (0x50 - 1)
113/* Bits for TMDS Control Register 7 */
114#define SP_PD_RT BIT(0)
115
116/*
117 * Video Control
118 */
119
120/* Video Status Register */
121#define SP_VIDEO_STATUS_REG 0x70
122#define SP_COLOR_DEPTH_MASK 0xf0
123#define SP_COLOR_DEPTH_SHIFT 4
124# define SP_COLOR_DEPTH_MODE_LEGACY 0x00
125# define SP_COLOR_DEPTH_MODE_24BIT 0x04
126# define SP_COLOR_DEPTH_MODE_30BIT 0x05
127# define SP_COLOR_DEPTH_MODE_36BIT 0x06
128# define SP_COLOR_DEPTH_MODE_48BIT 0x07
129
130/* Video Data Range Control Register */
131#define SP_VID_DATA_RANGE_CTRL_REG 0x83
132#define SP_R2Y_INPUT_LIMIT BIT(1)
133
134/* Pixel Clock High Resolution Counter Registers */
135#define SP_PCLK_HIGHRES_CNT_BASE (0x8c - 1)
136
137/*
138 * Audio Control
139 */
140
141/* Number of Audio Channels Status Registers */
142#define SP_AUD_CH_STATUS_REG_NUM 6
143
144/* Audio IN S/PDIF Channel Status Registers */
145#define SP_AUD_SPDIF_CH_STATUS_BASE 0xc7
146
147/* Audio IN S/PDIF Channel Status Register 4 */
148#define SP_FS_FREQ_MASK 0x0f
149# define SP_FS_FREQ_44100HZ 0x00
150# define SP_FS_FREQ_48000HZ 0x02
151# define SP_FS_FREQ_32000HZ 0x03
152# define SP_FS_FREQ_88200HZ 0x08
153# define SP_FS_FREQ_96000HZ 0x0a
154# define SP_FS_FREQ_176400HZ 0x0c
155# define SP_FS_FREQ_192000HZ 0x0e
156
157/*
158 * Micellaneous Control Block
159 */
160
161/* CHIP Control Register */
162#define SP_CHIP_CTRL_REG 0xe3
163#define SP_MAN_HDMI5V_DET BIT(3)
164#define SP_PLLLOCK_CKDT_EN BIT(2)
165#define SP_ANALOG_CKDT_EN BIT(1)
166#define SP_DIGITAL_CKDT_EN BIT(0)
167
168/* Packet Receiving Status Register */
169#define SP_PACKET_RECEIVING_STATUS_REG 0xf3
170#define SP_AVI_RCVD BIT(5)
171#define SP_VSI_RCVD BIT(1)
172
173/***************************************************************/
174/* Register definition of device address 0x80 */
175/***************************************************************/
176
177/* HDCP BCAPS Shadow Register */
178#define SP_HDCP_BCAPS_SHADOW_REG 0x2a
179#define SP_BCAPS_REPEATER BIT(5)
180
181/* HDCP Status Register */
182#define SP_RX_HDCP_STATUS_REG 0x3f
183#define SP_AUTH_EN BIT(4)
184
185/*
186 * InfoFrame and Control Packet Registers
187 */
188
189/* AVI InfoFrame packet checksum */
190#define SP_AVI_INFOFRAME_CHECKSUM 0xa3
191
192/* AVI InfoFrame Registers */
193#define SP_AVI_INFOFRAME_DATA_BASE 0xa4
194
195#define SP_AVI_COLOR_F_MASK 0x60
196#define SP_AVI_COLOR_F_SHIFT 5
197
198/* Audio InfoFrame Registers */
199#define SP_AUD_INFOFRAME_DATA_BASE 0xc4
200#define SP_AUD_INFOFRAME_LAYOUT_MASK 0x0f
201
202/* MPEG/HDMI Vendor Specific InfoFrame Packet type code */
203#define SP_MPEG_VS_INFOFRAME_TYPE_REG 0xe0
204
205/* MPEG/HDMI Vendor Specific InfoFrame Packet length */
206#define SP_MPEG_VS_INFOFRAME_LEN_REG 0xe2
207
208/* MPEG/HDMI Vendor Specific InfoFrame Packet version number */
209#define SP_MPEG_VS_INFOFRAME_VER_REG 0xe1
210
211/* MPEG/HDMI Vendor Specific InfoFrame Packet content */
212#define SP_MPEG_VS_INFOFRAME_DATA_BASE 0xe4
213
214/* General Control Packet Register */
215#define SP_GENERAL_CTRL_PACKET_REG 0x9f
216#define SP_CLEAR_AVMUTE BIT(4)
217#define SP_SET_AVMUTE BIT(0)
218
219/***************************************************************/
220/* Register definition of device address 0x70 */
221/***************************************************************/
222
223/* HDCP Status Register */
224#define SP_TX_HDCP_STATUS_REG 0x00
225#define SP_AUTH_FAIL BIT(5)
226#define SP_AUTHEN_PASS BIT(1)
227
228/* HDCP Control Register 0 */
229#define SP_HDCP_CTRL0_REG 0x01
230#define SP_RX_REPEATER BIT(6)
231#define SP_RE_AUTH BIT(5)
232#define SP_SW_AUTH_OK BIT(4)
233#define SP_HARD_AUTH_EN BIT(3)
234#define SP_HDCP_ENC_EN BIT(2)
235#define SP_BKSV_SRM_PASS BIT(1)
236#define SP_KSVLIST_VLD BIT(0)
237/* HDCP Function Enabled */
238#define SP_HDCP_FUNCTION_ENABLED (BIT(0) | BIT(1) | BIT(2) | BIT(3))
239
240/* HDCP Receiver BSTATUS Register 0 */
241#define SP_HDCP_RX_BSTATUS0_REG 0x1b
242/* HDCP Receiver BSTATUS Register 1 */
243#define SP_HDCP_RX_BSTATUS1_REG 0x1c
244
245/* HDCP Embedded "Blue Screen" Content Registers */
246#define SP_HDCP_VID0_BLUE_SCREEN_REG 0x2c
247#define SP_HDCP_VID1_BLUE_SCREEN_REG 0x2d
248#define SP_HDCP_VID2_BLUE_SCREEN_REG 0x2e
249
250/* HDCP Wait R0 Timing Register */
251#define SP_HDCP_WAIT_R0_TIME_REG 0x40
252
253/* HDCP Link Integrity Check Timer Register */
254#define SP_HDCP_LINK_CHECK_TIMER_REG 0x41
255
256/* HDCP Repeater Ready Wait Timer Register */
257#define SP_HDCP_RPTR_RDY_WAIT_TIME_REG 0x42
258
259/* HDCP Auto Timer Register */
260#define SP_HDCP_AUTO_TIMER_REG 0x51
261
262/* HDCP Key Status Register */
263#define SP_HDCP_KEY_STATUS_REG 0x5e
264
265/* HDCP Key Command Register */
266#define SP_HDCP_KEY_COMMAND_REG 0x5f
267#define SP_DISABLE_SYNC_HDCP BIT(2)
268
269/* OTP Memory Key Protection Registers */
270#define SP_OTP_KEY_PROTECT1_REG 0x60
271#define SP_OTP_KEY_PROTECT2_REG 0x61
272#define SP_OTP_KEY_PROTECT3_REG 0x62
273#define SP_OTP_PSW1 0xa2
274#define SP_OTP_PSW2 0x7e
275#define SP_OTP_PSW3 0xc6
276
277/* DP System Control Registers */
278#define SP_DP_SYSTEM_CTRL_BASE (0x80 - 1)
279/* Bits for DP System Control Register 2 */
280#define SP_CHA_STA BIT(2)
281/* Bits for DP System Control Register 3 */
282#define SP_HPD_STATUS BIT(6)
283#define SP_STRM_VALID BIT(2)
284/* Bits for DP System Control Register 4 */
285#define SP_ENHANCED_MODE BIT(3)
286
287/* DP Video Control Register */
288#define SP_DP_VIDEO_CTRL_REG 0x84
289#define SP_COLOR_F_MASK 0x06
290#define SP_COLOR_F_SHIFT 1
291#define SP_BPC_MASK 0xe0
292#define SP_BPC_SHIFT 5
293# define SP_BPC_6BITS 0x00
294# define SP_BPC_8BITS 0x01
295# define SP_BPC_10BITS 0x02
296# define SP_BPC_12BITS 0x03
297
298/* DP Audio Control Register */
299#define SP_DP_AUDIO_CTRL_REG 0x87
300#define SP_AUD_EN BIT(0)
301
302/* 10us Pulse Generate Timer Registers */
303#define SP_I2C_GEN_10US_TIMER0_REG 0x88
304#define SP_I2C_GEN_10US_TIMER1_REG 0x89
305
306/* Packet Send Control Register */
307#define SP_PACKET_SEND_CTRL_REG 0x90
308#define SP_AUD_IF_UP BIT(7)
309#define SP_AVI_IF_UD BIT(6)
310#define SP_MPEG_IF_UD BIT(5)
311#define SP_SPD_IF_UD BIT(4)
312#define SP_AUD_IF_EN BIT(3)
313#define SP_AVI_IF_EN BIT(2)
314#define SP_MPEG_IF_EN BIT(1)
315#define SP_SPD_IF_EN BIT(0)
316
317/* DP HDCP Control Register */
318#define SP_DP_HDCP_CTRL_REG 0x92
319#define SP_AUTO_EN BIT(7)
320#define SP_AUTO_START BIT(5)
321#define SP_LINK_POLLING BIT(1)
322
323/* DP Main Link Bandwidth Setting Register */
324#define SP_DP_MAIN_LINK_BW_SET_REG 0xa0
325#define SP_LINK_BW_SET_MASK 0x1f
326#define SP_INITIAL_SLIM_M_AUD_SEL BIT(5)
327
328/* DP Training Pattern Set Register */
329#define SP_DP_TRAINING_PATTERN_SET_REG 0xa2
330
331/* DP Lane 0 Link Training Control Register */
332#define SP_DP_LANE0_LT_CTRL_REG 0xa3
333#define SP_TX_SW_SET_MASK 0x1b
334#define SP_MAX_PRE_REACH BIT(5)
335#define SP_MAX_DRIVE_REACH BIT(4)
336#define SP_PRE_EMP_LEVEL1 BIT(3)
337#define SP_DRVIE_CURRENT_LEVEL1 BIT(0)
338
339/* DP Link Training Control Register */
340#define SP_DP_LT_CTRL_REG 0xa8
341#define SP_LT_ERROR_TYPE_MASK 0x70
342# define SP_LT_NO_ERROR 0x00
343# define SP_LT_AUX_WRITE_ERROR 0x01
344# define SP_LT_MAX_DRIVE_REACHED 0x02
345# define SP_LT_WRONG_LANE_COUNT_SET 0x03
346# define SP_LT_LOOP_SAME_5_TIME 0x04
347# define SP_LT_CR_FAIL_IN_EQ 0x05
348# define SP_LT_EQ_LOOP_5_TIME 0x06
349#define SP_LT_EN BIT(0)
350
351/* DP CEP Training Control Registers */
352#define SP_DP_CEP_TRAINING_CTRL0_REG 0xa9
353#define SP_DP_CEP_TRAINING_CTRL1_REG 0xaa
354
355/* DP Debug Register 1 */
356#define SP_DP_DEBUG1_REG 0xb0
357#define SP_DEBUG_PLL_LOCK BIT(4)
358#define SP_POLLING_EN BIT(1)
359
360/* DP Polling Control Register */
361#define SP_DP_POLLING_CTRL_REG 0xb4
362#define SP_AUTO_POLLING_DISABLE BIT(0)
363
364/* DP Link Debug Control Register */
365#define SP_DP_LINK_DEBUG_CTRL_REG 0xb8
366#define SP_M_VID_DEBUG BIT(5)
367#define SP_NEW_PRBS7 BIT(4)
368#define SP_INSERT_ER BIT(1)
369#define SP_PRBS31_EN BIT(0)
370
371/* AUX Misc control Register */
372#define SP_AUX_MISC_CTRL_REG 0xbf
373
374/* DP PLL control Register */
375#define SP_DP_PLL_CTRL_REG 0xc7
376#define SP_PLL_RST BIT(6)
377
378/* DP Analog Power Down Register */
379#define SP_DP_ANALOG_POWER_DOWN_REG 0xc8
380#define SP_CH0_PD BIT(0)
381
382/* DP Misc Control Register */
383#define SP_DP_MISC_CTRL_REG 0xcd
384#define SP_EQ_TRAINING_LOOP BIT(6)
385
386/* DP Extra I2C Device Address Register */
387#define SP_DP_EXTRA_I2C_DEV_ADDR_REG 0xce
388#define SP_I2C_STRETCH_DISABLE BIT(7)
389
390#define SP_I2C_EXTRA_ADDR 0x50
391
392/* DP Downspread Control Register 1 */
393#define SP_DP_DOWNSPREAD_CTRL1_REG 0xd0
394
395/* DP M Value Calculation Control Register */
396#define SP_DP_M_CALCULATION_CTRL_REG 0xd9
397#define SP_M_GEN_CLK_SEL BIT(0)
398
399/* AUX Channel Access Status Register */
400#define SP_AUX_CH_STATUS_REG 0xe0
401#define SP_AUX_STATUS 0x0f
402
403/* AUX Channel DEFER Control Register */
404#define SP_AUX_DEFER_CTRL_REG 0xe2
405#define SP_DEFER_CTRL_EN BIT(7)
406
407/* DP Buffer Data Count Register */
408#define SP_BUF_DATA_COUNT_REG 0xe4
409#define SP_BUF_DATA_COUNT_MASK 0x1f
410#define SP_BUF_CLR BIT(7)
411
412/* DP AUX Channel Control Register 1 */
413#define SP_DP_AUX_CH_CTRL1_REG 0xe5
414#define SP_AUX_TX_COMM_MASK 0x0f
415#define SP_AUX_LENGTH_MASK 0xf0
416#define SP_AUX_LENGTH_SHIFT 4
417
418/* DP AUX CH Address Register 0 */
419#define SP_AUX_ADDR_7_0_REG 0xe6
420
421/* DP AUX CH Address Register 1 */
422#define SP_AUX_ADDR_15_8_REG 0xe7
423
424/* DP AUX CH Address Register 2 */
425#define SP_AUX_ADDR_19_16_REG 0xe8
426#define SP_AUX_ADDR_19_16_MASK 0x0f
427
428/* DP AUX Channel Control Register 2 */
429#define SP_DP_AUX_CH_CTRL2_REG 0xe9
430#define SP_AUX_SEL_RXCM BIT(6)
431#define SP_AUX_CHSEL BIT(3)
432#define SP_AUX_PN_INV BIT(2)
433#define SP_ADDR_ONLY BIT(1)
434#define SP_AUX_EN BIT(0)
435
436/* DP Video Stream Control InfoFrame Register */
437#define SP_DP_3D_VSC_CTRL_REG 0xea
438#define SP_INFO_FRAME_VSC_EN BIT(0)
439
440/* DP Video Stream Data Byte 1 Register */
441#define SP_DP_VSC_DB1_REG 0xeb
442
443/* DP AUX Channel Control Register 3 */
444#define SP_DP_AUX_CH_CTRL3_REG 0xec
445#define SP_WAIT_COUNTER_7_0_MASK 0xff
446
447/* DP AUX Channel Control Register 4 */
448#define SP_DP_AUX_CH_CTRL4_REG 0xed
449
450/* DP AUX Buffer Data Registers */
451#define SP_DP_BUF_DATA0_REG 0xf0
452
453/***************************************************************/
454/* Register definition of device address 0x72 */
455/***************************************************************/
456
457/*
458 * Core Register Definitions
459 */
460
461/* Device ID Low Byte Register */
462#define SP_DEVICE_IDL_REG 0x02
463
464/* Device ID High Byte Register */
465#define SP_DEVICE_IDH_REG 0x03
466
467/* Device version register */
468#define SP_DEVICE_VERSION_REG 0x04
469
470/* Power Down Control Register */
471#define SP_POWERDOWN_CTRL_REG 0x05
472#define SP_REGISTER_PD BIT(7)
473#define SP_HDCP_PD BIT(5)
474#define SP_AUDIO_PD BIT(4)
475#define SP_VIDEO_PD BIT(3)
476#define SP_LINK_PD BIT(2)
477#define SP_TOTAL_PD BIT(1)
478
479/* Reset Control Register 1 */
480#define SP_RESET_CTRL1_REG 0x06
481#define SP_MISC_RST BIT(7)
482#define SP_VIDCAP_RST BIT(6)
483#define SP_VIDFIF_RST BIT(5)
484#define SP_AUDFIF_RST BIT(4)
485#define SP_AUDCAP_RST BIT(3)
486#define SP_HDCP_RST BIT(2)
487#define SP_SW_RST BIT(1)
488#define SP_HW_RST BIT(0)
489
490/* Reset Control Register 2 */
491#define SP_RESET_CTRL2_REG 0x07
492#define SP_AUX_RST BIT(2)
493#define SP_SERDES_FIFO_RST BIT(1)
494#define SP_I2C_REG_RST BIT(0)
495
496/* Video Control Register 1 */
497#define SP_VID_CTRL1_REG 0x08
498#define SP_VIDEO_EN BIT(7)
499#define SP_VIDEO_MUTE BIT(2)
500#define SP_DE_GEN BIT(1)
501#define SP_DEMUX BIT(0)
502
503/* Video Control Register 2 */
504#define SP_VID_CTRL2_REG 0x09
505#define SP_IN_COLOR_F_MASK 0x03
506#define SP_IN_YC_BIT_SEL BIT(2)
507#define SP_IN_BPC_MASK 0x70
508#define SP_IN_BPC_SHIFT 4
509# define SP_IN_BPC_12BIT 0x03
510# define SP_IN_BPC_10BIT 0x02
511# define SP_IN_BPC_8BIT 0x01
512# define SP_IN_BPC_6BIT 0x00
513#define SP_IN_D_RANGE BIT(7)
514
515/* Video Control Register 3 */
516#define SP_VID_CTRL3_REG 0x0a
517#define SP_HPD_OUT BIT(6)
518
519/* Video Control Register 5 */
520#define SP_VID_CTRL5_REG 0x0c
521#define SP_CSC_STD_SEL BIT(7)
522#define SP_XVYCC_RNG_LMT BIT(6)
523#define SP_RANGE_Y2R BIT(5)
524#define SP_CSPACE_Y2R BIT(4)
525#define SP_RGB_RNG_LMT BIT(3)
526#define SP_Y_RNG_LMT BIT(2)
527#define SP_RANGE_R2Y BIT(1)
528#define SP_CSPACE_R2Y BIT(0)
529
530/* Video Control Register 6 */
531#define SP_VID_CTRL6_REG 0x0d
532#define SP_TEST_PATTERN_EN BIT(7)
533#define SP_VIDEO_PROCESS_EN BIT(6)
534#define SP_VID_US_MODE BIT(3)
535#define SP_VID_DS_MODE BIT(2)
536#define SP_UP_SAMPLE BIT(1)
537#define SP_DOWN_SAMPLE BIT(0)
538
539/* Video Control Register 8 */
540#define SP_VID_CTRL8_REG 0x0f
541#define SP_VID_VRES_TH BIT(0)
542
543/* Total Line Status Low Byte Register */
544#define SP_TOTAL_LINE_STAL_REG 0x24
545
546/* Total Line Status High Byte Register */
547#define SP_TOTAL_LINE_STAH_REG 0x25
548
549/* Active Line Status Low Byte Register */
550#define SP_ACT_LINE_STAL_REG 0x26
551
552/* Active Line Status High Byte Register */
553#define SP_ACT_LINE_STAH_REG 0x27
554
555/* Vertical Front Porch Status Register */
556#define SP_V_F_PORCH_STA_REG 0x28
557
558/* Vertical SYNC Width Status Register */
559#define SP_V_SYNC_STA_REG 0x29
560
561/* Vertical Back Porch Status Register */
562#define SP_V_B_PORCH_STA_REG 0x2a
563
564/* Total Pixel Status Low Byte Register */
565#define SP_TOTAL_PIXEL_STAL_REG 0x2b
566
567/* Total Pixel Status High Byte Register */
568#define SP_TOTAL_PIXEL_STAH_REG 0x2c
569
570/* Active Pixel Status Low Byte Register */
571#define SP_ACT_PIXEL_STAL_REG 0x2d
572
573/* Active Pixel Status High Byte Register */
574#define SP_ACT_PIXEL_STAH_REG 0x2e
575
576/* Horizontal Front Porch Status Low Byte Register */
577#define SP_H_F_PORCH_STAL_REG 0x2f
578
579/* Horizontal Front Porch Statys High Byte Register */
580#define SP_H_F_PORCH_STAH_REG 0x30
581
582/* Horizontal SYNC Width Status Low Byte Register */
583#define SP_H_SYNC_STAL_REG 0x31
584
585/* Horizontal SYNC Width Status High Byte Register */
586#define SP_H_SYNC_STAH_REG 0x32
587
588/* Horizontal Back Porch Status Low Byte Register */
589#define SP_H_B_PORCH_STAL_REG 0x33
590
591/* Horizontal Back Porch Status High Byte Register */
592#define SP_H_B_PORCH_STAH_REG 0x34
593
594/* InfoFrame AVI Packet DB1 Register */
595#define SP_INFOFRAME_AVI_DB1_REG 0x70
596
597/* Bit Control Specific Register */
598#define SP_BIT_CTRL_SPECIFIC_REG 0x80
599#define SP_BIT_CTRL_SELECT_SHIFT 1
600#define SP_ENABLE_BIT_CTRL BIT(0)
601
602/* InfoFrame Audio Packet DB1 Register */
603#define SP_INFOFRAME_AUD_DB1_REG 0x83
604
605/* InfoFrame MPEG Packet DB1 Register */
606#define SP_INFOFRAME_MPEG_DB1_REG 0xb0
607
608/* Audio Channel Status Registers */
609#define SP_AUD_CH_STATUS_BASE 0xd0
610
611/* Audio Channel Num Register 5 */
612#define SP_I2S_CHANNEL_NUM_MASK 0xe0
613# define SP_I2S_CH_NUM_1 (0x00 << 5)
614# define SP_I2S_CH_NUM_2 (0x01 << 5)
615# define SP_I2S_CH_NUM_3 (0x02 << 5)
616# define SP_I2S_CH_NUM_4 (0x03 << 5)
617# define SP_I2S_CH_NUM_5 (0x04 << 5)
618# define SP_I2S_CH_NUM_6 (0x05 << 5)
619# define SP_I2S_CH_NUM_7 (0x06 << 5)
620# define SP_I2S_CH_NUM_8 (0x07 << 5)
621#define SP_EXT_VUCP BIT(2)
622#define SP_VBIT BIT(1)
623#define SP_AUDIO_LAYOUT BIT(0)
624
625/* Analog Debug Register 2 */
626#define SP_ANALOG_DEBUG2_REG 0xdd
627#define SP_FORCE_SW_OFF_BYPASS 0x20
628#define SP_XTAL_FRQ 0x1c
629# define SP_XTAL_FRQ_19M2 (0x00 << 2)
630# define SP_XTAL_FRQ_24M (0x01 << 2)
631# define SP_XTAL_FRQ_25M (0x02 << 2)
632# define SP_XTAL_FRQ_26M (0x03 << 2)
633# define SP_XTAL_FRQ_27M (0x04 << 2)
634# define SP_XTAL_FRQ_38M4 (0x05 << 2)
635# define SP_XTAL_FRQ_52M (0x06 << 2)
636#define SP_POWERON_TIME_1P5MS 0x03
637
638/* Analog Control 0 Register */
639#define SP_ANALOG_CTRL0_REG 0xe1
640
641/* Common Interrupt Status Register 1 */
642#define SP_COMMON_INT_STATUS_BASE (0xf1 - 1)
643#define SP_PLL_LOCK_CHG 0x40
644
645/* Common Interrupt Status Register 2 */
646#define SP_COMMON_INT_STATUS2 0xf2
647#define SP_HDCP_AUTH_CHG BIT(1)
648#define SP_HDCP_AUTH_DONE BIT(0)
649
650#define SP_HDCP_LINK_CHECK_FAIL BIT(0)
651
652/* Common Interrupt Status Register 4 */
653#define SP_COMMON_INT_STATUS4_REG 0xf4
654#define SP_HPD_IRQ BIT(6)
655#define SP_HPD_ESYNC_ERR BIT(4)
656#define SP_HPD_CHG BIT(2)
657#define SP_HPD_LOST BIT(1)
658#define SP_HPD_PLUG BIT(0)
659
660/* DP Interrupt Status Register */
661#define SP_DP_INT_STATUS1_REG 0xf7
662#define SP_TRAINING_FINISH BIT(5)
663#define SP_POLLING_ERR BIT(4)
664
665/* Common Interrupt Mask Register */
666#define SP_COMMON_INT_MASK_BASE (0xf8 - 1)
667
668#define SP_COMMON_INT_MASK4_REG 0xfb
669
670/* DP Interrupts Mask Register */
671#define SP_DP_INT_MASK1_REG 0xfe
672
673/* Interrupt Control Register */
674#define SP_INT_CTRL_REG 0xff
675
676/***************************************************************/
677/* Register definition of device address 0x7a */
678/***************************************************************/
679
680/* DP TX Link Training Control Register */
681#define SP_DP_TX_LT_CTRL0_REG 0x30
682
683/* PD 1.2 Lint Training 80bit Pattern Register */
684#define SP_DP_LT_80BIT_PATTERN0_REG 0x80
685#define SP_DP_LT_80BIT_PATTERN_REG_NUM 10
686
687/* Audio Interface Control Register 0 */
688#define SP_AUD_INTERFACE_CTRL0_REG 0x5f
689#define SP_AUD_INTERFACE_DISABLE 0x80
690
691/* Audio Interface Control Register 2 */
692#define SP_AUD_INTERFACE_CTRL2_REG 0x60
693#define SP_M_AUD_ADJUST_ST 0x04
694
695/* Audio Interface Control Register 3 */
696#define SP_AUD_INTERFACE_CTRL3_REG 0x62
697
698/* Audio Interface Control Register 4 */
699#define SP_AUD_INTERFACE_CTRL4_REG 0x67
700
701/* Audio Interface Control Register 5 */
702#define SP_AUD_INTERFACE_CTRL5_REG 0x68
703
704/* Audio Interface Control Register 6 */
705#define SP_AUD_INTERFACE_CTRL6_REG 0x69
706
707/* Firmware Version Register */
708#define SP_FW_VER_REG 0xb7
709
710#endif