Loading...
1# SPDX-License-Identifier: MIT
2# Copyright © 2019-2024 Advanced Micro Devices, Inc. All rights reserved.
3
4menu "Display Engine Configuration"
5 depends on DRM && DRM_AMDGPU
6
7config DRM_AMD_DC
8 bool "AMD DC - Enable new display engine"
9 default y
10 depends on BROKEN || !CC_IS_CLANG || ARM64 || LOONGARCH || RISCV || SPARC64 || X86_64
11 select SND_HDA_COMPONENT if SND_HDA_CORE
12 # !CC_IS_CLANG: https://github.com/ClangBuiltLinux/linux/issues/1752
13 select DRM_AMD_DC_FP if ARCH_HAS_KERNEL_FPU_SUPPORT && !(CC_IS_CLANG && (ARM64 || LOONGARCH || RISCV))
14 help
15 Choose this option if you want to use the new display engine
16 support for AMDGPU. This adds required support for Vega and
17 Raven ASICs.
18
19 calculate_bandwidth() is presently broken on all !(X86_64 || SPARC64 ||
20 ARM64 || LOONGARCH || RISCV) architectures built with Clang (all released
21 versions), whereby the stack frame gets blown up to well over 5k. This
22 would cause an immediate kernel panic on most architectures. We'll revert
23 this when the following bug report has been resolved:
24 https://github.com/llvm/llvm-project/issues/41896.
25
26config DRM_AMD_DC_FP
27 def_bool n
28 help
29 Floating point support, required for DCN-based SoCs
30
31config DRM_AMD_DC_SI
32 bool "AMD DC support for Southern Islands ASICs"
33 depends on DRM_AMDGPU_SI
34 depends on DRM_AMD_DC
35 help
36 Choose this option to enable new AMD DC support for SI asics
37 by default. This includes Tahiti, Pitcairn, Cape Verde, Oland.
38 Hainan is not supported by AMD DC and it has no physical DCE6.
39
40config DEBUG_KERNEL_DC
41 bool "Enable kgdb break in DC"
42 depends on DRM_AMD_DC
43 depends on KGDB
44 help
45 Choose this option if you want to hit kdgb_break in assert.
46
47config DRM_AMD_SECURE_DISPLAY
48 bool "Enable secure display support"
49 depends on DEBUG_FS
50 depends on DRM_AMD_DC_FP
51 help
52 Choose this option if you want to support secure display
53
54 This option enables the calculation of crc of specific region via
55 debugfs. Cooperate with specific DMCU FW.
56
57endmenu
1# SPDX-License-Identifier: GPL-2.0-only
2menu "Display Engine Configuration"
3 depends on DRM && DRM_AMDGPU
4
5config DRM_AMD_DC
6 bool "AMD DC - Enable new display engine"
7 default y
8 select SND_HDA_COMPONENT if SND_HDA_CORE
9 select DRM_AMD_DC_DCN1_0 if X86 && !(KCOV_INSTRUMENT_ALL && KCOV_ENABLE_COMPARISONS)
10 help
11 Choose this option if you want to use the new display engine
12 support for AMDGPU. This adds required support for Vega and
13 Raven ASICs.
14
15config DRM_AMD_DC_DCN1_0
16 def_bool n
17 help
18 RV family support for display engine
19
20config DRM_AMD_DC_DCN2_0
21 bool "DCN 2.0 family"
22 default y
23 depends on DRM_AMD_DC && X86
24 depends on DRM_AMD_DC_DCN1_0
25 help
26 Choose this option if you want to have
27 Navi support for display engine
28
29config DRM_AMD_DC_DCN2_1
30 bool "DCN 2.1 family"
31 depends on DRM_AMD_DC && X86
32 depends on DRM_AMD_DC_DCN2_0
33 help
34 Choose this option if you want to have
35 Renoir support for display engine
36
37config DRM_AMD_DC_DSC_SUPPORT
38 bool "DSC support"
39 default y
40 depends on DRM_AMD_DC && X86
41 depends on DRM_AMD_DC_DCN1_0
42 depends on DRM_AMD_DC_DCN2_0
43 help
44 Choose this option if you want to have
45 Dynamic Stream Compression support
46
47config DEBUG_KERNEL_DC
48 bool "Enable kgdb break in DC"
49 depends on DRM_AMD_DC
50 help
51 Choose this option
52 if you want to hit
53 kdgb_break in assert.
54
55endmenu