Loading...
1/*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#ifndef __AMDGPU_UCODE_H__
24#define __AMDGPU_UCODE_H__
25
26#include "amdgpu_socbb.h"
27
28struct common_firmware_header {
29 uint32_t size_bytes; /* size of the entire header+image(s) in bytes */
30 uint32_t header_size_bytes; /* size of just the header in bytes */
31 uint16_t header_version_major; /* header version */
32 uint16_t header_version_minor; /* header version */
33 uint16_t ip_version_major; /* IP version */
34 uint16_t ip_version_minor; /* IP version */
35 uint32_t ucode_version;
36 uint32_t ucode_size_bytes; /* size of ucode in bytes */
37 uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */
38 uint32_t crc32; /* crc32 checksum of the payload */
39};
40
41/* version_major=1, version_minor=0 */
42struct mc_firmware_header_v1_0 {
43 struct common_firmware_header header;
44 uint32_t io_debug_size_bytes; /* size of debug array in dwords */
45 uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */
46};
47
48/* version_major=1, version_minor=0 */
49struct smc_firmware_header_v1_0 {
50 struct common_firmware_header header;
51 uint32_t ucode_start_addr;
52};
53
54/* version_major=2, version_minor=0 */
55struct smc_firmware_header_v2_0 {
56 struct smc_firmware_header_v1_0 v1_0;
57 uint32_t ppt_offset_bytes; /* soft pptable offset */
58 uint32_t ppt_size_bytes; /* soft pptable size */
59};
60
61struct smc_soft_pptable_entry {
62 uint32_t id;
63 uint32_t ppt_offset_bytes;
64 uint32_t ppt_size_bytes;
65};
66
67/* version_major=2, version_minor=1 */
68struct smc_firmware_header_v2_1 {
69 struct smc_firmware_header_v1_0 v1_0;
70 uint32_t pptable_count;
71 uint32_t pptable_entry_offset;
72};
73
74struct psp_fw_legacy_bin_desc {
75 uint32_t fw_version;
76 uint32_t offset_bytes;
77 uint32_t size_bytes;
78};
79
80/* version_major=1, version_minor=0 */
81struct psp_firmware_header_v1_0 {
82 struct common_firmware_header header;
83 struct psp_fw_legacy_bin_desc sos;
84};
85
86/* version_major=1, version_minor=1 */
87struct psp_firmware_header_v1_1 {
88 struct psp_firmware_header_v1_0 v1_0;
89 struct psp_fw_legacy_bin_desc toc;
90 struct psp_fw_legacy_bin_desc kdb;
91};
92
93/* version_major=1, version_minor=2 */
94struct psp_firmware_header_v1_2 {
95 struct psp_firmware_header_v1_0 v1_0;
96 struct psp_fw_legacy_bin_desc res;
97 struct psp_fw_legacy_bin_desc kdb;
98};
99
100/* version_major=1, version_minor=3 */
101struct psp_firmware_header_v1_3 {
102 struct psp_firmware_header_v1_1 v1_1;
103 struct psp_fw_legacy_bin_desc spl;
104 struct psp_fw_legacy_bin_desc rl;
105 struct psp_fw_legacy_bin_desc sys_drv_aux;
106 struct psp_fw_legacy_bin_desc sos_aux;
107};
108
109struct psp_fw_bin_desc {
110 uint32_t fw_type;
111 uint32_t fw_version;
112 uint32_t offset_bytes;
113 uint32_t size_bytes;
114};
115
116enum psp_fw_type {
117 PSP_FW_TYPE_UNKOWN,
118 PSP_FW_TYPE_PSP_SOS,
119 PSP_FW_TYPE_PSP_SYS_DRV,
120 PSP_FW_TYPE_PSP_KDB,
121 PSP_FW_TYPE_PSP_TOC,
122 PSP_FW_TYPE_PSP_SPL,
123 PSP_FW_TYPE_PSP_RL,
124 PSP_FW_TYPE_PSP_SOC_DRV,
125 PSP_FW_TYPE_PSP_INTF_DRV,
126 PSP_FW_TYPE_PSP_DBG_DRV,
127 PSP_FW_TYPE_PSP_RAS_DRV,
128 PSP_FW_TYPE_PSP_IPKEYMGR_DRV,
129 PSP_FW_TYPE_MAX_INDEX,
130};
131
132/* version_major=2, version_minor=0 */
133struct psp_firmware_header_v2_0 {
134 struct common_firmware_header header;
135 uint32_t psp_fw_bin_count;
136 struct psp_fw_bin_desc psp_fw_bin[];
137};
138
139/* version_major=2, version_minor=1 */
140struct psp_firmware_header_v2_1 {
141 struct common_firmware_header header;
142 uint32_t psp_fw_bin_count;
143 uint32_t psp_aux_fw_bin_index;
144 struct psp_fw_bin_desc psp_fw_bin[];
145};
146
147/* version_major=1, version_minor=0 */
148struct ta_firmware_header_v1_0 {
149 struct common_firmware_header header;
150 struct psp_fw_legacy_bin_desc xgmi;
151 struct psp_fw_legacy_bin_desc ras;
152 struct psp_fw_legacy_bin_desc hdcp;
153 struct psp_fw_legacy_bin_desc dtm;
154 struct psp_fw_legacy_bin_desc securedisplay;
155};
156
157enum ta_fw_type {
158 TA_FW_TYPE_UNKOWN,
159 TA_FW_TYPE_PSP_ASD,
160 TA_FW_TYPE_PSP_XGMI,
161 TA_FW_TYPE_PSP_RAS,
162 TA_FW_TYPE_PSP_HDCP,
163 TA_FW_TYPE_PSP_DTM,
164 TA_FW_TYPE_PSP_RAP,
165 TA_FW_TYPE_PSP_SECUREDISPLAY,
166 TA_FW_TYPE_PSP_XGMI_AUX,
167 TA_FW_TYPE_MAX_INDEX,
168};
169
170/* version_major=2, version_minor=0 */
171struct ta_firmware_header_v2_0 {
172 struct common_firmware_header header;
173 uint32_t ta_fw_bin_count;
174 struct psp_fw_bin_desc ta_fw_bin[];
175};
176
177/* version_major=1, version_minor=0 */
178struct gfx_firmware_header_v1_0 {
179 struct common_firmware_header header;
180 uint32_t ucode_feature_version;
181 uint32_t jt_offset; /* jt location */
182 uint32_t jt_size; /* size of jt */
183};
184
185/* version_major=2, version_minor=0 */
186struct gfx_firmware_header_v2_0 {
187 struct common_firmware_header header;
188 uint32_t ucode_feature_version;
189 uint32_t ucode_size_bytes;
190 uint32_t ucode_offset_bytes;
191 uint32_t data_size_bytes;
192 uint32_t data_offset_bytes;
193 uint32_t ucode_start_addr_lo;
194 uint32_t ucode_start_addr_hi;
195};
196
197/* version_major=1, version_minor=0 */
198struct mes_firmware_header_v1_0 {
199 struct common_firmware_header header;
200 uint32_t mes_ucode_version;
201 uint32_t mes_ucode_size_bytes;
202 uint32_t mes_ucode_offset_bytes;
203 uint32_t mes_ucode_data_version;
204 uint32_t mes_ucode_data_size_bytes;
205 uint32_t mes_ucode_data_offset_bytes;
206 uint32_t mes_uc_start_addr_lo;
207 uint32_t mes_uc_start_addr_hi;
208 uint32_t mes_data_start_addr_lo;
209 uint32_t mes_data_start_addr_hi;
210};
211
212/* version_major=1, version_minor=0 */
213struct rlc_firmware_header_v1_0 {
214 struct common_firmware_header header;
215 uint32_t ucode_feature_version;
216 uint32_t save_and_restore_offset;
217 uint32_t clear_state_descriptor_offset;
218 uint32_t avail_scratch_ram_locations;
219 uint32_t master_pkt_description_offset;
220};
221
222/* version_major=2, version_minor=0 */
223struct rlc_firmware_header_v2_0 {
224 struct common_firmware_header header;
225 uint32_t ucode_feature_version;
226 uint32_t jt_offset; /* jt location */
227 uint32_t jt_size; /* size of jt */
228 uint32_t save_and_restore_offset;
229 uint32_t clear_state_descriptor_offset;
230 uint32_t avail_scratch_ram_locations;
231 uint32_t reg_restore_list_size;
232 uint32_t reg_list_format_start;
233 uint32_t reg_list_format_separate_start;
234 uint32_t starting_offsets_start;
235 uint32_t reg_list_format_size_bytes; /* size of reg list format array in bytes */
236 uint32_t reg_list_format_array_offset_bytes; /* payload offset from the start of the header */
237 uint32_t reg_list_size_bytes; /* size of reg list array in bytes */
238 uint32_t reg_list_array_offset_bytes; /* payload offset from the start of the header */
239 uint32_t reg_list_format_separate_size_bytes; /* size of reg list format array in bytes */
240 uint32_t reg_list_format_separate_array_offset_bytes; /* payload offset from the start of the header */
241 uint32_t reg_list_separate_size_bytes; /* size of reg list array in bytes */
242 uint32_t reg_list_separate_array_offset_bytes; /* payload offset from the start of the header */
243};
244
245/* version_major=2, version_minor=1 */
246struct rlc_firmware_header_v2_1 {
247 struct rlc_firmware_header_v2_0 v2_0;
248 uint32_t reg_list_format_direct_reg_list_length; /* length of direct reg list format array */
249 uint32_t save_restore_list_cntl_ucode_ver;
250 uint32_t save_restore_list_cntl_feature_ver;
251 uint32_t save_restore_list_cntl_size_bytes;
252 uint32_t save_restore_list_cntl_offset_bytes;
253 uint32_t save_restore_list_gpm_ucode_ver;
254 uint32_t save_restore_list_gpm_feature_ver;
255 uint32_t save_restore_list_gpm_size_bytes;
256 uint32_t save_restore_list_gpm_offset_bytes;
257 uint32_t save_restore_list_srm_ucode_ver;
258 uint32_t save_restore_list_srm_feature_ver;
259 uint32_t save_restore_list_srm_size_bytes;
260 uint32_t save_restore_list_srm_offset_bytes;
261};
262
263/* version_major=2, version_minor=2 */
264struct rlc_firmware_header_v2_2 {
265 struct rlc_firmware_header_v2_1 v2_1;
266 uint32_t rlc_iram_ucode_size_bytes;
267 uint32_t rlc_iram_ucode_offset_bytes;
268 uint32_t rlc_dram_ucode_size_bytes;
269 uint32_t rlc_dram_ucode_offset_bytes;
270};
271
272/* version_major=2, version_minor=3 */
273struct rlc_firmware_header_v2_3 {
274 struct rlc_firmware_header_v2_2 v2_2;
275 uint32_t rlcp_ucode_version;
276 uint32_t rlcp_ucode_feature_version;
277 uint32_t rlcp_ucode_size_bytes;
278 uint32_t rlcp_ucode_offset_bytes;
279 uint32_t rlcv_ucode_version;
280 uint32_t rlcv_ucode_feature_version;
281 uint32_t rlcv_ucode_size_bytes;
282 uint32_t rlcv_ucode_offset_bytes;
283};
284
285/* version_major=2, version_minor=4 */
286struct rlc_firmware_header_v2_4 {
287 struct rlc_firmware_header_v2_3 v2_3;
288 uint32_t global_tap_delays_ucode_size_bytes;
289 uint32_t global_tap_delays_ucode_offset_bytes;
290 uint32_t se0_tap_delays_ucode_size_bytes;
291 uint32_t se0_tap_delays_ucode_offset_bytes;
292 uint32_t se1_tap_delays_ucode_size_bytes;
293 uint32_t se1_tap_delays_ucode_offset_bytes;
294 uint32_t se2_tap_delays_ucode_size_bytes;
295 uint32_t se2_tap_delays_ucode_offset_bytes;
296 uint32_t se3_tap_delays_ucode_size_bytes;
297 uint32_t se3_tap_delays_ucode_offset_bytes;
298};
299
300/* version_major=1, version_minor=0 */
301struct sdma_firmware_header_v1_0 {
302 struct common_firmware_header header;
303 uint32_t ucode_feature_version;
304 uint32_t ucode_change_version;
305 uint32_t jt_offset; /* jt location */
306 uint32_t jt_size; /* size of jt */
307};
308
309/* version_major=1, version_minor=1 */
310struct sdma_firmware_header_v1_1 {
311 struct sdma_firmware_header_v1_0 v1_0;
312 uint32_t digest_size;
313};
314
315/* version_major=2, version_minor=0 */
316struct sdma_firmware_header_v2_0 {
317 struct common_firmware_header header;
318 uint32_t ucode_feature_version;
319 uint32_t ctx_ucode_size_bytes; /* context thread ucode size */
320 uint32_t ctx_jt_offset; /* context thread jt location */
321 uint32_t ctx_jt_size; /* context thread size of jt */
322 uint32_t ctl_ucode_offset;
323 uint32_t ctl_ucode_size_bytes; /* control thread ucode size */
324 uint32_t ctl_jt_offset; /* control thread jt location */
325 uint32_t ctl_jt_size; /* control thread size of jt */
326};
327
328/* version_major=1, version_minor=0 */
329struct vpe_firmware_header_v1_0 {
330 struct common_firmware_header header;
331 uint32_t ucode_feature_version;
332 uint32_t ctx_ucode_size_bytes; /* context thread ucode size */
333 uint32_t ctx_jt_offset; /* context thread jt location */
334 uint32_t ctx_jt_size; /* context thread size of jt */
335 uint32_t ctl_ucode_offset;
336 uint32_t ctl_ucode_size_bytes; /* control thread ucode size */
337 uint32_t ctl_jt_offset; /* control thread jt location */
338 uint32_t ctl_jt_size; /* control thread size of jt */
339};
340
341/* version_major=1, version_minor=0 */
342struct umsch_mm_firmware_header_v1_0 {
343 struct common_firmware_header header;
344 uint32_t umsch_mm_ucode_version;
345 uint32_t umsch_mm_ucode_size_bytes;
346 uint32_t umsch_mm_ucode_offset_bytes;
347 uint32_t umsch_mm_ucode_data_version;
348 uint32_t umsch_mm_ucode_data_size_bytes;
349 uint32_t umsch_mm_ucode_data_offset_bytes;
350 uint32_t umsch_mm_irq_start_addr_lo;
351 uint32_t umsch_mm_irq_start_addr_hi;
352 uint32_t umsch_mm_uc_start_addr_lo;
353 uint32_t umsch_mm_uc_start_addr_hi;
354 uint32_t umsch_mm_data_start_addr_lo;
355 uint32_t umsch_mm_data_start_addr_hi;
356};
357
358/* version_major=3, version_minor=0 */
359struct sdma_firmware_header_v3_0 {
360 struct common_firmware_header header;
361 uint32_t ucode_feature_version;
362 uint32_t ucode_offset_bytes;
363 uint32_t ucode_size_bytes;
364};
365
366/* gpu info payload */
367struct gpu_info_firmware_v1_0 {
368 uint32_t gc_num_se;
369 uint32_t gc_num_cu_per_sh;
370 uint32_t gc_num_sh_per_se;
371 uint32_t gc_num_rb_per_se;
372 uint32_t gc_num_tccs;
373 uint32_t gc_num_gprs;
374 uint32_t gc_num_max_gs_thds;
375 uint32_t gc_gs_table_depth;
376 uint32_t gc_gsprim_buff_depth;
377 uint32_t gc_parameter_cache_depth;
378 uint32_t gc_double_offchip_lds_buffer;
379 uint32_t gc_wave_size;
380 uint32_t gc_max_waves_per_simd;
381 uint32_t gc_max_scratch_slots_per_cu;
382 uint32_t gc_lds_size;
383};
384
385struct gpu_info_firmware_v1_1 {
386 struct gpu_info_firmware_v1_0 v1_0;
387 uint32_t num_sc_per_sh;
388 uint32_t num_packer_per_sc;
389};
390
391/* gpu info payload
392 * version_major=1, version_minor=1 */
393struct gpu_info_firmware_v1_2 {
394 struct gpu_info_firmware_v1_1 v1_1;
395 struct gpu_info_soc_bounding_box_v1_0 soc_bounding_box;
396};
397
398/* version_major=1, version_minor=0 */
399struct gpu_info_firmware_header_v1_0 {
400 struct common_firmware_header header;
401 uint16_t version_major; /* version */
402 uint16_t version_minor; /* version */
403};
404
405/* version_major=1, version_minor=0 */
406struct dmcu_firmware_header_v1_0 {
407 struct common_firmware_header header;
408 uint32_t intv_offset_bytes; /* interrupt vectors offset from end of header, in bytes */
409 uint32_t intv_size_bytes; /* size of interrupt vectors, in bytes */
410};
411
412/* version_major=1, version_minor=0 */
413struct dmcub_firmware_header_v1_0 {
414 struct common_firmware_header header;
415 uint32_t inst_const_bytes; /* size of instruction region, in bytes */
416 uint32_t bss_data_bytes; /* size of bss/data region, in bytes */
417};
418
419/* version_major=1, version_minor=0 */
420struct imu_firmware_header_v1_0 {
421 struct common_firmware_header header;
422 uint32_t imu_iram_ucode_size_bytes;
423 uint32_t imu_iram_ucode_offset_bytes;
424 uint32_t imu_dram_ucode_size_bytes;
425 uint32_t imu_dram_ucode_offset_bytes;
426};
427
428/* header is fixed size */
429union amdgpu_firmware_header {
430 struct common_firmware_header common;
431 struct mc_firmware_header_v1_0 mc;
432 struct smc_firmware_header_v1_0 smc;
433 struct smc_firmware_header_v2_0 smc_v2_0;
434 struct psp_firmware_header_v1_0 psp;
435 struct psp_firmware_header_v1_1 psp_v1_1;
436 struct psp_firmware_header_v1_3 psp_v1_3;
437 struct psp_firmware_header_v2_0 psp_v2_0;
438 struct psp_firmware_header_v2_0 psp_v2_1;
439 struct ta_firmware_header_v1_0 ta;
440 struct ta_firmware_header_v2_0 ta_v2_0;
441 struct gfx_firmware_header_v1_0 gfx;
442 struct gfx_firmware_header_v2_0 gfx_v2_0;
443 struct rlc_firmware_header_v1_0 rlc;
444 struct rlc_firmware_header_v2_0 rlc_v2_0;
445 struct rlc_firmware_header_v2_1 rlc_v2_1;
446 struct rlc_firmware_header_v2_2 rlc_v2_2;
447 struct rlc_firmware_header_v2_3 rlc_v2_3;
448 struct rlc_firmware_header_v2_4 rlc_v2_4;
449 struct sdma_firmware_header_v1_0 sdma;
450 struct sdma_firmware_header_v1_1 sdma_v1_1;
451 struct sdma_firmware_header_v2_0 sdma_v2_0;
452 struct sdma_firmware_header_v3_0 sdma_v3_0;
453 struct gpu_info_firmware_header_v1_0 gpu_info;
454 struct dmcu_firmware_header_v1_0 dmcu;
455 struct dmcub_firmware_header_v1_0 dmcub;
456 struct imu_firmware_header_v1_0 imu;
457 uint8_t raw[0x100];
458};
459
460#define UCODE_MAX_PSP_PACKAGING (((sizeof(union amdgpu_firmware_header) - sizeof(struct common_firmware_header) - 4) / sizeof(struct psp_fw_bin_desc)) * 2)
461
462/*
463 * fw loading support
464 */
465enum AMDGPU_UCODE_ID {
466 AMDGPU_UCODE_ID_CAP = 0,
467 AMDGPU_UCODE_ID_SDMA0,
468 AMDGPU_UCODE_ID_SDMA1,
469 AMDGPU_UCODE_ID_SDMA2,
470 AMDGPU_UCODE_ID_SDMA3,
471 AMDGPU_UCODE_ID_SDMA4,
472 AMDGPU_UCODE_ID_SDMA5,
473 AMDGPU_UCODE_ID_SDMA6,
474 AMDGPU_UCODE_ID_SDMA7,
475 AMDGPU_UCODE_ID_SDMA_UCODE_TH0,
476 AMDGPU_UCODE_ID_SDMA_UCODE_TH1,
477 AMDGPU_UCODE_ID_SDMA_RS64,
478 AMDGPU_UCODE_ID_CP_CE,
479 AMDGPU_UCODE_ID_CP_PFP,
480 AMDGPU_UCODE_ID_CP_ME,
481 AMDGPU_UCODE_ID_CP_RS64_PFP,
482 AMDGPU_UCODE_ID_CP_RS64_ME,
483 AMDGPU_UCODE_ID_CP_RS64_MEC,
484 AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK,
485 AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK,
486 AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK,
487 AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK,
488 AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK,
489 AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK,
490 AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK,
491 AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK,
492 AMDGPU_UCODE_ID_CP_MEC1,
493 AMDGPU_UCODE_ID_CP_MEC1_JT,
494 AMDGPU_UCODE_ID_CP_MEC2,
495 AMDGPU_UCODE_ID_CP_MEC2_JT,
496 AMDGPU_UCODE_ID_CP_MES,
497 AMDGPU_UCODE_ID_CP_MES_DATA,
498 AMDGPU_UCODE_ID_CP_MES1,
499 AMDGPU_UCODE_ID_CP_MES1_DATA,
500 AMDGPU_UCODE_ID_IMU_I,
501 AMDGPU_UCODE_ID_IMU_D,
502 AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS,
503 AMDGPU_UCODE_ID_SE0_TAP_DELAYS,
504 AMDGPU_UCODE_ID_SE1_TAP_DELAYS,
505 AMDGPU_UCODE_ID_SE2_TAP_DELAYS,
506 AMDGPU_UCODE_ID_SE3_TAP_DELAYS,
507 AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL,
508 AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM,
509 AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM,
510 AMDGPU_UCODE_ID_RLC_IRAM,
511 AMDGPU_UCODE_ID_RLC_DRAM,
512 AMDGPU_UCODE_ID_RLC_P,
513 AMDGPU_UCODE_ID_RLC_V,
514 AMDGPU_UCODE_ID_RLC_G,
515 AMDGPU_UCODE_ID_STORAGE,
516 AMDGPU_UCODE_ID_SMC,
517 AMDGPU_UCODE_ID_PPTABLE,
518 AMDGPU_UCODE_ID_UVD,
519 AMDGPU_UCODE_ID_UVD1,
520 AMDGPU_UCODE_ID_VCE,
521 AMDGPU_UCODE_ID_VCN,
522 AMDGPU_UCODE_ID_VCN1,
523 AMDGPU_UCODE_ID_DMCU_ERAM,
524 AMDGPU_UCODE_ID_DMCU_INTV,
525 AMDGPU_UCODE_ID_VCN0_RAM,
526 AMDGPU_UCODE_ID_VCN1_RAM,
527 AMDGPU_UCODE_ID_DMCUB,
528 AMDGPU_UCODE_ID_VPE_CTX,
529 AMDGPU_UCODE_ID_VPE_CTL,
530 AMDGPU_UCODE_ID_VPE,
531 AMDGPU_UCODE_ID_UMSCH_MM_UCODE,
532 AMDGPU_UCODE_ID_UMSCH_MM_DATA,
533 AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER,
534 AMDGPU_UCODE_ID_P2S_TABLE,
535 AMDGPU_UCODE_ID_JPEG_RAM,
536 AMDGPU_UCODE_ID_ISP,
537 AMDGPU_UCODE_ID_MAXIMUM,
538};
539
540/* engine firmware status */
541enum AMDGPU_UCODE_STATUS {
542 AMDGPU_UCODE_STATUS_INVALID,
543 AMDGPU_UCODE_STATUS_NOT_LOADED,
544 AMDGPU_UCODE_STATUS_LOADED,
545};
546
547enum amdgpu_firmware_load_type {
548 AMDGPU_FW_LOAD_DIRECT = 0,
549 AMDGPU_FW_LOAD_PSP,
550 AMDGPU_FW_LOAD_SMU,
551 AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO,
552};
553
554/* conform to smu_ucode_xfer_cz.h */
555#define AMDGPU_SDMA0_UCODE_LOADED 0x00000001
556#define AMDGPU_SDMA1_UCODE_LOADED 0x00000002
557#define AMDGPU_CPCE_UCODE_LOADED 0x00000004
558#define AMDGPU_CPPFP_UCODE_LOADED 0x00000008
559#define AMDGPU_CPME_UCODE_LOADED 0x00000010
560#define AMDGPU_CPMEC1_UCODE_LOADED 0x00000020
561#define AMDGPU_CPMEC2_UCODE_LOADED 0x00000040
562#define AMDGPU_CPRLC_UCODE_LOADED 0x00000100
563
564/* amdgpu firmware info */
565struct amdgpu_firmware_info {
566 /* ucode ID */
567 enum AMDGPU_UCODE_ID ucode_id;
568 /* request_firmware */
569 const struct firmware *fw;
570 /* starting mc address */
571 uint64_t mc_addr;
572 /* kernel linear address */
573 void *kaddr;
574 /* ucode_size_bytes */
575 uint32_t ucode_size;
576 /* starting tmr mc address */
577 uint32_t tmr_mc_addr_lo;
578 uint32_t tmr_mc_addr_hi;
579};
580
581struct amdgpu_firmware {
582 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
583 enum amdgpu_firmware_load_type load_type;
584 struct amdgpu_bo *fw_buf;
585 unsigned int fw_size;
586 unsigned int max_ucodes;
587 /* firmwares are loaded by psp instead of smu from vega10 */
588 const struct amdgpu_psp_funcs *funcs;
589 struct amdgpu_bo *rbuf;
590 struct mutex mutex;
591
592 /* gpu info firmware data pointer */
593 const struct firmware *gpu_info_fw;
594
595 void *fw_buf_ptr;
596 uint64_t fw_buf_mc;
597};
598
599void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr);
600void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr);
601void amdgpu_ucode_print_imu_hdr(const struct common_firmware_header *hdr);
602void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr);
603void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr);
604void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr);
605void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr);
606void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr);
607__printf(3, 4)
608int amdgpu_ucode_request(struct amdgpu_device *adev, const struct firmware **fw,
609 const char *fmt, ...);
610void amdgpu_ucode_release(const struct firmware **fw);
611bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
612 uint16_t hdr_major, uint16_t hdr_minor);
613
614int amdgpu_ucode_init_bo(struct amdgpu_device *adev);
615int amdgpu_ucode_create_bo(struct amdgpu_device *adev);
616int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev);
617void amdgpu_ucode_free_bo(struct amdgpu_device *adev);
618void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev);
619
620enum amdgpu_firmware_load_type
621amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type);
622
623const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id);
624
625void amdgpu_ucode_ip_version_decode(struct amdgpu_device *adev, int block_type, char *ucode_prefix, int len);
626
627#endif
1/*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#ifndef __AMDGPU_UCODE_H__
24#define __AMDGPU_UCODE_H__
25
26#include "amdgpu_socbb.h"
27
28struct common_firmware_header {
29 uint32_t size_bytes; /* size of the entire header+image(s) in bytes */
30 uint32_t header_size_bytes; /* size of just the header in bytes */
31 uint16_t header_version_major; /* header version */
32 uint16_t header_version_minor; /* header version */
33 uint16_t ip_version_major; /* IP version */
34 uint16_t ip_version_minor; /* IP version */
35 uint32_t ucode_version;
36 uint32_t ucode_size_bytes; /* size of ucode in bytes */
37 uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */
38 uint32_t crc32; /* crc32 checksum of the payload */
39};
40
41/* version_major=1, version_minor=0 */
42struct mc_firmware_header_v1_0 {
43 struct common_firmware_header header;
44 uint32_t io_debug_size_bytes; /* size of debug array in dwords */
45 uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */
46};
47
48/* version_major=1, version_minor=0 */
49struct smc_firmware_header_v1_0 {
50 struct common_firmware_header header;
51 uint32_t ucode_start_addr;
52};
53
54/* version_major=2, version_minor=0 */
55struct smc_firmware_header_v2_0 {
56 struct smc_firmware_header_v1_0 v1_0;
57 uint32_t ppt_offset_bytes; /* soft pptable offset */
58 uint32_t ppt_size_bytes; /* soft pptable size */
59};
60
61struct smc_soft_pptable_entry {
62 uint32_t id;
63 uint32_t ppt_offset_bytes;
64 uint32_t ppt_size_bytes;
65};
66
67/* version_major=2, version_minor=1 */
68struct smc_firmware_header_v2_1 {
69 struct smc_firmware_header_v1_0 v1_0;
70 uint32_t pptable_count;
71 uint32_t pptable_entry_offset;
72};
73
74/* version_major=1, version_minor=0 */
75struct psp_firmware_header_v1_0 {
76 struct common_firmware_header header;
77 uint32_t ucode_feature_version;
78 uint32_t sos_offset_bytes;
79 uint32_t sos_size_bytes;
80};
81
82/* version_major=1, version_minor=1 */
83struct psp_firmware_header_v1_1 {
84 struct psp_firmware_header_v1_0 v1_0;
85 uint32_t toc_header_version;
86 uint32_t toc_offset_bytes;
87 uint32_t toc_size_bytes;
88 uint32_t kdb_header_version;
89 uint32_t kdb_offset_bytes;
90 uint32_t kdb_size_bytes;
91};
92
93/* version_major=1, version_minor=2 */
94struct psp_firmware_header_v1_2 {
95 struct psp_firmware_header_v1_0 v1_0;
96 uint32_t reserve[3];
97 uint32_t kdb_header_version;
98 uint32_t kdb_offset_bytes;
99 uint32_t kdb_size_bytes;
100};
101
102/* version_major=1, version_minor=0 */
103struct ta_firmware_header_v1_0 {
104 struct common_firmware_header header;
105 uint32_t ta_xgmi_ucode_version;
106 uint32_t ta_xgmi_offset_bytes;
107 uint32_t ta_xgmi_size_bytes;
108 uint32_t ta_ras_ucode_version;
109 uint32_t ta_ras_offset_bytes;
110 uint32_t ta_ras_size_bytes;
111};
112
113/* version_major=1, version_minor=0 */
114struct gfx_firmware_header_v1_0 {
115 struct common_firmware_header header;
116 uint32_t ucode_feature_version;
117 uint32_t jt_offset; /* jt location */
118 uint32_t jt_size; /* size of jt */
119};
120
121/* version_major=1, version_minor=0 */
122struct mes_firmware_header_v1_0 {
123 struct common_firmware_header header;
124 uint32_t mes_ucode_version;
125 uint32_t mes_ucode_size_bytes;
126 uint32_t mes_ucode_offset_bytes;
127 uint32_t mes_ucode_data_version;
128 uint32_t mes_ucode_data_size_bytes;
129 uint32_t mes_ucode_data_offset_bytes;
130 uint32_t mes_uc_start_addr_lo;
131 uint32_t mes_uc_start_addr_hi;
132 uint32_t mes_data_start_addr_lo;
133 uint32_t mes_data_start_addr_hi;
134};
135
136/* version_major=1, version_minor=0 */
137struct rlc_firmware_header_v1_0 {
138 struct common_firmware_header header;
139 uint32_t ucode_feature_version;
140 uint32_t save_and_restore_offset;
141 uint32_t clear_state_descriptor_offset;
142 uint32_t avail_scratch_ram_locations;
143 uint32_t master_pkt_description_offset;
144};
145
146/* version_major=2, version_minor=0 */
147struct rlc_firmware_header_v2_0 {
148 struct common_firmware_header header;
149 uint32_t ucode_feature_version;
150 uint32_t jt_offset; /* jt location */
151 uint32_t jt_size; /* size of jt */
152 uint32_t save_and_restore_offset;
153 uint32_t clear_state_descriptor_offset;
154 uint32_t avail_scratch_ram_locations;
155 uint32_t reg_restore_list_size;
156 uint32_t reg_list_format_start;
157 uint32_t reg_list_format_separate_start;
158 uint32_t starting_offsets_start;
159 uint32_t reg_list_format_size_bytes; /* size of reg list format array in bytes */
160 uint32_t reg_list_format_array_offset_bytes; /* payload offset from the start of the header */
161 uint32_t reg_list_size_bytes; /* size of reg list array in bytes */
162 uint32_t reg_list_array_offset_bytes; /* payload offset from the start of the header */
163 uint32_t reg_list_format_separate_size_bytes; /* size of reg list format array in bytes */
164 uint32_t reg_list_format_separate_array_offset_bytes; /* payload offset from the start of the header */
165 uint32_t reg_list_separate_size_bytes; /* size of reg list array in bytes */
166 uint32_t reg_list_separate_array_offset_bytes; /* payload offset from the start of the header */
167};
168
169/* version_major=2, version_minor=1 */
170struct rlc_firmware_header_v2_1 {
171 struct rlc_firmware_header_v2_0 v2_0;
172 uint32_t reg_list_format_direct_reg_list_length; /* length of direct reg list format array */
173 uint32_t save_restore_list_cntl_ucode_ver;
174 uint32_t save_restore_list_cntl_feature_ver;
175 uint32_t save_restore_list_cntl_size_bytes;
176 uint32_t save_restore_list_cntl_offset_bytes;
177 uint32_t save_restore_list_gpm_ucode_ver;
178 uint32_t save_restore_list_gpm_feature_ver;
179 uint32_t save_restore_list_gpm_size_bytes;
180 uint32_t save_restore_list_gpm_offset_bytes;
181 uint32_t save_restore_list_srm_ucode_ver;
182 uint32_t save_restore_list_srm_feature_ver;
183 uint32_t save_restore_list_srm_size_bytes;
184 uint32_t save_restore_list_srm_offset_bytes;
185};
186
187/* version_major=1, version_minor=0 */
188struct sdma_firmware_header_v1_0 {
189 struct common_firmware_header header;
190 uint32_t ucode_feature_version;
191 uint32_t ucode_change_version;
192 uint32_t jt_offset; /* jt location */
193 uint32_t jt_size; /* size of jt */
194};
195
196/* version_major=1, version_minor=1 */
197struct sdma_firmware_header_v1_1 {
198 struct sdma_firmware_header_v1_0 v1_0;
199 uint32_t digest_size;
200};
201
202/* gpu info payload */
203struct gpu_info_firmware_v1_0 {
204 uint32_t gc_num_se;
205 uint32_t gc_num_cu_per_sh;
206 uint32_t gc_num_sh_per_se;
207 uint32_t gc_num_rb_per_se;
208 uint32_t gc_num_tccs;
209 uint32_t gc_num_gprs;
210 uint32_t gc_num_max_gs_thds;
211 uint32_t gc_gs_table_depth;
212 uint32_t gc_gsprim_buff_depth;
213 uint32_t gc_parameter_cache_depth;
214 uint32_t gc_double_offchip_lds_buffer;
215 uint32_t gc_wave_size;
216 uint32_t gc_max_waves_per_simd;
217 uint32_t gc_max_scratch_slots_per_cu;
218 uint32_t gc_lds_size;
219};
220
221struct gpu_info_firmware_v1_1 {
222 struct gpu_info_firmware_v1_0 v1_0;
223 uint32_t num_sc_per_sh;
224 uint32_t num_packer_per_sc;
225};
226
227/* gpu info payload
228 * version_major=1, version_minor=1 */
229struct gpu_info_firmware_v1_2 {
230 struct gpu_info_firmware_v1_1 v1_1;
231 struct gpu_info_soc_bounding_box_v1_0 soc_bounding_box;
232};
233
234/* version_major=1, version_minor=0 */
235struct gpu_info_firmware_header_v1_0 {
236 struct common_firmware_header header;
237 uint16_t version_major; /* version */
238 uint16_t version_minor; /* version */
239};
240
241/* version_major=1, version_minor=0 */
242struct dmcu_firmware_header_v1_0 {
243 struct common_firmware_header header;
244 uint32_t intv_offset_bytes; /* interrupt vectors offset from end of header, in bytes */
245 uint32_t intv_size_bytes; /* size of interrupt vectors, in bytes */
246};
247
248/* header is fixed size */
249union amdgpu_firmware_header {
250 struct common_firmware_header common;
251 struct mc_firmware_header_v1_0 mc;
252 struct smc_firmware_header_v1_0 smc;
253 struct smc_firmware_header_v2_0 smc_v2_0;
254 struct psp_firmware_header_v1_0 psp;
255 struct psp_firmware_header_v1_1 psp_v1_1;
256 struct ta_firmware_header_v1_0 ta;
257 struct gfx_firmware_header_v1_0 gfx;
258 struct rlc_firmware_header_v1_0 rlc;
259 struct rlc_firmware_header_v2_0 rlc_v2_0;
260 struct rlc_firmware_header_v2_1 rlc_v2_1;
261 struct sdma_firmware_header_v1_0 sdma;
262 struct sdma_firmware_header_v1_1 sdma_v1_1;
263 struct gpu_info_firmware_header_v1_0 gpu_info;
264 struct dmcu_firmware_header_v1_0 dmcu;
265 uint8_t raw[0x100];
266};
267
268/*
269 * fw loading support
270 */
271enum AMDGPU_UCODE_ID {
272 AMDGPU_UCODE_ID_SDMA0 = 0,
273 AMDGPU_UCODE_ID_SDMA1,
274 AMDGPU_UCODE_ID_SDMA2,
275 AMDGPU_UCODE_ID_SDMA3,
276 AMDGPU_UCODE_ID_SDMA4,
277 AMDGPU_UCODE_ID_SDMA5,
278 AMDGPU_UCODE_ID_SDMA6,
279 AMDGPU_UCODE_ID_SDMA7,
280 AMDGPU_UCODE_ID_CP_CE,
281 AMDGPU_UCODE_ID_CP_PFP,
282 AMDGPU_UCODE_ID_CP_ME,
283 AMDGPU_UCODE_ID_CP_MEC1,
284 AMDGPU_UCODE_ID_CP_MEC1_JT,
285 AMDGPU_UCODE_ID_CP_MEC2,
286 AMDGPU_UCODE_ID_CP_MEC2_JT,
287 AMDGPU_UCODE_ID_CP_MES,
288 AMDGPU_UCODE_ID_CP_MES_DATA,
289 AMDGPU_UCODE_ID_RLC_G,
290 AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL,
291 AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM,
292 AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM,
293 AMDGPU_UCODE_ID_STORAGE,
294 AMDGPU_UCODE_ID_SMC,
295 AMDGPU_UCODE_ID_UVD,
296 AMDGPU_UCODE_ID_UVD1,
297 AMDGPU_UCODE_ID_VCE,
298 AMDGPU_UCODE_ID_VCN,
299 AMDGPU_UCODE_ID_VCN1,
300 AMDGPU_UCODE_ID_DMCU_ERAM,
301 AMDGPU_UCODE_ID_DMCU_INTV,
302 AMDGPU_UCODE_ID_VCN0_RAM,
303 AMDGPU_UCODE_ID_VCN1_RAM,
304 AMDGPU_UCODE_ID_MAXIMUM,
305};
306
307/* engine firmware status */
308enum AMDGPU_UCODE_STATUS {
309 AMDGPU_UCODE_STATUS_INVALID,
310 AMDGPU_UCODE_STATUS_NOT_LOADED,
311 AMDGPU_UCODE_STATUS_LOADED,
312};
313
314enum amdgpu_firmware_load_type {
315 AMDGPU_FW_LOAD_DIRECT = 0,
316 AMDGPU_FW_LOAD_SMU,
317 AMDGPU_FW_LOAD_PSP,
318 AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO,
319};
320
321/* conform to smu_ucode_xfer_cz.h */
322#define AMDGPU_SDMA0_UCODE_LOADED 0x00000001
323#define AMDGPU_SDMA1_UCODE_LOADED 0x00000002
324#define AMDGPU_CPCE_UCODE_LOADED 0x00000004
325#define AMDGPU_CPPFP_UCODE_LOADED 0x00000008
326#define AMDGPU_CPME_UCODE_LOADED 0x00000010
327#define AMDGPU_CPMEC1_UCODE_LOADED 0x00000020
328#define AMDGPU_CPMEC2_UCODE_LOADED 0x00000040
329#define AMDGPU_CPRLC_UCODE_LOADED 0x00000100
330
331/* amdgpu firmware info */
332struct amdgpu_firmware_info {
333 /* ucode ID */
334 enum AMDGPU_UCODE_ID ucode_id;
335 /* request_firmware */
336 const struct firmware *fw;
337 /* starting mc address */
338 uint64_t mc_addr;
339 /* kernel linear address */
340 void *kaddr;
341 /* ucode_size_bytes */
342 uint32_t ucode_size;
343 /* starting tmr mc address */
344 uint32_t tmr_mc_addr_lo;
345 uint32_t tmr_mc_addr_hi;
346};
347
348struct amdgpu_firmware {
349 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
350 enum amdgpu_firmware_load_type load_type;
351 struct amdgpu_bo *fw_buf;
352 unsigned int fw_size;
353 unsigned int max_ucodes;
354 /* firmwares are loaded by psp instead of smu from vega10 */
355 const struct amdgpu_psp_funcs *funcs;
356 struct amdgpu_bo *rbuf;
357 struct mutex mutex;
358
359 /* gpu info firmware data pointer */
360 const struct firmware *gpu_info_fw;
361
362 void *fw_buf_ptr;
363 uint64_t fw_buf_mc;
364};
365
366void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr);
367void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr);
368void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr);
369void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr);
370void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr);
371void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr);
372void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr);
373int amdgpu_ucode_validate(const struct firmware *fw);
374bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
375 uint16_t hdr_major, uint16_t hdr_minor);
376
377int amdgpu_ucode_init_bo(struct amdgpu_device *adev);
378int amdgpu_ucode_create_bo(struct amdgpu_device *adev);
379int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev);
380void amdgpu_ucode_free_bo(struct amdgpu_device *adev);
381void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev);
382
383enum amdgpu_firmware_load_type
384amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type);
385
386#endif