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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) ST-Ericsson SA 2010
4 *
5 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
6 */
7
8#include <linux/bitops.h>
9#include <linux/cleanup.h>
10#include <linux/gpio/driver.h>
11#include <linux/init.h>
12#include <linux/interrupt.h>
13#include <linux/mfd/stmpe.h>
14#include <linux/property.h>
15#include <linux/platform_device.h>
16#include <linux/seq_file.h>
17#include <linux/slab.h>
18
19/*
20 * These registers are modified under the irq bus lock and cached to avoid
21 * unnecessary writes in bus_sync_unlock.
22 */
23enum { REG_RE, REG_FE, REG_IE };
24
25enum { LSB, CSB, MSB };
26
27#define CACHE_NR_REGS 3
28/* No variant has more than 24 GPIOs */
29#define CACHE_NR_BANKS (24 / 8)
30
31struct stmpe_gpio {
32 struct gpio_chip chip;
33 struct stmpe *stmpe;
34 struct mutex irq_lock;
35 u32 norequest_mask;
36 /* Caches of interrupt control registers for bus_lock */
37 u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
38 u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
39};
40
41static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
42{
43 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
44 struct stmpe *stmpe = stmpe_gpio->stmpe;
45 u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB + (offset / 8)];
46 u8 mask = BIT(offset % 8);
47 int ret;
48
49 ret = stmpe_reg_read(stmpe, reg);
50 if (ret < 0)
51 return ret;
52
53 return !!(ret & mask);
54}
55
56static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
57{
58 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
59 struct stmpe *stmpe = stmpe_gpio->stmpe;
60 int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
61 u8 reg = stmpe->regs[which + (offset / 8)];
62 u8 mask = BIT(offset % 8);
63
64 /*
65 * Some variants have single register for gpio set/clear functionality.
66 * For them we need to write 0 to clear and 1 to set.
67 */
68 if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
69 stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
70 else
71 stmpe_reg_write(stmpe, reg, mask);
72}
73
74static int stmpe_gpio_get_direction(struct gpio_chip *chip,
75 unsigned offset)
76{
77 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
78 struct stmpe *stmpe = stmpe_gpio->stmpe;
79 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
80 u8 mask = BIT(offset % 8);
81 int ret;
82
83 ret = stmpe_reg_read(stmpe, reg);
84 if (ret < 0)
85 return ret;
86
87 if (ret & mask)
88 return GPIO_LINE_DIRECTION_OUT;
89
90 return GPIO_LINE_DIRECTION_IN;
91}
92
93static int stmpe_gpio_direction_output(struct gpio_chip *chip,
94 unsigned offset, int val)
95{
96 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
97 struct stmpe *stmpe = stmpe_gpio->stmpe;
98 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
99 u8 mask = BIT(offset % 8);
100
101 stmpe_gpio_set(chip, offset, val);
102
103 return stmpe_set_bits(stmpe, reg, mask, mask);
104}
105
106static int stmpe_gpio_direction_input(struct gpio_chip *chip,
107 unsigned offset)
108{
109 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
110 struct stmpe *stmpe = stmpe_gpio->stmpe;
111 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
112 u8 mask = BIT(offset % 8);
113
114 return stmpe_set_bits(stmpe, reg, mask, 0);
115}
116
117static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
118{
119 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
120 struct stmpe *stmpe = stmpe_gpio->stmpe;
121
122 if (stmpe_gpio->norequest_mask & BIT(offset))
123 return -EINVAL;
124
125 return stmpe_set_altfunc(stmpe, BIT(offset), STMPE_BLOCK_GPIO);
126}
127
128static const struct gpio_chip template_chip = {
129 .label = "stmpe",
130 .owner = THIS_MODULE,
131 .get_direction = stmpe_gpio_get_direction,
132 .direction_input = stmpe_gpio_direction_input,
133 .get = stmpe_gpio_get,
134 .direction_output = stmpe_gpio_direction_output,
135 .set = stmpe_gpio_set,
136 .request = stmpe_gpio_request,
137 .can_sleep = true,
138};
139
140static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
141{
142 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
143 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
144 int offset = d->hwirq;
145 int regoffset = offset / 8;
146 int mask = BIT(offset % 8);
147
148 if (type & IRQ_TYPE_LEVEL_LOW || type & IRQ_TYPE_LEVEL_HIGH)
149 return -EINVAL;
150
151 /* STMPE801 and STMPE 1600 don't have RE and FE registers */
152 if (stmpe_gpio->stmpe->partnum == STMPE801 ||
153 stmpe_gpio->stmpe->partnum == STMPE1600)
154 return 0;
155
156 if (type & IRQ_TYPE_EDGE_RISING)
157 stmpe_gpio->regs[REG_RE][regoffset] |= mask;
158 else
159 stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;
160
161 if (type & IRQ_TYPE_EDGE_FALLING)
162 stmpe_gpio->regs[REG_FE][regoffset] |= mask;
163 else
164 stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;
165
166 return 0;
167}
168
169static void stmpe_gpio_irq_lock(struct irq_data *d)
170{
171 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
172 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
173
174 mutex_lock(&stmpe_gpio->irq_lock);
175}
176
177static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
178{
179 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
180 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
181 struct stmpe *stmpe = stmpe_gpio->stmpe;
182 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
183 static const u8 regmap[CACHE_NR_REGS][CACHE_NR_BANKS] = {
184 [REG_RE][LSB] = STMPE_IDX_GPRER_LSB,
185 [REG_RE][CSB] = STMPE_IDX_GPRER_CSB,
186 [REG_RE][MSB] = STMPE_IDX_GPRER_MSB,
187 [REG_FE][LSB] = STMPE_IDX_GPFER_LSB,
188 [REG_FE][CSB] = STMPE_IDX_GPFER_CSB,
189 [REG_FE][MSB] = STMPE_IDX_GPFER_MSB,
190 [REG_IE][LSB] = STMPE_IDX_IEGPIOR_LSB,
191 [REG_IE][CSB] = STMPE_IDX_IEGPIOR_CSB,
192 [REG_IE][MSB] = STMPE_IDX_IEGPIOR_MSB,
193 };
194 int ret, i, j;
195
196 /*
197 * STMPE1600: to be able to get IRQ from pins,
198 * a read must be done on GPMR register, or a write in
199 * GPSR or GPCR registers
200 */
201 if (stmpe->partnum == STMPE1600) {
202 ret = stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_LSB]);
203 if (ret < 0) {
204 dev_err(stmpe->dev, "Failed to read GPMR_LSB: %d\n", ret);
205 goto err;
206 }
207 ret = stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_CSB]);
208 if (ret < 0) {
209 dev_err(stmpe->dev, "Failed to read GPMR_CSB: %d\n", ret);
210 goto err;
211 }
212 }
213
214 for (i = 0; i < CACHE_NR_REGS; i++) {
215 /* STMPE801 and STMPE1600 don't have RE and FE registers */
216 if ((stmpe->partnum == STMPE801 ||
217 stmpe->partnum == STMPE1600) &&
218 (i != REG_IE))
219 continue;
220
221 for (j = 0; j < num_banks; j++) {
222 u8 old = stmpe_gpio->oldregs[i][j];
223 u8 new = stmpe_gpio->regs[i][j];
224
225 if (new == old)
226 continue;
227
228 stmpe_gpio->oldregs[i][j] = new;
229 stmpe_reg_write(stmpe, stmpe->regs[regmap[i][j]], new);
230 }
231 }
232
233err:
234 mutex_unlock(&stmpe_gpio->irq_lock);
235}
236
237static void stmpe_gpio_irq_mask(struct irq_data *d)
238{
239 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
240 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
241 int offset = d->hwirq;
242 int regoffset = offset / 8;
243 int mask = BIT(offset % 8);
244
245 stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
246 gpiochip_disable_irq(gc, offset);
247}
248
249static void stmpe_gpio_irq_unmask(struct irq_data *d)
250{
251 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
252 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
253 int offset = d->hwirq;
254 int regoffset = offset / 8;
255 int mask = BIT(offset % 8);
256
257 gpiochip_enable_irq(gc, offset);
258 stmpe_gpio->regs[REG_IE][regoffset] |= mask;
259}
260
261static void stmpe_dbg_show_one(struct seq_file *s,
262 struct gpio_chip *gc,
263 unsigned offset, unsigned gpio)
264{
265 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
266 struct stmpe *stmpe = stmpe_gpio->stmpe;
267 bool val = !!stmpe_gpio_get(gc, offset);
268 u8 bank = offset / 8;
269 u8 dir_reg = stmpe->regs[STMPE_IDX_GPDR_LSB + bank];
270 u8 mask = BIT(offset % 8);
271 int ret;
272 u8 dir;
273
274 char *label __free(kfree) = gpiochip_dup_line_label(gc, offset);
275 if (IS_ERR(label))
276 return;
277
278 ret = stmpe_reg_read(stmpe, dir_reg);
279 if (ret < 0)
280 return;
281 dir = !!(ret & mask);
282
283 if (dir) {
284 seq_printf(s, " gpio-%-3d (%-20.20s) out %s",
285 gpio, label ?: "(none)",
286 val ? "hi" : "lo");
287 } else {
288 u8 edge_det_reg;
289 u8 rise_reg;
290 u8 fall_reg;
291 u8 irqen_reg;
292
293 static const char * const edge_det_values[] = {
294 "edge-inactive",
295 "edge-asserted",
296 "not-supported"
297 };
298 static const char * const rise_values[] = {
299 "no-rising-edge-detection",
300 "rising-edge-detection",
301 "not-supported"
302 };
303 static const char * const fall_values[] = {
304 "no-falling-edge-detection",
305 "falling-edge-detection",
306 "not-supported"
307 };
308 #define NOT_SUPPORTED_IDX 2
309 u8 edge_det = NOT_SUPPORTED_IDX;
310 u8 rise = NOT_SUPPORTED_IDX;
311 u8 fall = NOT_SUPPORTED_IDX;
312 bool irqen;
313
314 switch (stmpe->partnum) {
315 case STMPE610:
316 case STMPE811:
317 case STMPE1601:
318 case STMPE2401:
319 case STMPE2403:
320 edge_det_reg = stmpe->regs[STMPE_IDX_GPEDR_LSB + bank];
321 ret = stmpe_reg_read(stmpe, edge_det_reg);
322 if (ret < 0)
323 return;
324 edge_det = !!(ret & mask);
325 fallthrough;
326 case STMPE1801:
327 rise_reg = stmpe->regs[STMPE_IDX_GPRER_LSB + bank];
328 fall_reg = stmpe->regs[STMPE_IDX_GPFER_LSB + bank];
329
330 ret = stmpe_reg_read(stmpe, rise_reg);
331 if (ret < 0)
332 return;
333 rise = !!(ret & mask);
334 ret = stmpe_reg_read(stmpe, fall_reg);
335 if (ret < 0)
336 return;
337 fall = !!(ret & mask);
338 fallthrough;
339 case STMPE801:
340 case STMPE1600:
341 irqen_reg = stmpe->regs[STMPE_IDX_IEGPIOR_LSB + bank];
342 break;
343
344 default:
345 return;
346 }
347
348 ret = stmpe_reg_read(stmpe, irqen_reg);
349 if (ret < 0)
350 return;
351 irqen = !!(ret & mask);
352
353 seq_printf(s, " gpio-%-3d (%-20.20s) in %s %13s %13s %25s %25s",
354 gpio, label ?: "(none)",
355 val ? "hi" : "lo",
356 edge_det_values[edge_det],
357 irqen ? "IRQ-enabled" : "IRQ-disabled",
358 rise_values[rise],
359 fall_values[fall]);
360 }
361}
362
363static void stmpe_dbg_show(struct seq_file *s, struct gpio_chip *gc)
364{
365 unsigned i;
366 unsigned gpio = gc->base;
367
368 for (i = 0; i < gc->ngpio; i++, gpio++) {
369 stmpe_dbg_show_one(s, gc, i, gpio);
370 seq_putc(s, '\n');
371 }
372}
373
374static const struct irq_chip stmpe_gpio_irq_chip = {
375 .name = "stmpe-gpio",
376 .irq_bus_lock = stmpe_gpio_irq_lock,
377 .irq_bus_sync_unlock = stmpe_gpio_irq_sync_unlock,
378 .irq_mask = stmpe_gpio_irq_mask,
379 .irq_unmask = stmpe_gpio_irq_unmask,
380 .irq_set_type = stmpe_gpio_irq_set_type,
381 .flags = IRQCHIP_IMMUTABLE,
382 GPIOCHIP_IRQ_RESOURCE_HELPERS,
383};
384
385#define MAX_GPIOS 24
386
387static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
388{
389 struct stmpe_gpio *stmpe_gpio = dev;
390 struct stmpe *stmpe = stmpe_gpio->stmpe;
391 u8 statmsbreg;
392 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
393 u8 status[DIV_ROUND_UP(MAX_GPIOS, 8)];
394 int ret;
395 int i;
396
397 /*
398 * the stmpe_block_read() call below, imposes to set statmsbreg
399 * with the register located at the lowest address. As STMPE1600
400 * variant is the only one which respect registers address's order
401 * (LSB regs located at lowest address than MSB ones) whereas all
402 * the others have a registers layout with MSB located before the
403 * LSB regs.
404 */
405 if (stmpe->partnum == STMPE1600)
406 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_LSB];
407 else
408 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];
409
410 ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
411 if (ret < 0)
412 return IRQ_NONE;
413
414 for (i = 0; i < num_banks; i++) {
415 int bank = (stmpe_gpio->stmpe->partnum == STMPE1600) ? i :
416 num_banks - i - 1;
417 unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
418 unsigned int stat = status[i];
419
420 stat &= enabled;
421 if (!stat)
422 continue;
423
424 while (stat) {
425 int bit = __ffs(stat);
426 int line = bank * 8 + bit;
427 int child_irq = irq_find_mapping(stmpe_gpio->chip.irq.domain,
428 line);
429
430 handle_nested_irq(child_irq);
431 stat &= ~BIT(bit);
432 }
433
434 /*
435 * interrupt status register write has no effect on
436 * 801/1801/1600, bits are cleared when read.
437 * Edge detect register is not present on 801/1600/1801
438 */
439 if (stmpe->partnum != STMPE801 && stmpe->partnum != STMPE1600 &&
440 stmpe->partnum != STMPE1801) {
441 stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
442 stmpe_reg_write(stmpe,
443 stmpe->regs[STMPE_IDX_GPEDR_MSB] + i,
444 status[i]);
445 }
446 }
447
448 return IRQ_HANDLED;
449}
450
451static void stmpe_init_irq_valid_mask(struct gpio_chip *gc,
452 unsigned long *valid_mask,
453 unsigned int ngpios)
454{
455 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
456 int i;
457
458 if (!stmpe_gpio->norequest_mask)
459 return;
460
461 /* Forbid unused lines to be mapped as IRQs */
462 for (i = 0; i < sizeof(u32); i++) {
463 if (stmpe_gpio->norequest_mask & BIT(i))
464 clear_bit(i, valid_mask);
465 }
466}
467
468static void stmpe_gpio_disable(void *stmpe)
469{
470 stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
471}
472
473static int stmpe_gpio_probe(struct platform_device *pdev)
474{
475 struct device *dev = &pdev->dev;
476 struct stmpe *stmpe = dev_get_drvdata(dev->parent);
477 struct stmpe_gpio *stmpe_gpio;
478 int ret, irq;
479
480 if (stmpe->num_gpios > MAX_GPIOS) {
481 dev_err(dev, "Need to increase maximum GPIO number\n");
482 return -EINVAL;
483 }
484
485 stmpe_gpio = devm_kzalloc(dev, sizeof(*stmpe_gpio), GFP_KERNEL);
486 if (!stmpe_gpio)
487 return -ENOMEM;
488
489 mutex_init(&stmpe_gpio->irq_lock);
490
491 stmpe_gpio->stmpe = stmpe;
492 stmpe_gpio->chip = template_chip;
493 stmpe_gpio->chip.ngpio = stmpe->num_gpios;
494 stmpe_gpio->chip.parent = dev;
495 stmpe_gpio->chip.base = -1;
496
497 if (IS_ENABLED(CONFIG_DEBUG_FS))
498 stmpe_gpio->chip.dbg_show = stmpe_dbg_show;
499
500 device_property_read_u32(dev, "st,norequest-mask", &stmpe_gpio->norequest_mask);
501
502 ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
503 if (ret)
504 return ret;
505
506 ret = devm_add_action_or_reset(dev, stmpe_gpio_disable, stmpe);
507 if (ret)
508 return ret;
509
510 irq = platform_get_irq(pdev, 0);
511 if (irq > 0) {
512 struct gpio_irq_chip *girq;
513
514 ret = devm_request_threaded_irq(dev, irq, NULL, stmpe_gpio_irq,
515 IRQF_ONESHOT, "stmpe-gpio", stmpe_gpio);
516 if (ret)
517 return dev_err_probe(dev, ret, "unable to register IRQ handler\n");
518
519 girq = &stmpe_gpio->chip.irq;
520 gpio_irq_chip_set_chip(girq, &stmpe_gpio_irq_chip);
521 /* This will let us handle the parent IRQ in the driver */
522 girq->parent_handler = NULL;
523 girq->num_parents = 0;
524 girq->parents = NULL;
525 girq->default_type = IRQ_TYPE_NONE;
526 girq->handler = handle_simple_irq;
527 girq->threaded = true;
528 girq->init_valid_mask = stmpe_init_irq_valid_mask;
529 }
530
531 return devm_gpiochip_add_data(dev, &stmpe_gpio->chip, stmpe_gpio);
532}
533
534static struct platform_driver stmpe_gpio_driver = {
535 .driver = {
536 .suppress_bind_attrs = true,
537 .name = "stmpe-gpio",
538 },
539 .probe = stmpe_gpio_probe,
540};
541
542static int __init stmpe_gpio_init(void)
543{
544 return platform_driver_register(&stmpe_gpio_driver);
545}
546subsys_initcall(stmpe_gpio_init);
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) ST-Ericsson SA 2010
4 *
5 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
6 */
7
8#include <linux/init.h>
9#include <linux/platform_device.h>
10#include <linux/slab.h>
11#include <linux/gpio/driver.h>
12#include <linux/interrupt.h>
13#include <linux/of.h>
14#include <linux/mfd/stmpe.h>
15#include <linux/seq_file.h>
16#include <linux/bitops.h>
17
18/*
19 * These registers are modified under the irq bus lock and cached to avoid
20 * unnecessary writes in bus_sync_unlock.
21 */
22enum { REG_RE, REG_FE, REG_IE };
23
24enum { LSB, CSB, MSB };
25
26#define CACHE_NR_REGS 3
27/* No variant has more than 24 GPIOs */
28#define CACHE_NR_BANKS (24 / 8)
29
30struct stmpe_gpio {
31 struct gpio_chip chip;
32 struct stmpe *stmpe;
33 struct device *dev;
34 struct mutex irq_lock;
35 u32 norequest_mask;
36 /* Caches of interrupt control registers for bus_lock */
37 u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
38 u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
39};
40
41static int stmpe_gpio_get(struct gpio_chip *chip, unsigned offset)
42{
43 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
44 struct stmpe *stmpe = stmpe_gpio->stmpe;
45 u8 reg = stmpe->regs[STMPE_IDX_GPMR_LSB + (offset / 8)];
46 u8 mask = BIT(offset % 8);
47 int ret;
48
49 ret = stmpe_reg_read(stmpe, reg);
50 if (ret < 0)
51 return ret;
52
53 return !!(ret & mask);
54}
55
56static void stmpe_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
57{
58 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
59 struct stmpe *stmpe = stmpe_gpio->stmpe;
60 int which = val ? STMPE_IDX_GPSR_LSB : STMPE_IDX_GPCR_LSB;
61 u8 reg = stmpe->regs[which + (offset / 8)];
62 u8 mask = BIT(offset % 8);
63
64 /*
65 * Some variants have single register for gpio set/clear functionality.
66 * For them we need to write 0 to clear and 1 to set.
67 */
68 if (stmpe->regs[STMPE_IDX_GPSR_LSB] == stmpe->regs[STMPE_IDX_GPCR_LSB])
69 stmpe_set_bits(stmpe, reg, mask, val ? mask : 0);
70 else
71 stmpe_reg_write(stmpe, reg, mask);
72}
73
74static int stmpe_gpio_get_direction(struct gpio_chip *chip,
75 unsigned offset)
76{
77 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
78 struct stmpe *stmpe = stmpe_gpio->stmpe;
79 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
80 u8 mask = BIT(offset % 8);
81 int ret;
82
83 ret = stmpe_reg_read(stmpe, reg);
84 if (ret < 0)
85 return ret;
86
87 return !(ret & mask);
88}
89
90static int stmpe_gpio_direction_output(struct gpio_chip *chip,
91 unsigned offset, int val)
92{
93 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
94 struct stmpe *stmpe = stmpe_gpio->stmpe;
95 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
96 u8 mask = BIT(offset % 8);
97
98 stmpe_gpio_set(chip, offset, val);
99
100 return stmpe_set_bits(stmpe, reg, mask, mask);
101}
102
103static int stmpe_gpio_direction_input(struct gpio_chip *chip,
104 unsigned offset)
105{
106 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
107 struct stmpe *stmpe = stmpe_gpio->stmpe;
108 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB + (offset / 8)];
109 u8 mask = BIT(offset % 8);
110
111 return stmpe_set_bits(stmpe, reg, mask, 0);
112}
113
114static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
115{
116 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(chip);
117 struct stmpe *stmpe = stmpe_gpio->stmpe;
118
119 if (stmpe_gpio->norequest_mask & BIT(offset))
120 return -EINVAL;
121
122 return stmpe_set_altfunc(stmpe, BIT(offset), STMPE_BLOCK_GPIO);
123}
124
125static const struct gpio_chip template_chip = {
126 .label = "stmpe",
127 .owner = THIS_MODULE,
128 .get_direction = stmpe_gpio_get_direction,
129 .direction_input = stmpe_gpio_direction_input,
130 .get = stmpe_gpio_get,
131 .direction_output = stmpe_gpio_direction_output,
132 .set = stmpe_gpio_set,
133 .request = stmpe_gpio_request,
134 .can_sleep = true,
135};
136
137static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
138{
139 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
140 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
141 int offset = d->hwirq;
142 int regoffset = offset / 8;
143 int mask = BIT(offset % 8);
144
145 if (type & IRQ_TYPE_LEVEL_LOW || type & IRQ_TYPE_LEVEL_HIGH)
146 return -EINVAL;
147
148 /* STMPE801 and STMPE 1600 don't have RE and FE registers */
149 if (stmpe_gpio->stmpe->partnum == STMPE801 ||
150 stmpe_gpio->stmpe->partnum == STMPE1600)
151 return 0;
152
153 if (type & IRQ_TYPE_EDGE_RISING)
154 stmpe_gpio->regs[REG_RE][regoffset] |= mask;
155 else
156 stmpe_gpio->regs[REG_RE][regoffset] &= ~mask;
157
158 if (type & IRQ_TYPE_EDGE_FALLING)
159 stmpe_gpio->regs[REG_FE][regoffset] |= mask;
160 else
161 stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;
162
163 return 0;
164}
165
166static void stmpe_gpio_irq_lock(struct irq_data *d)
167{
168 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
169 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
170
171 mutex_lock(&stmpe_gpio->irq_lock);
172}
173
174static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
175{
176 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
177 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
178 struct stmpe *stmpe = stmpe_gpio->stmpe;
179 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
180 static const u8 regmap[CACHE_NR_REGS][CACHE_NR_BANKS] = {
181 [REG_RE][LSB] = STMPE_IDX_GPRER_LSB,
182 [REG_RE][CSB] = STMPE_IDX_GPRER_CSB,
183 [REG_RE][MSB] = STMPE_IDX_GPRER_MSB,
184 [REG_FE][LSB] = STMPE_IDX_GPFER_LSB,
185 [REG_FE][CSB] = STMPE_IDX_GPFER_CSB,
186 [REG_FE][MSB] = STMPE_IDX_GPFER_MSB,
187 [REG_IE][LSB] = STMPE_IDX_IEGPIOR_LSB,
188 [REG_IE][CSB] = STMPE_IDX_IEGPIOR_CSB,
189 [REG_IE][MSB] = STMPE_IDX_IEGPIOR_MSB,
190 };
191 int i, j;
192
193 /*
194 * STMPE1600: to be able to get IRQ from pins,
195 * a read must be done on GPMR register, or a write in
196 * GPSR or GPCR registers
197 */
198 if (stmpe->partnum == STMPE1600) {
199 stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_LSB]);
200 stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_CSB]);
201 }
202
203 for (i = 0; i < CACHE_NR_REGS; i++) {
204 /* STMPE801 and STMPE1600 don't have RE and FE registers */
205 if ((stmpe->partnum == STMPE801 ||
206 stmpe->partnum == STMPE1600) &&
207 (i != REG_IE))
208 continue;
209
210 for (j = 0; j < num_banks; j++) {
211 u8 old = stmpe_gpio->oldregs[i][j];
212 u8 new = stmpe_gpio->regs[i][j];
213
214 if (new == old)
215 continue;
216
217 stmpe_gpio->oldregs[i][j] = new;
218 stmpe_reg_write(stmpe, stmpe->regs[regmap[i][j]], new);
219 }
220 }
221
222 mutex_unlock(&stmpe_gpio->irq_lock);
223}
224
225static void stmpe_gpio_irq_mask(struct irq_data *d)
226{
227 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
228 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
229 int offset = d->hwirq;
230 int regoffset = offset / 8;
231 int mask = BIT(offset % 8);
232
233 stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
234}
235
236static void stmpe_gpio_irq_unmask(struct irq_data *d)
237{
238 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
239 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
240 int offset = d->hwirq;
241 int regoffset = offset / 8;
242 int mask = BIT(offset % 8);
243
244 stmpe_gpio->regs[REG_IE][regoffset] |= mask;
245}
246
247static void stmpe_dbg_show_one(struct seq_file *s,
248 struct gpio_chip *gc,
249 unsigned offset, unsigned gpio)
250{
251 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
252 struct stmpe *stmpe = stmpe_gpio->stmpe;
253 const char *label = gpiochip_is_requested(gc, offset);
254 bool val = !!stmpe_gpio_get(gc, offset);
255 u8 bank = offset / 8;
256 u8 dir_reg = stmpe->regs[STMPE_IDX_GPDR_LSB + bank];
257 u8 mask = BIT(offset % 8);
258 int ret;
259 u8 dir;
260
261 ret = stmpe_reg_read(stmpe, dir_reg);
262 if (ret < 0)
263 return;
264 dir = !!(ret & mask);
265
266 if (dir) {
267 seq_printf(s, " gpio-%-3d (%-20.20s) out %s",
268 gpio, label ?: "(none)",
269 val ? "hi" : "lo");
270 } else {
271 u8 edge_det_reg;
272 u8 rise_reg;
273 u8 fall_reg;
274 u8 irqen_reg;
275
276 static const char * const edge_det_values[] = {
277 "edge-inactive",
278 "edge-asserted",
279 "not-supported"
280 };
281 static const char * const rise_values[] = {
282 "no-rising-edge-detection",
283 "rising-edge-detection",
284 "not-supported"
285 };
286 static const char * const fall_values[] = {
287 "no-falling-edge-detection",
288 "falling-edge-detection",
289 "not-supported"
290 };
291 #define NOT_SUPPORTED_IDX 2
292 u8 edge_det = NOT_SUPPORTED_IDX;
293 u8 rise = NOT_SUPPORTED_IDX;
294 u8 fall = NOT_SUPPORTED_IDX;
295 bool irqen;
296
297 switch (stmpe->partnum) {
298 case STMPE610:
299 case STMPE811:
300 case STMPE1601:
301 case STMPE2401:
302 case STMPE2403:
303 edge_det_reg = stmpe->regs[STMPE_IDX_GPEDR_LSB + bank];
304 ret = stmpe_reg_read(stmpe, edge_det_reg);
305 if (ret < 0)
306 return;
307 edge_det = !!(ret & mask);
308 /* fall through */
309 case STMPE1801:
310 rise_reg = stmpe->regs[STMPE_IDX_GPRER_LSB + bank];
311 fall_reg = stmpe->regs[STMPE_IDX_GPFER_LSB + bank];
312
313 ret = stmpe_reg_read(stmpe, rise_reg);
314 if (ret < 0)
315 return;
316 rise = !!(ret & mask);
317 ret = stmpe_reg_read(stmpe, fall_reg);
318 if (ret < 0)
319 return;
320 fall = !!(ret & mask);
321 /* fall through */
322 case STMPE801:
323 case STMPE1600:
324 irqen_reg = stmpe->regs[STMPE_IDX_IEGPIOR_LSB + bank];
325 break;
326
327 default:
328 return;
329 }
330
331 ret = stmpe_reg_read(stmpe, irqen_reg);
332 if (ret < 0)
333 return;
334 irqen = !!(ret & mask);
335
336 seq_printf(s, " gpio-%-3d (%-20.20s) in %s %13s %13s %25s %25s",
337 gpio, label ?: "(none)",
338 val ? "hi" : "lo",
339 edge_det_values[edge_det],
340 irqen ? "IRQ-enabled" : "IRQ-disabled",
341 rise_values[rise],
342 fall_values[fall]);
343 }
344}
345
346static void stmpe_dbg_show(struct seq_file *s, struct gpio_chip *gc)
347{
348 unsigned i;
349 unsigned gpio = gc->base;
350
351 for (i = 0; i < gc->ngpio; i++, gpio++) {
352 stmpe_dbg_show_one(s, gc, i, gpio);
353 seq_putc(s, '\n');
354 }
355}
356
357static struct irq_chip stmpe_gpio_irq_chip = {
358 .name = "stmpe-gpio",
359 .irq_bus_lock = stmpe_gpio_irq_lock,
360 .irq_bus_sync_unlock = stmpe_gpio_irq_sync_unlock,
361 .irq_mask = stmpe_gpio_irq_mask,
362 .irq_unmask = stmpe_gpio_irq_unmask,
363 .irq_set_type = stmpe_gpio_irq_set_type,
364};
365
366#define MAX_GPIOS 24
367
368static irqreturn_t stmpe_gpio_irq(int irq, void *dev)
369{
370 struct stmpe_gpio *stmpe_gpio = dev;
371 struct stmpe *stmpe = stmpe_gpio->stmpe;
372 u8 statmsbreg;
373 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
374 u8 status[DIV_ROUND_UP(MAX_GPIOS, 8)];
375 int ret;
376 int i;
377
378 /*
379 * the stmpe_block_read() call below, imposes to set statmsbreg
380 * with the register located at the lowest address. As STMPE1600
381 * variant is the only one which respect registers address's order
382 * (LSB regs located at lowest address than MSB ones) whereas all
383 * the others have a registers layout with MSB located before the
384 * LSB regs.
385 */
386 if (stmpe->partnum == STMPE1600)
387 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_LSB];
388 else
389 statmsbreg = stmpe->regs[STMPE_IDX_ISGPIOR_MSB];
390
391 ret = stmpe_block_read(stmpe, statmsbreg, num_banks, status);
392 if (ret < 0)
393 return IRQ_NONE;
394
395 for (i = 0; i < num_banks; i++) {
396 int bank = (stmpe_gpio->stmpe->partnum == STMPE1600) ? i :
397 num_banks - i - 1;
398 unsigned int enabled = stmpe_gpio->regs[REG_IE][bank];
399 unsigned int stat = status[i];
400
401 stat &= enabled;
402 if (!stat)
403 continue;
404
405 while (stat) {
406 int bit = __ffs(stat);
407 int line = bank * 8 + bit;
408 int child_irq = irq_find_mapping(stmpe_gpio->chip.irq.domain,
409 line);
410
411 handle_nested_irq(child_irq);
412 stat &= ~BIT(bit);
413 }
414
415 /*
416 * interrupt status register write has no effect on
417 * 801/1801/1600, bits are cleared when read.
418 * Edge detect register is not present on 801/1600/1801
419 */
420 if (stmpe->partnum != STMPE801 && stmpe->partnum != STMPE1600 &&
421 stmpe->partnum != STMPE1801) {
422 stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
423 stmpe_reg_write(stmpe,
424 stmpe->regs[STMPE_IDX_GPEDR_MSB] + i,
425 status[i]);
426 }
427 }
428
429 return IRQ_HANDLED;
430}
431
432static void stmpe_init_irq_valid_mask(struct gpio_chip *gc,
433 unsigned long *valid_mask,
434 unsigned int ngpios)
435{
436 struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
437 int i;
438
439 if (!stmpe_gpio->norequest_mask)
440 return;
441
442 /* Forbid unused lines to be mapped as IRQs */
443 for (i = 0; i < sizeof(u32); i++) {
444 if (stmpe_gpio->norequest_mask & BIT(i))
445 clear_bit(i, valid_mask);
446 }
447}
448
449static int stmpe_gpio_probe(struct platform_device *pdev)
450{
451 struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
452 struct device_node *np = pdev->dev.of_node;
453 struct stmpe_gpio *stmpe_gpio;
454 int ret, irq;
455
456 if (stmpe->num_gpios > MAX_GPIOS) {
457 dev_err(&pdev->dev, "Need to increase maximum GPIO number\n");
458 return -EINVAL;
459 }
460
461 stmpe_gpio = kzalloc(sizeof(*stmpe_gpio), GFP_KERNEL);
462 if (!stmpe_gpio)
463 return -ENOMEM;
464
465 mutex_init(&stmpe_gpio->irq_lock);
466
467 stmpe_gpio->dev = &pdev->dev;
468 stmpe_gpio->stmpe = stmpe;
469 stmpe_gpio->chip = template_chip;
470 stmpe_gpio->chip.ngpio = stmpe->num_gpios;
471 stmpe_gpio->chip.parent = &pdev->dev;
472 stmpe_gpio->chip.of_node = np;
473 stmpe_gpio->chip.base = -1;
474 /*
475 * REVISIT: this makes sure the valid mask gets allocated and
476 * filled in when adding the gpio_chip, but the rest of the
477 * gpio_irqchip is still filled in using the old method
478 * in gpiochip_irqchip_add_nested() so clean this up once we
479 * get the gpio_irqchip to initialize while adding the
480 * gpio_chip also for threaded irqchips.
481 */
482 stmpe_gpio->chip.irq.init_valid_mask = stmpe_init_irq_valid_mask;
483
484 if (IS_ENABLED(CONFIG_DEBUG_FS))
485 stmpe_gpio->chip.dbg_show = stmpe_dbg_show;
486
487 of_property_read_u32(np, "st,norequest-mask",
488 &stmpe_gpio->norequest_mask);
489
490 irq = platform_get_irq(pdev, 0);
491 if (irq < 0)
492 dev_info(&pdev->dev,
493 "device configured in no-irq mode: "
494 "irqs are not available\n");
495
496 ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
497 if (ret)
498 goto out_free;
499
500 ret = gpiochip_add_data(&stmpe_gpio->chip, stmpe_gpio);
501 if (ret) {
502 dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
503 goto out_disable;
504 }
505
506 if (irq > 0) {
507 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
508 stmpe_gpio_irq, IRQF_ONESHOT,
509 "stmpe-gpio", stmpe_gpio);
510 if (ret) {
511 dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
512 goto out_disable;
513 }
514 ret = gpiochip_irqchip_add_nested(&stmpe_gpio->chip,
515 &stmpe_gpio_irq_chip,
516 0,
517 handle_simple_irq,
518 IRQ_TYPE_NONE);
519 if (ret) {
520 dev_err(&pdev->dev,
521 "could not connect irqchip to gpiochip\n");
522 goto out_disable;
523 }
524
525 gpiochip_set_nested_irqchip(&stmpe_gpio->chip,
526 &stmpe_gpio_irq_chip,
527 irq);
528 }
529
530 platform_set_drvdata(pdev, stmpe_gpio);
531
532 return 0;
533
534out_disable:
535 stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
536 gpiochip_remove(&stmpe_gpio->chip);
537out_free:
538 kfree(stmpe_gpio);
539 return ret;
540}
541
542static struct platform_driver stmpe_gpio_driver = {
543 .driver = {
544 .suppress_bind_attrs = true,
545 .name = "stmpe-gpio",
546 },
547 .probe = stmpe_gpio_probe,
548};
549
550static int __init stmpe_gpio_init(void)
551{
552 return platform_driver_register(&stmpe_gpio_driver);
553}
554subsys_initcall(stmpe_gpio_init);