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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
4 */
5#include <linux/bits.h>
6#include <linux/gpio/driver.h>
7#include <linux/interrupt.h>
8#include <linux/irq.h>
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/pci.h>
12#include <linux/slab.h>
13
14#define PCH_EDGE_FALLING 0
15#define PCH_EDGE_RISING 1
16#define PCH_LEVEL_L 2
17#define PCH_LEVEL_H 3
18#define PCH_EDGE_BOTH 4
19#define PCH_IM_MASK GENMASK(2, 0)
20
21#define PCH_IRQ_BASE 24
22
23struct pch_regs {
24 u32 ien;
25 u32 istatus;
26 u32 idisp;
27 u32 iclr;
28 u32 imask;
29 u32 imaskclr;
30 u32 po;
31 u32 pi;
32 u32 pm;
33 u32 im0;
34 u32 im1;
35 u32 reserved[3];
36 u32 gpio_use_sel;
37 u32 reset;
38};
39
40#define PCI_DEVICE_ID_INTEL_EG20T_PCH 0x8803
41#define PCI_DEVICE_ID_ROHM_ML7223m_IOH 0x8014
42#define PCI_DEVICE_ID_ROHM_ML7223n_IOH 0x8043
43#define PCI_DEVICE_ID_ROHM_EG20T_PCH 0x8803
44
45enum pch_type_t {
46 INTEL_EG20T_PCH,
47 OKISEMI_ML7223m_IOH, /* LAPIS Semiconductor ML7223 IOH PCIe Bus-m */
48 OKISEMI_ML7223n_IOH /* LAPIS Semiconductor ML7223 IOH PCIe Bus-n */
49};
50
51/* Specifies number of GPIO PINS */
52static int gpio_pins[] = {
53 [INTEL_EG20T_PCH] = 12,
54 [OKISEMI_ML7223m_IOH] = 8,
55 [OKISEMI_ML7223n_IOH] = 8,
56};
57
58/**
59 * struct pch_gpio_reg_data - The register store data.
60 * @ien_reg: To store contents of IEN register.
61 * @imask_reg: To store contents of IMASK register.
62 * @po_reg: To store contents of PO register.
63 * @pm_reg: To store contents of PM register.
64 * @im0_reg: To store contents of IM0 register.
65 * @im1_reg: To store contents of IM1 register.
66 * @gpio_use_sel_reg : To store contents of GPIO_USE_SEL register.
67 * (Only ML7223 Bus-n)
68 */
69struct pch_gpio_reg_data {
70 u32 ien_reg;
71 u32 imask_reg;
72 u32 po_reg;
73 u32 pm_reg;
74 u32 im0_reg;
75 u32 im1_reg;
76 u32 gpio_use_sel_reg;
77};
78
79/**
80 * struct pch_gpio - GPIO private data structure.
81 * @base: PCI base address of Memory mapped I/O register.
82 * @reg: Memory mapped PCH GPIO register list.
83 * @dev: Pointer to device structure.
84 * @gpio: Data for GPIO infrastructure.
85 * @pch_gpio_reg: Memory mapped Register data is saved here
86 * when suspend.
87 * @irq_base: Save base of IRQ number for interrupt
88 * @ioh: IOH ID
89 * @spinlock: Used for register access protection
90 */
91struct pch_gpio {
92 void __iomem *base;
93 struct pch_regs __iomem *reg;
94 struct device *dev;
95 struct gpio_chip gpio;
96 struct pch_gpio_reg_data pch_gpio_reg;
97 int irq_base;
98 enum pch_type_t ioh;
99 spinlock_t spinlock;
100};
101
102static void pch_gpio_set(struct gpio_chip *gpio, unsigned int nr, int val)
103{
104 u32 reg_val;
105 struct pch_gpio *chip = gpiochip_get_data(gpio);
106 unsigned long flags;
107
108 spin_lock_irqsave(&chip->spinlock, flags);
109 reg_val = ioread32(&chip->reg->po);
110 if (val)
111 reg_val |= BIT(nr);
112 else
113 reg_val &= ~BIT(nr);
114
115 iowrite32(reg_val, &chip->reg->po);
116 spin_unlock_irqrestore(&chip->spinlock, flags);
117}
118
119static int pch_gpio_get(struct gpio_chip *gpio, unsigned int nr)
120{
121 struct pch_gpio *chip = gpiochip_get_data(gpio);
122
123 return !!(ioread32(&chip->reg->pi) & BIT(nr));
124}
125
126static int pch_gpio_direction_output(struct gpio_chip *gpio, unsigned int nr,
127 int val)
128{
129 struct pch_gpio *chip = gpiochip_get_data(gpio);
130 u32 pm;
131 u32 reg_val;
132 unsigned long flags;
133
134 spin_lock_irqsave(&chip->spinlock, flags);
135
136 reg_val = ioread32(&chip->reg->po);
137 if (val)
138 reg_val |= BIT(nr);
139 else
140 reg_val &= ~BIT(nr);
141 iowrite32(reg_val, &chip->reg->po);
142
143 pm = ioread32(&chip->reg->pm);
144 pm &= BIT(gpio_pins[chip->ioh]) - 1;
145 pm |= BIT(nr);
146 iowrite32(pm, &chip->reg->pm);
147
148 spin_unlock_irqrestore(&chip->spinlock, flags);
149
150 return 0;
151}
152
153static int pch_gpio_direction_input(struct gpio_chip *gpio, unsigned int nr)
154{
155 struct pch_gpio *chip = gpiochip_get_data(gpio);
156 u32 pm;
157 unsigned long flags;
158
159 spin_lock_irqsave(&chip->spinlock, flags);
160 pm = ioread32(&chip->reg->pm);
161 pm &= BIT(gpio_pins[chip->ioh]) - 1;
162 pm &= ~BIT(nr);
163 iowrite32(pm, &chip->reg->pm);
164 spin_unlock_irqrestore(&chip->spinlock, flags);
165
166 return 0;
167}
168
169/*
170 * Save register configuration and disable interrupts.
171 */
172static void __maybe_unused pch_gpio_save_reg_conf(struct pch_gpio *chip)
173{
174 chip->pch_gpio_reg.ien_reg = ioread32(&chip->reg->ien);
175 chip->pch_gpio_reg.imask_reg = ioread32(&chip->reg->imask);
176 chip->pch_gpio_reg.po_reg = ioread32(&chip->reg->po);
177 chip->pch_gpio_reg.pm_reg = ioread32(&chip->reg->pm);
178 chip->pch_gpio_reg.im0_reg = ioread32(&chip->reg->im0);
179 if (chip->ioh == INTEL_EG20T_PCH)
180 chip->pch_gpio_reg.im1_reg = ioread32(&chip->reg->im1);
181 if (chip->ioh == OKISEMI_ML7223n_IOH)
182 chip->pch_gpio_reg.gpio_use_sel_reg = ioread32(&chip->reg->gpio_use_sel);
183}
184
185/*
186 * This function restores the register configuration of the GPIO device.
187 */
188static void __maybe_unused pch_gpio_restore_reg_conf(struct pch_gpio *chip)
189{
190 iowrite32(chip->pch_gpio_reg.ien_reg, &chip->reg->ien);
191 iowrite32(chip->pch_gpio_reg.imask_reg, &chip->reg->imask);
192 /* to store contents of PO register */
193 iowrite32(chip->pch_gpio_reg.po_reg, &chip->reg->po);
194 /* to store contents of PM register */
195 iowrite32(chip->pch_gpio_reg.pm_reg, &chip->reg->pm);
196 iowrite32(chip->pch_gpio_reg.im0_reg, &chip->reg->im0);
197 if (chip->ioh == INTEL_EG20T_PCH)
198 iowrite32(chip->pch_gpio_reg.im1_reg, &chip->reg->im1);
199 if (chip->ioh == OKISEMI_ML7223n_IOH)
200 iowrite32(chip->pch_gpio_reg.gpio_use_sel_reg, &chip->reg->gpio_use_sel);
201}
202
203static int pch_gpio_to_irq(struct gpio_chip *gpio, unsigned int offset)
204{
205 struct pch_gpio *chip = gpiochip_get_data(gpio);
206
207 return chip->irq_base + offset;
208}
209
210static void pch_gpio_setup(struct pch_gpio *chip)
211{
212 struct gpio_chip *gpio = &chip->gpio;
213
214 gpio->label = dev_name(chip->dev);
215 gpio->parent = chip->dev;
216 gpio->owner = THIS_MODULE;
217 gpio->direction_input = pch_gpio_direction_input;
218 gpio->get = pch_gpio_get;
219 gpio->direction_output = pch_gpio_direction_output;
220 gpio->set = pch_gpio_set;
221 gpio->base = -1;
222 gpio->ngpio = gpio_pins[chip->ioh];
223 gpio->can_sleep = false;
224 gpio->to_irq = pch_gpio_to_irq;
225}
226
227static int pch_irq_type(struct irq_data *d, unsigned int type)
228{
229 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
230 struct pch_gpio *chip = gc->private;
231 u32 im, im_pos, val;
232 u32 __iomem *im_reg;
233 unsigned long flags;
234 int ch, irq = d->irq;
235
236 ch = irq - chip->irq_base;
237 if (irq < chip->irq_base + 8) {
238 im_reg = &chip->reg->im0;
239 im_pos = ch - 0;
240 } else {
241 im_reg = &chip->reg->im1;
242 im_pos = ch - 8;
243 }
244 dev_dbg(chip->dev, "irq=%d type=%d ch=%d pos=%d\n", irq, type, ch, im_pos);
245
246 switch (type) {
247 case IRQ_TYPE_EDGE_RISING:
248 val = PCH_EDGE_RISING;
249 break;
250 case IRQ_TYPE_EDGE_FALLING:
251 val = PCH_EDGE_FALLING;
252 break;
253 case IRQ_TYPE_EDGE_BOTH:
254 val = PCH_EDGE_BOTH;
255 break;
256 case IRQ_TYPE_LEVEL_HIGH:
257 val = PCH_LEVEL_H;
258 break;
259 case IRQ_TYPE_LEVEL_LOW:
260 val = PCH_LEVEL_L;
261 break;
262 default:
263 return 0;
264 }
265
266 spin_lock_irqsave(&chip->spinlock, flags);
267
268 /* Set interrupt mode */
269 im = ioread32(im_reg) & ~(PCH_IM_MASK << (im_pos * 4));
270 iowrite32(im | (val << (im_pos * 4)), im_reg);
271
272 /* And the handler */
273 if (type & IRQ_TYPE_LEVEL_MASK)
274 irq_set_handler_locked(d, handle_level_irq);
275 else if (type & IRQ_TYPE_EDGE_BOTH)
276 irq_set_handler_locked(d, handle_edge_irq);
277
278 spin_unlock_irqrestore(&chip->spinlock, flags);
279 return 0;
280}
281
282static void pch_irq_unmask(struct irq_data *d)
283{
284 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
285 struct pch_gpio *chip = gc->private;
286
287 iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->imaskclr);
288}
289
290static void pch_irq_mask(struct irq_data *d)
291{
292 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
293 struct pch_gpio *chip = gc->private;
294
295 iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->imask);
296}
297
298static void pch_irq_ack(struct irq_data *d)
299{
300 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
301 struct pch_gpio *chip = gc->private;
302
303 iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->iclr);
304}
305
306static irqreturn_t pch_gpio_handler(int irq, void *dev_id)
307{
308 struct pch_gpio *chip = dev_id;
309 unsigned long reg_val = ioread32(&chip->reg->istatus);
310 int i;
311
312 dev_vdbg(chip->dev, "irq=%d status=0x%lx\n", irq, reg_val);
313
314 reg_val &= BIT(gpio_pins[chip->ioh]) - 1;
315
316 for_each_set_bit(i, ®_val, gpio_pins[chip->ioh])
317 generic_handle_irq(chip->irq_base + i);
318
319 return IRQ_RETVAL(reg_val);
320}
321
322static int pch_gpio_alloc_generic_chip(struct pch_gpio *chip,
323 unsigned int irq_start,
324 unsigned int num)
325{
326 struct irq_chip_generic *gc;
327 struct irq_chip_type *ct;
328 int rv;
329
330 gc = devm_irq_alloc_generic_chip(chip->dev, "pch_gpio", 1, irq_start,
331 chip->base, handle_simple_irq);
332 if (!gc)
333 return -ENOMEM;
334
335 gc->private = chip;
336 ct = gc->chip_types;
337
338 ct->chip.irq_ack = pch_irq_ack;
339 ct->chip.irq_mask = pch_irq_mask;
340 ct->chip.irq_unmask = pch_irq_unmask;
341 ct->chip.irq_set_type = pch_irq_type;
342
343 rv = devm_irq_setup_generic_chip(chip->dev, gc, IRQ_MSK(num),
344 IRQ_GC_INIT_MASK_CACHE,
345 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
346
347 return rv;
348}
349
350static int pch_gpio_probe(struct pci_dev *pdev,
351 const struct pci_device_id *id)
352{
353 struct device *dev = &pdev->dev;
354 s32 ret;
355 struct pch_gpio *chip;
356 int irq_base;
357
358 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
359 if (chip == NULL)
360 return -ENOMEM;
361
362 chip->dev = dev;
363 ret = pcim_enable_device(pdev);
364 if (ret)
365 return dev_err_probe(dev, ret, "Failed to enable PCI device\n");
366
367 ret = pcim_iomap_regions(pdev, BIT(1), KBUILD_MODNAME);
368 if (ret)
369 return dev_err_probe(dev, ret, "Failed to request and map PCI regions\n");
370
371 chip->base = pcim_iomap_table(pdev)[1];
372 chip->ioh = id->driver_data;
373 chip->reg = chip->base;
374 pci_set_drvdata(pdev, chip);
375 spin_lock_init(&chip->spinlock);
376 pch_gpio_setup(chip);
377
378 ret = devm_gpiochip_add_data(dev, &chip->gpio, chip);
379 if (ret)
380 return dev_err_probe(dev, ret, "Failed to register GPIO\n");
381
382 irq_base = devm_irq_alloc_descs(dev, -1, 0,
383 gpio_pins[chip->ioh], NUMA_NO_NODE);
384 if (irq_base < 0) {
385 dev_warn(dev, "PCH gpio: Failed to get IRQ base num\n");
386 chip->irq_base = -1;
387 return 0;
388 }
389 chip->irq_base = irq_base;
390
391 /* Mask all interrupts, but enable them */
392 iowrite32(BIT(gpio_pins[chip->ioh]) - 1, &chip->reg->imask);
393 iowrite32(BIT(gpio_pins[chip->ioh]) - 1, &chip->reg->ien);
394
395 ret = devm_request_irq(dev, pdev->irq, pch_gpio_handler,
396 IRQF_SHARED, KBUILD_MODNAME, chip);
397 if (ret)
398 return dev_err_probe(dev, ret, "Failed to request IRQ\n");
399
400 return pch_gpio_alloc_generic_chip(chip, irq_base, gpio_pins[chip->ioh]);
401}
402
403static int __maybe_unused pch_gpio_suspend(struct device *dev)
404{
405 struct pch_gpio *chip = dev_get_drvdata(dev);
406 unsigned long flags;
407
408 spin_lock_irqsave(&chip->spinlock, flags);
409 pch_gpio_save_reg_conf(chip);
410 spin_unlock_irqrestore(&chip->spinlock, flags);
411
412 return 0;
413}
414
415static int __maybe_unused pch_gpio_resume(struct device *dev)
416{
417 struct pch_gpio *chip = dev_get_drvdata(dev);
418 unsigned long flags;
419
420 spin_lock_irqsave(&chip->spinlock, flags);
421 iowrite32(0x01, &chip->reg->reset);
422 iowrite32(0x00, &chip->reg->reset);
423 pch_gpio_restore_reg_conf(chip);
424 spin_unlock_irqrestore(&chip->spinlock, flags);
425
426 return 0;
427}
428
429static SIMPLE_DEV_PM_OPS(pch_gpio_pm_ops, pch_gpio_suspend, pch_gpio_resume);
430
431static const struct pci_device_id pch_gpio_pcidev_id[] = {
432 { PCI_DEVICE_DATA(INTEL, EG20T_PCH, INTEL_EG20T_PCH) },
433 { PCI_DEVICE_DATA(ROHM, ML7223m_IOH, OKISEMI_ML7223m_IOH) },
434 { PCI_DEVICE_DATA(ROHM, ML7223n_IOH, OKISEMI_ML7223n_IOH) },
435 { PCI_DEVICE_DATA(ROHM, EG20T_PCH, INTEL_EG20T_PCH) },
436 { }
437};
438MODULE_DEVICE_TABLE(pci, pch_gpio_pcidev_id);
439
440static struct pci_driver pch_gpio_driver = {
441 .name = "pch_gpio",
442 .id_table = pch_gpio_pcidev_id,
443 .probe = pch_gpio_probe,
444 .driver = {
445 .pm = &pch_gpio_pm_ops,
446 },
447};
448
449module_pci_driver(pch_gpio_driver);
450
451MODULE_DESCRIPTION("PCH GPIO PCI Driver");
452MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
4 */
5#include <linux/gpio/driver.h>
6#include <linux/interrupt.h>
7#include <linux/irq.h>
8#include <linux/kernel.h>
9#include <linux/module.h>
10#include <linux/pci.h>
11#include <linux/slab.h>
12
13#define PCH_EDGE_FALLING 0
14#define PCH_EDGE_RISING BIT(0)
15#define PCH_LEVEL_L BIT(1)
16#define PCH_LEVEL_H (BIT(0) | BIT(1))
17#define PCH_EDGE_BOTH BIT(2)
18#define PCH_IM_MASK (BIT(0) | BIT(1) | BIT(2))
19
20#define PCH_IRQ_BASE 24
21
22struct pch_regs {
23 u32 ien;
24 u32 istatus;
25 u32 idisp;
26 u32 iclr;
27 u32 imask;
28 u32 imaskclr;
29 u32 po;
30 u32 pi;
31 u32 pm;
32 u32 im0;
33 u32 im1;
34 u32 reserved[3];
35 u32 gpio_use_sel;
36 u32 reset;
37};
38
39enum pch_type_t {
40 INTEL_EG20T_PCH,
41 OKISEMI_ML7223m_IOH, /* LAPIS Semiconductor ML7223 IOH PCIe Bus-m */
42 OKISEMI_ML7223n_IOH /* LAPIS Semiconductor ML7223 IOH PCIe Bus-n */
43};
44
45/* Specifies number of GPIO PINS */
46static int gpio_pins[] = {
47 [INTEL_EG20T_PCH] = 12,
48 [OKISEMI_ML7223m_IOH] = 8,
49 [OKISEMI_ML7223n_IOH] = 8,
50};
51
52/**
53 * struct pch_gpio_reg_data - The register store data.
54 * @ien_reg: To store contents of IEN register.
55 * @imask_reg: To store contents of IMASK register.
56 * @po_reg: To store contents of PO register.
57 * @pm_reg: To store contents of PM register.
58 * @im0_reg: To store contents of IM0 register.
59 * @im1_reg: To store contents of IM1 register.
60 * @gpio_use_sel_reg : To store contents of GPIO_USE_SEL register.
61 * (Only ML7223 Bus-n)
62 */
63struct pch_gpio_reg_data {
64 u32 ien_reg;
65 u32 imask_reg;
66 u32 po_reg;
67 u32 pm_reg;
68 u32 im0_reg;
69 u32 im1_reg;
70 u32 gpio_use_sel_reg;
71};
72
73/**
74 * struct pch_gpio - GPIO private data structure.
75 * @base: PCI base address of Memory mapped I/O register.
76 * @reg: Memory mapped PCH GPIO register list.
77 * @dev: Pointer to device structure.
78 * @gpio: Data for GPIO infrastructure.
79 * @pch_gpio_reg: Memory mapped Register data is saved here
80 * when suspend.
81 * @lock: Used for register access protection
82 * @irq_base: Save base of IRQ number for interrupt
83 * @ioh: IOH ID
84 * @spinlock: Used for register access protection
85 */
86struct pch_gpio {
87 void __iomem *base;
88 struct pch_regs __iomem *reg;
89 struct device *dev;
90 struct gpio_chip gpio;
91 struct pch_gpio_reg_data pch_gpio_reg;
92 int irq_base;
93 enum pch_type_t ioh;
94 spinlock_t spinlock;
95};
96
97static void pch_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
98{
99 u32 reg_val;
100 struct pch_gpio *chip = gpiochip_get_data(gpio);
101 unsigned long flags;
102
103 spin_lock_irqsave(&chip->spinlock, flags);
104 reg_val = ioread32(&chip->reg->po);
105 if (val)
106 reg_val |= (1 << nr);
107 else
108 reg_val &= ~(1 << nr);
109
110 iowrite32(reg_val, &chip->reg->po);
111 spin_unlock_irqrestore(&chip->spinlock, flags);
112}
113
114static int pch_gpio_get(struct gpio_chip *gpio, unsigned nr)
115{
116 struct pch_gpio *chip = gpiochip_get_data(gpio);
117
118 return (ioread32(&chip->reg->pi) >> nr) & 1;
119}
120
121static int pch_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
122 int val)
123{
124 struct pch_gpio *chip = gpiochip_get_data(gpio);
125 u32 pm;
126 u32 reg_val;
127 unsigned long flags;
128
129 spin_lock_irqsave(&chip->spinlock, flags);
130
131 reg_val = ioread32(&chip->reg->po);
132 if (val)
133 reg_val |= (1 << nr);
134 else
135 reg_val &= ~(1 << nr);
136 iowrite32(reg_val, &chip->reg->po);
137
138 pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1);
139 pm |= (1 << nr);
140 iowrite32(pm, &chip->reg->pm);
141
142 spin_unlock_irqrestore(&chip->spinlock, flags);
143
144 return 0;
145}
146
147static int pch_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
148{
149 struct pch_gpio *chip = gpiochip_get_data(gpio);
150 u32 pm;
151 unsigned long flags;
152
153 spin_lock_irqsave(&chip->spinlock, flags);
154 pm = ioread32(&chip->reg->pm) & ((1 << gpio_pins[chip->ioh]) - 1);
155 pm &= ~(1 << nr);
156 iowrite32(pm, &chip->reg->pm);
157 spin_unlock_irqrestore(&chip->spinlock, flags);
158
159 return 0;
160}
161
162/*
163 * Save register configuration and disable interrupts.
164 */
165static void __maybe_unused pch_gpio_save_reg_conf(struct pch_gpio *chip)
166{
167 chip->pch_gpio_reg.ien_reg = ioread32(&chip->reg->ien);
168 chip->pch_gpio_reg.imask_reg = ioread32(&chip->reg->imask);
169 chip->pch_gpio_reg.po_reg = ioread32(&chip->reg->po);
170 chip->pch_gpio_reg.pm_reg = ioread32(&chip->reg->pm);
171 chip->pch_gpio_reg.im0_reg = ioread32(&chip->reg->im0);
172 if (chip->ioh == INTEL_EG20T_PCH)
173 chip->pch_gpio_reg.im1_reg = ioread32(&chip->reg->im1);
174 if (chip->ioh == OKISEMI_ML7223n_IOH)
175 chip->pch_gpio_reg.gpio_use_sel_reg = ioread32(&chip->reg->gpio_use_sel);
176}
177
178/*
179 * This function restores the register configuration of the GPIO device.
180 */
181static void __maybe_unused pch_gpio_restore_reg_conf(struct pch_gpio *chip)
182{
183 iowrite32(chip->pch_gpio_reg.ien_reg, &chip->reg->ien);
184 iowrite32(chip->pch_gpio_reg.imask_reg, &chip->reg->imask);
185 /* to store contents of PO register */
186 iowrite32(chip->pch_gpio_reg.po_reg, &chip->reg->po);
187 /* to store contents of PM register */
188 iowrite32(chip->pch_gpio_reg.pm_reg, &chip->reg->pm);
189 iowrite32(chip->pch_gpio_reg.im0_reg, &chip->reg->im0);
190 if (chip->ioh == INTEL_EG20T_PCH)
191 iowrite32(chip->pch_gpio_reg.im1_reg, &chip->reg->im1);
192 if (chip->ioh == OKISEMI_ML7223n_IOH)
193 iowrite32(chip->pch_gpio_reg.gpio_use_sel_reg, &chip->reg->gpio_use_sel);
194}
195
196static int pch_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
197{
198 struct pch_gpio *chip = gpiochip_get_data(gpio);
199 return chip->irq_base + offset;
200}
201
202static void pch_gpio_setup(struct pch_gpio *chip)
203{
204 struct gpio_chip *gpio = &chip->gpio;
205
206 gpio->label = dev_name(chip->dev);
207 gpio->parent = chip->dev;
208 gpio->owner = THIS_MODULE;
209 gpio->direction_input = pch_gpio_direction_input;
210 gpio->get = pch_gpio_get;
211 gpio->direction_output = pch_gpio_direction_output;
212 gpio->set = pch_gpio_set;
213 gpio->base = -1;
214 gpio->ngpio = gpio_pins[chip->ioh];
215 gpio->can_sleep = false;
216 gpio->to_irq = pch_gpio_to_irq;
217}
218
219static int pch_irq_type(struct irq_data *d, unsigned int type)
220{
221 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
222 struct pch_gpio *chip = gc->private;
223 u32 im, im_pos, val;
224 u32 __iomem *im_reg;
225 unsigned long flags;
226 int ch, irq = d->irq;
227
228 ch = irq - chip->irq_base;
229 if (irq <= chip->irq_base + 7) {
230 im_reg = &chip->reg->im0;
231 im_pos = ch;
232 } else {
233 im_reg = &chip->reg->im1;
234 im_pos = ch - 8;
235 }
236 dev_dbg(chip->dev, "irq=%d type=%d ch=%d pos=%d\n", irq, type, ch, im_pos);
237
238 spin_lock_irqsave(&chip->spinlock, flags);
239
240 switch (type) {
241 case IRQ_TYPE_EDGE_RISING:
242 val = PCH_EDGE_RISING;
243 break;
244 case IRQ_TYPE_EDGE_FALLING:
245 val = PCH_EDGE_FALLING;
246 break;
247 case IRQ_TYPE_EDGE_BOTH:
248 val = PCH_EDGE_BOTH;
249 break;
250 case IRQ_TYPE_LEVEL_HIGH:
251 val = PCH_LEVEL_H;
252 break;
253 case IRQ_TYPE_LEVEL_LOW:
254 val = PCH_LEVEL_L;
255 break;
256 default:
257 goto unlock;
258 }
259
260 /* Set interrupt mode */
261 im = ioread32(im_reg) & ~(PCH_IM_MASK << (im_pos * 4));
262 iowrite32(im | (val << (im_pos * 4)), im_reg);
263
264 /* And the handler */
265 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
266 irq_set_handler_locked(d, handle_level_irq);
267 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
268 irq_set_handler_locked(d, handle_edge_irq);
269
270unlock:
271 spin_unlock_irqrestore(&chip->spinlock, flags);
272 return 0;
273}
274
275static void pch_irq_unmask(struct irq_data *d)
276{
277 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
278 struct pch_gpio *chip = gc->private;
279
280 iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imaskclr);
281}
282
283static void pch_irq_mask(struct irq_data *d)
284{
285 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
286 struct pch_gpio *chip = gc->private;
287
288 iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->imask);
289}
290
291static void pch_irq_ack(struct irq_data *d)
292{
293 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
294 struct pch_gpio *chip = gc->private;
295
296 iowrite32(1 << (d->irq - chip->irq_base), &chip->reg->iclr);
297}
298
299static irqreturn_t pch_gpio_handler(int irq, void *dev_id)
300{
301 struct pch_gpio *chip = dev_id;
302 unsigned long reg_val = ioread32(&chip->reg->istatus);
303 int i, ret = IRQ_NONE;
304
305 for_each_set_bit(i, ®_val, gpio_pins[chip->ioh]) {
306 dev_dbg(chip->dev, "[%d]:irq=%d status=0x%lx\n", i, irq, reg_val);
307 generic_handle_irq(chip->irq_base + i);
308 ret = IRQ_HANDLED;
309 }
310 return ret;
311}
312
313static int pch_gpio_alloc_generic_chip(struct pch_gpio *chip,
314 unsigned int irq_start,
315 unsigned int num)
316{
317 struct irq_chip_generic *gc;
318 struct irq_chip_type *ct;
319 int rv;
320
321 gc = devm_irq_alloc_generic_chip(chip->dev, "pch_gpio", 1, irq_start,
322 chip->base, handle_simple_irq);
323 if (!gc)
324 return -ENOMEM;
325
326 gc->private = chip;
327 ct = gc->chip_types;
328
329 ct->chip.irq_ack = pch_irq_ack;
330 ct->chip.irq_mask = pch_irq_mask;
331 ct->chip.irq_unmask = pch_irq_unmask;
332 ct->chip.irq_set_type = pch_irq_type;
333
334 rv = devm_irq_setup_generic_chip(chip->dev, gc, IRQ_MSK(num),
335 IRQ_GC_INIT_MASK_CACHE,
336 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
337
338 return rv;
339}
340
341static int pch_gpio_probe(struct pci_dev *pdev,
342 const struct pci_device_id *id)
343{
344 s32 ret;
345 struct pch_gpio *chip;
346 int irq_base;
347 u32 msk;
348
349 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
350 if (chip == NULL)
351 return -ENOMEM;
352
353 chip->dev = &pdev->dev;
354 ret = pcim_enable_device(pdev);
355 if (ret) {
356 dev_err(&pdev->dev, "pci_enable_device FAILED");
357 return ret;
358 }
359
360 ret = pcim_iomap_regions(pdev, 1 << 1, KBUILD_MODNAME);
361 if (ret) {
362 dev_err(&pdev->dev, "pci_request_regions FAILED-%d", ret);
363 return ret;
364 }
365
366 chip->base = pcim_iomap_table(pdev)[1];
367
368 if (pdev->device == 0x8803)
369 chip->ioh = INTEL_EG20T_PCH;
370 else if (pdev->device == 0x8014)
371 chip->ioh = OKISEMI_ML7223m_IOH;
372 else if (pdev->device == 0x8043)
373 chip->ioh = OKISEMI_ML7223n_IOH;
374
375 chip->reg = chip->base;
376 pci_set_drvdata(pdev, chip);
377 spin_lock_init(&chip->spinlock);
378 pch_gpio_setup(chip);
379
380 ret = devm_gpiochip_add_data(&pdev->dev, &chip->gpio, chip);
381 if (ret) {
382 dev_err(&pdev->dev, "PCH gpio: Failed to register GPIO\n");
383 return ret;
384 }
385
386 irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0,
387 gpio_pins[chip->ioh], NUMA_NO_NODE);
388 if (irq_base < 0) {
389 dev_warn(&pdev->dev, "PCH gpio: Failed to get IRQ base num\n");
390 chip->irq_base = -1;
391 return 0;
392 }
393 chip->irq_base = irq_base;
394
395 /* Mask all interrupts, but enable them */
396 msk = (1 << gpio_pins[chip->ioh]) - 1;
397 iowrite32(msk, &chip->reg->imask);
398 iowrite32(msk, &chip->reg->ien);
399
400 ret = devm_request_irq(&pdev->dev, pdev->irq, pch_gpio_handler,
401 IRQF_SHARED, KBUILD_MODNAME, chip);
402 if (ret) {
403 dev_err(&pdev->dev, "request_irq failed\n");
404 return ret;
405 }
406
407 return pch_gpio_alloc_generic_chip(chip, irq_base, gpio_pins[chip->ioh]);
408}
409
410static int __maybe_unused pch_gpio_suspend(struct device *dev)
411{
412 struct pch_gpio *chip = dev_get_drvdata(dev);
413 unsigned long flags;
414
415 spin_lock_irqsave(&chip->spinlock, flags);
416 pch_gpio_save_reg_conf(chip);
417 spin_unlock_irqrestore(&chip->spinlock, flags);
418
419 return 0;
420}
421
422static int __maybe_unused pch_gpio_resume(struct device *dev)
423{
424 struct pch_gpio *chip = dev_get_drvdata(dev);
425 unsigned long flags;
426
427 spin_lock_irqsave(&chip->spinlock, flags);
428 iowrite32(0x01, &chip->reg->reset);
429 iowrite32(0x00, &chip->reg->reset);
430 pch_gpio_restore_reg_conf(chip);
431 spin_unlock_irqrestore(&chip->spinlock, flags);
432
433 return 0;
434}
435
436static SIMPLE_DEV_PM_OPS(pch_gpio_pm_ops, pch_gpio_suspend, pch_gpio_resume);
437
438static const struct pci_device_id pch_gpio_pcidev_id[] = {
439 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8803) },
440 { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8014) },
441 { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8043) },
442 { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8803) },
443 { 0, }
444};
445MODULE_DEVICE_TABLE(pci, pch_gpio_pcidev_id);
446
447static struct pci_driver pch_gpio_driver = {
448 .name = "pch_gpio",
449 .id_table = pch_gpio_pcidev_id,
450 .probe = pch_gpio_probe,
451 .driver = {
452 .pm = &pch_gpio_pm_ops,
453 },
454};
455
456module_pci_driver(pch_gpio_driver);
457
458MODULE_DESCRIPTION("PCH GPIO PCI Driver");
459MODULE_LICENSE("GPL v2");