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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Driver for Aeroflex Gaisler GRGPIO General Purpose I/O cores.
4 *
5 * 2013 (c) Aeroflex Gaisler AB
6 *
7 * This driver supports the GRGPIO GPIO core available in the GRLIB VHDL
8 * IP core library.
9 *
10 * Full documentation of the GRGPIO core can be found here:
11 * http://www.gaisler.com/products/grlib/grip.pdf
12 *
13 * See "Documentation/devicetree/bindings/gpio/gpio-grgpio.txt" for
14 * information on open firmware properties.
15 *
16 * Contributors: Andreas Larsson <andreas@gaisler.com>
17 */
18
19#include <linux/bitops.h>
20#include <linux/err.h>
21#include <linux/gpio/driver.h>
22#include <linux/init.h>
23#include <linux/interrupt.h>
24#include <linux/io.h>
25#include <linux/irq.h>
26#include <linux/irqdomain.h>
27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/of.h>
30#include <linux/platform_device.h>
31#include <linux/slab.h>
32#include <linux/spinlock.h>
33
34#define GRGPIO_MAX_NGPIO 32
35
36#define GRGPIO_DATA 0x00
37#define GRGPIO_OUTPUT 0x04
38#define GRGPIO_DIR 0x08
39#define GRGPIO_IMASK 0x0c
40#define GRGPIO_IPOL 0x10
41#define GRGPIO_IEDGE 0x14
42#define GRGPIO_BYPASS 0x18
43#define GRGPIO_IMAP_BASE 0x20
44
45/* Structure for an irq of the core - called an underlying irq */
46struct grgpio_uirq {
47 u8 refcnt; /* Reference counter to manage requesting/freeing of uirq */
48 u8 uirq; /* Underlying irq of the gpio driver */
49};
50
51/*
52 * Structure for an irq of a gpio line handed out by this driver. The index is
53 * used to map to the corresponding underlying irq.
54 */
55struct grgpio_lirq {
56 s8 index; /* Index into struct grgpio_priv's uirqs, or -1 */
57 u8 irq; /* irq for the gpio line */
58};
59
60struct grgpio_priv {
61 struct gpio_chip gc;
62 void __iomem *regs;
63 struct device *dev;
64
65 u32 imask; /* irq mask shadow register */
66
67 /*
68 * The grgpio core can have multiple "underlying" irqs. The gpio lines
69 * can be mapped to any one or none of these underlying irqs
70 * independently of each other. This driver sets up an irq domain and
71 * hands out separate irqs to each gpio line
72 */
73 struct irq_domain *domain;
74
75 /*
76 * This array contains information on each underlying irq, each
77 * irq of the grgpio core itself.
78 */
79 struct grgpio_uirq uirqs[GRGPIO_MAX_NGPIO];
80
81 /*
82 * This array contains information for each gpio line on the irqs
83 * obtains from this driver. An index value of -1 for a certain gpio
84 * line indicates that the line has no irq. Otherwise the index connects
85 * the irq to the underlying irq by pointing into the uirqs array.
86 */
87 struct grgpio_lirq lirqs[GRGPIO_MAX_NGPIO];
88};
89
90static void grgpio_set_imask(struct grgpio_priv *priv, unsigned int offset,
91 int val)
92{
93 struct gpio_chip *gc = &priv->gc;
94
95 if (val)
96 priv->imask |= BIT(offset);
97 else
98 priv->imask &= ~BIT(offset);
99 gc->write_reg(priv->regs + GRGPIO_IMASK, priv->imask);
100}
101
102static int grgpio_to_irq(struct gpio_chip *gc, unsigned offset)
103{
104 struct grgpio_priv *priv = gpiochip_get_data(gc);
105
106 if (offset >= gc->ngpio)
107 return -ENXIO;
108
109 if (priv->lirqs[offset].index < 0)
110 return -ENXIO;
111
112 return irq_create_mapping(priv->domain, offset);
113}
114
115/* -------------------- IRQ chip functions -------------------- */
116
117static int grgpio_irq_set_type(struct irq_data *d, unsigned int type)
118{
119 struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
120 unsigned long flags;
121 u32 mask = BIT(d->hwirq);
122 u32 ipol;
123 u32 iedge;
124 u32 pol;
125 u32 edge;
126
127 switch (type) {
128 case IRQ_TYPE_LEVEL_LOW:
129 pol = 0;
130 edge = 0;
131 break;
132 case IRQ_TYPE_LEVEL_HIGH:
133 pol = mask;
134 edge = 0;
135 break;
136 case IRQ_TYPE_EDGE_FALLING:
137 pol = 0;
138 edge = mask;
139 break;
140 case IRQ_TYPE_EDGE_RISING:
141 pol = mask;
142 edge = mask;
143 break;
144 default:
145 return -EINVAL;
146 }
147
148 raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
149
150 ipol = priv->gc.read_reg(priv->regs + GRGPIO_IPOL) & ~mask;
151 iedge = priv->gc.read_reg(priv->regs + GRGPIO_IEDGE) & ~mask;
152
153 priv->gc.write_reg(priv->regs + GRGPIO_IPOL, ipol | pol);
154 priv->gc.write_reg(priv->regs + GRGPIO_IEDGE, iedge | edge);
155
156 raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
157
158 return 0;
159}
160
161static void grgpio_irq_mask(struct irq_data *d)
162{
163 struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
164 int offset = d->hwirq;
165 unsigned long flags;
166
167 raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
168
169 grgpio_set_imask(priv, offset, 0);
170
171 raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
172}
173
174static void grgpio_irq_unmask(struct irq_data *d)
175{
176 struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
177 int offset = d->hwirq;
178 unsigned long flags;
179
180 raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
181
182 grgpio_set_imask(priv, offset, 1);
183
184 raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
185}
186
187static struct irq_chip grgpio_irq_chip = {
188 .name = "grgpio",
189 .irq_mask = grgpio_irq_mask,
190 .irq_unmask = grgpio_irq_unmask,
191 .irq_set_type = grgpio_irq_set_type,
192};
193
194static irqreturn_t grgpio_irq_handler(int irq, void *dev)
195{
196 struct grgpio_priv *priv = dev;
197 int ngpio = priv->gc.ngpio;
198 unsigned long flags;
199 int i;
200 int match = 0;
201
202 raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
203
204 /*
205 * For each gpio line, call its interrupt handler if it its underlying
206 * irq matches the current irq that is handled.
207 */
208 for (i = 0; i < ngpio; i++) {
209 struct grgpio_lirq *lirq = &priv->lirqs[i];
210
211 if (priv->imask & BIT(i) && lirq->index >= 0 &&
212 priv->uirqs[lirq->index].uirq == irq) {
213 generic_handle_irq(lirq->irq);
214 match = 1;
215 }
216 }
217
218 raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
219
220 if (!match)
221 dev_warn(priv->dev, "No gpio line matched irq %d\n", irq);
222
223 return IRQ_HANDLED;
224}
225
226/*
227 * This function will be called as a consequence of the call to
228 * irq_create_mapping in grgpio_to_irq
229 */
230static int grgpio_irq_map(struct irq_domain *d, unsigned int irq,
231 irq_hw_number_t hwirq)
232{
233 struct grgpio_priv *priv = d->host_data;
234 struct grgpio_lirq *lirq;
235 struct grgpio_uirq *uirq;
236 unsigned long flags;
237 int offset = hwirq;
238 int ret = 0;
239
240 if (!priv)
241 return -EINVAL;
242
243 lirq = &priv->lirqs[offset];
244 if (lirq->index < 0)
245 return -EINVAL;
246
247 dev_dbg(priv->dev, "Mapping irq %d for gpio line %d\n",
248 irq, offset);
249
250 raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
251
252 /* Request underlying irq if not already requested */
253 lirq->irq = irq;
254 uirq = &priv->uirqs[lirq->index];
255 if (uirq->refcnt == 0) {
256 raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
257 ret = request_irq(uirq->uirq, grgpio_irq_handler, 0,
258 dev_name(priv->dev), priv);
259 if (ret) {
260 dev_err(priv->dev,
261 "Could not request underlying irq %d\n",
262 uirq->uirq);
263 return ret;
264 }
265 raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
266 }
267 uirq->refcnt++;
268
269 raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
270
271 /* Setup irq */
272 irq_set_chip_data(irq, priv);
273 irq_set_chip_and_handler(irq, &grgpio_irq_chip,
274 handle_simple_irq);
275 irq_set_noprobe(irq);
276
277 return ret;
278}
279
280static void grgpio_irq_unmap(struct irq_domain *d, unsigned int irq)
281{
282 struct grgpio_priv *priv = d->host_data;
283 int index;
284 struct grgpio_lirq *lirq;
285 struct grgpio_uirq *uirq;
286 unsigned long flags;
287 int ngpio = priv->gc.ngpio;
288 int i;
289
290 irq_set_chip_and_handler(irq, NULL, NULL);
291 irq_set_chip_data(irq, NULL);
292
293 raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
294
295 /* Free underlying irq if last user unmapped */
296 index = -1;
297 for (i = 0; i < ngpio; i++) {
298 lirq = &priv->lirqs[i];
299 if (lirq->irq == irq) {
300 grgpio_set_imask(priv, i, 0);
301 lirq->irq = 0;
302 index = lirq->index;
303 break;
304 }
305 }
306 WARN_ON(index < 0);
307
308 if (index >= 0) {
309 uirq = &priv->uirqs[lirq->index];
310 uirq->refcnt--;
311 if (uirq->refcnt == 0) {
312 raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
313 free_irq(uirq->uirq, priv);
314 return;
315 }
316 }
317
318 raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
319}
320
321static void grgpio_irq_domain_remove(void *data)
322{
323 struct irq_domain *domain = data;
324
325 irq_domain_remove(domain);
326}
327
328static const struct irq_domain_ops grgpio_irq_domain_ops = {
329 .map = grgpio_irq_map,
330 .unmap = grgpio_irq_unmap,
331};
332
333/* ------------------------------------------------------------ */
334
335static int grgpio_probe(struct platform_device *ofdev)
336{
337 struct device_node *np = ofdev->dev.of_node;
338 struct device *dev = &ofdev->dev;
339 void __iomem *regs;
340 struct gpio_chip *gc;
341 struct grgpio_priv *priv;
342 int err;
343 u32 prop;
344 s32 *irqmap;
345 int size;
346 int i;
347
348 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
349 if (!priv)
350 return -ENOMEM;
351
352 regs = devm_platform_ioremap_resource(ofdev, 0);
353 if (IS_ERR(regs))
354 return PTR_ERR(regs);
355
356 gc = &priv->gc;
357 err = bgpio_init(gc, dev, 4, regs + GRGPIO_DATA,
358 regs + GRGPIO_OUTPUT, NULL, regs + GRGPIO_DIR, NULL,
359 BGPIOF_BIG_ENDIAN_BYTE_ORDER);
360 if (err) {
361 dev_err(dev, "bgpio_init() failed\n");
362 return err;
363 }
364
365 priv->regs = regs;
366 priv->imask = gc->read_reg(regs + GRGPIO_IMASK);
367 priv->dev = dev;
368
369 gc->owner = THIS_MODULE;
370 gc->to_irq = grgpio_to_irq;
371 gc->label = devm_kasprintf(dev, GFP_KERNEL, "%pOF", np);
372 if (!gc->label)
373 return -ENOMEM;
374
375 gc->base = -1;
376
377 err = of_property_read_u32(np, "nbits", &prop);
378 if (err || prop <= 0 || prop > GRGPIO_MAX_NGPIO) {
379 gc->ngpio = GRGPIO_MAX_NGPIO;
380 dev_dbg(dev, "No or invalid nbits property: assume %d\n",
381 gc->ngpio);
382 } else {
383 gc->ngpio = prop;
384 }
385
386 /*
387 * The irqmap contains the index values indicating which underlying irq,
388 * if anyone, is connected to that line
389 */
390 irqmap = (s32 *)of_get_property(np, "irqmap", &size);
391 if (irqmap) {
392 if (size < gc->ngpio) {
393 dev_err(dev,
394 "irqmap shorter than ngpio (%d < %d)\n",
395 size, gc->ngpio);
396 return -EINVAL;
397 }
398
399 priv->domain = irq_domain_add_linear(np, gc->ngpio,
400 &grgpio_irq_domain_ops,
401 priv);
402 if (!priv->domain) {
403 dev_err(dev, "Could not add irq domain\n");
404 return -EINVAL;
405 }
406
407 err = devm_add_action_or_reset(dev, grgpio_irq_domain_remove,
408 priv->domain);
409 if (err)
410 return err;
411
412 for (i = 0; i < gc->ngpio; i++) {
413 struct grgpio_lirq *lirq;
414 int ret;
415
416 lirq = &priv->lirqs[i];
417 lirq->index = irqmap[i];
418
419 if (lirq->index < 0)
420 continue;
421
422 ret = platform_get_irq(ofdev, lirq->index);
423 if (ret <= 0) {
424 /*
425 * Continue without irq functionality for that
426 * gpio line
427 */
428 continue;
429 }
430 priv->uirqs[lirq->index].uirq = ret;
431 }
432 }
433
434 err = devm_gpiochip_add_data(dev, gc, priv);
435 if (err) {
436 dev_err(dev, "Could not add gpiochip\n");
437 return err;
438 }
439
440 dev_info(dev, "regs=0x%p, base=%d, ngpio=%d, irqs=%s\n",
441 priv->regs, gc->base, gc->ngpio, priv->domain ? "on" : "off");
442
443 return 0;
444}
445
446static const struct of_device_id grgpio_match[] = {
447 {.name = "GAISLER_GPIO"},
448 {.name = "01_01a"},
449 {},
450};
451
452MODULE_DEVICE_TABLE(of, grgpio_match);
453
454static struct platform_driver grgpio_driver = {
455 .driver = {
456 .name = "grgpio",
457 .of_match_table = grgpio_match,
458 },
459 .probe = grgpio_probe,
460};
461module_platform_driver(grgpio_driver);
462
463MODULE_AUTHOR("Aeroflex Gaisler AB.");
464MODULE_DESCRIPTION("Driver for Aeroflex Gaisler GRGPIO");
465MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Driver for Aeroflex Gaisler GRGPIO General Purpose I/O cores.
4 *
5 * 2013 (c) Aeroflex Gaisler AB
6 *
7 * This driver supports the GRGPIO GPIO core available in the GRLIB VHDL
8 * IP core library.
9 *
10 * Full documentation of the GRGPIO core can be found here:
11 * http://www.gaisler.com/products/grlib/grip.pdf
12 *
13 * See "Documentation/devicetree/bindings/gpio/gpio-grgpio.txt" for
14 * information on open firmware properties.
15 *
16 * Contributors: Andreas Larsson <andreas@gaisler.com>
17 */
18
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/init.h>
22#include <linux/spinlock.h>
23#include <linux/io.h>
24#include <linux/of.h>
25#include <linux/of_platform.h>
26#include <linux/gpio/driver.h>
27#include <linux/slab.h>
28#include <linux/err.h>
29#include <linux/interrupt.h>
30#include <linux/irq.h>
31#include <linux/irqdomain.h>
32#include <linux/bitops.h>
33
34#define GRGPIO_MAX_NGPIO 32
35
36#define GRGPIO_DATA 0x00
37#define GRGPIO_OUTPUT 0x04
38#define GRGPIO_DIR 0x08
39#define GRGPIO_IMASK 0x0c
40#define GRGPIO_IPOL 0x10
41#define GRGPIO_IEDGE 0x14
42#define GRGPIO_BYPASS 0x18
43#define GRGPIO_IMAP_BASE 0x20
44
45/* Structure for an irq of the core - called an underlying irq */
46struct grgpio_uirq {
47 u8 refcnt; /* Reference counter to manage requesting/freeing of uirq */
48 u8 uirq; /* Underlying irq of the gpio driver */
49};
50
51/*
52 * Structure for an irq of a gpio line handed out by this driver. The index is
53 * used to map to the corresponding underlying irq.
54 */
55struct grgpio_lirq {
56 s8 index; /* Index into struct grgpio_priv's uirqs, or -1 */
57 u8 irq; /* irq for the gpio line */
58};
59
60struct grgpio_priv {
61 struct gpio_chip gc;
62 void __iomem *regs;
63 struct device *dev;
64
65 u32 imask; /* irq mask shadow register */
66
67 /*
68 * The grgpio core can have multiple "underlying" irqs. The gpio lines
69 * can be mapped to any one or none of these underlying irqs
70 * independently of each other. This driver sets up an irq domain and
71 * hands out separate irqs to each gpio line
72 */
73 struct irq_domain *domain;
74
75 /*
76 * This array contains information on each underlying irq, each
77 * irq of the grgpio core itself.
78 */
79 struct grgpio_uirq uirqs[GRGPIO_MAX_NGPIO];
80
81 /*
82 * This array contains information for each gpio line on the irqs
83 * obtains from this driver. An index value of -1 for a certain gpio
84 * line indicates that the line has no irq. Otherwise the index connects
85 * the irq to the underlying irq by pointing into the uirqs array.
86 */
87 struct grgpio_lirq lirqs[GRGPIO_MAX_NGPIO];
88};
89
90static void grgpio_set_imask(struct grgpio_priv *priv, unsigned int offset,
91 int val)
92{
93 struct gpio_chip *gc = &priv->gc;
94
95 if (val)
96 priv->imask |= BIT(offset);
97 else
98 priv->imask &= ~BIT(offset);
99 gc->write_reg(priv->regs + GRGPIO_IMASK, priv->imask);
100}
101
102static int grgpio_to_irq(struct gpio_chip *gc, unsigned offset)
103{
104 struct grgpio_priv *priv = gpiochip_get_data(gc);
105
106 if (offset >= gc->ngpio)
107 return -ENXIO;
108
109 if (priv->lirqs[offset].index < 0)
110 return -ENXIO;
111
112 return irq_create_mapping(priv->domain, offset);
113}
114
115/* -------------------- IRQ chip functions -------------------- */
116
117static int grgpio_irq_set_type(struct irq_data *d, unsigned int type)
118{
119 struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
120 unsigned long flags;
121 u32 mask = BIT(d->hwirq);
122 u32 ipol;
123 u32 iedge;
124 u32 pol;
125 u32 edge;
126
127 switch (type) {
128 case IRQ_TYPE_LEVEL_LOW:
129 pol = 0;
130 edge = 0;
131 break;
132 case IRQ_TYPE_LEVEL_HIGH:
133 pol = mask;
134 edge = 0;
135 break;
136 case IRQ_TYPE_EDGE_FALLING:
137 pol = 0;
138 edge = mask;
139 break;
140 case IRQ_TYPE_EDGE_RISING:
141 pol = mask;
142 edge = mask;
143 break;
144 default:
145 return -EINVAL;
146 }
147
148 spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
149
150 ipol = priv->gc.read_reg(priv->regs + GRGPIO_IPOL) & ~mask;
151 iedge = priv->gc.read_reg(priv->regs + GRGPIO_IEDGE) & ~mask;
152
153 priv->gc.write_reg(priv->regs + GRGPIO_IPOL, ipol | pol);
154 priv->gc.write_reg(priv->regs + GRGPIO_IEDGE, iedge | edge);
155
156 spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
157
158 return 0;
159}
160
161static void grgpio_irq_mask(struct irq_data *d)
162{
163 struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
164 int offset = d->hwirq;
165 unsigned long flags;
166
167 spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
168
169 grgpio_set_imask(priv, offset, 0);
170
171 spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
172}
173
174static void grgpio_irq_unmask(struct irq_data *d)
175{
176 struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
177 int offset = d->hwirq;
178 unsigned long flags;
179
180 spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
181
182 grgpio_set_imask(priv, offset, 1);
183
184 spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
185}
186
187static struct irq_chip grgpio_irq_chip = {
188 .name = "grgpio",
189 .irq_mask = grgpio_irq_mask,
190 .irq_unmask = grgpio_irq_unmask,
191 .irq_set_type = grgpio_irq_set_type,
192};
193
194static irqreturn_t grgpio_irq_handler(int irq, void *dev)
195{
196 struct grgpio_priv *priv = dev;
197 int ngpio = priv->gc.ngpio;
198 unsigned long flags;
199 int i;
200 int match = 0;
201
202 spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
203
204 /*
205 * For each gpio line, call its interrupt handler if it its underlying
206 * irq matches the current irq that is handled.
207 */
208 for (i = 0; i < ngpio; i++) {
209 struct grgpio_lirq *lirq = &priv->lirqs[i];
210
211 if (priv->imask & BIT(i) && lirq->index >= 0 &&
212 priv->uirqs[lirq->index].uirq == irq) {
213 generic_handle_irq(lirq->irq);
214 match = 1;
215 }
216 }
217
218 spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
219
220 if (!match)
221 dev_warn(priv->dev, "No gpio line matched irq %d\n", irq);
222
223 return IRQ_HANDLED;
224}
225
226/*
227 * This function will be called as a consequence of the call to
228 * irq_create_mapping in grgpio_to_irq
229 */
230static int grgpio_irq_map(struct irq_domain *d, unsigned int irq,
231 irq_hw_number_t hwirq)
232{
233 struct grgpio_priv *priv = d->host_data;
234 struct grgpio_lirq *lirq;
235 struct grgpio_uirq *uirq;
236 unsigned long flags;
237 int offset = hwirq;
238 int ret = 0;
239
240 if (!priv)
241 return -EINVAL;
242
243 lirq = &priv->lirqs[offset];
244 if (lirq->index < 0)
245 return -EINVAL;
246
247 dev_dbg(priv->dev, "Mapping irq %d for gpio line %d\n",
248 irq, offset);
249
250 spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
251
252 /* Request underlying irq if not already requested */
253 lirq->irq = irq;
254 uirq = &priv->uirqs[lirq->index];
255 if (uirq->refcnt == 0) {
256 ret = request_irq(uirq->uirq, grgpio_irq_handler, 0,
257 dev_name(priv->dev), priv);
258 if (ret) {
259 dev_err(priv->dev,
260 "Could not request underlying irq %d\n",
261 uirq->uirq);
262
263 spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
264
265 return ret;
266 }
267 }
268 uirq->refcnt++;
269
270 spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
271
272 /* Setup irq */
273 irq_set_chip_data(irq, priv);
274 irq_set_chip_and_handler(irq, &grgpio_irq_chip,
275 handle_simple_irq);
276 irq_set_noprobe(irq);
277
278 return ret;
279}
280
281static void grgpio_irq_unmap(struct irq_domain *d, unsigned int irq)
282{
283 struct grgpio_priv *priv = d->host_data;
284 int index;
285 struct grgpio_lirq *lirq;
286 struct grgpio_uirq *uirq;
287 unsigned long flags;
288 int ngpio = priv->gc.ngpio;
289 int i;
290
291 irq_set_chip_and_handler(irq, NULL, NULL);
292 irq_set_chip_data(irq, NULL);
293
294 spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
295
296 /* Free underlying irq if last user unmapped */
297 index = -1;
298 for (i = 0; i < ngpio; i++) {
299 lirq = &priv->lirqs[i];
300 if (lirq->irq == irq) {
301 grgpio_set_imask(priv, i, 0);
302 lirq->irq = 0;
303 index = lirq->index;
304 break;
305 }
306 }
307 WARN_ON(index < 0);
308
309 if (index >= 0) {
310 uirq = &priv->uirqs[lirq->index];
311 uirq->refcnt--;
312 if (uirq->refcnt == 0)
313 free_irq(uirq->uirq, priv);
314 }
315
316 spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
317}
318
319static const struct irq_domain_ops grgpio_irq_domain_ops = {
320 .map = grgpio_irq_map,
321 .unmap = grgpio_irq_unmap,
322};
323
324/* ------------------------------------------------------------ */
325
326static int grgpio_probe(struct platform_device *ofdev)
327{
328 struct device_node *np = ofdev->dev.of_node;
329 void __iomem *regs;
330 struct gpio_chip *gc;
331 struct grgpio_priv *priv;
332 int err;
333 u32 prop;
334 s32 *irqmap;
335 int size;
336 int i;
337
338 priv = devm_kzalloc(&ofdev->dev, sizeof(*priv), GFP_KERNEL);
339 if (!priv)
340 return -ENOMEM;
341
342 regs = devm_platform_ioremap_resource(ofdev, 0);
343 if (IS_ERR(regs))
344 return PTR_ERR(regs);
345
346 gc = &priv->gc;
347 err = bgpio_init(gc, &ofdev->dev, 4, regs + GRGPIO_DATA,
348 regs + GRGPIO_OUTPUT, NULL, regs + GRGPIO_DIR, NULL,
349 BGPIOF_BIG_ENDIAN_BYTE_ORDER);
350 if (err) {
351 dev_err(&ofdev->dev, "bgpio_init() failed\n");
352 return err;
353 }
354
355 priv->regs = regs;
356 priv->imask = gc->read_reg(regs + GRGPIO_IMASK);
357 priv->dev = &ofdev->dev;
358
359 gc->of_node = np;
360 gc->owner = THIS_MODULE;
361 gc->to_irq = grgpio_to_irq;
362 gc->label = devm_kasprintf(&ofdev->dev, GFP_KERNEL, "%pOF", np);
363 gc->base = -1;
364
365 err = of_property_read_u32(np, "nbits", &prop);
366 if (err || prop <= 0 || prop > GRGPIO_MAX_NGPIO) {
367 gc->ngpio = GRGPIO_MAX_NGPIO;
368 dev_dbg(&ofdev->dev,
369 "No or invalid nbits property: assume %d\n", gc->ngpio);
370 } else {
371 gc->ngpio = prop;
372 }
373
374 /*
375 * The irqmap contains the index values indicating which underlying irq,
376 * if anyone, is connected to that line
377 */
378 irqmap = (s32 *)of_get_property(np, "irqmap", &size);
379 if (irqmap) {
380 if (size < gc->ngpio) {
381 dev_err(&ofdev->dev,
382 "irqmap shorter than ngpio (%d < %d)\n",
383 size, gc->ngpio);
384 return -EINVAL;
385 }
386
387 priv->domain = irq_domain_add_linear(np, gc->ngpio,
388 &grgpio_irq_domain_ops,
389 priv);
390 if (!priv->domain) {
391 dev_err(&ofdev->dev, "Could not add irq domain\n");
392 return -EINVAL;
393 }
394
395 for (i = 0; i < gc->ngpio; i++) {
396 struct grgpio_lirq *lirq;
397 int ret;
398
399 lirq = &priv->lirqs[i];
400 lirq->index = irqmap[i];
401
402 if (lirq->index < 0)
403 continue;
404
405 ret = platform_get_irq(ofdev, lirq->index);
406 if (ret <= 0) {
407 /*
408 * Continue without irq functionality for that
409 * gpio line
410 */
411 continue;
412 }
413 priv->uirqs[lirq->index].uirq = ret;
414 }
415 }
416
417 platform_set_drvdata(ofdev, priv);
418
419 err = gpiochip_add_data(gc, priv);
420 if (err) {
421 dev_err(&ofdev->dev, "Could not add gpiochip\n");
422 if (priv->domain)
423 irq_domain_remove(priv->domain);
424 return err;
425 }
426
427 dev_info(&ofdev->dev, "regs=0x%p, base=%d, ngpio=%d, irqs=%s\n",
428 priv->regs, gc->base, gc->ngpio, priv->domain ? "on" : "off");
429
430 return 0;
431}
432
433static int grgpio_remove(struct platform_device *ofdev)
434{
435 struct grgpio_priv *priv = platform_get_drvdata(ofdev);
436 unsigned long flags;
437 int i;
438 int ret = 0;
439
440 spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
441
442 if (priv->domain) {
443 for (i = 0; i < GRGPIO_MAX_NGPIO; i++) {
444 if (priv->uirqs[i].refcnt != 0) {
445 ret = -EBUSY;
446 goto out;
447 }
448 }
449 }
450
451 gpiochip_remove(&priv->gc);
452
453 if (priv->domain)
454 irq_domain_remove(priv->domain);
455
456out:
457 spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
458
459 return ret;
460}
461
462static const struct of_device_id grgpio_match[] = {
463 {.name = "GAISLER_GPIO"},
464 {.name = "01_01a"},
465 {},
466};
467
468MODULE_DEVICE_TABLE(of, grgpio_match);
469
470static struct platform_driver grgpio_driver = {
471 .driver = {
472 .name = "grgpio",
473 .of_match_table = grgpio_match,
474 },
475 .probe = grgpio_probe,
476 .remove = grgpio_remove,
477};
478module_platform_driver(grgpio_driver);
479
480MODULE_AUTHOR("Aeroflex Gaisler AB.");
481MODULE_DESCRIPTION("Driver for Aeroflex Gaisler GRGPIO");
482MODULE_LICENSE("GPL");