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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright IBM Corp. 2004, 2011
4 * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>,
5 * Holger Smolinski <Holger.Smolinski@de.ibm.com>,
6 * Thomas Spatzier <tspat@de.ibm.com>,
7 *
8 * This file contains interrupt related functions.
9 */
10
11#include <linux/kernel_stat.h>
12#include <linux/interrupt.h>
13#include <linux/seq_file.h>
14#include <linux/proc_fs.h>
15#include <linux/profile.h>
16#include <linux/export.h>
17#include <linux/kernel.h>
18#include <linux/ftrace.h>
19#include <linux/errno.h>
20#include <linux/slab.h>
21#include <linux/init.h>
22#include <linux/cpu.h>
23#include <linux/irq.h>
24#include <linux/entry-common.h>
25#include <asm/irq_regs.h>
26#include <asm/cputime.h>
27#include <asm/lowcore.h>
28#include <asm/irq.h>
29#include <asm/hw_irq.h>
30#include <asm/stacktrace.h>
31#include <asm/softirq_stack.h>
32#include <asm/vtime.h>
33#include <asm/asm.h>
34#include "entry.h"
35
36DEFINE_PER_CPU_SHARED_ALIGNED(struct irq_stat, irq_stat);
37EXPORT_PER_CPU_SYMBOL_GPL(irq_stat);
38
39struct irq_class {
40 int irq;
41 char *name;
42 char *desc;
43};
44
45/*
46 * The list of "main" irq classes on s390. This is the list of interrupts
47 * that appear both in /proc/stat ("intr" line) and /proc/interrupts.
48 * Historically only external and I/O interrupts have been part of /proc/stat.
49 * We can't add the split external and I/O sub classes since the first field
50 * in the "intr" line in /proc/stat is supposed to be the sum of all other
51 * fields.
52 * Since the external and I/O interrupt fields are already sums we would end
53 * up with having a sum which accounts each interrupt twice.
54 */
55static const struct irq_class irqclass_main_desc[NR_IRQS_BASE] = {
56 {.irq = EXT_INTERRUPT, .name = "EXT"},
57 {.irq = IO_INTERRUPT, .name = "I/O"},
58 {.irq = THIN_INTERRUPT, .name = "AIO"},
59};
60
61/*
62 * The list of split external and I/O interrupts that appear only in
63 * /proc/interrupts.
64 * In addition this list contains non external / I/O events like NMIs.
65 */
66static const struct irq_class irqclass_sub_desc[] = {
67 {.irq = IRQEXT_CLK, .name = "CLK", .desc = "[EXT] Clock Comparator"},
68 {.irq = IRQEXT_EXC, .name = "EXC", .desc = "[EXT] External Call"},
69 {.irq = IRQEXT_EMS, .name = "EMS", .desc = "[EXT] Emergency Signal"},
70 {.irq = IRQEXT_TMR, .name = "TMR", .desc = "[EXT] CPU Timer"},
71 {.irq = IRQEXT_TLA, .name = "TAL", .desc = "[EXT] Timing Alert"},
72 {.irq = IRQEXT_PFL, .name = "PFL", .desc = "[EXT] Pseudo Page Fault"},
73 {.irq = IRQEXT_DSD, .name = "DSD", .desc = "[EXT] DASD Diag"},
74 {.irq = IRQEXT_VRT, .name = "VRT", .desc = "[EXT] Virtio"},
75 {.irq = IRQEXT_SCP, .name = "SCP", .desc = "[EXT] Service Call"},
76 {.irq = IRQEXT_IUC, .name = "IUC", .desc = "[EXT] IUCV"},
77 {.irq = IRQEXT_CMS, .name = "CMS", .desc = "[EXT] CPU-Measurement: Sampling"},
78 {.irq = IRQEXT_CMC, .name = "CMC", .desc = "[EXT] CPU-Measurement: Counter"},
79 {.irq = IRQEXT_FTP, .name = "FTP", .desc = "[EXT] HMC FTP Service"},
80 {.irq = IRQEXT_WTI, .name = "WTI", .desc = "[EXT] Warning Track"},
81 {.irq = IRQIO_CIO, .name = "CIO", .desc = "[I/O] Common I/O Layer Interrupt"},
82 {.irq = IRQIO_DAS, .name = "DAS", .desc = "[I/O] DASD"},
83 {.irq = IRQIO_C15, .name = "C15", .desc = "[I/O] 3215"},
84 {.irq = IRQIO_C70, .name = "C70", .desc = "[I/O] 3270"},
85 {.irq = IRQIO_TAP, .name = "TAP", .desc = "[I/O] Tape"},
86 {.irq = IRQIO_VMR, .name = "VMR", .desc = "[I/O] Unit Record Devices"},
87 {.irq = IRQIO_LCS, .name = "LCS", .desc = "[I/O] LCS"},
88 {.irq = IRQIO_CTC, .name = "CTC", .desc = "[I/O] CTC"},
89 {.irq = IRQIO_ADM, .name = "ADM", .desc = "[I/O] EADM Subchannel"},
90 {.irq = IRQIO_CSC, .name = "CSC", .desc = "[I/O] CHSC Subchannel"},
91 {.irq = IRQIO_VIR, .name = "VIR", .desc = "[I/O] Virtual I/O Devices"},
92 {.irq = IRQIO_QAI, .name = "QAI", .desc = "[AIO] QDIO Adapter Interrupt"},
93 {.irq = IRQIO_APB, .name = "APB", .desc = "[AIO] AP Bus"},
94 {.irq = IRQIO_PCF, .name = "PCF", .desc = "[AIO] PCI Floating Interrupt"},
95 {.irq = IRQIO_PCD, .name = "PCD", .desc = "[AIO] PCI Directed Interrupt"},
96 {.irq = IRQIO_MSI, .name = "MSI", .desc = "[AIO] MSI Interrupt"},
97 {.irq = IRQIO_VAI, .name = "VAI", .desc = "[AIO] Virtual I/O Devices AI"},
98 {.irq = IRQIO_GAL, .name = "GAL", .desc = "[AIO] GIB Alert"},
99 {.irq = NMI_NMI, .name = "NMI", .desc = "[NMI] Machine Check"},
100 {.irq = CPU_RST, .name = "RST", .desc = "[CPU] CPU Restart"},
101};
102
103static void do_IRQ(struct pt_regs *regs, int irq)
104{
105 if (tod_after_eq(get_lowcore()->int_clock,
106 get_lowcore()->clock_comparator))
107 /* Serve timer interrupts first. */
108 clock_comparator_work();
109 generic_handle_irq(irq);
110}
111
112static int on_async_stack(void)
113{
114 unsigned long frame = current_frame_address();
115
116 return ((get_lowcore()->async_stack ^ frame) & ~(THREAD_SIZE - 1)) == 0;
117}
118
119static void do_irq_async(struct pt_regs *regs, int irq)
120{
121 if (on_async_stack()) {
122 do_IRQ(regs, irq);
123 } else {
124 call_on_stack(2, get_lowcore()->async_stack, void, do_IRQ,
125 struct pt_regs *, regs, int, irq);
126 }
127}
128
129static int irq_pending(struct pt_regs *regs)
130{
131 int cc;
132
133 asm volatile(
134 " tpi 0\n"
135 CC_IPM(cc)
136 : CC_OUT(cc, cc)
137 :
138 : CC_CLOBBER);
139 return CC_TRANSFORM(cc);
140}
141
142void noinstr do_io_irq(struct pt_regs *regs)
143{
144 irqentry_state_t state = irqentry_enter(regs);
145 struct pt_regs *old_regs = set_irq_regs(regs);
146 bool from_idle;
147
148 irq_enter_rcu();
149
150 if (user_mode(regs)) {
151 update_timer_sys();
152 if (static_branch_likely(&cpu_has_bear))
153 current->thread.last_break = regs->last_break;
154 }
155
156 from_idle = test_and_clear_cpu_flag(CIF_ENABLED_WAIT);
157 if (from_idle)
158 account_idle_time_irq();
159
160 set_cpu_flag(CIF_NOHZ_DELAY);
161 do {
162 regs->tpi_info = get_lowcore()->tpi_info;
163 if (get_lowcore()->tpi_info.adapter_IO)
164 do_irq_async(regs, THIN_INTERRUPT);
165 else
166 do_irq_async(regs, IO_INTERRUPT);
167 } while (MACHINE_IS_LPAR && irq_pending(regs));
168
169 irq_exit_rcu();
170
171 set_irq_regs(old_regs);
172 irqentry_exit(regs, state);
173
174 if (from_idle)
175 regs->psw.mask &= ~(PSW_MASK_EXT | PSW_MASK_IO | PSW_MASK_WAIT);
176}
177
178void noinstr do_ext_irq(struct pt_regs *regs)
179{
180 irqentry_state_t state = irqentry_enter(regs);
181 struct pt_regs *old_regs = set_irq_regs(regs);
182 bool from_idle;
183
184 irq_enter_rcu();
185
186 if (user_mode(regs)) {
187 update_timer_sys();
188 if (static_branch_likely(&cpu_has_bear))
189 current->thread.last_break = regs->last_break;
190 }
191
192 regs->int_code = get_lowcore()->ext_int_code_addr;
193 regs->int_parm = get_lowcore()->ext_params;
194 regs->int_parm_long = get_lowcore()->ext_params2;
195
196 from_idle = test_and_clear_cpu_flag(CIF_ENABLED_WAIT);
197 if (from_idle)
198 account_idle_time_irq();
199
200 do_irq_async(regs, EXT_INTERRUPT);
201
202 irq_exit_rcu();
203 set_irq_regs(old_regs);
204 irqentry_exit(regs, state);
205
206 if (from_idle)
207 regs->psw.mask &= ~(PSW_MASK_EXT | PSW_MASK_IO | PSW_MASK_WAIT);
208}
209
210static void show_msi_interrupt(struct seq_file *p, int irq)
211{
212 struct irq_desc *desc;
213 unsigned long flags;
214 int cpu;
215
216 rcu_read_lock();
217 desc = irq_to_desc(irq);
218 if (!desc)
219 goto out;
220
221 raw_spin_lock_irqsave(&desc->lock, flags);
222 seq_printf(p, "%3d: ", irq);
223 for_each_online_cpu(cpu)
224 seq_printf(p, "%10u ", irq_desc_kstat_cpu(desc, cpu));
225
226 if (desc->irq_data.chip)
227 seq_printf(p, " %8s", desc->irq_data.chip->name);
228
229 if (desc->action)
230 seq_printf(p, " %s", desc->action->name);
231
232 seq_putc(p, '\n');
233 raw_spin_unlock_irqrestore(&desc->lock, flags);
234out:
235 rcu_read_unlock();
236}
237
238/*
239 * show_interrupts is needed by /proc/interrupts.
240 */
241int show_interrupts(struct seq_file *p, void *v)
242{
243 int index = *(loff_t *) v;
244 int cpu, irq;
245
246 cpus_read_lock();
247 if (index == 0) {
248 seq_puts(p, " ");
249 for_each_online_cpu(cpu)
250 seq_printf(p, "CPU%-8d", cpu);
251 seq_putc(p, '\n');
252 }
253 if (index < NR_IRQS_BASE) {
254 seq_printf(p, "%s: ", irqclass_main_desc[index].name);
255 irq = irqclass_main_desc[index].irq;
256 for_each_online_cpu(cpu)
257 seq_printf(p, "%10u ", kstat_irqs_cpu(irq, cpu));
258 seq_putc(p, '\n');
259 goto out;
260 }
261 if (index < irq_get_nr_irqs()) {
262 show_msi_interrupt(p, index);
263 goto out;
264 }
265 for (index = 0; index < NR_ARCH_IRQS; index++) {
266 seq_printf(p, "%s: ", irqclass_sub_desc[index].name);
267 irq = irqclass_sub_desc[index].irq;
268 for_each_online_cpu(cpu)
269 seq_printf(p, "%10u ",
270 per_cpu(irq_stat, cpu).irqs[irq]);
271 if (irqclass_sub_desc[index].desc)
272 seq_printf(p, " %s", irqclass_sub_desc[index].desc);
273 seq_putc(p, '\n');
274 }
275out:
276 cpus_read_unlock();
277 return 0;
278}
279
280unsigned int arch_dynirq_lower_bound(unsigned int from)
281{
282 return from < NR_IRQS_BASE ? NR_IRQS_BASE : from;
283}
284
285/*
286 * ext_int_hash[index] is the list head for all external interrupts that hash
287 * to this index.
288 */
289static struct hlist_head ext_int_hash[32] ____cacheline_aligned;
290
291struct ext_int_info {
292 ext_int_handler_t handler;
293 struct hlist_node entry;
294 struct rcu_head rcu;
295 u16 code;
296};
297
298/* ext_int_hash_lock protects the handler lists for external interrupts */
299static DEFINE_SPINLOCK(ext_int_hash_lock);
300
301static inline int ext_hash(u16 code)
302{
303 BUILD_BUG_ON(!is_power_of_2(ARRAY_SIZE(ext_int_hash)));
304
305 return (code + (code >> 9)) & (ARRAY_SIZE(ext_int_hash) - 1);
306}
307
308int register_external_irq(u16 code, ext_int_handler_t handler)
309{
310 struct ext_int_info *p;
311 unsigned long flags;
312 int index;
313
314 p = kmalloc(sizeof(*p), GFP_ATOMIC);
315 if (!p)
316 return -ENOMEM;
317 p->code = code;
318 p->handler = handler;
319 index = ext_hash(code);
320
321 spin_lock_irqsave(&ext_int_hash_lock, flags);
322 hlist_add_head_rcu(&p->entry, &ext_int_hash[index]);
323 spin_unlock_irqrestore(&ext_int_hash_lock, flags);
324 return 0;
325}
326EXPORT_SYMBOL(register_external_irq);
327
328int unregister_external_irq(u16 code, ext_int_handler_t handler)
329{
330 struct ext_int_info *p;
331 unsigned long flags;
332 int index = ext_hash(code);
333
334 spin_lock_irqsave(&ext_int_hash_lock, flags);
335 hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) {
336 if (p->code == code && p->handler == handler) {
337 hlist_del_rcu(&p->entry);
338 kfree_rcu(p, rcu);
339 }
340 }
341 spin_unlock_irqrestore(&ext_int_hash_lock, flags);
342 return 0;
343}
344EXPORT_SYMBOL(unregister_external_irq);
345
346static irqreturn_t do_ext_interrupt(int irq, void *dummy)
347{
348 struct pt_regs *regs = get_irq_regs();
349 struct ext_code ext_code;
350 struct ext_int_info *p;
351 int index;
352
353 ext_code.int_code = regs->int_code;
354 if (ext_code.code != EXT_IRQ_CLK_COMP)
355 set_cpu_flag(CIF_NOHZ_DELAY);
356
357 index = ext_hash(ext_code.code);
358 rcu_read_lock();
359 hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) {
360 if (unlikely(p->code != ext_code.code))
361 continue;
362 p->handler(ext_code, regs->int_parm, regs->int_parm_long);
363 }
364 rcu_read_unlock();
365 return IRQ_HANDLED;
366}
367
368static void __init init_ext_interrupts(void)
369{
370 int idx;
371
372 for (idx = 0; idx < ARRAY_SIZE(ext_int_hash); idx++)
373 INIT_HLIST_HEAD(&ext_int_hash[idx]);
374
375 irq_set_chip_and_handler(EXT_INTERRUPT,
376 &dummy_irq_chip, handle_percpu_irq);
377 if (request_irq(EXT_INTERRUPT, do_ext_interrupt, 0, "EXT", NULL))
378 panic("Failed to register EXT interrupt\n");
379}
380
381void __init init_IRQ(void)
382{
383 BUILD_BUG_ON(ARRAY_SIZE(irqclass_sub_desc) != NR_ARCH_IRQS);
384 init_cio_interrupts();
385 init_airq_interrupts();
386 init_ext_interrupts();
387}
388
389static DEFINE_SPINLOCK(irq_subclass_lock);
390static unsigned char irq_subclass_refcount[64];
391
392void irq_subclass_register(enum irq_subclass subclass)
393{
394 spin_lock(&irq_subclass_lock);
395 if (!irq_subclass_refcount[subclass])
396 system_ctl_set_bit(0, subclass);
397 irq_subclass_refcount[subclass]++;
398 spin_unlock(&irq_subclass_lock);
399}
400EXPORT_SYMBOL(irq_subclass_register);
401
402void irq_subclass_unregister(enum irq_subclass subclass)
403{
404 spin_lock(&irq_subclass_lock);
405 irq_subclass_refcount[subclass]--;
406 if (!irq_subclass_refcount[subclass])
407 system_ctl_clear_bit(0, subclass);
408 spin_unlock(&irq_subclass_lock);
409}
410EXPORT_SYMBOL(irq_subclass_unregister);
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright IBM Corp. 2004, 2011
4 * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>,
5 * Holger Smolinski <Holger.Smolinski@de.ibm.com>,
6 * Thomas Spatzier <tspat@de.ibm.com>,
7 *
8 * This file contains interrupt related functions.
9 */
10
11#include <linux/kernel_stat.h>
12#include <linux/interrupt.h>
13#include <linux/seq_file.h>
14#include <linux/proc_fs.h>
15#include <linux/profile.h>
16#include <linux/export.h>
17#include <linux/kernel.h>
18#include <linux/ftrace.h>
19#include <linux/errno.h>
20#include <linux/slab.h>
21#include <linux/init.h>
22#include <linux/cpu.h>
23#include <linux/irq.h>
24#include <asm/irq_regs.h>
25#include <asm/cputime.h>
26#include <asm/lowcore.h>
27#include <asm/irq.h>
28#include <asm/hw_irq.h>
29#include <asm/stacktrace.h>
30#include "entry.h"
31
32DEFINE_PER_CPU_SHARED_ALIGNED(struct irq_stat, irq_stat);
33EXPORT_PER_CPU_SYMBOL_GPL(irq_stat);
34
35struct irq_class {
36 int irq;
37 char *name;
38 char *desc;
39};
40
41/*
42 * The list of "main" irq classes on s390. This is the list of interrupts
43 * that appear both in /proc/stat ("intr" line) and /proc/interrupts.
44 * Historically only external and I/O interrupts have been part of /proc/stat.
45 * We can't add the split external and I/O sub classes since the first field
46 * in the "intr" line in /proc/stat is supposed to be the sum of all other
47 * fields.
48 * Since the external and I/O interrupt fields are already sums we would end
49 * up with having a sum which accounts each interrupt twice.
50 */
51static const struct irq_class irqclass_main_desc[NR_IRQS_BASE] = {
52 {.irq = EXT_INTERRUPT, .name = "EXT"},
53 {.irq = IO_INTERRUPT, .name = "I/O"},
54 {.irq = THIN_INTERRUPT, .name = "AIO"},
55};
56
57/*
58 * The list of split external and I/O interrupts that appear only in
59 * /proc/interrupts.
60 * In addition this list contains non external / I/O events like NMIs.
61 */
62static const struct irq_class irqclass_sub_desc[] = {
63 {.irq = IRQEXT_CLK, .name = "CLK", .desc = "[EXT] Clock Comparator"},
64 {.irq = IRQEXT_EXC, .name = "EXC", .desc = "[EXT] External Call"},
65 {.irq = IRQEXT_EMS, .name = "EMS", .desc = "[EXT] Emergency Signal"},
66 {.irq = IRQEXT_TMR, .name = "TMR", .desc = "[EXT] CPU Timer"},
67 {.irq = IRQEXT_TLA, .name = "TAL", .desc = "[EXT] Timing Alert"},
68 {.irq = IRQEXT_PFL, .name = "PFL", .desc = "[EXT] Pseudo Page Fault"},
69 {.irq = IRQEXT_DSD, .name = "DSD", .desc = "[EXT] DASD Diag"},
70 {.irq = IRQEXT_VRT, .name = "VRT", .desc = "[EXT] Virtio"},
71 {.irq = IRQEXT_SCP, .name = "SCP", .desc = "[EXT] Service Call"},
72 {.irq = IRQEXT_IUC, .name = "IUC", .desc = "[EXT] IUCV"},
73 {.irq = IRQEXT_CMS, .name = "CMS", .desc = "[EXT] CPU-Measurement: Sampling"},
74 {.irq = IRQEXT_CMC, .name = "CMC", .desc = "[EXT] CPU-Measurement: Counter"},
75 {.irq = IRQEXT_FTP, .name = "FTP", .desc = "[EXT] HMC FTP Service"},
76 {.irq = IRQIO_CIO, .name = "CIO", .desc = "[I/O] Common I/O Layer Interrupt"},
77 {.irq = IRQIO_DAS, .name = "DAS", .desc = "[I/O] DASD"},
78 {.irq = IRQIO_C15, .name = "C15", .desc = "[I/O] 3215"},
79 {.irq = IRQIO_C70, .name = "C70", .desc = "[I/O] 3270"},
80 {.irq = IRQIO_TAP, .name = "TAP", .desc = "[I/O] Tape"},
81 {.irq = IRQIO_VMR, .name = "VMR", .desc = "[I/O] Unit Record Devices"},
82 {.irq = IRQIO_LCS, .name = "LCS", .desc = "[I/O] LCS"},
83 {.irq = IRQIO_CTC, .name = "CTC", .desc = "[I/O] CTC"},
84 {.irq = IRQIO_ADM, .name = "ADM", .desc = "[I/O] EADM Subchannel"},
85 {.irq = IRQIO_CSC, .name = "CSC", .desc = "[I/O] CHSC Subchannel"},
86 {.irq = IRQIO_VIR, .name = "VIR", .desc = "[I/O] Virtual I/O Devices"},
87 {.irq = IRQIO_QAI, .name = "QAI", .desc = "[AIO] QDIO Adapter Interrupt"},
88 {.irq = IRQIO_APB, .name = "APB", .desc = "[AIO] AP Bus"},
89 {.irq = IRQIO_PCF, .name = "PCF", .desc = "[AIO] PCI Floating Interrupt"},
90 {.irq = IRQIO_PCD, .name = "PCD", .desc = "[AIO] PCI Directed Interrupt"},
91 {.irq = IRQIO_MSI, .name = "MSI", .desc = "[AIO] MSI Interrupt"},
92 {.irq = IRQIO_VAI, .name = "VAI", .desc = "[AIO] Virtual I/O Devices AI"},
93 {.irq = IRQIO_GAL, .name = "GAL", .desc = "[AIO] GIB Alert"},
94 {.irq = NMI_NMI, .name = "NMI", .desc = "[NMI] Machine Check"},
95 {.irq = CPU_RST, .name = "RST", .desc = "[CPU] CPU Restart"},
96};
97
98void __init init_IRQ(void)
99{
100 BUILD_BUG_ON(ARRAY_SIZE(irqclass_sub_desc) != NR_ARCH_IRQS);
101 init_cio_interrupts();
102 init_airq_interrupts();
103 init_ext_interrupts();
104}
105
106void do_IRQ(struct pt_regs *regs, int irq)
107{
108 struct pt_regs *old_regs;
109
110 old_regs = set_irq_regs(regs);
111 irq_enter();
112 if (tod_after_eq(S390_lowcore.int_clock,
113 S390_lowcore.clock_comparator))
114 /* Serve timer interrupts first. */
115 clock_comparator_work();
116 generic_handle_irq(irq);
117 irq_exit();
118 set_irq_regs(old_regs);
119}
120
121static void show_msi_interrupt(struct seq_file *p, int irq)
122{
123 struct irq_desc *desc;
124 unsigned long flags;
125 int cpu;
126
127 irq_lock_sparse();
128 desc = irq_to_desc(irq);
129 if (!desc)
130 goto out;
131
132 raw_spin_lock_irqsave(&desc->lock, flags);
133 seq_printf(p, "%3d: ", irq);
134 for_each_online_cpu(cpu)
135 seq_printf(p, "%10u ", kstat_irqs_cpu(irq, cpu));
136
137 if (desc->irq_data.chip)
138 seq_printf(p, " %8s", desc->irq_data.chip->name);
139
140 if (desc->action)
141 seq_printf(p, " %s", desc->action->name);
142
143 seq_putc(p, '\n');
144 raw_spin_unlock_irqrestore(&desc->lock, flags);
145out:
146 irq_unlock_sparse();
147}
148
149/*
150 * show_interrupts is needed by /proc/interrupts.
151 */
152int show_interrupts(struct seq_file *p, void *v)
153{
154 int index = *(loff_t *) v;
155 int cpu, irq;
156
157 get_online_cpus();
158 if (index == 0) {
159 seq_puts(p, " ");
160 for_each_online_cpu(cpu)
161 seq_printf(p, "CPU%-8d", cpu);
162 seq_putc(p, '\n');
163 }
164 if (index < NR_IRQS_BASE) {
165 seq_printf(p, "%s: ", irqclass_main_desc[index].name);
166 irq = irqclass_main_desc[index].irq;
167 for_each_online_cpu(cpu)
168 seq_printf(p, "%10u ", kstat_irqs_cpu(irq, cpu));
169 seq_putc(p, '\n');
170 goto out;
171 }
172 if (index < nr_irqs) {
173 show_msi_interrupt(p, index);
174 goto out;
175 }
176 for (index = 0; index < NR_ARCH_IRQS; index++) {
177 seq_printf(p, "%s: ", irqclass_sub_desc[index].name);
178 irq = irqclass_sub_desc[index].irq;
179 for_each_online_cpu(cpu)
180 seq_printf(p, "%10u ",
181 per_cpu(irq_stat, cpu).irqs[irq]);
182 if (irqclass_sub_desc[index].desc)
183 seq_printf(p, " %s", irqclass_sub_desc[index].desc);
184 seq_putc(p, '\n');
185 }
186out:
187 put_online_cpus();
188 return 0;
189}
190
191unsigned int arch_dynirq_lower_bound(unsigned int from)
192{
193 return from < NR_IRQS_BASE ? NR_IRQS_BASE : from;
194}
195
196/*
197 * Switch to the asynchronous interrupt stack for softirq execution.
198 */
199void do_softirq_own_stack(void)
200{
201 unsigned long old, new;
202
203 old = current_stack_pointer();
204 /* Check against async. stack address range. */
205 new = S390_lowcore.async_stack;
206 if (((new - old) >> (PAGE_SHIFT + THREAD_SIZE_ORDER)) != 0) {
207 CALL_ON_STACK(__do_softirq, new, 0);
208 } else {
209 /* We are already on the async stack. */
210 __do_softirq();
211 }
212}
213
214/*
215 * ext_int_hash[index] is the list head for all external interrupts that hash
216 * to this index.
217 */
218static struct hlist_head ext_int_hash[32] ____cacheline_aligned;
219
220struct ext_int_info {
221 ext_int_handler_t handler;
222 struct hlist_node entry;
223 struct rcu_head rcu;
224 u16 code;
225};
226
227/* ext_int_hash_lock protects the handler lists for external interrupts */
228static DEFINE_SPINLOCK(ext_int_hash_lock);
229
230static inline int ext_hash(u16 code)
231{
232 BUILD_BUG_ON(!is_power_of_2(ARRAY_SIZE(ext_int_hash)));
233
234 return (code + (code >> 9)) & (ARRAY_SIZE(ext_int_hash) - 1);
235}
236
237int register_external_irq(u16 code, ext_int_handler_t handler)
238{
239 struct ext_int_info *p;
240 unsigned long flags;
241 int index;
242
243 p = kmalloc(sizeof(*p), GFP_ATOMIC);
244 if (!p)
245 return -ENOMEM;
246 p->code = code;
247 p->handler = handler;
248 index = ext_hash(code);
249
250 spin_lock_irqsave(&ext_int_hash_lock, flags);
251 hlist_add_head_rcu(&p->entry, &ext_int_hash[index]);
252 spin_unlock_irqrestore(&ext_int_hash_lock, flags);
253 return 0;
254}
255EXPORT_SYMBOL(register_external_irq);
256
257int unregister_external_irq(u16 code, ext_int_handler_t handler)
258{
259 struct ext_int_info *p;
260 unsigned long flags;
261 int index = ext_hash(code);
262
263 spin_lock_irqsave(&ext_int_hash_lock, flags);
264 hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) {
265 if (p->code == code && p->handler == handler) {
266 hlist_del_rcu(&p->entry);
267 kfree_rcu(p, rcu);
268 }
269 }
270 spin_unlock_irqrestore(&ext_int_hash_lock, flags);
271 return 0;
272}
273EXPORT_SYMBOL(unregister_external_irq);
274
275static irqreturn_t do_ext_interrupt(int irq, void *dummy)
276{
277 struct pt_regs *regs = get_irq_regs();
278 struct ext_code ext_code;
279 struct ext_int_info *p;
280 int index;
281
282 ext_code = *(struct ext_code *) ®s->int_code;
283 if (ext_code.code != EXT_IRQ_CLK_COMP)
284 set_cpu_flag(CIF_NOHZ_DELAY);
285
286 index = ext_hash(ext_code.code);
287 rcu_read_lock();
288 hlist_for_each_entry_rcu(p, &ext_int_hash[index], entry) {
289 if (unlikely(p->code != ext_code.code))
290 continue;
291 p->handler(ext_code, regs->int_parm, regs->int_parm_long);
292 }
293 rcu_read_unlock();
294 return IRQ_HANDLED;
295}
296
297static struct irqaction external_interrupt = {
298 .name = "EXT",
299 .handler = do_ext_interrupt,
300};
301
302void __init init_ext_interrupts(void)
303{
304 int idx;
305
306 for (idx = 0; idx < ARRAY_SIZE(ext_int_hash); idx++)
307 INIT_HLIST_HEAD(&ext_int_hash[idx]);
308
309 irq_set_chip_and_handler(EXT_INTERRUPT,
310 &dummy_irq_chip, handle_percpu_irq);
311 setup_irq(EXT_INTERRUPT, &external_interrupt);
312}
313
314static DEFINE_SPINLOCK(irq_subclass_lock);
315static unsigned char irq_subclass_refcount[64];
316
317void irq_subclass_register(enum irq_subclass subclass)
318{
319 spin_lock(&irq_subclass_lock);
320 if (!irq_subclass_refcount[subclass])
321 ctl_set_bit(0, subclass);
322 irq_subclass_refcount[subclass]++;
323 spin_unlock(&irq_subclass_lock);
324}
325EXPORT_SYMBOL(irq_subclass_register);
326
327void irq_subclass_unregister(enum irq_subclass subclass)
328{
329 spin_lock(&irq_subclass_lock);
330 irq_subclass_refcount[subclass]--;
331 if (!irq_subclass_refcount[subclass])
332 ctl_clear_bit(0, subclass);
333 spin_unlock(&irq_subclass_lock);
334}
335EXPORT_SYMBOL(irq_subclass_unregister);