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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * In-kernel vector facility support functions
4 *
5 * Copyright IBM Corp. 2015
6 * Author(s): Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
7 */
8#include <linux/kernel.h>
9#include <linux/cpu.h>
10#include <linux/sched.h>
11#include <asm/fpu.h>
12
13void __kernel_fpu_begin(struct kernel_fpu *state, int flags)
14{
15 __vector128 *vxrs = state->vxrs;
16 int mask;
17
18 /*
19 * Limit the save to the FPU/vector registers already
20 * in use by the previous context.
21 */
22 flags &= state->hdr.mask;
23 if (flags & KERNEL_FPC)
24 fpu_stfpc(&state->hdr.fpc);
25 if (!cpu_has_vx()) {
26 if (flags & KERNEL_VXR_LOW)
27 save_fp_regs_vx(vxrs);
28 return;
29 }
30 mask = flags & KERNEL_VXR;
31 if (mask == KERNEL_VXR) {
32 vxrs += fpu_vstm(0, 15, vxrs);
33 vxrs += fpu_vstm(16, 31, vxrs);
34 return;
35 }
36 if (mask == KERNEL_VXR_MID) {
37 vxrs += fpu_vstm(8, 23, vxrs);
38 return;
39 }
40 mask = flags & KERNEL_VXR_LOW;
41 if (mask) {
42 if (mask == KERNEL_VXR_LOW)
43 vxrs += fpu_vstm(0, 15, vxrs);
44 else if (mask == KERNEL_VXR_V0V7)
45 vxrs += fpu_vstm(0, 7, vxrs);
46 else
47 vxrs += fpu_vstm(8, 15, vxrs);
48 }
49 mask = flags & KERNEL_VXR_HIGH;
50 if (mask) {
51 if (mask == KERNEL_VXR_HIGH)
52 vxrs += fpu_vstm(16, 31, vxrs);
53 else if (mask == KERNEL_VXR_V16V23)
54 vxrs += fpu_vstm(16, 23, vxrs);
55 else
56 vxrs += fpu_vstm(24, 31, vxrs);
57 }
58}
59EXPORT_SYMBOL(__kernel_fpu_begin);
60
61void __kernel_fpu_end(struct kernel_fpu *state, int flags)
62{
63 __vector128 *vxrs = state->vxrs;
64 int mask;
65
66 /*
67 * Limit the restore to the FPU/vector registers of the
68 * previous context that have been overwritten by the
69 * current context.
70 */
71 flags &= state->hdr.mask;
72 if (flags & KERNEL_FPC)
73 fpu_lfpc(&state->hdr.fpc);
74 if (!cpu_has_vx()) {
75 if (flags & KERNEL_VXR_LOW)
76 load_fp_regs_vx(vxrs);
77 return;
78 }
79 mask = flags & KERNEL_VXR;
80 if (mask == KERNEL_VXR) {
81 vxrs += fpu_vlm(0, 15, vxrs);
82 vxrs += fpu_vlm(16, 31, vxrs);
83 return;
84 }
85 if (mask == KERNEL_VXR_MID) {
86 vxrs += fpu_vlm(8, 23, vxrs);
87 return;
88 }
89 mask = flags & KERNEL_VXR_LOW;
90 if (mask) {
91 if (mask == KERNEL_VXR_LOW)
92 vxrs += fpu_vlm(0, 15, vxrs);
93 else if (mask == KERNEL_VXR_V0V7)
94 vxrs += fpu_vlm(0, 7, vxrs);
95 else
96 vxrs += fpu_vlm(8, 15, vxrs);
97 }
98 mask = flags & KERNEL_VXR_HIGH;
99 if (mask) {
100 if (mask == KERNEL_VXR_HIGH)
101 vxrs += fpu_vlm(16, 31, vxrs);
102 else if (mask == KERNEL_VXR_V16V23)
103 vxrs += fpu_vlm(16, 23, vxrs);
104 else
105 vxrs += fpu_vlm(24, 31, vxrs);
106 }
107}
108EXPORT_SYMBOL(__kernel_fpu_end);
109
110void load_fpu_state(struct fpu *state, int flags)
111{
112 __vector128 *vxrs = &state->vxrs[0];
113 int mask;
114
115 if (flags & KERNEL_FPC)
116 fpu_lfpc_safe(&state->fpc);
117 if (!cpu_has_vx()) {
118 if (flags & KERNEL_VXR_V0V7)
119 load_fp_regs_vx(state->vxrs);
120 return;
121 }
122 mask = flags & KERNEL_VXR;
123 if (mask == KERNEL_VXR) {
124 fpu_vlm(0, 15, &vxrs[0]);
125 fpu_vlm(16, 31, &vxrs[16]);
126 return;
127 }
128 if (mask == KERNEL_VXR_MID) {
129 fpu_vlm(8, 23, &vxrs[8]);
130 return;
131 }
132 mask = flags & KERNEL_VXR_LOW;
133 if (mask) {
134 if (mask == KERNEL_VXR_LOW)
135 fpu_vlm(0, 15, &vxrs[0]);
136 else if (mask == KERNEL_VXR_V0V7)
137 fpu_vlm(0, 7, &vxrs[0]);
138 else
139 fpu_vlm(8, 15, &vxrs[8]);
140 }
141 mask = flags & KERNEL_VXR_HIGH;
142 if (mask) {
143 if (mask == KERNEL_VXR_HIGH)
144 fpu_vlm(16, 31, &vxrs[16]);
145 else if (mask == KERNEL_VXR_V16V23)
146 fpu_vlm(16, 23, &vxrs[16]);
147 else
148 fpu_vlm(24, 31, &vxrs[24]);
149 }
150}
151
152void save_fpu_state(struct fpu *state, int flags)
153{
154 __vector128 *vxrs = &state->vxrs[0];
155 int mask;
156
157 if (flags & KERNEL_FPC)
158 fpu_stfpc(&state->fpc);
159 if (!cpu_has_vx()) {
160 if (flags & KERNEL_VXR_LOW)
161 save_fp_regs_vx(state->vxrs);
162 return;
163 }
164 mask = flags & KERNEL_VXR;
165 if (mask == KERNEL_VXR) {
166 fpu_vstm(0, 15, &vxrs[0]);
167 fpu_vstm(16, 31, &vxrs[16]);
168 return;
169 }
170 if (mask == KERNEL_VXR_MID) {
171 fpu_vstm(8, 23, &vxrs[8]);
172 return;
173 }
174 mask = flags & KERNEL_VXR_LOW;
175 if (mask) {
176 if (mask == KERNEL_VXR_LOW)
177 fpu_vstm(0, 15, &vxrs[0]);
178 else if (mask == KERNEL_VXR_V0V7)
179 fpu_vstm(0, 7, &vxrs[0]);
180 else
181 fpu_vstm(8, 15, &vxrs[8]);
182 }
183 mask = flags & KERNEL_VXR_HIGH;
184 if (mask) {
185 if (mask == KERNEL_VXR_HIGH)
186 fpu_vstm(16, 31, &vxrs[16]);
187 else if (mask == KERNEL_VXR_V16V23)
188 fpu_vstm(16, 23, &vxrs[16]);
189 else
190 fpu_vstm(24, 31, &vxrs[24]);
191 }
192}
193EXPORT_SYMBOL(save_fpu_state);
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * In-kernel vector facility support functions
4 *
5 * Copyright IBM Corp. 2015
6 * Author(s): Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
7 */
8#include <linux/kernel.h>
9#include <linux/cpu.h>
10#include <linux/sched.h>
11#include <asm/fpu/types.h>
12#include <asm/fpu/api.h>
13
14asm(".include \"asm/vx-insn.h\"\n");
15
16void __kernel_fpu_begin(struct kernel_fpu *state, u32 flags)
17{
18 /*
19 * Limit the save to the FPU/vector registers already
20 * in use by the previous context
21 */
22 flags &= state->mask;
23
24 if (flags & KERNEL_FPC)
25 /* Save floating point control */
26 asm volatile("stfpc %0" : "=Q" (state->fpc));
27
28 if (!MACHINE_HAS_VX) {
29 if (flags & KERNEL_VXR_V0V7) {
30 /* Save floating-point registers */
31 asm volatile("std 0,%0" : "=Q" (state->fprs[0]));
32 asm volatile("std 1,%0" : "=Q" (state->fprs[1]));
33 asm volatile("std 2,%0" : "=Q" (state->fprs[2]));
34 asm volatile("std 3,%0" : "=Q" (state->fprs[3]));
35 asm volatile("std 4,%0" : "=Q" (state->fprs[4]));
36 asm volatile("std 5,%0" : "=Q" (state->fprs[5]));
37 asm volatile("std 6,%0" : "=Q" (state->fprs[6]));
38 asm volatile("std 7,%0" : "=Q" (state->fprs[7]));
39 asm volatile("std 8,%0" : "=Q" (state->fprs[8]));
40 asm volatile("std 9,%0" : "=Q" (state->fprs[9]));
41 asm volatile("std 10,%0" : "=Q" (state->fprs[10]));
42 asm volatile("std 11,%0" : "=Q" (state->fprs[11]));
43 asm volatile("std 12,%0" : "=Q" (state->fprs[12]));
44 asm volatile("std 13,%0" : "=Q" (state->fprs[13]));
45 asm volatile("std 14,%0" : "=Q" (state->fprs[14]));
46 asm volatile("std 15,%0" : "=Q" (state->fprs[15]));
47 }
48 return;
49 }
50
51 /* Test and save vector registers */
52 asm volatile (
53 /*
54 * Test if any vector register must be saved and, if so,
55 * test if all register can be saved.
56 */
57 " la 1,%[vxrs]\n" /* load save area */
58 " tmll %[m],30\n" /* KERNEL_VXR */
59 " jz 7f\n" /* no work -> done */
60 " jo 5f\n" /* -> save V0..V31 */
61 /*
62 * Test for special case KERNEL_FPU_MID only. In this
63 * case a vstm V8..V23 is the best instruction
64 */
65 " chi %[m],12\n" /* KERNEL_VXR_MID */
66 " jne 0f\n" /* -> save V8..V23 */
67 " VSTM 8,23,128,1\n" /* vstm %v8,%v23,128(%r1) */
68 " j 7f\n"
69 /* Test and save the first half of 16 vector registers */
70 "0: tmll %[m],6\n" /* KERNEL_VXR_LOW */
71 " jz 3f\n" /* -> KERNEL_VXR_HIGH */
72 " jo 2f\n" /* 11 -> save V0..V15 */
73 " brc 2,1f\n" /* 10 -> save V8..V15 */
74 " VSTM 0,7,0,1\n" /* vstm %v0,%v7,0(%r1) */
75 " j 3f\n"
76 "1: VSTM 8,15,128,1\n" /* vstm %v8,%v15,128(%r1) */
77 " j 3f\n"
78 "2: VSTM 0,15,0,1\n" /* vstm %v0,%v15,0(%r1) */
79 /* Test and save the second half of 16 vector registers */
80 "3: tmll %[m],24\n" /* KERNEL_VXR_HIGH */
81 " jz 7f\n"
82 " jo 6f\n" /* 11 -> save V16..V31 */
83 " brc 2,4f\n" /* 10 -> save V24..V31 */
84 " VSTM 16,23,256,1\n" /* vstm %v16,%v23,256(%r1) */
85 " j 7f\n"
86 "4: VSTM 24,31,384,1\n" /* vstm %v24,%v31,384(%r1) */
87 " j 7f\n"
88 "5: VSTM 0,15,0,1\n" /* vstm %v0,%v15,0(%r1) */
89 "6: VSTM 16,31,256,1\n" /* vstm %v16,%v31,256(%r1) */
90 "7:"
91 : [vxrs] "=Q" (*(struct vx_array *) &state->vxrs)
92 : [m] "d" (flags)
93 : "1", "cc");
94}
95EXPORT_SYMBOL(__kernel_fpu_begin);
96
97void __kernel_fpu_end(struct kernel_fpu *state, u32 flags)
98{
99 /*
100 * Limit the restore to the FPU/vector registers of the
101 * previous context that have been overwritte by the
102 * current context
103 */
104 flags &= state->mask;
105
106 if (flags & KERNEL_FPC)
107 /* Restore floating-point controls */
108 asm volatile("lfpc %0" : : "Q" (state->fpc));
109
110 if (!MACHINE_HAS_VX) {
111 if (flags & KERNEL_VXR_V0V7) {
112 /* Restore floating-point registers */
113 asm volatile("ld 0,%0" : : "Q" (state->fprs[0]));
114 asm volatile("ld 1,%0" : : "Q" (state->fprs[1]));
115 asm volatile("ld 2,%0" : : "Q" (state->fprs[2]));
116 asm volatile("ld 3,%0" : : "Q" (state->fprs[3]));
117 asm volatile("ld 4,%0" : : "Q" (state->fprs[4]));
118 asm volatile("ld 5,%0" : : "Q" (state->fprs[5]));
119 asm volatile("ld 6,%0" : : "Q" (state->fprs[6]));
120 asm volatile("ld 7,%0" : : "Q" (state->fprs[7]));
121 asm volatile("ld 8,%0" : : "Q" (state->fprs[8]));
122 asm volatile("ld 9,%0" : : "Q" (state->fprs[9]));
123 asm volatile("ld 10,%0" : : "Q" (state->fprs[10]));
124 asm volatile("ld 11,%0" : : "Q" (state->fprs[11]));
125 asm volatile("ld 12,%0" : : "Q" (state->fprs[12]));
126 asm volatile("ld 13,%0" : : "Q" (state->fprs[13]));
127 asm volatile("ld 14,%0" : : "Q" (state->fprs[14]));
128 asm volatile("ld 15,%0" : : "Q" (state->fprs[15]));
129 }
130 return;
131 }
132
133 /* Test and restore (load) vector registers */
134 asm volatile (
135 /*
136 * Test if any vector register must be loaded and, if so,
137 * test if all registers can be loaded at once.
138 */
139 " la 1,%[vxrs]\n" /* load restore area */
140 " tmll %[m],30\n" /* KERNEL_VXR */
141 " jz 7f\n" /* no work -> done */
142 " jo 5f\n" /* -> restore V0..V31 */
143 /*
144 * Test for special case KERNEL_FPU_MID only. In this
145 * case a vlm V8..V23 is the best instruction
146 */
147 " chi %[m],12\n" /* KERNEL_VXR_MID */
148 " jne 0f\n" /* -> restore V8..V23 */
149 " VLM 8,23,128,1\n" /* vlm %v8,%v23,128(%r1) */
150 " j 7f\n"
151 /* Test and restore the first half of 16 vector registers */
152 "0: tmll %[m],6\n" /* KERNEL_VXR_LOW */
153 " jz 3f\n" /* -> KERNEL_VXR_HIGH */
154 " jo 2f\n" /* 11 -> restore V0..V15 */
155 " brc 2,1f\n" /* 10 -> restore V8..V15 */
156 " VLM 0,7,0,1\n" /* vlm %v0,%v7,0(%r1) */
157 " j 3f\n"
158 "1: VLM 8,15,128,1\n" /* vlm %v8,%v15,128(%r1) */
159 " j 3f\n"
160 "2: VLM 0,15,0,1\n" /* vlm %v0,%v15,0(%r1) */
161 /* Test and restore the second half of 16 vector registers */
162 "3: tmll %[m],24\n" /* KERNEL_VXR_HIGH */
163 " jz 7f\n"
164 " jo 6f\n" /* 11 -> restore V16..V31 */
165 " brc 2,4f\n" /* 10 -> restore V24..V31 */
166 " VLM 16,23,256,1\n" /* vlm %v16,%v23,256(%r1) */
167 " j 7f\n"
168 "4: VLM 24,31,384,1\n" /* vlm %v24,%v31,384(%r1) */
169 " j 7f\n"
170 "5: VLM 0,15,0,1\n" /* vlm %v0,%v15,0(%r1) */
171 "6: VLM 16,31,256,1\n" /* vlm %v16,%v31,256(%r1) */
172 "7:"
173 : [vxrs] "=Q" (*(struct vx_array *) &state->vxrs)
174 : [m] "d" (flags)
175 : "1", "cc");
176}
177EXPORT_SYMBOL(__kernel_fpu_end);