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1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * arch/arm/mach-pxa/include/mach/pcm990_baseboard.h
4 *
5 * (c) 2003 Phytec Messtechnik GmbH <armlinux@phytec.de>
6 * (c) 2007 Juergen Beisert <j.beisert@pengutronix.de>
7 */
8
9#include "pcm027.h"
10#include <mach/irqs.h> /* PXA_GPIO_TO_IRQ */
11
12/*
13 * definitions relevant only when the PCM-990
14 * development base board is in use
15 */
16
17/* CPLD's interrupt controller is connected to PCM-027 GPIO 9 */
18#define PCM990_CTRL_INT_IRQ_GPIO 9
19#define PCM990_CTRL_INT_IRQ PXA_GPIO_TO_IRQ(PCM990_CTRL_INT_IRQ_GPIO)
20#define PCM990_CTRL_INT_IRQ_EDGE IRQ_TYPE_EDGE_RISING
21#define PCM990_CTRL_PHYS PXA_CS1_PHYS /* 16-Bit */
22#define PCM990_CTRL_SIZE (1*1024*1024)
23
24#define PCM990_CTRL_PWR_IRQ_GPIO 14
25#define PCM990_CTRL_PWR_IRQ PXA_GPIO_TO_IRQ(PCM990_CTRL_PWR_IRQ_GPIO)
26#define PCM990_CTRL_PWR_IRQ_EDGE IRQ_TYPE_EDGE_RISING
27
28/* visible CPLD (U7) registers */
29#define PCM990_CTRL_REG0 0x0000 /* RESET REGISTER */
30#define PCM990_CTRL_SYSRES 0x0001 /* System RESET REGISTER */
31#define PCM990_CTRL_RESOUT 0x0002 /* RESETOUT Enable REGISTER */
32#define PCM990_CTRL_RESGPIO 0x0004 /* RESETGPIO Enable REGISTER */
33
34#define PCM990_CTRL_REG1 0x0002 /* Power REGISTER */
35#define PCM990_CTRL_5VOFF 0x0001 /* Disable 5V Regulators */
36#define PCM990_CTRL_CANPWR 0x0004 /* Enable CANPWR ADUM */
37#define PCM990_CTRL_PM_5V 0x0008 /* Read 5V OK */
38
39#define PCM990_CTRL_REG2 0x0004 /* LED REGISTER */
40#define PCM990_CTRL_LEDPWR 0x0001 /* POWER LED enable */
41#define PCM990_CTRL_LEDBAS 0x0002 /* BASIS LED enable */
42#define PCM990_CTRL_LEDUSR 0x0004 /* USER LED enable */
43
44#define PCM990_CTRL_REG3 0x0006 /* LCD CTRL REGISTER 3 */
45#define PCM990_CTRL_LCDPWR 0x0001 /* RW LCD Power on */
46#define PCM990_CTRL_LCDON 0x0002 /* RW LCD Latch on */
47#define PCM990_CTRL_LCDPOS1 0x0004 /* RW POS 1 */
48#define PCM990_CTRL_LCDPOS2 0x0008 /* RW POS 2 */
49
50#define PCM990_CTRL_REG4 0x0008 /* MMC1 CTRL REGISTER 4 */
51#define PCM990_CTRL_MMC1PWR 0x0001 /* RW MMC1 Power on */
52
53#define PCM990_CTRL_REG5 0x000A /* MMC2 CTRL REGISTER 5 */
54#define PCM990_CTRL_MMC2PWR 0x0001 /* RW MMC2 Power on */
55#define PCM990_CTRL_MMC2LED 0x0002 /* RW MMC2 LED */
56#define PCM990_CTRL_MMC2DE 0x0004 /* R MMC2 Card detect */
57#define PCM990_CTRL_MMC2WP 0x0008 /* R MMC2 Card write protect */
58
59#define PCM990_CTRL_INTSETCLR 0x000C /* Interrupt Clear REGISTER */
60#define PCM990_CTRL_INTC0 0x0001 /* Clear Reg BT Detect */
61#define PCM990_CTRL_INTC1 0x0002 /* Clear Reg FR RI */
62#define PCM990_CTRL_INTC2 0x0004 /* Clear Reg MMC1 Detect */
63#define PCM990_CTRL_INTC3 0x0008 /* Clear Reg PM_5V off */
64
65#define PCM990_CTRL_INTMSKENA 0x000E /* Interrupt Enable REGISTER */
66#define PCM990_CTRL_ENAINT0 0x0001 /* Enable Int BT Detect */
67#define PCM990_CTRL_ENAINT1 0x0002 /* Enable Int FR RI */
68#define PCM990_CTRL_ENAINT2 0x0004 /* Enable Int MMC1 Detect */
69#define PCM990_CTRL_ENAINT3 0x0008 /* Enable Int PM_5V off */
70
71#define PCM990_CTRL_REG8 0x0014 /* Uart REGISTER */
72#define PCM990_CTRL_FFSD 0x0001 /* BT Uart Enable */
73#define PCM990_CTRL_BTSD 0x0002 /* FF Uart Enable */
74#define PCM990_CTRL_FFRI 0x0004 /* FF Uart RI detect */
75#define PCM990_CTRL_BTRX 0x0008 /* BT Uart Rx detect */
76
77#define PCM990_CTRL_REG9 0x0010 /* AC97 Flash REGISTER */
78#define PCM990_CTRL_FLWP 0x0001 /* pC Flash Write Protect */
79#define PCM990_CTRL_FLDIS 0x0002 /* pC Flash Disable */
80#define PCM990_CTRL_AC97ENA 0x0004 /* Enable AC97 Expansion */
81
82#define PCM990_CTRL_REG10 0x0012 /* GPS-REGISTER */
83#define PCM990_CTRL_GPSPWR 0x0004 /* GPS-Modul Power on */
84#define PCM990_CTRL_GPSENA 0x0008 /* GPS-Modul Enable */
85
86#define PCM990_CTRL_REG11 0x0014 /* Accu REGISTER */
87#define PCM990_CTRL_ACENA 0x0001 /* Charge Enable */
88#define PCM990_CTRL_ACSEL 0x0002 /* Charge Akku -> DC Enable */
89#define PCM990_CTRL_ACPRES 0x0004 /* DC Present */
90#define PCM990_CTRL_ACALARM 0x0008 /* Error Akku */
91
92/*
93 * IDE
94 */
95#define PCM990_IDE_IRQ_GPIO 13
96#define PCM990_IDE_IRQ PXA_GPIO_TO_IRQ(PCM990_IDE_IRQ_GPIO)
97#define PCM990_IDE_IRQ_EDGE IRQ_TYPE_EDGE_RISING
98#define PCM990_IDE_PLD_PHYS 0x20000000 /* 16 bit wide */
99#define PCM990_IDE_PLD_BASE 0xee000000
100#define PCM990_IDE_PLD_SIZE (1*1024*1024)
101
102/* visible CPLD (U6) registers */
103#define PCM990_IDE_PLD_REG0 0x1000 /* OFFSET IDE REGISTER 0 */
104#define PCM990_IDE_PM5V 0x0004 /* R System VCC_5V */
105#define PCM990_IDE_STBY 0x0008 /* R System StandBy */
106
107#define PCM990_IDE_PLD_REG1 0x1002 /* OFFSET IDE REGISTER 1 */
108#define PCM990_IDE_IDEMODE 0x0001 /* R TrueIDE Mode */
109#define PCM990_IDE_DMAENA 0x0004 /* RW DMA Enable */
110#define PCM990_IDE_DMA1_0 0x0008 /* RW 1=DREQ1 0=DREQ0 */
111
112#define PCM990_IDE_PLD_REG2 0x1004 /* OFFSET IDE REGISTER 2 */
113#define PCM990_IDE_RESENA 0x0001 /* RW IDE Reset Bit enable */
114#define PCM990_IDE_RES 0x0002 /* RW IDE Reset Bit */
115#define PCM990_IDE_RDY 0x0008 /* RDY */
116
117#define PCM990_IDE_PLD_REG3 0x1006 /* OFFSET IDE REGISTER 3 */
118#define PCM990_IDE_IDEOE 0x0001 /* RW Latch on Databus */
119#define PCM990_IDE_IDEON 0x0002 /* RW Latch on Control Address */
120#define PCM990_IDE_IDEIN 0x0004 /* RW Latch on Interrupt usw. */
121
122#define PCM990_IDE_PLD_REG4 0x1008 /* OFFSET IDE REGISTER 4 */
123#define PCM990_IDE_PWRENA 0x0001 /* RW IDE Power enable */
124#define PCM990_IDE_5V 0x0002 /* R IDE Power 5V */
125#define PCM990_IDE_PWG 0x0008 /* R IDE Power is on */
126
127#define PCM990_IDE_PLD_P2V(x) ((x) - PCM990_IDE_PLD_PHYS + PCM990_IDE_PLD_BASE)
128#define PCM990_IDE_PLD_V2P(x) ((x) - PCM990_IDE_PLD_BASE + PCM990_IDE_PLD_PHYS)
129
130/*
131 * Compact Flash
132 */
133#define PCM990_CF_IRQ_GPIO 11
134#define PCM990_CF_IRQ PXA_GPIO_TO_IRQ(PCM990_CF_IRQ_GPIO)
135#define PCM990_CF_IRQ_EDGE IRQ_TYPE_EDGE_RISING
136
137#define PCM990_CF_CD_GPIO 12
138#define PCM990_CF_CD PXA_GPIO_TO_IRQ(PCM990_CF_CD_GPIO)
139#define PCM990_CF_CD_EDGE IRQ_TYPE_EDGE_RISING
140
141#define PCM990_CF_PLD_PHYS 0x30000000 /* 16 bit wide */
142
143/* visible CPLD (U6) registers */
144#define PCM990_CF_PLD_REG0 0x1000 /* OFFSET CF REGISTER 0 */
145#define PCM990_CF_REG0_LED 0x0001 /* RW LED on */
146#define PCM990_CF_REG0_BLK 0x0002 /* RW LED flash when access */
147#define PCM990_CF_REG0_PM5V 0x0004 /* R System VCC_5V enable */
148#define PCM990_CF_REG0_STBY 0x0008 /* R System StandBy */
149
150#define PCM990_CF_PLD_REG1 0x1002 /* OFFSET CF REGISTER 1 */
151#define PCM990_CF_REG1_IDEMODE 0x0001 /* RW CF card run as TrueIDE */
152#define PCM990_CF_REG1_CF0 0x0002 /* RW CF card at ADDR 0x28000000 */
153
154#define PCM990_CF_PLD_REG2 0x1004 /* OFFSET CF REGISTER 2 */
155#define PCM990_CF_REG2_RES 0x0002 /* RW CF RESET BIT */
156#define PCM990_CF_REG2_RDYENA 0x0004 /* RW Enable CF_RDY */
157#define PCM990_CF_REG2_RDY 0x0008 /* R CF_RDY auf PWAIT */
158
159#define PCM990_CF_PLD_REG3 0x1006 /* OFFSET CF REGISTER 3 */
160#define PCM990_CF_REG3_CFOE 0x0001 /* RW Latch on Databus */
161#define PCM990_CF_REG3_CFON 0x0002 /* RW Latch on Control Address */
162#define PCM990_CF_REG3_CFIN 0x0004 /* RW Latch on Interrupt usw. */
163#define PCM990_CF_REG3_CFCD 0x0008 /* RW Latch on CD1/2 VS1/2 usw */
164
165#define PCM990_CF_PLD_REG4 0x1008 /* OFFSET CF REGISTER 4 */
166#define PCM990_CF_REG4_PWRENA 0x0001 /* RW CF Power on (CD1/2 = "00") */
167#define PCM990_CF_REG4_5_3V 0x0002 /* RW 1 = 5V CF_VCC 0 = 3 V CF_VCC */
168#define PCM990_CF_REG4_3B 0x0004 /* RW 3.0V Backup from VCC (5_3V=0) */
169#define PCM990_CF_REG4_PWG 0x0008 /* R CF-Power is on */
170
171#define PCM990_CF_PLD_REG5 0x100A /* OFFSET CF REGISTER 5 */
172#define PCM990_CF_REG5_BVD1 0x0001 /* R CF /BVD1 */
173#define PCM990_CF_REG5_BVD2 0x0002 /* R CF /BVD2 */
174#define PCM990_CF_REG5_VS1 0x0004 /* R CF /VS1 */
175#define PCM990_CF_REG5_VS2 0x0008 /* R CF /VS2 */
176
177#define PCM990_CF_PLD_REG6 0x100C /* OFFSET CF REGISTER 6 */
178#define PCM990_CF_REG6_CD1 0x0001 /* R CF Card_Detect1 */
179#define PCM990_CF_REG6_CD2 0x0002 /* R CF Card_Detect2 */
180
181/*
182 * Wolfson AC97 Touch
183 */
184#define PCM990_AC97_IRQ_GPIO 10
185#define PCM990_AC97_IRQ PXA_GPIO_TO_IRQ(PCM990_AC97_IRQ_GPIO)
186#define PCM990_AC97_IRQ_EDGE IRQ_TYPE_EDGE_RISING
187
188/*
189 * MMC phyCORE
190 */
191#define PCM990_MMC0_IRQ_GPIO 9
192#define PCM990_MMC0_IRQ PXA_GPIO_TO_IRQ(PCM990_MMC0_IRQ_GPIO)
193#define PCM990_MMC0_IRQ_EDGE IRQ_TYPE_EDGE_FALLING
194
195/*
196 * USB phyCore
197 */
198#define PCM990_USB_OVERCURRENT (88 | GPIO_ALT_FN_1_IN)
199#define PCM990_USB_PWR_EN (89 | GPIO_ALT_FN_2_OUT)