1/* SPDX-License-Identifier: GPL-2.0-or-later */
 2/*
 3 * sleep mode for CSR SiRFprimaII
 4 *
 5 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
 6 */
 7
 8#include <linux/linkage.h>
 9#include <asm/ptrace.h>
10#include <asm/assembler.h>
11
12#include "pm.h"
13
14#define DENALI_CTL_22_OFF	0x58
15#define DENALI_CTL_112_OFF	0x1c0
16
17	.text
18
19ENTRY(sirfsoc_finish_suspend)
20	@ r5: 	mem controller
21	ldr     r0, =sirfsoc_memc_base
22	ldr	r5, [r0]
23	@ r6: 	pwrc base offset
24	ldr     r0, =sirfsoc_pwrc_base
25	ldr	r6, [r0]
26	@ r7: 	rtc iobrg controller
27	ldr     r0, =sirfsoc_rtciobrg_base
28	ldr	r7, [r0]
29
30	@ Read the power control register and set the
31	@ sleep force bit.
32	add	r0, r6, #SIRFSOC_PWRC_PDN_CTRL
33	bl	__sirfsoc_rtc_iobrg_readl
34	orr	r0,r0,#SIRFSOC_PWR_SLEEPFORCE
35	add	r1, r6, #SIRFSOC_PWRC_PDN_CTRL
36	bl	sirfsoc_rtc_iobrg_pre_writel
37	mov	r1, #0x1
38
39	@ read the MEM ctl register and set the self
40	@ refresh bit
41
42	ldr	r2, [r5, #DENALI_CTL_22_OFF]
43	orr	r2, r2, #0x1
44
45	@ Following code has to run from cache since
46	@ the RAM is going to self refresh mode
47	.align 5
48	str	r2, [r5, #DENALI_CTL_22_OFF]
49
501:
51	ldr	r4, [r5, #DENALI_CTL_112_OFF]
52	tst	r4, #0x1
53	bne	1b
54
55	@ write SLEEPFORCE through rtc iobridge
56
57	str	r1, [r7]
58	@ wait rtc io bridge sync
591:
60	ldr	r3, [r7]
61	tst	r3, #0x01
62	bne	1b
63	b .