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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * ox810se.dtsi - Device tree file for Oxford Semiconductor OX810SE SoC
4 *
5 * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
6 */
7
8#include <dt-bindings/clock/oxsemi,ox810se.h>
9#include <dt-bindings/reset/oxsemi,ox810se.h>
10
11/ {
12 #address-cells = <1>;
13 #size-cells = <1>;
14 compatible = "oxsemi,ox810se";
15
16 cpus {
17 #address-cells = <0>;
18 #size-cells = <0>;
19
20 cpu {
21 device_type = "cpu";
22 compatible = "arm,arm926ej-s";
23 clocks = <&armclk>;
24 };
25 };
26
27 memory {
28 device_type = "memory";
29 /* Max 256MB @ 0x48000000 */
30 reg = <0x48000000 0x10000000>;
31 };
32
33 clocks {
34 osc: oscillator {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <25000000>;
38 };
39
40 gmacclk: gmacclk {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <125000000>;
44 };
45
46 rpsclk: rpsclk {
47 compatible = "fixed-factor-clock";
48 #clock-cells = <0>;
49 clock-div = <1>;
50 clock-mult = <1>;
51 clocks = <&osc>;
52 };
53
54 pll400: pll400 {
55 compatible = "fixed-clock";
56 #clock-cells = <0>;
57 clock-frequency = <733333333>;
58 };
59
60 sysclk: sysclk {
61 compatible = "fixed-factor-clock";
62 #clock-cells = <0>;
63 clock-div = <4>;
64 clock-mult = <1>;
65 clocks = <&pll400>;
66 };
67
68 armclk: armclk {
69 compatible = "fixed-factor-clock";
70 #clock-cells = <0>;
71 clock-div = <2>;
72 clock-mult = <1>;
73 clocks = <&pll400>;
74 };
75 };
76
77 soc {
78 #address-cells = <1>;
79 #size-cells = <1>;
80 compatible = "simple-bus";
81 ranges;
82 interrupt-parent = <&intc>;
83
84 apb-bridge@44000000 {
85 #address-cells = <1>;
86 #size-cells = <1>;
87 compatible = "simple-bus";
88 ranges = <0 0x44000000 0x1000000>;
89
90 pinctrl: pinctrl {
91 compatible = "oxsemi,ox810se-pinctrl";
92
93 /* Regmap for sys registers */
94 oxsemi,sys-ctrl = <&sys>;
95
96 pinctrl_uart0: uart0 {
97 uart0a {
98 pins = "gpio31";
99 function = "fct3";
100 };
101 uart0b {
102 pins = "gpio32";
103 function = "fct3";
104 };
105 };
106
107 pinctrl_uart0_modem: uart0_modem {
108 uart0c {
109 pins = "gpio27";
110 function = "fct3";
111 };
112 uart0d {
113 pins = "gpio28";
114 function = "fct3";
115 };
116 uart0e {
117 pins = "gpio29";
118 function = "fct3";
119 };
120 uart0f {
121 pins = "gpio30";
122 function = "fct3";
123 };
124 uart0g {
125 pins = "gpio33";
126 function = "fct3";
127 };
128 uart0h {
129 pins = "gpio34";
130 function = "fct3";
131 };
132 };
133
134 pinctrl_uart1: uart1 {
135 uart1a {
136 pins = "gpio20";
137 function = "fct3";
138 };
139 uart1b {
140 pins = "gpio22";
141 function = "fct3";
142 };
143 };
144
145 pinctrl_uart1_modem: uart1_modem {
146 uart1c {
147 pins = "gpio8";
148 function = "fct3";
149 };
150 uart1d {
151 pins = "gpio9";
152 function = "fct3";
153 };
154 uart1e {
155 pins = "gpio23";
156 function = "fct3";
157 };
158 uart1f {
159 pins = "gpio24";
160 function = "fct3";
161 };
162 uart1g {
163 pins = "gpio25";
164 function = "fct3";
165 };
166 uart1h {
167 pins = "gpio26";
168 function = "fct3";
169 };
170 };
171
172 pinctrl_uart2: uart2 {
173 uart2a {
174 pins = "gpio6";
175 function = "fct3";
176 };
177 uart2b {
178 pins = "gpio7";
179 function = "fct3";
180 };
181 };
182
183 pinctrl_uart2_modem: uart2_modem {
184 uart2c {
185 pins = "gpio0";
186 function = "fct3";
187 };
188 uart2d {
189 pins = "gpio1";
190 function = "fct3";
191 };
192 uart2e {
193 pins = "gpio2";
194 function = "fct3";
195 };
196 uart2f {
197 pins = "gpio3";
198 function = "fct3";
199 };
200 uart2g {
201 pins = "gpio4";
202 function = "fct3";
203 };
204 uart2h {
205 pins = "gpio5";
206 function = "fct3";
207 };
208 };
209 };
210
211 gpio0: gpio@0 {
212 compatible = "oxsemi,ox810se-gpio";
213 reg = <0x000000 0x100000>;
214 interrupts = <21>;
215 #gpio-cells = <2>;
216 gpio-controller;
217 interrupt-controller;
218 #interrupt-cells = <2>;
219 ngpios = <32>;
220 oxsemi,gpio-bank = <0>;
221 gpio-ranges = <&pinctrl 0 0 32>;
222 };
223
224 gpio1: gpio@100000 {
225 compatible = "oxsemi,ox810se-gpio";
226 reg = <0x100000 0x100000>;
227 interrupts = <22>;
228 #gpio-cells = <2>;
229 gpio-controller;
230 interrupt-controller;
231 #interrupt-cells = <2>;
232 ngpios = <3>;
233 oxsemi,gpio-bank = <1>;
234 gpio-ranges = <&pinctrl 0 32 3>;
235 };
236
237 uart0: serial@200000 {
238 compatible = "ns16550a";
239 reg = <0x200000 0x100000>;
240 clocks = <&sysclk>;
241 interrupts = <23>;
242 reg-shift = <0>;
243 fifo-size = <16>;
244 reg-io-width = <1>;
245 current-speed = <115200>;
246 no-loopback-test;
247 status = "disabled";
248 resets = <&reset RESET_UART1>;
249 };
250
251 uart1: serial@300000 {
252 compatible = "ns16550a";
253 reg = <0x300000 0x100000>;
254 clocks = <&sysclk>;
255 interrupts = <24>;
256 reg-shift = <0>;
257 fifo-size = <16>;
258 reg-io-width = <1>;
259 current-speed = <115200>;
260 no-loopback-test;
261 status = "disabled";
262 resets = <&reset RESET_UART2>;
263 };
264
265 uart2: serial@900000 {
266 compatible = "ns16550a";
267 reg = <0x900000 0x100000>;
268 clocks = <&sysclk>;
269 interrupts = <29>;
270 reg-shift = <0>;
271 fifo-size = <16>;
272 reg-io-width = <1>;
273 current-speed = <115200>;
274 no-loopback-test;
275 status = "disabled";
276 resets = <&reset RESET_UART3>;
277 };
278
279 uart3: serial@a00000 {
280 compatible = "ns16550a";
281 reg = <0xa00000 0x100000>;
282 clocks = <&sysclk>;
283 interrupts = <30>;
284 reg-shift = <0>;
285 fifo-size = <16>;
286 reg-io-width = <1>;
287 current-speed = <115200>;
288 no-loopback-test;
289 status = "disabled";
290 resets = <&reset RESET_UART4>;
291 };
292 };
293
294 apb-bridge@45000000 {
295 #address-cells = <1>;
296 #size-cells = <1>;
297 compatible = "simple-bus";
298 ranges = <0 0x45000000 0x1000000>;
299
300 sys: sys-ctrl@0 {
301 compatible = "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd";
302 reg = <0x000000 0x100000>;
303
304 reset: reset-controller {
305 compatible = "oxsemi,ox810se-reset";
306 #reset-cells = <1>;
307 };
308
309 stdclk: stdclk {
310 compatible = "oxsemi,ox810se-stdclk";
311 #clock-cells = <1>;
312 };
313 };
314
315 rps@300000 {
316 #address-cells = <1>;
317 #size-cells = <1>;
318 compatible = "simple-bus";
319 ranges = <0 0x300000 0x100000>;
320
321 intc: interrupt-controller@0 {
322 compatible = "oxsemi,ox810se-rps-irq";
323 interrupt-controller;
324 reg = <0 0x200>;
325 #interrupt-cells = <1>;
326 valid-mask = <0xFFFFFFFF>;
327 clear-mask = <0>;
328 };
329
330 timer0: timer@200 {
331 compatible = "oxsemi,ox810se-rps-timer";
332 reg = <0x200 0x40>;
333 clocks = <&rpsclk>;
334 interrupts = <4 5>;
335 };
336 };
337 };
338 };
339};