Loading...
Note: File does not exist in v6.13.7.
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2014 Gateworks Corporation
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7
8/ {
9 /* these are used by bootloader for disabling nodes */
10 aliases {
11 led0 = &led0;
12 led1 = &led1;
13 led2 = &led2;
14 nand = &gpmi;
15 usb0 = &usbh1;
16 usb1 = &usbotg;
17 };
18
19 chosen {
20 bootargs = "console=ttymxc1,115200";
21 };
22
23 leds {
24 compatible = "gpio-leds";
25 pinctrl-names = "default";
26 pinctrl-0 = <&pinctrl_gpio_leds>;
27
28 led0: user1 {
29 label = "user1";
30 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
31 default-state = "on";
32 linux,default-trigger = "heartbeat";
33 };
34
35 led1: user2 {
36 label = "user2";
37 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
38 default-state = "off";
39 };
40
41 led2: user3 {
42 label = "user3";
43 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
44 default-state = "off";
45 };
46 };
47
48 memory@10000000 {
49 device_type = "memory";
50 reg = <0x10000000 0x20000000>;
51 };
52
53 reg_1p0v: regulator-1p0v {
54 compatible = "regulator-fixed";
55 regulator-name = "1P0V";
56 regulator-min-microvolt = <1000000>;
57 regulator-max-microvolt = <1000000>;
58 regulator-always-on;
59 };
60
61 reg_3p3v: regulator-3p3v {
62 compatible = "regulator-fixed";
63 regulator-name = "3P3V";
64 regulator-min-microvolt = <3300000>;
65 regulator-max-microvolt = <3300000>;
66 regulator-always-on;
67 };
68
69 reg_5p0v: regulator-5p0v {
70 compatible = "regulator-fixed";
71 regulator-name = "5P0V";
72 regulator-min-microvolt = <5000000>;
73 regulator-max-microvolt = <5000000>;
74 regulator-always-on;
75 };
76};
77
78&gpmi {
79 pinctrl-names = "default";
80 pinctrl-0 = <&pinctrl_gpmi_nand>;
81 status = "okay";
82};
83
84&hdmi {
85 ddc-i2c-bus = <&i2c3>;
86 status = "okay";
87};
88
89&i2c1 {
90 clock-frequency = <100000>;
91 pinctrl-names = "default";
92 pinctrl-0 = <&pinctrl_i2c1>;
93 status = "okay";
94
95 eeprom1: eeprom@50 {
96 compatible = "atmel,24c02";
97 reg = <0x50>;
98 pagesize = <16>;
99 };
100
101 eeprom2: eeprom@51 {
102 compatible = "atmel,24c02";
103 reg = <0x51>;
104 pagesize = <16>;
105 };
106
107 eeprom3: eeprom@52 {
108 compatible = "atmel,24c02";
109 reg = <0x52>;
110 pagesize = <16>;
111 };
112
113 eeprom4: eeprom@53 {
114 compatible = "atmel,24c02";
115 reg = <0x53>;
116 pagesize = <16>;
117 };
118
119 gpio: pca9555@23 {
120 compatible = "nxp,pca9555";
121 reg = <0x23>;
122 gpio-controller;
123 #gpio-cells = <2>;
124 };
125
126 rtc: ds1672@68 {
127 compatible = "dallas,ds1672";
128 reg = <0x68>;
129 };
130};
131
132&i2c2 {
133 clock-frequency = <100000>;
134 pinctrl-names = "default";
135 pinctrl-0 = <&pinctrl_i2c2>;
136 status = "okay";
137
138 ltc3676: pmic@3c {
139 compatible = "lltc,ltc3676";
140 reg = <0x3c>;
141 pinctrl-names = "default";
142 pinctrl-0 = <&pinctrl_pmic>;
143 interrupt-parent = <&gpio1>;
144 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
145
146 regulators {
147 /* VDD_SOC (1+R1/R2 = 1.635) */
148 reg_vdd_soc: sw1 {
149 regulator-name = "vddsoc";
150 regulator-min-microvolt = <674400>;
151 regulator-max-microvolt = <1308000>;
152 lltc,fb-voltage-divider = <127000 200000>;
153 regulator-ramp-delay = <7000>;
154 regulator-boot-on;
155 regulator-always-on;
156 };
157
158 /* VDD_1P8 (1+R1/R2 = 2.505): ENET-PHY */
159 reg_1p8v: sw2 {
160 regulator-name = "vdd1p8";
161 regulator-min-microvolt = <1033310>;
162 regulator-max-microvolt = <2004000>;
163 lltc,fb-voltage-divider = <301000 200000>;
164 regulator-ramp-delay = <7000>;
165 regulator-boot-on;
166 regulator-always-on;
167 };
168
169 /* VDD_ARM (1+R1/R2 = 1.635) */
170 reg_vdd_arm: sw3 {
171 regulator-name = "vddarm";
172 regulator-min-microvolt = <674400>;
173 regulator-max-microvolt = <1308000>;
174 lltc,fb-voltage-divider = <127000 200000>;
175 regulator-ramp-delay = <7000>;
176 regulator-boot-on;
177 regulator-always-on;
178 };
179
180 /* VDD_DDR (1+R1/R2 = 2.105) */
181 reg_vdd_ddr: sw4 {
182 regulator-name = "vddddr";
183 regulator-min-microvolt = <868310>;
184 regulator-max-microvolt = <1684000>;
185 lltc,fb-voltage-divider = <221000 200000>;
186 regulator-ramp-delay = <7000>;
187 regulator-boot-on;
188 regulator-always-on;
189 };
190
191 /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
192 reg_2p5v: ldo2 {
193 regulator-name = "vdd2p5";
194 regulator-min-microvolt = <2490375>;
195 regulator-max-microvolt = <2490375>;
196 lltc,fb-voltage-divider = <487000 200000>;
197 regulator-boot-on;
198 regulator-always-on;
199 };
200
201 /* VDD_HIGH (1+R1/R2 = 4.17) */
202 reg_3p0v: ldo4 {
203 regulator-name = "vdd3p0";
204 regulator-min-microvolt = <3023250>;
205 regulator-max-microvolt = <3023250>;
206 lltc,fb-voltage-divider = <634000 200000>;
207 regulator-boot-on;
208 regulator-always-on;
209 };
210 };
211 };
212};
213
214&i2c3 {
215 clock-frequency = <100000>;
216 pinctrl-names = "default";
217 pinctrl-0 = <&pinctrl_i2c3>;
218 status = "okay";
219};
220
221&pcie {
222 pinctrl-names = "default";
223 pinctrl-0 = <&pinctrl_pcie>;
224 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
225 status = "okay";
226};
227
228&pwm2 {
229 pinctrl-names = "default";
230 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
231 status = "disabled";
232};
233
234&pwm3 {
235 pinctrl-names = "default";
236 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
237 status = "disabled";
238};
239
240&uart2 {
241 pinctrl-names = "default";
242 pinctrl-0 = <&pinctrl_uart2>;
243 status = "okay";
244};
245
246&uart3 {
247 pinctrl-names = "default";
248 pinctrl-0 = <&pinctrl_uart3>;
249 status = "okay";
250};
251
252&uart5 {
253 pinctrl-names = "default";
254 pinctrl-0 = <&pinctrl_uart5>;
255 status = "okay"; };
256
257&usbh1 {
258 status = "okay";
259};
260
261&wdog1 {
262 pinctrl-names = "default";
263 pinctrl-0 = <&pinctrl_wdog>;
264 fsl,ext-reset-output;
265};
266
267&iomuxc {
268 pinctrl_gpio_leds: gpioledsgrp {
269 fsl,pins = <
270 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
271 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
272 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
273 >;
274 };
275
276 pinctrl_gpmi_nand: gpminandgrp {
277 fsl,pins = <
278 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
279 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
280 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
281 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
282 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
283 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
284 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
285 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
286 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
287 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
288 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
289 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
290 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
291 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
292 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
293 >;
294 };
295
296 pinctrl_i2c1: i2c1grp {
297 fsl,pins = <
298 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
299 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
300 >;
301 };
302
303 pinctrl_i2c2: i2c2grp {
304 fsl,pins = <
305 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
306 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
307 >;
308 };
309
310 pinctrl_i2c3: i2c3grp {
311 fsl,pins = <
312 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
313 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
314 >;
315 };
316
317 pinctrl_pcie: pciegrp {
318 fsl,pins = <
319 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
320 >;
321 };
322
323 pinctrl_pmic: pmicgrp {
324 fsl,pins = <
325 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
326 >;
327 };
328
329 pinctrl_pwm2: pwm2grp {
330 fsl,pins = <
331 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
332 >;
333 };
334
335 pinctrl_pwm3: pwm3grp {
336 fsl,pins = <
337 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
338 >;
339 };
340
341 pinctrl_uart2: uart2grp {
342 fsl,pins = <
343 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
344 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
345 >;
346 };
347
348 pinctrl_uart3: uart3grp {
349 fsl,pins = <
350 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
351 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
352 >;
353 };
354
355 pinctrl_uart5: uart5grp {
356 fsl,pins = <
357 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
358 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
359 >;
360 };
361
362 pinctrl_wdog: wdoggrp {
363 fsl,pins = <
364 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
365 >;
366 };
367};