1/* SPDX-License-Identifier: GPL-2.0-only */
 2/*
 3 * soc-intel-quirks.h - prototypes for quirk autodetection
 4 *
 5 * Copyright (c) 2019, Intel Corporation.
 6 *
 7 */
 8
 9#ifndef _SND_SOC_INTEL_QUIRKS_H
10#define _SND_SOC_INTEL_QUIRKS_H
11
12#include <linux/platform_data/x86/soc.h>
13
14#if IS_REACHABLE(CONFIG_IOSF_MBI)
15
16#include <linux/dmi.h>
17#include <asm/iosf_mbi.h>
18
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
19static inline bool soc_intel_is_byt_cr(struct platform_device *pdev)
20{
21	/*
22	 * List of systems which:
23	 * 1. Use a non CR version of the Bay Trail SoC
24	 * 2. Contain at least 6 interrupt resources so that the
25	 *    platform_get_resource(pdev, IORESOURCE_IRQ, 5) check below
26	 *    succeeds
27	 * 3. Despite 1. and 2. still have their IPC IRQ at index 0 rather then 5
28	 *
29	 * This needs to be here so that it can be shared between the SST and
30	 * SOF drivers. We rely on the compiler to optimize this out in files
31	 * where soc_intel_is_byt_cr is not used.
32	 */
33	static const struct dmi_system_id force_bytcr_table[] = {
34		{	/* Lenovo Yoga Tablet 2 series */
35			.matches = {
36				DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
37				DMI_MATCH(DMI_PRODUCT_FAMILY, "YOGATablet2"),
38			},
39		},
40		{}
41	};
42	struct device *dev = &pdev->dev;
43	int status = 0;
44
45	if (!soc_intel_is_byt())
46		return false;
47
48	if (dmi_check_system(force_bytcr_table))
49		return true;
50
51	if (iosf_mbi_available()) {
52		u32 bios_status;
53
54		status = iosf_mbi_read(BT_MBI_UNIT_PMC, /* 0x04 PUNIT */
55				       MBI_REG_READ, /* 0x10 */
56				       0x006, /* BIOS_CONFIG */
57				       &bios_status);
58
59		if (status) {
60			dev_err(dev, "could not read PUNIT BIOS_CONFIG\n");
61		} else {
62			/* bits 26:27 mirror PMIC options */
63			bios_status = (bios_status >> 26) & 3;
64
65			if (bios_status == 1 || bios_status == 3) {
66				dev_info(dev, "Detected Baytrail-CR platform\n");
67				return true;
68			}
69
70			dev_info(dev, "BYT-CR not detected\n");
71		}
72	} else {
73		dev_info(dev, "IOSF_MBI not available, no BYT-CR detection\n");
74	}
75
76	if (!platform_get_resource(pdev, IORESOURCE_IRQ, 5)) {
77		/*
78		 * Some devices detected as BYT-T have only a single IRQ listed,
79		 * causing platform_get_irq with index 5 to return -ENXIO.
80		 * The correct IRQ in this case is at index 0, as on BYT-CR.
81		 */
82		dev_info(dev, "Falling back to Baytrail-CR platform\n");
83		return true;
84	}
85
86	return false;
87}
88
89#else
90
91static inline bool soc_intel_is_byt_cr(struct platform_device *pdev)
92{
93	return false;
94}
95
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
96#endif
97
98#endif /* _SND_SOC_INTEL_QUIRKS_H */

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 * soc-intel-quirks.h - prototypes for quirk autodetection
  4 *
  5 * Copyright (c) 2019, Intel Corporation.
  6 *
  7 */
  8
  9#ifndef _SND_SOC_INTEL_QUIRKS_H
 10#define _SND_SOC_INTEL_QUIRKS_H
 11
 12#if IS_ENABLED(CONFIG_X86)
 13
 14#include <asm/cpu_device_id.h>
 15#include <asm/intel-family.h>
 
 16#include <asm/iosf_mbi.h>
 17
 18#define ICPU(model)	{ X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, }
 19
 20#define SOC_INTEL_IS_CPU(soc, type)				\
 21static inline bool soc_intel_is_##soc(void)			\
 22{								\
 23	static const struct x86_cpu_id soc##_cpu_ids[] = {	\
 24		ICPU(type),					\
 25		{}						\
 26	};							\
 27	const struct x86_cpu_id *id;				\
 28								\
 29	id = x86_match_cpu(soc##_cpu_ids);			\
 30	if (id)							\
 31		return true;					\
 32	return false;						\
 33}
 34
 35SOC_INTEL_IS_CPU(byt, INTEL_FAM6_ATOM_SILVERMONT);
 36SOC_INTEL_IS_CPU(cht, INTEL_FAM6_ATOM_AIRMONT);
 37SOC_INTEL_IS_CPU(apl, INTEL_FAM6_ATOM_GOLDMONT);
 38SOC_INTEL_IS_CPU(glk, INTEL_FAM6_ATOM_GOLDMONT_PLUS);
 39SOC_INTEL_IS_CPU(cml, INTEL_FAM6_KABYLAKE_L);
 40
 41static inline bool soc_intel_is_byt_cr(struct platform_device *pdev)
 42{
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 43	struct device *dev = &pdev->dev;
 44	int status = 0;
 45
 46	if (!soc_intel_is_byt())
 47		return false;
 48
 
 
 
 49	if (iosf_mbi_available()) {
 50		u32 bios_status;
 51
 52		status = iosf_mbi_read(BT_MBI_UNIT_PMC, /* 0x04 PUNIT */
 53				       MBI_REG_READ, /* 0x10 */
 54				       0x006, /* BIOS_CONFIG */
 55				       &bios_status);
 56
 57		if (status) {
 58			dev_err(dev, "could not read PUNIT BIOS_CONFIG\n");
 59		} else {
 60			/* bits 26:27 mirror PMIC options */
 61			bios_status = (bios_status >> 26) & 3;
 62
 63			if (bios_status == 1 || bios_status == 3) {
 64				dev_info(dev, "Detected Baytrail-CR platform\n");
 65				return true;
 66			}
 67
 68			dev_info(dev, "BYT-CR not detected\n");
 69		}
 70	} else {
 71		dev_info(dev, "IOSF_MBI not available, no BYT-CR detection\n");
 72	}
 73
 74	if (!platform_get_resource(pdev, IORESOURCE_IRQ, 5)) {
 75		/*
 76		 * Some devices detected as BYT-T have only a single IRQ listed,
 77		 * causing platform_get_irq with index 5 to return -ENXIO.
 78		 * The correct IRQ in this case is at index 0, as on BYT-CR.
 79		 */
 80		dev_info(dev, "Falling back to Baytrail-CR platform\n");
 81		return true;
 82	}
 83
 84	return false;
 85}
 86
 87#else
 88
 89static inline bool soc_intel_is_byt_cr(struct platform_device *pdev)
 90{
 91	return false;
 92}
 93
 94static inline bool soc_intel_is_byt(void)
 95{
 96	return false;
 97}
 98
 99static inline bool soc_intel_is_cht(void)
100{
101	return false;
102}
103
104static inline bool soc_intel_is_apl(void)
105{
106	return false;
107}
108
109static inline bool soc_intel_is_glk(void)
110{
111	return false;
112}
113
114static inline bool soc_intel_is_cml(void)
115{
116	return false;
117}
118#endif
119
120 #endif /* _SND_SOC_INTEL_QUIRKS_H */