1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * rt1011.c -- rt1011 ALSA SoC amplifier component driver
   4 *
   5 * Copyright(c) 2019 Realtek Semiconductor Corp.
   6 *
   7 * Author: Shuming Fan <shumingf@realtek.com>
   8 *
   9 */
  10
  11#include <linux/module.h>
  12#include <linux/moduleparam.h>
  13#include <linux/init.h>
  14#include <linux/delay.h>
  15#include <linux/pm.h>
 
  16#include <linux/i2c.h>
  17#include <linux/acpi.h>
  18#include <linux/regmap.h>
 
  19#include <linux/platform_device.h>
  20#include <linux/firmware.h>
  21#include <sound/core.h>
  22#include <sound/pcm.h>
  23#include <sound/pcm_params.h>
  24#include <sound/soc.h>
  25#include <sound/soc-dapm.h>
  26#include <sound/initval.h>
  27#include <sound/tlv.h>
  28
  29#include "rl6231.h"
  30#include "rt1011.h"
  31
  32static int rt1011_calibrate(struct rt1011_priv *rt1011,
  33	unsigned char cali_flag);
  34
  35static const struct reg_sequence init_list[] = {
  36
  37	{ RT1011_POWER_9, 0xa840 },
  38
  39	{ RT1011_ADC_SET_5, 0x0a20 },
  40	{ RT1011_DAC_SET_2, 0xa032 },
 
  41
  42	{ RT1011_SPK_PRO_DC_DET_1, 0xb00c },
  43	{ RT1011_SPK_PRO_DC_DET_2, 0xcccc },
  44
  45	{ RT1011_A_TIMING_1, 0x6054 },
  46
  47	{ RT1011_POWER_7, 0x3e55 },
  48	{ RT1011_POWER_8, 0x0520 },
  49	{ RT1011_BOOST_CON_1, 0xe188 },
  50	{ RT1011_POWER_4, 0x16f2 },
  51
  52	{ RT1011_CROSS_BQ_SET_1, 0x0004 },
  53	{ RT1011_SIL_DET, 0xc313 },
  54	{ RT1011_SINE_GEN_REG_1, 0x0707 },
  55
  56	{ RT1011_DC_CALIB_CLASSD_3, 0xcb00 },
  57
  58	{ RT1011_DAC_SET_1, 0xe702 },
  59	{ RT1011_DAC_SET_3, 0x2004 },
  60};
 
  61
  62static const struct reg_default rt1011_reg[] = {
  63	{0x0000, 0x0000},
  64	{0x0002, 0x0000},
  65	{0x0004, 0xa000},
  66	{0x0006, 0x0000},
  67	{0x0008, 0x0003},
  68	{0x000a, 0x087e},
  69	{0x000c, 0x0020},
  70	{0x000e, 0x9002},
  71	{0x0010, 0x0000},
  72	{0x0012, 0x0000},
  73	{0x0020, 0x0c40},
  74	{0x0022, 0x4313},
  75	{0x0076, 0x0000},
  76	{0x0078, 0x0000},
  77	{0x007a, 0x0000},
  78	{0x007c, 0x10ec},
  79	{0x007d, 0x1011},
  80	{0x00f0, 0x5000},
  81	{0x00f2, 0x0374},
  82	{0x00f3, 0x0000},
  83	{0x00f4, 0x0000},
  84	{0x0100, 0x0038},
  85	{0x0102, 0xff02},
  86	{0x0104, 0x0232},
  87	{0x0106, 0x200c},
  88	{0x0107, 0x0000},
  89	{0x0108, 0x2f2f},
  90	{0x010a, 0x2f2f},
  91	{0x010c, 0x002f},
  92	{0x010e, 0xe000},
  93	{0x0110, 0x0820},
  94	{0x0111, 0x4010},
  95	{0x0112, 0x0000},
  96	{0x0114, 0x0000},
  97	{0x0116, 0x0000},
  98	{0x0118, 0x0000},
  99	{0x011a, 0x0101},
 100	{0x011c, 0x4567},
 101	{0x011e, 0x0000},
 102	{0x0120, 0x0000},
 103	{0x0122, 0x0000},
 104	{0x0124, 0x0123},
 105	{0x0126, 0x4567},
 106	{0x0200, 0x0000},
 107	{0x0300, 0xffdd},
 108	{0x0302, 0x001e},
 109	{0x0311, 0x0000},
 110	{0x0313, 0x5254},
 111	{0x0314, 0x0062},
 112	{0x0316, 0x7f40},
 113	{0x0319, 0x000f},
 114	{0x031a, 0xffff},
 115	{0x031b, 0x0000},
 116	{0x031c, 0x009f},
 117	{0x031d, 0xffff},
 118	{0x031e, 0x0000},
 119	{0x031f, 0x0000},
 120	{0x0320, 0xe31c},
 121	{0x0321, 0x0000},
 122	{0x0322, 0x0000},
 123	{0x0324, 0x0000},
 124	{0x0326, 0x0002},
 125	{0x0328, 0x20b2},
 126	{0x0329, 0x0175},
 127	{0x032a, 0x32ad},
 128	{0x032b, 0x3455},
 129	{0x032c, 0x0528},
 130	{0x032d, 0xa800},
 131	{0x032e, 0x030e},
 132	{0x0330, 0x2080},
 133	{0x0332, 0x0034},
 134	{0x0334, 0x0000},
 135	{0x0508, 0x0010},
 136	{0x050a, 0x0018},
 137	{0x050c, 0x0000},
 138	{0x050d, 0xffff},
 139	{0x050e, 0x1f1f},
 140	{0x050f, 0x04ff},
 141	{0x0510, 0x4020},
 142	{0x0511, 0x01f0},
 143	{0x0512, 0x0702},
 144	{0x0516, 0xbb80},
 145	{0x0517, 0xffff},
 146	{0x0518, 0xffff},
 147	{0x0519, 0x307f},
 148	{0x051a, 0xffff},
 149	{0x051b, 0x0000},
 150	{0x051c, 0x0000},
 151	{0x051d, 0x2000},
 152	{0x051e, 0x0000},
 153	{0x051f, 0x0000},
 154	{0x0520, 0x0000},
 155	{0x0521, 0x1001},
 156	{0x0522, 0x7fff},
 157	{0x0524, 0x7fff},
 158	{0x0526, 0x0000},
 159	{0x0528, 0x0000},
 160	{0x052a, 0x0000},
 161	{0x0530, 0x0401},
 162	{0x0532, 0x3000},
 163	{0x0534, 0x0000},
 164	{0x0535, 0xffff},
 165	{0x0536, 0x101c},
 166	{0x0538, 0x1814},
 167	{0x053a, 0x100c},
 168	{0x053c, 0x0804},
 169	{0x053d, 0x0000},
 170	{0x053e, 0x0000},
 171	{0x053f, 0x0000},
 172	{0x0540, 0x0000},
 173	{0x0541, 0x0000},
 174	{0x0542, 0x0000},
 175	{0x0543, 0x0000},
 176	{0x0544, 0x001c},
 177	{0x0545, 0x1814},
 178	{0x0546, 0x100c},
 179	{0x0547, 0x0804},
 180	{0x0548, 0x0000},
 181	{0x0549, 0x0000},
 182	{0x054a, 0x0000},
 183	{0x054b, 0x0000},
 184	{0x054c, 0x0000},
 185	{0x054d, 0x0000},
 186	{0x054e, 0x0000},
 187	{0x054f, 0x0000},
 188	{0x0566, 0x0000},
 189	{0x0568, 0x20f1},
 190	{0x056a, 0x0007},
 191	{0x0600, 0x9d00},
 192	{0x0611, 0x2000},
 193	{0x0612, 0x505f},
 194	{0x0613, 0x0444},
 195	{0x0614, 0x4000},
 196	{0x0615, 0x4004},
 197	{0x0616, 0x0606},
 198	{0x0617, 0x8904},
 199	{0x0618, 0xe021},
 200	{0x0621, 0x2000},
 201	{0x0622, 0x505f},
 202	{0x0623, 0x0444},
 203	{0x0624, 0x4000},
 204	{0x0625, 0x4004},
 205	{0x0626, 0x0606},
 206	{0x0627, 0x8704},
 207	{0x0628, 0xe021},
 208	{0x0631, 0x2000},
 209	{0x0632, 0x517f},
 210	{0x0633, 0x0440},
 211	{0x0634, 0x4000},
 212	{0x0635, 0x4104},
 213	{0x0636, 0x0306},
 214	{0x0637, 0x8904},
 215	{0x0638, 0xe021},
 216	{0x0702, 0x0014},
 217	{0x0704, 0x0000},
 218	{0x0706, 0x0014},
 219	{0x0708, 0x0000},
 220	{0x070a, 0x0000},
 221	{0x0710, 0x0200},
 222	{0x0711, 0x0000},
 223	{0x0712, 0x0200},
 224	{0x0713, 0x0000},
 225	{0x0720, 0x0200},
 226	{0x0721, 0x0000},
 227	{0x0722, 0x0000},
 228	{0x0723, 0x0000},
 229	{0x0724, 0x0000},
 230	{0x0725, 0x0000},
 231	{0x0726, 0x0000},
 232	{0x0727, 0x0000},
 233	{0x0728, 0x0000},
 234	{0x0729, 0x0000},
 235	{0x0730, 0x0200},
 236	{0x0731, 0x0000},
 237	{0x0732, 0x0000},
 238	{0x0733, 0x0000},
 239	{0x0734, 0x0000},
 240	{0x0735, 0x0000},
 241	{0x0736, 0x0000},
 242	{0x0737, 0x0000},
 243	{0x0738, 0x0000},
 244	{0x0739, 0x0000},
 245	{0x0740, 0x0200},
 246	{0x0741, 0x0000},
 247	{0x0742, 0x0000},
 248	{0x0743, 0x0000},
 249	{0x0744, 0x0000},
 250	{0x0745, 0x0000},
 251	{0x0746, 0x0000},
 252	{0x0747, 0x0000},
 253	{0x0748, 0x0000},
 254	{0x0749, 0x0000},
 255	{0x0750, 0x0200},
 256	{0x0751, 0x0000},
 257	{0x0752, 0x0000},
 258	{0x0753, 0x0000},
 259	{0x0754, 0x0000},
 260	{0x0755, 0x0000},
 261	{0x0756, 0x0000},
 262	{0x0757, 0x0000},
 263	{0x0758, 0x0000},
 264	{0x0759, 0x0000},
 265	{0x0760, 0x0200},
 266	{0x0761, 0x0000},
 267	{0x0762, 0x0000},
 268	{0x0763, 0x0000},
 269	{0x0764, 0x0000},
 270	{0x0765, 0x0000},
 271	{0x0766, 0x0000},
 272	{0x0767, 0x0000},
 273	{0x0768, 0x0000},
 274	{0x0769, 0x0000},
 275	{0x0770, 0x0200},
 276	{0x0771, 0x0000},
 277	{0x0772, 0x0000},
 278	{0x0773, 0x0000},
 279	{0x0774, 0x0000},
 280	{0x0775, 0x0000},
 281	{0x0776, 0x0000},
 282	{0x0777, 0x0000},
 283	{0x0778, 0x0000},
 284	{0x0779, 0x0000},
 285	{0x0780, 0x0200},
 286	{0x0781, 0x0000},
 287	{0x0782, 0x0000},
 288	{0x0783, 0x0000},
 289	{0x0784, 0x0000},
 290	{0x0785, 0x0000},
 291	{0x0786, 0x0000},
 292	{0x0787, 0x0000},
 293	{0x0788, 0x0000},
 294	{0x0789, 0x0000},
 295	{0x0790, 0x0200},
 296	{0x0791, 0x0000},
 297	{0x0792, 0x0000},
 298	{0x0793, 0x0000},
 299	{0x0794, 0x0000},
 300	{0x0795, 0x0000},
 301	{0x0796, 0x0000},
 302	{0x0797, 0x0000},
 303	{0x0798, 0x0000},
 304	{0x0799, 0x0000},
 305	{0x07a0, 0x0200},
 306	{0x07a1, 0x0000},
 307	{0x07a2, 0x0000},
 308	{0x07a3, 0x0000},
 309	{0x07a4, 0x0000},
 310	{0x07a5, 0x0000},
 311	{0x07a6, 0x0000},
 312	{0x07a7, 0x0000},
 313	{0x07a8, 0x0000},
 314	{0x07a9, 0x0000},
 315	{0x07b0, 0x0200},
 316	{0x07b1, 0x0000},
 317	{0x07b2, 0x0000},
 318	{0x07b3, 0x0000},
 319	{0x07b4, 0x0000},
 320	{0x07b5, 0x0000},
 321	{0x07b6, 0x0000},
 322	{0x07b7, 0x0000},
 323	{0x07b8, 0x0000},
 324	{0x07b9, 0x0000},
 325	{0x07c0, 0x0200},
 326	{0x07c1, 0x0000},
 327	{0x07c2, 0x0000},
 328	{0x07c3, 0x0000},
 329	{0x07c4, 0x0000},
 330	{0x07c5, 0x0000},
 331	{0x07c6, 0x0000},
 332	{0x07c7, 0x0000},
 333	{0x07c8, 0x0000},
 334	{0x07c9, 0x0000},
 335	{0x1000, 0x4040},
 336	{0x1002, 0x6505},
 337	{0x1004, 0x5405},
 338	{0x1006, 0x5555},
 339	{0x1007, 0x003f},
 340	{0x1008, 0x7fd7},
 341	{0x1009, 0x770f},
 342	{0x100a, 0xfffe},
 343	{0x100b, 0xe000},
 344	{0x100c, 0x0000},
 345	{0x100d, 0x0007},
 346	{0x1010, 0xa433},
 347	{0x1020, 0x0000},
 348	{0x1022, 0x0000},
 349	{0x1024, 0x0000},
 350	{0x1200, 0x5a01},
 351	{0x1202, 0x6324},
 352	{0x1204, 0x0b00},
 353	{0x1206, 0x0000},
 354	{0x1208, 0x0000},
 355	{0x120a, 0x0024},
 356	{0x120c, 0x0000},
 357	{0x120e, 0x000e},
 358	{0x1210, 0x0000},
 359	{0x1212, 0x0000},
 360	{0x1300, 0x0701},
 361	{0x1302, 0x12f9},
 362	{0x1304, 0x3405},
 363	{0x1305, 0x0844},
 364	{0x1306, 0x5611},
 365	{0x1308, 0x555e},
 366	{0x130a, 0xa605},
 367	{0x130c, 0x2000},
 368	{0x130e, 0x0000},
 369	{0x130f, 0x0001},
 370	{0x1310, 0xaa48},
 371	{0x1312, 0x0285},
 372	{0x1314, 0xaaaa},
 373	{0x1316, 0xaaa0},
 374	{0x1318, 0x2aaa},
 375	{0x131a, 0xaa07},
 376	{0x1322, 0x0029},
 377	{0x1323, 0x4a52},
 378	{0x1324, 0x002c},
 379	{0x1325, 0x0b02},
 380	{0x1326, 0x002d},
 381	{0x1327, 0x6b5a},
 382	{0x1328, 0x002e},
 383	{0x1329, 0xcbb2},
 384	{0x132a, 0x0030},
 385	{0x132b, 0x2c0b},
 386	{0x1330, 0x0031},
 387	{0x1331, 0x8c63},
 388	{0x1332, 0x0032},
 389	{0x1333, 0xecbb},
 390	{0x1334, 0x0034},
 391	{0x1335, 0x4d13},
 392	{0x1336, 0x0037},
 393	{0x1337, 0x0dc3},
 394	{0x1338, 0x003d},
 395	{0x1339, 0xef7b},
 396	{0x133a, 0x0044},
 397	{0x133b, 0xd134},
 398	{0x133c, 0x0047},
 399	{0x133d, 0x91e4},
 400	{0x133e, 0x004d},
 401	{0x133f, 0xc370},
 402	{0x1340, 0x0053},
 403	{0x1341, 0xf4fd},
 404	{0x1342, 0x0060},
 405	{0x1343, 0x5816},
 406	{0x1344, 0x006c},
 407	{0x1345, 0xbb2e},
 408	{0x1346, 0x0072},
 409	{0x1347, 0xecbb},
 410	{0x1348, 0x0076},
 411	{0x1349, 0x5d97},
 412	{0x1500, 0x0702},
 413	{0x1502, 0x002f},
 414	{0x1504, 0x0000},
 415	{0x1510, 0x0064},
 416	{0x1512, 0x0000},
 417	{0x1514, 0xdf47},
 418	{0x1516, 0x079c},
 419	{0x1518, 0xfbf5},
 420	{0x151a, 0x00bc},
 421	{0x151c, 0x3b85},
 422	{0x151e, 0x02b3},
 423	{0x1520, 0x3333},
 424	{0x1522, 0x0000},
 425	{0x1524, 0x4000},
 426	{0x1528, 0x0064},
 427	{0x152a, 0x0000},
 428	{0x152c, 0x0000},
 429	{0x152e, 0x0000},
 430	{0x1530, 0x0000},
 431	{0x1532, 0x0000},
 432	{0x1534, 0x0000},
 433	{0x1536, 0x0000},
 434	{0x1538, 0x0040},
 435	{0x1539, 0x0000},
 436	{0x153a, 0x0040},
 437	{0x153b, 0x0000},
 438	{0x153c, 0x0064},
 439	{0x153e, 0x0bf9},
 440	{0x1540, 0xb2a9},
 441	{0x1544, 0x0200},
 442	{0x1546, 0x0000},
 443	{0x1548, 0x00ca},
 444	{0x1552, 0x03ff},
 445	{0x1554, 0x017f},
 446	{0x1556, 0x017f},
 447	{0x155a, 0x0000},
 448	{0x155c, 0x0000},
 449	{0x1560, 0x0040},
 450	{0x1562, 0x0000},
 451	{0x1570, 0x03ff},
 452	{0x1571, 0xdcff},
 453	{0x1572, 0x1e00},
 454	{0x1573, 0x224f},
 455	{0x1574, 0x0000},
 456	{0x1575, 0x0000},
 457	{0x1576, 0x1e00},
 458	{0x1577, 0x0000},
 459	{0x1578, 0x0000},
 460	{0x1579, 0x1128},
 461	{0x157a, 0x03ff},
 462	{0x157b, 0xdcff},
 463	{0x157c, 0x1e00},
 464	{0x157d, 0x224f},
 465	{0x157e, 0x0000},
 466	{0x157f, 0x0000},
 467	{0x1580, 0x1e00},
 468	{0x1581, 0x0000},
 469	{0x1582, 0x0000},
 470	{0x1583, 0x1128},
 471	{0x1590, 0x03ff},
 472	{0x1591, 0xdcff},
 473	{0x1592, 0x1e00},
 474	{0x1593, 0x224f},
 475	{0x1594, 0x0000},
 476	{0x1595, 0x0000},
 477	{0x1596, 0x1e00},
 478	{0x1597, 0x0000},
 479	{0x1598, 0x0000},
 480	{0x1599, 0x1128},
 481	{0x159a, 0x03ff},
 482	{0x159b, 0xdcff},
 483	{0x159c, 0x1e00},
 484	{0x159d, 0x224f},
 485	{0x159e, 0x0000},
 486	{0x159f, 0x0000},
 487	{0x15a0, 0x1e00},
 488	{0x15a1, 0x0000},
 489	{0x15a2, 0x0000},
 490	{0x15a3, 0x1128},
 491	{0x15b0, 0x007f},
 492	{0x15b1, 0xffff},
 493	{0x15b2, 0x007f},
 494	{0x15b3, 0xffff},
 495	{0x15b4, 0x007f},
 496	{0x15b5, 0xffff},
 497	{0x15b8, 0x007f},
 498	{0x15b9, 0xffff},
 499	{0x15bc, 0x0000},
 500	{0x15bd, 0x0000},
 501	{0x15be, 0xff00},
 502	{0x15bf, 0x0000},
 503	{0x15c0, 0xff00},
 504	{0x15c1, 0x0000},
 505	{0x15c3, 0xfc00},
 506	{0x15c4, 0xbb80},
 507	{0x15d0, 0x0000},
 508	{0x15d1, 0x0000},
 509	{0x15d2, 0x0000},
 510	{0x15d3, 0x0000},
 511	{0x15d4, 0x0000},
 512	{0x15d5, 0x0000},
 513	{0x15d6, 0x0000},
 514	{0x15d7, 0x0000},
 515	{0x15d8, 0x0200},
 516	{0x15d9, 0x0000},
 517	{0x15da, 0x0000},
 518	{0x15db, 0x0000},
 519	{0x15dc, 0x0000},
 520	{0x15dd, 0x0000},
 521	{0x15de, 0x0000},
 522	{0x15df, 0x0000},
 523	{0x15e0, 0x0000},
 524	{0x15e1, 0x0000},
 525	{0x15e2, 0x0200},
 526	{0x15e3, 0x0000},
 527	{0x15e4, 0x0000},
 528	{0x15e5, 0x0000},
 529	{0x15e6, 0x0000},
 530	{0x15e7, 0x0000},
 531	{0x15e8, 0x0000},
 532	{0x15e9, 0x0000},
 533	{0x15ea, 0x0000},
 534	{0x15eb, 0x0000},
 535	{0x15ec, 0x0200},
 536	{0x15ed, 0x0000},
 537	{0x15ee, 0x0000},
 538	{0x15ef, 0x0000},
 539	{0x15f0, 0x0000},
 540	{0x15f1, 0x0000},
 541	{0x15f2, 0x0000},
 542	{0x15f3, 0x0000},
 543	{0x15f4, 0x0000},
 544	{0x15f5, 0x0000},
 545	{0x15f6, 0x0200},
 546	{0x15f7, 0x0200},
 547	{0x15f8, 0x8200},
 548	{0x15f9, 0x0000},
 549	{0x1600, 0x007d},
 550	{0x1601, 0xa178},
 551	{0x1602, 0x00c2},
 552	{0x1603, 0x5383},
 553	{0x1604, 0x0000},
 554	{0x1605, 0x02c1},
 555	{0x1606, 0x007d},
 556	{0x1607, 0xa178},
 557	{0x1608, 0x00c2},
 558	{0x1609, 0x5383},
 559	{0x160a, 0x003e},
 560	{0x160b, 0xd37d},
 561	{0x1611, 0x3210},
 562	{0x1612, 0x7418},
 563	{0x1613, 0xc0ff},
 564	{0x1614, 0x0000},
 565	{0x1615, 0x00ff},
 566	{0x1616, 0x0000},
 567	{0x1617, 0x0000},
 568	{0x1621, 0x6210},
 569	{0x1622, 0x7418},
 570	{0x1623, 0xc0ff},
 571	{0x1624, 0x0000},
 572	{0x1625, 0x00ff},
 573	{0x1626, 0x0000},
 574	{0x1627, 0x0000},
 575	{0x1631, 0x3a14},
 576	{0x1632, 0x7418},
 577	{0x1633, 0xc3ff},
 578	{0x1634, 0x0000},
 579	{0x1635, 0x00ff},
 580	{0x1636, 0x0000},
 581	{0x1637, 0x0000},
 582	{0x1638, 0x0000},
 583	{0x163a, 0x0000},
 584	{0x163c, 0x0000},
 585	{0x163e, 0x0000},
 586	{0x1640, 0x0000},
 587	{0x1642, 0x0000},
 588	{0x1644, 0x0000},
 589	{0x1646, 0x0000},
 590	{0x1648, 0x0000},
 591	{0x1650, 0x0000},
 592	{0x1652, 0x0000},
 593	{0x1654, 0x0000},
 594	{0x1656, 0x0000},
 595	{0x1658, 0x0000},
 596	{0x1660, 0x0000},
 597	{0x1662, 0x0000},
 598	{0x1664, 0x0000},
 599	{0x1666, 0x0000},
 600	{0x1668, 0x0000},
 601	{0x1670, 0x0000},
 602	{0x1672, 0x0000},
 603	{0x1674, 0x0000},
 604	{0x1676, 0x0000},
 605	{0x1678, 0x0000},
 606	{0x1680, 0x0000},
 607	{0x1682, 0x0000},
 608	{0x1684, 0x0000},
 609	{0x1686, 0x0000},
 610	{0x1688, 0x0000},
 611	{0x1690, 0x0000},
 612	{0x1692, 0x0000},
 613	{0x1694, 0x0000},
 614	{0x1696, 0x0000},
 615	{0x1698, 0x0000},
 616	{0x1700, 0x0000},
 617	{0x1702, 0x0000},
 618	{0x1704, 0x0000},
 619	{0x1706, 0x0000},
 620	{0x1708, 0x0000},
 621	{0x1710, 0x0000},
 622	{0x1712, 0x0000},
 623	{0x1714, 0x0000},
 624	{0x1716, 0x0000},
 625	{0x1718, 0x0000},
 626	{0x1720, 0x0000},
 627	{0x1722, 0x0000},
 628	{0x1724, 0x0000},
 629	{0x1726, 0x0000},
 630	{0x1728, 0x0000},
 631	{0x1730, 0x0000},
 632	{0x1732, 0x0000},
 633	{0x1734, 0x0000},
 634	{0x1736, 0x0000},
 635	{0x1738, 0x0000},
 636	{0x173a, 0x0000},
 637	{0x173c, 0x0000},
 638	{0x173e, 0x0000},
 639	{0x17bb, 0x0500},
 640	{0x17bd, 0x0004},
 641	{0x17bf, 0x0004},
 642	{0x17c1, 0x0004},
 643	{0x17c2, 0x7fff},
 644	{0x17c3, 0x0000},
 645	{0x17c5, 0x0000},
 646	{0x17c7, 0x0000},
 647	{0x17c9, 0x0000},
 648	{0x17cb, 0x2010},
 649	{0x17cd, 0x0000},
 650	{0x17cf, 0x0000},
 651	{0x17d1, 0x0000},
 652	{0x17d3, 0x0000},
 653	{0x17d5, 0x0000},
 654	{0x17d7, 0x0000},
 655	{0x17d9, 0x0000},
 656	{0x17db, 0x0000},
 657	{0x17dd, 0x0000},
 658	{0x17df, 0x0000},
 659	{0x17e1, 0x0000},
 660	{0x17e3, 0x0000},
 661	{0x17e5, 0x0000},
 662	{0x17e7, 0x0000},
 663	{0x17e9, 0x0000},
 664	{0x17eb, 0x0000},
 665	{0x17ed, 0x0000},
 666	{0x17ef, 0x0000},
 667	{0x17f1, 0x0000},
 668	{0x17f3, 0x0000},
 669	{0x17f5, 0x0000},
 670	{0x17f7, 0x0000},
 671	{0x17f9, 0x0000},
 672	{0x17fb, 0x0000},
 673	{0x17fd, 0x0000},
 674	{0x17ff, 0x0000},
 675	{0x1801, 0x0000},
 676	{0x1803, 0x0000},
 677};
 678
 679static int rt1011_reg_init(struct snd_soc_component *component)
 680{
 681	struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
 682
 683	regmap_multi_reg_write(rt1011->regmap,
 684		init_list, ARRAY_SIZE(init_list));
 685	return 0;
 686}
 687
 688static bool rt1011_volatile_register(struct device *dev, unsigned int reg)
 689{
 690	switch (reg) {
 691	case RT1011_RESET:
 692	case RT1011_SRC_2:
 693	case RT1011_CLK_DET:
 694	case RT1011_SIL_DET:
 695	case RT1011_VERSION_ID:
 696	case RT1011_VENDOR_ID:
 697	case RT1011_DEVICE_ID:
 698	case RT1011_DUM_RO:
 699	case RT1011_DAC_SET_3:
 700	case RT1011_PWM_CAL:
 701	case RT1011_SPK_VOL_TEST_OUT:
 702	case RT1011_VBAT_VOL_DET_1:
 703	case RT1011_VBAT_TEST_OUT_1:
 704	case RT1011_VBAT_TEST_OUT_2:
 705	case RT1011_VBAT_PROTECTION:
 706	case RT1011_VBAT_DET:
 707	case RT1011_BOOST_CON_1:
 708	case RT1011_SHORT_CIRCUIT_DET_1:
 709	case RT1011_SPK_TEMP_PROTECT_3:
 710	case RT1011_SPK_TEMP_PROTECT_6:
 711	case RT1011_SPK_PRO_DC_DET_3:
 712	case RT1011_SPK_PRO_DC_DET_7:
 713	case RT1011_SPK_PRO_DC_DET_8:
 714	case RT1011_SPL_1:
 715	case RT1011_SPL_4:
 716	case RT1011_EXCUR_PROTECT_1:
 717	case RT1011_CROSS_BQ_SET_1:
 718	case RT1011_CROSS_BQ_SET_2:
 719	case RT1011_BQ_SET_0:
 720	case RT1011_BQ_SET_1:
 721	case RT1011_BQ_SET_2:
 722	case RT1011_TEST_PAD_STATUS:
 723	case RT1011_DC_CALIB_CLASSD_1:
 724	case RT1011_DC_CALIB_CLASSD_5:
 725	case RT1011_DC_CALIB_CLASSD_6:
 726	case RT1011_DC_CALIB_CLASSD_7:
 727	case RT1011_DC_CALIB_CLASSD_8:
 728	case RT1011_SINE_GEN_REG_2:
 729	case RT1011_STP_CALIB_RS_TEMP:
 730	case RT1011_SPK_RESISTANCE_1:
 731	case RT1011_SPK_RESISTANCE_2:
 732	case RT1011_SPK_THERMAL:
 733	case RT1011_ALC_BK_GAIN_O:
 734	case RT1011_ALC_BK_GAIN_O_PRE:
 735	case RT1011_SPK_DC_O_23_16:
 736	case RT1011_SPK_DC_O_15_0:
 737	case RT1011_INIT_RECIPROCAL_SYN_24_16:
 738	case RT1011_INIT_RECIPROCAL_SYN_15_0:
 739	case RT1011_SPK_EXCURSION_23_16:
 740	case RT1011_SPK_EXCURSION_15_0:
 741	case RT1011_SEP_MAIN_OUT_23_16:
 742	case RT1011_SEP_MAIN_OUT_15_0:
 743	case RT1011_ALC_DRC_HB_INTERNAL_5:
 744	case RT1011_ALC_DRC_HB_INTERNAL_6:
 745	case RT1011_ALC_DRC_HB_INTERNAL_7:
 746	case RT1011_ALC_DRC_BB_INTERNAL_5:
 747	case RT1011_ALC_DRC_BB_INTERNAL_6:
 748	case RT1011_ALC_DRC_BB_INTERNAL_7:
 749	case RT1011_ALC_DRC_POS_INTERNAL_5:
 750	case RT1011_ALC_DRC_POS_INTERNAL_6:
 751	case RT1011_ALC_DRC_POS_INTERNAL_7:
 752	case RT1011_ALC_DRC_POS_INTERNAL_8:
 753	case RT1011_ALC_DRC_POS_INTERNAL_9:
 754	case RT1011_ALC_DRC_POS_INTERNAL_10:
 755	case RT1011_ALC_DRC_POS_INTERNAL_11:
 756	case RT1011_IRQ_1:
 757	case RT1011_EFUSE_CONTROL_1:
 758	case RT1011_EFUSE_CONTROL_2:
 759	case RT1011_EFUSE_MATCH_DONE ... RT1011_EFUSE_READ_R0_3_15_0:
 760		return true;
 761
 762	default:
 763		return false;
 764	}
 765}
 766
 767static bool rt1011_readable_register(struct device *dev, unsigned int reg)
 768{
 769	switch (reg) {
 770	case RT1011_RESET:
 771	case RT1011_CLK_1:
 772	case RT1011_CLK_2:
 773	case RT1011_CLK_3:
 774	case RT1011_CLK_4:
 775	case RT1011_PLL_1:
 776	case RT1011_PLL_2:
 777	case RT1011_SRC_1:
 778	case RT1011_SRC_2:
 779	case RT1011_SRC_3:
 780	case RT1011_CLK_DET:
 781	case RT1011_SIL_DET:
 782	case RT1011_PRIV_INDEX:
 783	case RT1011_PRIV_DATA:
 784	case RT1011_CUSTOMER_ID:
 785	case RT1011_FM_VER:
 786	case RT1011_VERSION_ID:
 787	case RT1011_VENDOR_ID:
 788	case RT1011_DEVICE_ID:
 789	case RT1011_DUM_RW_0:
 790	case RT1011_DUM_YUN:
 791	case RT1011_DUM_RW_1:
 792	case RT1011_DUM_RO:
 793	case RT1011_MAN_I2C_DEV:
 794	case RT1011_DAC_SET_1:
 795	case RT1011_DAC_SET_2:
 796	case RT1011_DAC_SET_3:
 797	case RT1011_ADC_SET:
 798	case RT1011_ADC_SET_1:
 799	case RT1011_ADC_SET_2:
 800	case RT1011_ADC_SET_3:
 801	case RT1011_ADC_SET_4:
 802	case RT1011_ADC_SET_5:
 803	case RT1011_TDM_TOTAL_SET:
 804	case RT1011_TDM1_SET_TCON:
 805	case RT1011_TDM1_SET_1:
 806	case RT1011_TDM1_SET_2:
 807	case RT1011_TDM1_SET_3:
 808	case RT1011_TDM1_SET_4:
 809	case RT1011_TDM1_SET_5:
 810	case RT1011_TDM2_SET_1:
 811	case RT1011_TDM2_SET_2:
 812	case RT1011_TDM2_SET_3:
 813	case RT1011_TDM2_SET_4:
 814	case RT1011_TDM2_SET_5:
 815	case RT1011_PWM_CAL:
 816	case RT1011_MIXER_1:
 817	case RT1011_MIXER_2:
 818	case RT1011_ADRC_LIMIT:
 819	case RT1011_A_PRO:
 820	case RT1011_A_TIMING_1:
 821	case RT1011_A_TIMING_2:
 822	case RT1011_A_TEMP_SEN:
 823	case RT1011_SPK_VOL_DET_1:
 824	case RT1011_SPK_VOL_DET_2:
 825	case RT1011_SPK_VOL_TEST_OUT:
 826	case RT1011_VBAT_VOL_DET_1:
 827	case RT1011_VBAT_VOL_DET_2:
 828	case RT1011_VBAT_TEST_OUT_1:
 829	case RT1011_VBAT_TEST_OUT_2:
 830	case RT1011_VBAT_PROTECTION:
 831	case RT1011_VBAT_DET:
 832	case RT1011_POWER_1:
 833	case RT1011_POWER_2:
 834	case RT1011_POWER_3:
 835	case RT1011_POWER_4:
 836	case RT1011_POWER_5:
 837	case RT1011_POWER_6:
 838	case RT1011_POWER_7:
 839	case RT1011_POWER_8:
 840	case RT1011_POWER_9:
 841	case RT1011_CLASS_D_POS:
 842	case RT1011_BOOST_CON_1:
 843	case RT1011_BOOST_CON_2:
 844	case RT1011_ANALOG_CTRL:
 845	case RT1011_POWER_SEQ:
 846	case RT1011_SHORT_CIRCUIT_DET_1:
 847	case RT1011_SHORT_CIRCUIT_DET_2:
 848	case RT1011_SPK_TEMP_PROTECT_0:
 849	case RT1011_SPK_TEMP_PROTECT_1:
 850	case RT1011_SPK_TEMP_PROTECT_2:
 851	case RT1011_SPK_TEMP_PROTECT_3:
 852	case RT1011_SPK_TEMP_PROTECT_4:
 853	case RT1011_SPK_TEMP_PROTECT_5:
 854	case RT1011_SPK_TEMP_PROTECT_6:
 855	case RT1011_SPK_TEMP_PROTECT_7:
 856	case RT1011_SPK_TEMP_PROTECT_8:
 857	case RT1011_SPK_TEMP_PROTECT_9:
 858	case RT1011_SPK_PRO_DC_DET_1:
 859	case RT1011_SPK_PRO_DC_DET_2:
 860	case RT1011_SPK_PRO_DC_DET_3:
 861	case RT1011_SPK_PRO_DC_DET_4:
 862	case RT1011_SPK_PRO_DC_DET_5:
 863	case RT1011_SPK_PRO_DC_DET_6:
 864	case RT1011_SPK_PRO_DC_DET_7:
 865	case RT1011_SPK_PRO_DC_DET_8:
 866	case RT1011_SPL_1:
 867	case RT1011_SPL_2:
 868	case RT1011_SPL_3:
 869	case RT1011_SPL_4:
 870	case RT1011_THER_FOLD_BACK_1:
 871	case RT1011_THER_FOLD_BACK_2:
 872	case RT1011_EXCUR_PROTECT_1:
 873	case RT1011_EXCUR_PROTECT_2:
 874	case RT1011_EXCUR_PROTECT_3:
 875	case RT1011_EXCUR_PROTECT_4:
 876	case RT1011_BAT_GAIN_1:
 877	case RT1011_BAT_GAIN_2:
 878	case RT1011_BAT_GAIN_3:
 879	case RT1011_BAT_GAIN_4:
 880	case RT1011_BAT_GAIN_5:
 881	case RT1011_BAT_GAIN_6:
 882	case RT1011_BAT_GAIN_7:
 883	case RT1011_BAT_GAIN_8:
 884	case RT1011_BAT_GAIN_9:
 885	case RT1011_BAT_GAIN_10:
 886	case RT1011_BAT_GAIN_11:
 887	case RT1011_BAT_RT_THMAX_1:
 888	case RT1011_BAT_RT_THMAX_2:
 889	case RT1011_BAT_RT_THMAX_3:
 890	case RT1011_BAT_RT_THMAX_4:
 891	case RT1011_BAT_RT_THMAX_5:
 892	case RT1011_BAT_RT_THMAX_6:
 893	case RT1011_BAT_RT_THMAX_7:
 894	case RT1011_BAT_RT_THMAX_8:
 895	case RT1011_BAT_RT_THMAX_9:
 896	case RT1011_BAT_RT_THMAX_10:
 897	case RT1011_BAT_RT_THMAX_11:
 898	case RT1011_BAT_RT_THMAX_12:
 899	case RT1011_SPREAD_SPECTURM:
 900	case RT1011_PRO_GAIN_MODE:
 901	case RT1011_RT_DRC_CROSS:
 902	case RT1011_RT_DRC_HB_1:
 903	case RT1011_RT_DRC_HB_2:
 904	case RT1011_RT_DRC_HB_3:
 905	case RT1011_RT_DRC_HB_4:
 906	case RT1011_RT_DRC_HB_5:
 907	case RT1011_RT_DRC_HB_6:
 908	case RT1011_RT_DRC_HB_7:
 909	case RT1011_RT_DRC_HB_8:
 910	case RT1011_RT_DRC_BB_1:
 911	case RT1011_RT_DRC_BB_2:
 912	case RT1011_RT_DRC_BB_3:
 913	case RT1011_RT_DRC_BB_4:
 914	case RT1011_RT_DRC_BB_5:
 915	case RT1011_RT_DRC_BB_6:
 916	case RT1011_RT_DRC_BB_7:
 917	case RT1011_RT_DRC_BB_8:
 918	case RT1011_RT_DRC_POS_1:
 919	case RT1011_RT_DRC_POS_2:
 920	case RT1011_RT_DRC_POS_3:
 921	case RT1011_RT_DRC_POS_4:
 922	case RT1011_RT_DRC_POS_5:
 923	case RT1011_RT_DRC_POS_6:
 924	case RT1011_RT_DRC_POS_7:
 925	case RT1011_RT_DRC_POS_8:
 926	case RT1011_CROSS_BQ_SET_1:
 927	case RT1011_CROSS_BQ_SET_2:
 928	case RT1011_BQ_SET_0:
 929	case RT1011_BQ_SET_1:
 930	case RT1011_BQ_SET_2:
 931	case RT1011_BQ_PRE_GAIN_28_16:
 932	case RT1011_BQ_PRE_GAIN_15_0:
 933	case RT1011_BQ_POST_GAIN_28_16:
 934	case RT1011_BQ_POST_GAIN_15_0:
 935	case RT1011_BQ_H0_28_16 ... RT1011_BQ_A2_15_0:
 936	case RT1011_BQ_1_H0_28_16 ... RT1011_BQ_1_A2_15_0:
 937	case RT1011_BQ_2_H0_28_16 ... RT1011_BQ_2_A2_15_0:
 938	case RT1011_BQ_3_H0_28_16 ... RT1011_BQ_3_A2_15_0:
 939	case RT1011_BQ_4_H0_28_16 ... RT1011_BQ_4_A2_15_0:
 940	case RT1011_BQ_5_H0_28_16 ... RT1011_BQ_5_A2_15_0:
 941	case RT1011_BQ_6_H0_28_16 ... RT1011_BQ_6_A2_15_0:
 942	case RT1011_BQ_7_H0_28_16 ... RT1011_BQ_7_A2_15_0:
 943	case RT1011_BQ_8_H0_28_16 ... RT1011_BQ_8_A2_15_0:
 944	case RT1011_BQ_9_H0_28_16 ... RT1011_BQ_9_A2_15_0:
 945	case RT1011_BQ_10_H0_28_16 ... RT1011_BQ_10_A2_15_0:
 946	case RT1011_TEST_PAD_STATUS ... RT1011_PLL_INTERNAL_SET:
 947	case RT1011_TEST_OUT_1 ... RT1011_TEST_OUT_3:
 948	case RT1011_DC_CALIB_CLASSD_1 ... RT1011_DC_CALIB_CLASSD_10:
 949	case RT1011_CLASSD_INTERNAL_SET_1 ... RT1011_VREF_LV_1:
 950	case RT1011_SMART_BOOST_TIMING_1 ... RT1011_SMART_BOOST_TIMING_36:
 951	case RT1011_SINE_GEN_REG_1 ... RT1011_SINE_GEN_REG_3:
 952	case RT1011_STP_INITIAL_RS_TEMP ... RT1011_SPK_THERMAL:
 953	case RT1011_STP_OTP_TH ... RT1011_INIT_RECIPROCAL_SYN_15_0:
 954	case RT1011_STP_BQ_1_A1_L_28_16 ... RT1011_STP_BQ_1_H0_R_15_0:
 955	case RT1011_STP_BQ_2_A1_L_28_16 ... RT1011_SEP_RE_REG_15_0:
 956	case RT1011_DRC_CF_PARAMS_1 ... RT1011_DRC_CF_PARAMS_12:
 957	case RT1011_ALC_DRC_HB_INTERNAL_1 ... RT1011_ALC_DRC_HB_INTERNAL_7:
 958	case RT1011_ALC_DRC_BB_INTERNAL_1 ... RT1011_ALC_DRC_BB_INTERNAL_7:
 959	case RT1011_ALC_DRC_POS_INTERNAL_1 ... RT1011_ALC_DRC_POS_INTERNAL_8:
 960	case RT1011_ALC_DRC_POS_INTERNAL_9 ... RT1011_BQ_1_PARAMS_CHECK_5:
 961	case RT1011_BQ_2_PARAMS_CHECK_1 ... RT1011_BQ_2_PARAMS_CHECK_5:
 962	case RT1011_BQ_3_PARAMS_CHECK_1 ... RT1011_BQ_3_PARAMS_CHECK_5:
 963	case RT1011_BQ_4_PARAMS_CHECK_1 ... RT1011_BQ_4_PARAMS_CHECK_5:
 964	case RT1011_BQ_5_PARAMS_CHECK_1 ... RT1011_BQ_5_PARAMS_CHECK_5:
 965	case RT1011_BQ_6_PARAMS_CHECK_1 ... RT1011_BQ_6_PARAMS_CHECK_5:
 966	case RT1011_BQ_7_PARAMS_CHECK_1 ... RT1011_BQ_7_PARAMS_CHECK_5:
 967	case RT1011_BQ_8_PARAMS_CHECK_1 ... RT1011_BQ_8_PARAMS_CHECK_5:
 968	case RT1011_BQ_9_PARAMS_CHECK_1 ... RT1011_BQ_9_PARAMS_CHECK_5:
 969	case RT1011_BQ_10_PARAMS_CHECK_1 ... RT1011_BQ_10_PARAMS_CHECK_5:
 970	case RT1011_IRQ_1 ... RT1011_PART_NUMBER_EFUSE:
 971	case RT1011_EFUSE_CONTROL_1 ... RT1011_EFUSE_READ_R0_3_15_0:
 972		return true;
 973	default:
 974		return false;
 975	}
 976}
 977
 978static const char * const rt1011_din_source_select[] = {
 979	"Left",
 980	"Right",
 981	"Left + Right average",
 982};
 983
 984static SOC_ENUM_SINGLE_DECL(rt1011_din_source_enum, RT1011_CROSS_BQ_SET_1, 5,
 985	rt1011_din_source_select);
 986
 987static const char * const rt1011_tdm_data_out_select[] = {
 988	"TDM_O_LR", "BQ1", "DVOL", "BQ10", "ALC", "DMIX", "ADC_SRC_LR",
 989	"ADC_O_LR", "ADC_MONO", "RSPK_BPF_LR", "DMIX_ADD", "ENVELOPE_FS",
 990	"SEP_O_GAIN", "ALC_BK_GAIN", "STP_V_C", "DMIX_ABST"
 991};
 992
 993static const char * const rt1011_tdm_l_ch_data_select[] = {
 994	"Slot0", "Slot1", "Slot2", "Slot3", "Slot4", "Slot5", "Slot6", "Slot7"
 995};
 996static SOC_ENUM_SINGLE_DECL(rt1011_tdm1_l_dac1_enum, RT1011_TDM1_SET_4, 12,
 997	rt1011_tdm_l_ch_data_select);
 998static SOC_ENUM_SINGLE_DECL(rt1011_tdm2_l_dac1_enum, RT1011_TDM2_SET_4, 12,
 999	rt1011_tdm_l_ch_data_select);
1000
1001static SOC_ENUM_SINGLE_DECL(rt1011_tdm1_adc1_dat_enum,
1002	RT1011_ADCDAT_OUT_SOURCE, 0, rt1011_tdm_data_out_select);
1003static SOC_ENUM_SINGLE_DECL(rt1011_tdm1_adc1_loc_enum, RT1011_TDM1_SET_2, 0,
1004	rt1011_tdm_l_ch_data_select);
1005
1006static const char * const rt1011_adc_data_mode_select[] = {
1007	"Stereo", "Mono"
1008};
1009static SOC_ENUM_SINGLE_DECL(rt1011_adc_dout_mode_enum, RT1011_TDM1_SET_1, 12,
1010	rt1011_adc_data_mode_select);
1011
1012static const char * const rt1011_tdm_adc_data_len_control[] = {
1013	"1CH", "2CH", "3CH", "4CH", "5CH", "6CH", "7CH", "8CH"
1014};
1015static SOC_ENUM_SINGLE_DECL(rt1011_tdm1_dout_len_enum, RT1011_TDM1_SET_2, 13,
1016	rt1011_tdm_adc_data_len_control);
1017static SOC_ENUM_SINGLE_DECL(rt1011_tdm2_dout_len_enum, RT1011_TDM2_SET_2, 13,
1018	rt1011_tdm_adc_data_len_control);
1019
1020static const char * const rt1011_tdm_adc_swap_select[] = {
1021	"L/R", "R/L", "L/L", "R/R"
1022};
1023
1024static SOC_ENUM_SINGLE_DECL(rt1011_tdm_adc1_1_enum, RT1011_TDM1_SET_3, 6,
1025	rt1011_tdm_adc_swap_select);
1026static SOC_ENUM_SINGLE_DECL(rt1011_tdm_adc2_1_enum, RT1011_TDM1_SET_3, 4,
1027	rt1011_tdm_adc_swap_select);
1028
1029static void rt1011_reset(struct regmap *regmap)
1030{
1031	regmap_write(regmap, RT1011_RESET, 0);
1032}
1033
1034static int rt1011_recv_spk_mode_get(struct snd_kcontrol *kcontrol,
1035		struct snd_ctl_elem_value *ucontrol)
1036{
1037	struct snd_soc_component *component =
1038		snd_soc_kcontrol_component(kcontrol);
1039	struct rt1011_priv *rt1011 =
1040		snd_soc_component_get_drvdata(component);
1041
1042	ucontrol->value.integer.value[0] = rt1011->recv_spk_mode;
1043
1044	return 0;
1045}
1046
1047static int rt1011_recv_spk_mode_put(struct snd_kcontrol *kcontrol,
1048		struct snd_ctl_elem_value *ucontrol)
1049{
1050	struct snd_soc_component *component =
1051		snd_soc_kcontrol_component(kcontrol);
1052	struct rt1011_priv *rt1011 =
1053		snd_soc_component_get_drvdata(component);
1054
1055	if (ucontrol->value.integer.value[0] == rt1011->recv_spk_mode)
1056		return 0;
1057
1058	if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
1059		rt1011->recv_spk_mode = ucontrol->value.integer.value[0];
1060
1061		if (rt1011->recv_spk_mode) {
1062
1063			/* 1: recevier mode on */
1064			snd_soc_component_update_bits(component,
1065				RT1011_CLASSD_INTERNAL_SET_3,
1066				RT1011_REG_GAIN_CLASSD_RI_SPK_MASK,
1067				RT1011_REG_GAIN_CLASSD_RI_410K);
1068			snd_soc_component_update_bits(component,
1069				RT1011_CLASSD_INTERNAL_SET_1,
1070				RT1011_RECV_MODE_SPK_MASK,
1071				RT1011_RECV_MODE);
1072		} else {
1073			/* 0: speaker mode on */
1074			snd_soc_component_update_bits(component,
1075				RT1011_CLASSD_INTERNAL_SET_3,
1076				RT1011_REG_GAIN_CLASSD_RI_SPK_MASK,
1077				RT1011_REG_GAIN_CLASSD_RI_72P5K);
1078			snd_soc_component_update_bits(component,
1079				RT1011_CLASSD_INTERNAL_SET_1,
1080				RT1011_RECV_MODE_SPK_MASK,
1081				RT1011_SPK_MODE);
1082		}
1083	}
1084
1085	return 0;
1086}
1087
1088static bool rt1011_validate_bq_drc_coeff(unsigned short reg)
1089{
1090	if ((reg == RT1011_DAC_SET_1) ||
1091		(reg >= RT1011_ADC_SET && reg <= RT1011_ADC_SET_1) ||
1092		(reg == RT1011_ADC_SET_4) || (reg == RT1011_ADC_SET_5) ||
1093		(reg == RT1011_MIXER_1) ||
1094		(reg == RT1011_A_TIMING_1) ||
1095		(reg >= RT1011_POWER_7 && reg <= RT1011_POWER_8) ||
1096		(reg == RT1011_CLASS_D_POS) || (reg == RT1011_ANALOG_CTRL) ||
1097		(reg >= RT1011_SPK_TEMP_PROTECT_0 && reg <= RT1011_SPK_TEMP_PROTECT_6) ||
1098		(reg >= RT1011_SPK_PRO_DC_DET_5 && reg <= RT1011_BAT_GAIN_1) ||
1099		(reg >= RT1011_RT_DRC_CROSS && reg <= RT1011_RT_DRC_POS_8) ||
1100		(reg >= RT1011_CROSS_BQ_SET_1 && reg <= RT1011_BQ_10_A2_15_0) ||
1101		(reg >= RT1011_SMART_BOOST_TIMING_1 && reg <= RT1011_SMART_BOOST_TIMING_36) ||
1102		(reg == RT1011_SINE_GEN_REG_1) ||
1103		(reg >= RT1011_STP_ALPHA_RECIPROCAL_MSB && reg <= RT1011_BQ_6_PARAMS_CHECK_5) ||
1104		(reg >= RT1011_BQ_7_PARAMS_CHECK_1 && reg <= RT1011_BQ_10_PARAMS_CHECK_5))
 
 
 
 
1105		return true;
1106
1107	return false;
1108}
1109
1110static int rt1011_bq_drc_coeff_get(struct snd_kcontrol *kcontrol,
1111					struct snd_ctl_elem_value *ucontrol)
1112{
1113	struct snd_soc_component *component =
1114		snd_soc_kcontrol_component(kcontrol);
1115	struct rt1011_priv *rt1011 =
1116		snd_soc_component_get_drvdata(component);
1117	struct rt1011_bq_drc_params *bq_drc_info;
1118	struct rt1011_bq_drc_params *params =
1119		(struct rt1011_bq_drc_params *)ucontrol->value.integer.value;
1120	unsigned int i, mode_idx = 0;
1121
1122	if (strstr(ucontrol->id.name, "AdvanceMode Initial Set"))
1123		mode_idx = RT1011_ADVMODE_INITIAL_SET;
1124	else if (strstr(ucontrol->id.name, "AdvanceMode SEP BQ Coeff"))
1125		mode_idx = RT1011_ADVMODE_SEP_BQ_COEFF;
1126	else if (strstr(ucontrol->id.name, "AdvanceMode EQ BQ Coeff"))
1127		mode_idx = RT1011_ADVMODE_EQ_BQ_COEFF;
1128	else if (strstr(ucontrol->id.name, "AdvanceMode BQ UI Coeff"))
1129		mode_idx = RT1011_ADVMODE_BQ_UI_COEFF;
1130	else if (strstr(ucontrol->id.name, "AdvanceMode SmartBoost Coeff"))
1131		mode_idx = RT1011_ADVMODE_SMARTBOOST_COEFF;
1132	else
1133		return -EINVAL;
1134
1135	pr_info("%s, id.name=%s, mode_idx=%d\n", __func__,
1136		ucontrol->id.name, mode_idx);
1137	bq_drc_info = rt1011->bq_drc_params[mode_idx];
1138
1139	for (i = 0; i < RT1011_BQ_DRC_NUM; i++) {
1140		params[i].reg = bq_drc_info[i].reg;
1141		params[i].val = bq_drc_info[i].val;
1142	}
1143
1144	return 0;
1145}
1146
1147static int rt1011_bq_drc_coeff_put(struct snd_kcontrol *kcontrol,
1148					struct snd_ctl_elem_value *ucontrol)
1149{
1150	struct snd_soc_component *component =
1151		snd_soc_kcontrol_component(kcontrol);
1152	struct rt1011_priv *rt1011 =
1153		snd_soc_component_get_drvdata(component);
1154	struct rt1011_bq_drc_params *bq_drc_info;
1155	struct rt1011_bq_drc_params *params =
1156		(struct rt1011_bq_drc_params *)ucontrol->value.integer.value;
1157	unsigned int i, mode_idx = 0;
1158
 
 
 
1159	if (strstr(ucontrol->id.name, "AdvanceMode Initial Set"))
1160		mode_idx = RT1011_ADVMODE_INITIAL_SET;
1161	else if (strstr(ucontrol->id.name, "AdvanceMode SEP BQ Coeff"))
1162		mode_idx = RT1011_ADVMODE_SEP_BQ_COEFF;
1163	else if (strstr(ucontrol->id.name, "AdvanceMode EQ BQ Coeff"))
1164		mode_idx = RT1011_ADVMODE_EQ_BQ_COEFF;
1165	else if (strstr(ucontrol->id.name, "AdvanceMode BQ UI Coeff"))
1166		mode_idx = RT1011_ADVMODE_BQ_UI_COEFF;
1167	else if (strstr(ucontrol->id.name, "AdvanceMode SmartBoost Coeff"))
1168		mode_idx = RT1011_ADVMODE_SMARTBOOST_COEFF;
1169	else
1170		return -EINVAL;
1171
1172	bq_drc_info = rt1011->bq_drc_params[mode_idx];
1173	memset(bq_drc_info, 0,
1174		sizeof(struct rt1011_bq_drc_params) * RT1011_BQ_DRC_NUM);
1175
1176	pr_info("%s, id.name=%s, mode_idx=%d\n", __func__,
1177		ucontrol->id.name, mode_idx);
1178	for (i = 0; i < RT1011_BQ_DRC_NUM; i++) {
1179		bq_drc_info[i].reg = params[i].reg;
1180		bq_drc_info[i].val = params[i].val;
1181	}
1182
1183	for (i = 0; i < RT1011_BQ_DRC_NUM; i++) {
1184		if (bq_drc_info[i].reg == 0)
1185			break;
1186		else if (rt1011_validate_bq_drc_coeff(bq_drc_info[i].reg)) {
1187			snd_soc_component_write(component, bq_drc_info[i].reg,
1188					bq_drc_info[i].val);
1189		}
1190	}
1191
1192	return 0;
1193}
1194
1195static int rt1011_bq_drc_info(struct snd_kcontrol *kcontrol,
1196			 struct snd_ctl_elem_info *uinfo)
1197{
1198	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1199	uinfo->count = 128;
1200	uinfo->value.integer.max = 0x17ffffff;
1201
1202	return 0;
1203}
1204
1205#define RT1011_BQ_DRC(xname) \
1206{	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1207	.info = rt1011_bq_drc_info, \
1208	.get = rt1011_bq_drc_coeff_get, \
1209	.put = rt1011_bq_drc_coeff_put \
1210}
1211
1212static int rt1011_r0_cali_get(struct snd_kcontrol *kcontrol,
1213		struct snd_ctl_elem_value *ucontrol)
1214{
1215	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1216	struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
1217
1218	ucontrol->value.integer.value[0] = rt1011->cali_done;
1219
1220	return 0;
1221}
1222
1223static int rt1011_r0_cali_put(struct snd_kcontrol *kcontrol,
1224		struct snd_ctl_elem_value *ucontrol)
1225{
1226	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1227	struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
1228
 
 
 
1229	rt1011->cali_done = 0;
1230	if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF &&
1231		ucontrol->value.integer.value[0])
1232		rt1011_calibrate(rt1011, 1);
1233
1234	return 0;
1235}
1236
1237static int rt1011_r0_load(struct rt1011_priv *rt1011)
1238{
1239	if (!rt1011->r0_reg)
1240		return -EINVAL;
1241
1242	/* write R0 to register */
1243	regmap_write(rt1011->regmap, RT1011_INIT_RECIPROCAL_REG_24_16,
1244		((rt1011->r0_reg>>16) & 0x1ff));
1245	regmap_write(rt1011->regmap, RT1011_INIT_RECIPROCAL_REG_15_0,
1246		(rt1011->r0_reg & 0xffff));
1247	regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_4, 0x4080);
1248
1249	return 0;
1250}
1251
1252static int rt1011_r0_load_mode_get(struct snd_kcontrol *kcontrol,
1253		struct snd_ctl_elem_value *ucontrol)
1254{
1255	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1256	struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
1257
1258	ucontrol->value.integer.value[0] = rt1011->r0_reg;
1259
1260	return 0;
1261}
1262
1263static int rt1011_r0_load_mode_put(struct snd_kcontrol *kcontrol,
1264		struct snd_ctl_elem_value *ucontrol)
1265{
1266	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1267	struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
1268	struct device *dev;
1269	unsigned int r0_integer, r0_factor, format;
1270
1271	if (ucontrol->value.integer.value[0] == rt1011->r0_reg)
1272		return 0;
1273
 
 
 
1274	if (ucontrol->value.integer.value[0] == 0)
1275		return -EINVAL;
1276
1277	dev = regmap_get_device(rt1011->regmap);
1278	if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
1279		rt1011->r0_reg = ucontrol->value.integer.value[0];
1280
1281		format = 2147483648U; /* 2^24 * 128 */
1282		r0_integer = format / rt1011->r0_reg / 128;
1283		r0_factor = ((format / rt1011->r0_reg * 100) / 128)
1284						- (r0_integer * 100);
1285		dev_info(dev, "New r0 resistance about %d.%02d ohm, reg=0x%X\n",
1286			r0_integer, r0_factor, rt1011->r0_reg);
1287
1288		if (rt1011->r0_reg)
1289			rt1011_r0_load(rt1011);
1290	}
1291
1292	return 0;
1293}
1294
1295static int rt1011_r0_load_info(struct snd_kcontrol *kcontrol,
1296			 struct snd_ctl_elem_info *uinfo)
1297{
1298	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1299	uinfo->count = 1;
1300	uinfo->value.integer.max = 0x1ffffff;
1301
1302	return 0;
1303}
1304
1305#define RT1011_R0_LOAD(xname) \
1306{	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1307	.info = rt1011_r0_load_info, \
1308	.get = rt1011_r0_load_mode_get, \
1309	.put = rt1011_r0_load_mode_put \
1310}
1311
1312static const char * const rt1011_i2s_ref[] = {
1313	"None", "Left Channel", "Right Channel"
1314};
1315
1316static SOC_ENUM_SINGLE_DECL(rt1011_i2s_ref_enum, 0, 0,
1317	rt1011_i2s_ref);
1318
1319static int rt1011_i2s_ref_put(struct snd_kcontrol *kcontrol,
1320		struct snd_ctl_elem_value *ucontrol)
1321{
1322	struct snd_soc_component *component =
1323		snd_soc_kcontrol_component(kcontrol);
1324	struct rt1011_priv *rt1011 =
1325		snd_soc_component_get_drvdata(component);
1326
1327	rt1011->i2s_ref = ucontrol->value.enumerated.item[0];
1328	switch (rt1011->i2s_ref) {
1329	case RT1011_I2S_REF_LEFT_CH:
1330		regmap_write(rt1011->regmap, RT1011_TDM_TOTAL_SET, 0x0240);
1331		regmap_write(rt1011->regmap, RT1011_TDM1_SET_2, 0x8);
1332		regmap_write(rt1011->regmap, RT1011_TDM1_SET_1, 0x1022);
1333		regmap_write(rt1011->regmap, RT1011_ADCDAT_OUT_SOURCE, 0x4);
1334		break;
1335	case RT1011_I2S_REF_RIGHT_CH:
1336		regmap_write(rt1011->regmap, RT1011_TDM_TOTAL_SET, 0x0240);
1337		regmap_write(rt1011->regmap, RT1011_TDM1_SET_2, 0x8);
1338		regmap_write(rt1011->regmap, RT1011_TDM1_SET_1, 0x10a2);
1339		regmap_write(rt1011->regmap, RT1011_ADCDAT_OUT_SOURCE, 0x4);
1340		break;
1341	default:
1342		dev_info(component->dev, "I2S Reference: Do nothing\n");
1343	}
1344
1345	return 0;
1346}
1347
1348static int rt1011_i2s_ref_get(struct snd_kcontrol *kcontrol,
1349		struct snd_ctl_elem_value *ucontrol)
1350{
1351	struct snd_soc_component *component =
1352		snd_soc_kcontrol_component(kcontrol);
1353	struct rt1011_priv *rt1011 =
1354		snd_soc_component_get_drvdata(component);
1355
1356	ucontrol->value.enumerated.item[0] = rt1011->i2s_ref;
1357
1358	return 0;
1359}
1360
1361static const struct snd_kcontrol_new rt1011_snd_controls[] = {
1362	/* I2S Data In Selection */
1363	SOC_ENUM("DIN Source", rt1011_din_source_enum),
1364
1365	/* TDM Data In Selection */
1366	SOC_ENUM("TDM1 DIN Source", rt1011_tdm1_l_dac1_enum),
1367	SOC_ENUM("TDM2 DIN Source", rt1011_tdm2_l_dac1_enum),
1368
1369	/* TDM1 Data Out Selection */
1370	SOC_ENUM("TDM1 DOUT Source", rt1011_tdm1_adc1_dat_enum),
1371	SOC_ENUM("TDM1 DOUT Location", rt1011_tdm1_adc1_loc_enum),
1372	SOC_ENUM("TDM1 ADC1DAT Swap Select", rt1011_tdm_adc1_1_enum),
1373	SOC_ENUM("TDM1 ADC2DAT Swap Select", rt1011_tdm_adc2_1_enum),
1374
1375	/* Data Out Mode */
1376	SOC_ENUM("I2S ADC DOUT Mode", rt1011_adc_dout_mode_enum),
1377	SOC_ENUM("TDM1 DOUT Length", rt1011_tdm1_dout_len_enum),
1378	SOC_ENUM("TDM2 DOUT Length", rt1011_tdm2_dout_len_enum),
1379
1380	/* Speaker/Receiver Mode */
1381	SOC_SINGLE_EXT("RECV SPK Mode", SND_SOC_NOPM, 0, 1, 0,
1382		rt1011_recv_spk_mode_get, rt1011_recv_spk_mode_put),
1383
1384	/* BiQuad/DRC/SmartBoost Settings */
1385	RT1011_BQ_DRC("AdvanceMode Initial Set"),
1386	RT1011_BQ_DRC("AdvanceMode SEP BQ Coeff"),
1387	RT1011_BQ_DRC("AdvanceMode EQ BQ Coeff"),
1388	RT1011_BQ_DRC("AdvanceMode BQ UI Coeff"),
1389	RT1011_BQ_DRC("AdvanceMode SmartBoost Coeff"),
1390
1391	/* R0 */
1392	SOC_SINGLE_EXT("R0 Calibration", SND_SOC_NOPM, 0, 1, 0,
1393		rt1011_r0_cali_get, rt1011_r0_cali_put),
1394	RT1011_R0_LOAD("R0 Load Mode"),
1395
1396	/* R0 temperature */
1397	SOC_SINGLE("R0 Temperature", RT1011_STP_INITIAL_RESISTANCE_TEMP,
1398		2, 255, 0),
1399	/* I2S Reference */
1400	SOC_ENUM_EXT("I2S Reference", rt1011_i2s_ref_enum,
1401		rt1011_i2s_ref_get, rt1011_i2s_ref_put),
1402};
1403
1404static int rt1011_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
1405			 struct snd_soc_dapm_widget *sink)
1406{
1407	struct snd_soc_component *component =
1408		snd_soc_dapm_to_component(source->dapm);
1409	struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
1410
1411	if (rt1011->sysclk_src == RT1011_FS_SYS_PRE_S_PLL1)
1412		return 1;
1413	else
1414		return 0;
1415}
1416
1417static int rt1011_dac_event(struct snd_soc_dapm_widget *w,
1418	struct snd_kcontrol *kcontrol, int event)
1419{
1420	struct snd_soc_component *component =
1421		snd_soc_dapm_to_component(w->dapm);
1422
1423	switch (event) {
1424	case SND_SOC_DAPM_POST_PMU:
1425		snd_soc_component_update_bits(component,
1426			RT1011_SPK_TEMP_PROTECT_0,
1427			RT1011_STP_EN_MASK | RT1011_STP_RS_CLB_EN_MASK,
1428			RT1011_STP_EN | RT1011_STP_RS_CLB_EN);
1429		snd_soc_component_update_bits(component, RT1011_POWER_9,
1430			RT1011_POW_MNL_SDB_MASK, RT1011_POW_MNL_SDB);
1431		msleep(50);
1432		snd_soc_component_update_bits(component,
1433			RT1011_CLASSD_INTERNAL_SET_1,
1434			RT1011_DRIVER_READY_SPK, RT1011_DRIVER_READY_SPK);
1435		break;
1436	case SND_SOC_DAPM_PRE_PMD:
1437		snd_soc_component_update_bits(component, RT1011_POWER_9,
1438			RT1011_POW_MNL_SDB_MASK, 0);
1439		snd_soc_component_update_bits(component,
1440			RT1011_SPK_TEMP_PROTECT_0,
1441			RT1011_STP_EN_MASK | RT1011_STP_RS_CLB_EN_MASK, 0);
1442		msleep(200);
1443		snd_soc_component_update_bits(component,
1444			RT1011_CLASSD_INTERNAL_SET_1,
1445			RT1011_DRIVER_READY_SPK, 0);
1446		break;
1447
1448	default:
1449		return 0;
1450	}
1451
1452	return 0;
1453}
1454
1455
1456static const struct snd_soc_dapm_widget rt1011_dapm_widgets[] = {
1457	SND_SOC_DAPM_SUPPLY("LDO2", RT1011_POWER_1,
1458		RT1011_POW_LDO2_BIT, 0, NULL, 0),
1459	SND_SOC_DAPM_SUPPLY("ISENSE SPK", RT1011_POWER_1,
1460		RT1011_POW_ISENSE_SPK_BIT, 0, NULL, 0),
1461	SND_SOC_DAPM_SUPPLY("VSENSE SPK", RT1011_POWER_1,
1462		RT1011_POW_VSENSE_SPK_BIT, 0, NULL, 0),
1463
1464	SND_SOC_DAPM_SUPPLY("PLL", RT1011_POWER_2,
1465		RT1011_PLLEN_BIT, 0, NULL, 0),
1466	SND_SOC_DAPM_SUPPLY("BG", RT1011_POWER_2,
1467		RT1011_POW_BG_BIT, 0, NULL, 0),
1468	SND_SOC_DAPM_SUPPLY("BG MBIAS", RT1011_POWER_2,
1469		RT1011_POW_BG_MBIAS_LV_BIT, 0, NULL, 0),
1470
1471	SND_SOC_DAPM_SUPPLY("DET VBAT", RT1011_POWER_3,
1472		RT1011_POW_DET_VBAT_BIT, 0, NULL, 0),
1473	SND_SOC_DAPM_SUPPLY("MBIAS", RT1011_POWER_3,
1474		RT1011_POW_MBIAS_LV_BIT, 0, NULL, 0),
1475	SND_SOC_DAPM_SUPPLY("ADC I", RT1011_POWER_3,
1476		RT1011_POW_ADC_I_BIT, 0, NULL, 0),
1477	SND_SOC_DAPM_SUPPLY("ADC V", RT1011_POWER_3,
1478		RT1011_POW_ADC_V_BIT, 0, NULL, 0),
1479	SND_SOC_DAPM_SUPPLY("ADC T", RT1011_POWER_3,
1480		RT1011_POW_ADC_T_BIT, 0, NULL, 0),
1481	SND_SOC_DAPM_SUPPLY("DITHER ADC T", RT1011_POWER_3,
1482		RT1011_POWD_ADC_T_BIT, 0, NULL, 0),
1483	SND_SOC_DAPM_SUPPLY("MIX I", RT1011_POWER_3,
1484		RT1011_POW_MIX_I_BIT, 0, NULL, 0),
1485	SND_SOC_DAPM_SUPPLY("MIX V", RT1011_POWER_3,
1486		RT1011_POW_MIX_V_BIT, 0, NULL, 0),
1487	SND_SOC_DAPM_SUPPLY("SUM I", RT1011_POWER_3,
1488		RT1011_POW_SUM_I_BIT, 0, NULL, 0),
1489	SND_SOC_DAPM_SUPPLY("SUM V", RT1011_POWER_3,
1490		RT1011_POW_SUM_V_BIT, 0, NULL, 0),
1491	SND_SOC_DAPM_SUPPLY("MIX T", RT1011_POWER_3,
1492		RT1011_POW_MIX_T_BIT, 0, NULL, 0),
1493	SND_SOC_DAPM_SUPPLY("VREF", RT1011_POWER_3,
1494		RT1011_POW_VREF_LV_BIT, 0, NULL, 0),
1495
1496	SND_SOC_DAPM_SUPPLY("BOOST SWR", RT1011_POWER_4,
1497		RT1011_POW_EN_SWR_BIT, 0, NULL, 0),
1498	SND_SOC_DAPM_SUPPLY("BGOK SWR", RT1011_POWER_4,
1499		RT1011_POW_EN_PASS_BGOK_SWR_BIT, 0, NULL, 0),
1500	SND_SOC_DAPM_SUPPLY("VPOK SWR", RT1011_POWER_4,
1501		RT1011_POW_EN_PASS_VPOK_SWR_BIT, 0, NULL, 0),
1502
1503	SND_SOC_DAPM_SUPPLY("TEMP REG", RT1011_A_TEMP_SEN,
1504		RT1011_POW_TEMP_REG_BIT, 0, NULL, 0),
1505
1506	/* Audio Interface */
1507	SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
1508	/* Digital Interface */
1509	SND_SOC_DAPM_SUPPLY("DAC Power", RT1011_POWER_1,
1510		RT1011_POW_DAC_BIT, 0, NULL, 0),
1511	SND_SOC_DAPM_SUPPLY("CLK12M", RT1011_POWER_1,
1512		RT1011_POW_CLK12M_BIT, 0, NULL, 0),
1513	SND_SOC_DAPM_DAC_E("DAC", NULL, RT1011_DAC_SET_3,
1514		RT1011_DA_MUTE_EN_SFT, 1, rt1011_dac_event,
1515		SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
1516
1517	/* Output Lines */
1518	SND_SOC_DAPM_OUTPUT("SPO"),
1519};
1520
1521static const struct snd_soc_dapm_route rt1011_dapm_routes[] = {
1522
1523	{ "DAC", NULL, "AIF1RX" },
1524	{ "DAC", NULL, "DAC Power" },
1525	{ "DAC", NULL, "LDO2" },
1526	{ "DAC", NULL, "ISENSE SPK" },
1527	{ "DAC", NULL, "VSENSE SPK" },
1528	{ "DAC", NULL, "CLK12M" },
1529
1530	{ "DAC", NULL, "PLL", rt1011_is_sys_clk_from_pll },
1531	{ "DAC", NULL, "BG" },
1532	{ "DAC", NULL, "BG MBIAS" },
1533
1534	{ "DAC", NULL, "BOOST SWR" },
1535	{ "DAC", NULL, "BGOK SWR" },
1536	{ "DAC", NULL, "VPOK SWR" },
1537
1538	{ "DAC", NULL, "DET VBAT" },
1539	{ "DAC", NULL, "MBIAS" },
1540	{ "DAC", NULL, "VREF" },
1541	{ "DAC", NULL, "ADC I" },
1542	{ "DAC", NULL, "ADC V" },
1543	{ "DAC", NULL, "ADC T" },
1544	{ "DAC", NULL, "DITHER ADC T" },
1545	{ "DAC", NULL, "MIX I" },
1546	{ "DAC", NULL, "MIX V" },
1547	{ "DAC", NULL, "SUM I" },
1548	{ "DAC", NULL, "SUM V" },
1549	{ "DAC", NULL, "MIX T" },
1550
1551	{ "DAC", NULL, "TEMP REG" },
1552
1553	{ "SPO", NULL, "DAC" },
1554};
1555
1556static int rt1011_get_clk_info(int sclk, int rate)
1557{
1558	int i;
1559	static const int pd[] = {1, 2, 3, 4, 6, 8, 12, 16};
1560
1561	if (sclk <= 0 || rate <= 0)
1562		return -EINVAL;
1563
1564	rate = rate << 8;
1565	for (i = 0; i < ARRAY_SIZE(pd); i++)
1566		if (sclk == rate * pd[i])
1567			return i;
1568
1569	return -EINVAL;
1570}
1571
1572static int rt1011_hw_params(struct snd_pcm_substream *substream,
1573	struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1574{
1575	struct snd_soc_component *component = dai->component;
1576	struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
1577	unsigned int val_len = 0, ch_len = 0, val_clk, mask_clk;
1578	int pre_div, bclk_ms, frame_size;
1579
1580	rt1011->lrck = params_rate(params);
1581	pre_div = rt1011_get_clk_info(rt1011->sysclk, rt1011->lrck);
1582	if (pre_div < 0) {
1583		dev_warn(component->dev, "Force using PLL ");
1584		snd_soc_dai_set_pll(dai, 0, RT1011_PLL1_S_BCLK,
1585			rt1011->lrck * 64, rt1011->lrck * 256);
1586		snd_soc_dai_set_sysclk(dai, RT1011_FS_SYS_PRE_S_PLL1,
1587			rt1011->lrck * 256, SND_SOC_CLOCK_IN);
1588		pre_div = 0;
1589	}
1590	frame_size = snd_soc_params_to_frame_size(params);
1591	if (frame_size < 0) {
1592		dev_err(component->dev, "Unsupported frame size: %d\n",
1593			frame_size);
1594		return -EINVAL;
1595	}
1596
1597	bclk_ms = frame_size > 32;
1598	rt1011->bclk = rt1011->lrck * (32 << bclk_ms);
1599
1600	dev_dbg(component->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
1601				bclk_ms, pre_div, dai->id);
1602
1603	dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
1604				rt1011->lrck, pre_div, dai->id);
1605
1606	switch (params_width(params)) {
1607	case 16:
1608		val_len |= RT1011_I2S_TX_DL_16B;
1609		val_len |= RT1011_I2S_RX_DL_16B;
1610		ch_len |= RT1011_I2S_CH_TX_LEN_16B;
1611		ch_len |= RT1011_I2S_CH_RX_LEN_16B;
1612		break;
1613	case 20:
1614		val_len |= RT1011_I2S_TX_DL_20B;
1615		val_len |= RT1011_I2S_RX_DL_20B;
1616		ch_len |= RT1011_I2S_CH_TX_LEN_20B;
1617		ch_len |= RT1011_I2S_CH_RX_LEN_20B;
1618		break;
1619	case 24:
1620		val_len |= RT1011_I2S_TX_DL_24B;
1621		val_len |= RT1011_I2S_RX_DL_24B;
1622		ch_len |= RT1011_I2S_CH_TX_LEN_24B;
1623		ch_len |= RT1011_I2S_CH_RX_LEN_24B;
1624		break;
1625	case 32:
1626		val_len |= RT1011_I2S_TX_DL_32B;
1627		val_len |= RT1011_I2S_RX_DL_32B;
1628		ch_len |= RT1011_I2S_CH_TX_LEN_32B;
1629		ch_len |= RT1011_I2S_CH_RX_LEN_32B;
1630		break;
1631	case 8:
1632		val_len |= RT1011_I2S_TX_DL_8B;
1633		val_len |= RT1011_I2S_RX_DL_8B;
1634		ch_len |= RT1011_I2S_CH_TX_LEN_8B;
1635		ch_len |= RT1011_I2S_CH_RX_LEN_8B;
1636		break;
1637	default:
1638		return -EINVAL;
1639	}
1640
1641	switch (dai->id) {
1642	case RT1011_AIF1:
1643		mask_clk = RT1011_FS_SYS_DIV_MASK;
1644		val_clk = pre_div << RT1011_FS_SYS_DIV_SFT;
1645		snd_soc_component_update_bits(component, RT1011_TDM_TOTAL_SET,
1646			RT1011_I2S_TX_DL_MASK | RT1011_I2S_RX_DL_MASK,
1647			val_len);
1648		snd_soc_component_update_bits(component, RT1011_TDM1_SET_1,
1649			RT1011_I2S_CH_TX_LEN_MASK |
1650			RT1011_I2S_CH_RX_LEN_MASK,
1651			ch_len);
1652		break;
1653	default:
1654		dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
1655		return -EINVAL;
1656	}
1657
1658	snd_soc_component_update_bits(component,
1659		RT1011_CLK_2, mask_clk, val_clk);
1660
1661	return 0;
1662}
1663
1664static int rt1011_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1665{
1666	struct snd_soc_component *component = dai->component;
1667	struct snd_soc_dapm_context *dapm =
1668		snd_soc_component_get_dapm(component);
1669	unsigned int reg_val = 0, reg_bclk_inv = 0;
1670	int ret = 0;
1671
1672	snd_soc_dapm_mutex_lock(dapm);
1673	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1674	case SND_SOC_DAIFMT_CBS_CFS:
1675		reg_val |= RT1011_I2S_TDM_MS_S;
1676		break;
1677	default:
1678		ret = -EINVAL;
1679		goto _set_fmt_err_;
1680	}
1681
1682	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1683	case SND_SOC_DAIFMT_NB_NF:
1684		break;
1685	case SND_SOC_DAIFMT_IB_NF:
1686		reg_bclk_inv |= RT1011_TDM_INV_BCLK;
1687		break;
1688	default:
1689		ret = -EINVAL;
1690		goto _set_fmt_err_;
1691	}
1692
1693	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1694	case SND_SOC_DAIFMT_I2S:
1695		break;
1696	case SND_SOC_DAIFMT_LEFT_J:
1697		reg_val |= RT1011_I2S_TDM_DF_LEFT;
1698		break;
1699	case SND_SOC_DAIFMT_DSP_A:
1700		reg_val |= RT1011_I2S_TDM_DF_PCM_A;
1701		break;
1702	case SND_SOC_DAIFMT_DSP_B:
1703		reg_val |= RT1011_I2S_TDM_DF_PCM_B;
1704		break;
1705	default:
1706		ret = -EINVAL;
1707		goto _set_fmt_err_;
1708	}
1709
1710	switch (dai->id) {
1711	case RT1011_AIF1:
1712		snd_soc_component_update_bits(component, RT1011_TDM_TOTAL_SET,
1713			RT1011_I2S_TDM_MS_MASK | RT1011_I2S_TDM_DF_MASK,
1714			reg_val);
1715		snd_soc_component_update_bits(component, RT1011_TDM1_SET_1,
1716			RT1011_TDM_INV_BCLK_MASK, reg_bclk_inv);
1717		snd_soc_component_update_bits(component, RT1011_TDM2_SET_1,
1718			RT1011_TDM_INV_BCLK_MASK, reg_bclk_inv);
1719		break;
1720	default:
1721		dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
1722		ret = -EINVAL;
1723	}
1724
1725_set_fmt_err_:
1726	snd_soc_dapm_mutex_unlock(dapm);
1727	return ret;
1728}
1729
1730static int rt1011_set_component_sysclk(struct snd_soc_component *component,
1731		int clk_id, int source, unsigned int freq, int dir)
1732{
1733	struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
1734	unsigned int reg_val = 0;
1735
1736	if (freq == rt1011->sysclk && clk_id == rt1011->sysclk_src)
1737		return 0;
1738
1739	/* disable MCLK detect in default */
1740	snd_soc_component_update_bits(component, RT1011_CLK_DET,
1741			RT1011_EN_MCLK_DET_MASK, 0);
1742
1743	switch (clk_id) {
1744	case RT1011_FS_SYS_PRE_S_MCLK:
1745		reg_val |= RT1011_FS_SYS_PRE_MCLK;
1746		snd_soc_component_update_bits(component, RT1011_CLK_DET,
1747			RT1011_EN_MCLK_DET_MASK, RT1011_EN_MCLK_DET);
1748		break;
1749	case RT1011_FS_SYS_PRE_S_BCLK:
1750		reg_val |= RT1011_FS_SYS_PRE_BCLK;
1751		break;
1752	case RT1011_FS_SYS_PRE_S_PLL1:
1753		reg_val |= RT1011_FS_SYS_PRE_PLL1;
1754		break;
1755	case RT1011_FS_SYS_PRE_S_RCCLK:
1756		reg_val |= RT1011_FS_SYS_PRE_RCCLK;
1757		break;
1758	default:
1759		dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
1760		return -EINVAL;
1761	}
1762	snd_soc_component_update_bits(component, RT1011_CLK_2,
1763		RT1011_FS_SYS_PRE_MASK, reg_val);
1764	rt1011->sysclk = freq;
1765	rt1011->sysclk_src = clk_id;
1766
1767	dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
1768		freq, clk_id);
1769
1770	return 0;
1771}
1772
1773static int rt1011_set_component_pll(struct snd_soc_component *component,
1774		int pll_id, int source, unsigned int freq_in,
1775		unsigned int freq_out)
1776{
1777	struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
1778	struct rl6231_pll_code pll_code;
1779	int ret;
1780
1781	if (source == rt1011->pll_src && freq_in == rt1011->pll_in &&
1782	    freq_out == rt1011->pll_out)
1783		return 0;
1784
1785	if (!freq_in || !freq_out) {
1786		dev_dbg(component->dev, "PLL disabled\n");
1787
1788		rt1011->pll_in = 0;
1789		rt1011->pll_out = 0;
1790		snd_soc_component_update_bits(component, RT1011_CLK_2,
1791			RT1011_FS_SYS_PRE_MASK, RT1011_FS_SYS_PRE_BCLK);
1792		return 0;
1793	}
1794
1795	switch (source) {
1796	case RT1011_PLL2_S_MCLK:
1797		snd_soc_component_update_bits(component, RT1011_CLK_2,
1798			RT1011_PLL2_SRC_MASK, RT1011_PLL2_SRC_MCLK);
1799		snd_soc_component_update_bits(component, RT1011_CLK_2,
1800			RT1011_PLL1_SRC_MASK, RT1011_PLL1_SRC_PLL2);
1801		snd_soc_component_update_bits(component, RT1011_CLK_DET,
1802			RT1011_EN_MCLK_DET_MASK, RT1011_EN_MCLK_DET);
1803		break;
1804	case RT1011_PLL1_S_BCLK:
1805		snd_soc_component_update_bits(component, RT1011_CLK_2,
1806				RT1011_PLL1_SRC_MASK, RT1011_PLL1_SRC_BCLK);
1807		break;
1808	case RT1011_PLL2_S_RCCLK:
1809		snd_soc_component_update_bits(component, RT1011_CLK_2,
1810			RT1011_PLL2_SRC_MASK, RT1011_PLL2_SRC_RCCLK);
1811		snd_soc_component_update_bits(component, RT1011_CLK_2,
1812			RT1011_PLL1_SRC_MASK, RT1011_PLL1_SRC_PLL2);
1813		break;
1814	default:
1815		dev_err(component->dev, "Unknown PLL Source %d\n", source);
1816		return -EINVAL;
1817	}
1818
1819	ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
1820	if (ret < 0) {
1821		dev_err(component->dev, "Unsupported input clock %d\n",
1822			freq_in);
1823		return ret;
1824	}
1825
1826	dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
1827		pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
1828		pll_code.n_code, pll_code.k_code);
1829
1830	snd_soc_component_write(component, RT1011_PLL_1,
1831		((pll_code.m_bp ? 0 : pll_code.m_code) << RT1011_PLL1_QM_SFT) |
1832		(pll_code.m_bp << RT1011_PLL1_BPM_SFT) |
1833		pll_code.n_code);
1834	snd_soc_component_write(component, RT1011_PLL_2,
1835		pll_code.k_code);
1836
1837	rt1011->pll_in = freq_in;
1838	rt1011->pll_out = freq_out;
1839	rt1011->pll_src = source;
1840
1841	return 0;
1842}
1843
1844static int rt1011_set_tdm_slot(struct snd_soc_dai *dai,
1845	unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
1846{
1847	struct snd_soc_component *component = dai->component;
1848	struct snd_soc_dapm_context *dapm =
1849		snd_soc_component_get_dapm(component);
1850	unsigned int val = 0, tdm_en = 0, rx_slotnum, tx_slotnum;
1851	int ret = 0, first_bit, last_bit;
1852
1853	snd_soc_dapm_mutex_lock(dapm);
1854	if (rx_mask || tx_mask)
1855		tdm_en = RT1011_TDM_I2S_DOCK_EN_1;
1856
1857	switch (slots) {
1858	case 4:
1859		val |= RT1011_I2S_TX_4CH;
1860		val |= RT1011_I2S_RX_4CH;
1861		break;
1862	case 6:
1863		val |= RT1011_I2S_TX_6CH;
1864		val |= RT1011_I2S_RX_6CH;
1865		break;
1866	case 8:
1867		val |= RT1011_I2S_TX_8CH;
1868		val |= RT1011_I2S_RX_8CH;
1869		break;
1870	case 2:
1871		break;
1872	default:
1873		ret = -EINVAL;
1874		goto _set_tdm_err_;
1875	}
1876
1877	switch (slot_width) {
1878	case 20:
1879		val |= RT1011_I2S_CH_TX_LEN_20B;
1880		val |= RT1011_I2S_CH_RX_LEN_20B;
1881		break;
1882	case 24:
1883		val |= RT1011_I2S_CH_TX_LEN_24B;
1884		val |= RT1011_I2S_CH_RX_LEN_24B;
1885		break;
1886	case 32:
1887		val |= RT1011_I2S_CH_TX_LEN_32B;
1888		val |= RT1011_I2S_CH_RX_LEN_32B;
1889		break;
1890	case 16:
1891		break;
1892	default:
1893		ret = -EINVAL;
1894		goto _set_tdm_err_;
1895	}
1896
1897	/* Rx slot configuration */
1898	rx_slotnum = hweight_long(rx_mask);
1899	if (rx_slotnum > 1 || !rx_slotnum) {
1900		ret = -EINVAL;
1901		dev_err(component->dev, "too many rx slots or zero slot\n");
1902		goto _set_tdm_err_;
1903	}
1904
1905	first_bit = __ffs(rx_mask);
1906	switch (first_bit) {
1907	case 0:
1908	case 2:
1909	case 4:
1910	case 6:
1911		snd_soc_component_update_bits(component,
1912			RT1011_CROSS_BQ_SET_1, RT1011_MONO_LR_SEL_MASK,
1913			RT1011_MONO_L_CHANNEL);
1914		snd_soc_component_update_bits(component,
1915			RT1011_TDM1_SET_4,
1916			RT1011_TDM_I2S_TX_L_DAC1_1_MASK |
1917			RT1011_TDM_I2S_TX_R_DAC1_1_MASK,
1918			(first_bit << RT1011_TDM_I2S_TX_L_DAC1_1_SFT) |
1919			((first_bit+1) << RT1011_TDM_I2S_TX_R_DAC1_1_SFT));
1920		break;
1921	case 1:
1922	case 3:
1923	case 5:
1924	case 7:
1925		snd_soc_component_update_bits(component,
1926			RT1011_CROSS_BQ_SET_1, RT1011_MONO_LR_SEL_MASK,
1927			RT1011_MONO_R_CHANNEL);
1928		snd_soc_component_update_bits(component,
1929			RT1011_TDM1_SET_4,
1930			RT1011_TDM_I2S_TX_L_DAC1_1_MASK |
1931			RT1011_TDM_I2S_TX_R_DAC1_1_MASK,
1932			((first_bit-1) << RT1011_TDM_I2S_TX_L_DAC1_1_SFT) |
1933			(first_bit << RT1011_TDM_I2S_TX_R_DAC1_1_SFT));
1934		break;
1935	default:
1936		ret = -EINVAL;
1937		goto _set_tdm_err_;
1938	}
1939
1940	/* Tx slot configuration */
1941	tx_slotnum = hweight_long(tx_mask);
1942	if (tx_slotnum > 2 || !tx_slotnum) {
1943		ret = -EINVAL;
1944		dev_err(component->dev, "too many tx slots or zero slot\n");
1945		goto _set_tdm_err_;
1946	}
1947
1948	first_bit = __ffs(tx_mask);
1949	last_bit = __fls(tx_mask);
1950	if (last_bit - first_bit > 1) {
1951		ret = -EINVAL;
1952		dev_err(component->dev, "tx slot location error\n");
1953		goto _set_tdm_err_;
1954	}
1955
1956	if (tx_slotnum == 1) {
1957		snd_soc_component_update_bits(component, RT1011_TDM1_SET_2,
1958			RT1011_TDM_I2S_DOCK_ADCDAT_LEN_1_MASK |
1959			RT1011_TDM_ADCDAT1_DATA_LOCATION, first_bit);
1960		switch (first_bit) {
1961		case 1:
1962			snd_soc_component_update_bits(component,
1963				RT1011_TDM1_SET_3,
1964				RT1011_TDM_I2S_RX_ADC1_1_MASK,
1965				RT1011_TDM_I2S_RX_ADC1_1_LL);
1966			break;
1967		case 3:
1968			snd_soc_component_update_bits(component,
1969				RT1011_TDM1_SET_3,
1970				RT1011_TDM_I2S_RX_ADC2_1_MASK,
1971				RT1011_TDM_I2S_RX_ADC2_1_LL);
1972			break;
1973		case 5:
1974			snd_soc_component_update_bits(component,
1975				RT1011_TDM1_SET_3,
1976				RT1011_TDM_I2S_RX_ADC3_1_MASK,
1977				RT1011_TDM_I2S_RX_ADC3_1_LL);
1978			break;
1979		case 7:
1980			snd_soc_component_update_bits(component,
1981				RT1011_TDM1_SET_3,
1982				RT1011_TDM_I2S_RX_ADC4_1_MASK,
1983				RT1011_TDM_I2S_RX_ADC4_1_LL);
1984			break;
1985		case 0:
1986			snd_soc_component_update_bits(component,
1987				RT1011_TDM1_SET_3,
1988				RT1011_TDM_I2S_RX_ADC1_1_MASK, 0);
1989			break;
1990		case 2:
1991			snd_soc_component_update_bits(component,
1992				RT1011_TDM1_SET_3,
1993				RT1011_TDM_I2S_RX_ADC2_1_MASK, 0);
1994			break;
1995		case 4:
1996			snd_soc_component_update_bits(component,
1997				RT1011_TDM1_SET_3,
1998				RT1011_TDM_I2S_RX_ADC3_1_MASK, 0);
1999			break;
2000		case 6:
2001			snd_soc_component_update_bits(component,
2002				RT1011_TDM1_SET_3,
2003				RT1011_TDM_I2S_RX_ADC4_1_MASK, 0);
2004			break;
2005		default:
2006			ret = -EINVAL;
2007			dev_dbg(component->dev,
2008				"tx slot location error\n");
2009			goto _set_tdm_err_;
2010		}
2011	} else if (tx_slotnum == 2) {
2012		switch (first_bit) {
2013		case 0:
2014		case 2:
2015		case 4:
2016		case 6:
2017			snd_soc_component_update_bits(component,
2018				RT1011_TDM1_SET_2,
2019				RT1011_TDM_I2S_DOCK_ADCDAT_LEN_1_MASK |
2020				RT1011_TDM_ADCDAT1_DATA_LOCATION,
2021				RT1011_TDM_I2S_DOCK_ADCDAT_2CH | first_bit);
2022			break;
2023		default:
2024			ret = -EINVAL;
2025			dev_dbg(component->dev,
2026				"tx slot location should be paired and start from slot0/2/4/6\n");
2027			goto _set_tdm_err_;
2028		}
2029	}
2030
2031	snd_soc_component_update_bits(component, RT1011_TDM1_SET_1,
2032		RT1011_I2S_CH_TX_MASK | RT1011_I2S_CH_RX_MASK |
2033		RT1011_I2S_CH_TX_LEN_MASK | RT1011_I2S_CH_RX_LEN_MASK, val);
2034	snd_soc_component_update_bits(component, RT1011_TDM2_SET_1,
2035		RT1011_I2S_CH_TX_MASK | RT1011_I2S_CH_RX_MASK |
2036		RT1011_I2S_CH_TX_LEN_MASK | RT1011_I2S_CH_RX_LEN_MASK, val);
2037	snd_soc_component_update_bits(component, RT1011_TDM1_SET_2,
2038		RT1011_TDM_I2S_DOCK_EN_1_MASK, tdm_en);
2039	snd_soc_component_update_bits(component, RT1011_TDM2_SET_2,
2040		RT1011_TDM_I2S_DOCK_EN_2_MASK, tdm_en);
2041
2042	snd_soc_component_update_bits(component, RT1011_TDM_TOTAL_SET,
2043		RT1011_ADCDAT1_PIN_CONFIG | RT1011_ADCDAT2_PIN_CONFIG,
2044		RT1011_ADCDAT1_OUTPUT | RT1011_ADCDAT2_OUTPUT);
2045
2046_set_tdm_err_:
2047	snd_soc_dapm_mutex_unlock(dapm);
2048	return ret;
2049}
2050
2051static int rt1011_probe(struct snd_soc_component *component)
2052{
2053	struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
2054	int i;
2055
2056	rt1011->component = component;
2057
2058	schedule_work(&rt1011->cali_work);
2059
2060	rt1011->i2s_ref = 0;
2061	rt1011->bq_drc_params = devm_kcalloc(component->dev,
2062		RT1011_ADVMODE_NUM, sizeof(struct rt1011_bq_drc_params *),
2063		GFP_KERNEL);
2064	if (!rt1011->bq_drc_params)
2065		return -ENOMEM;
2066
2067	for (i = 0; i < RT1011_ADVMODE_NUM; i++) {
2068		rt1011->bq_drc_params[i] = devm_kcalloc(component->dev,
2069			RT1011_BQ_DRC_NUM, sizeof(struct rt1011_bq_drc_params),
2070			GFP_KERNEL);
2071		if (!rt1011->bq_drc_params[i])
2072			return -ENOMEM;
2073	}
2074
2075	return 0;
2076}
2077
2078static void rt1011_remove(struct snd_soc_component *component)
2079{
2080	struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
2081
2082	cancel_work_sync(&rt1011->cali_work);
2083	rt1011_reset(rt1011->regmap);
2084}
2085
2086#ifdef CONFIG_PM
2087static int rt1011_suspend(struct snd_soc_component *component)
2088{
2089	struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
2090
2091	regcache_cache_only(rt1011->regmap, true);
2092	regcache_mark_dirty(rt1011->regmap);
2093
2094	return 0;
2095}
2096
2097static int rt1011_resume(struct snd_soc_component *component)
2098{
2099	struct rt1011_priv *rt1011 = snd_soc_component_get_drvdata(component);
2100
2101	regcache_cache_only(rt1011->regmap, false);
2102	regcache_sync(rt1011->regmap);
2103
2104	return 0;
2105}
2106#else
2107#define rt1011_suspend NULL
2108#define rt1011_resume NULL
2109#endif
2110
2111static int rt1011_set_bias_level(struct snd_soc_component *component,
2112				 enum snd_soc_bias_level level)
2113{
2114	switch (level) {
2115	case SND_SOC_BIAS_OFF:
2116		snd_soc_component_write(component,
2117			RT1011_SYSTEM_RESET_1, 0x0000);
2118		snd_soc_component_write(component,
2119			RT1011_SYSTEM_RESET_2, 0x0000);
2120		snd_soc_component_write(component,
2121			RT1011_SYSTEM_RESET_3, 0x0001);
2122		snd_soc_component_write(component,
2123			RT1011_SYSTEM_RESET_1, 0x003f);
2124		snd_soc_component_write(component,
2125			RT1011_SYSTEM_RESET_2, 0x7fd7);
2126		snd_soc_component_write(component,
2127			RT1011_SYSTEM_RESET_3, 0x770f);
2128		break;
2129	default:
2130		break;
2131	}
2132
2133	return 0;
2134}
2135
2136#define RT1011_STEREO_RATES SNDRV_PCM_RATE_8000_192000
2137#define RT1011_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
2138			SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S16_LE | \
2139			SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2140
2141static const struct snd_soc_dai_ops rt1011_aif_dai_ops = {
2142	.hw_params = rt1011_hw_params,
2143	.set_fmt = rt1011_set_dai_fmt,
2144	.set_tdm_slot = rt1011_set_tdm_slot,
2145};
2146
2147static struct snd_soc_dai_driver rt1011_dai[] = {
2148	{
2149		.name = "rt1011-aif",
2150		.playback = {
2151			.stream_name = "AIF1 Playback",
2152			.channels_min = 1,
2153			.channels_max = 2,
2154			.rates = RT1011_STEREO_RATES,
2155			.formats = RT1011_FORMATS,
2156		},
2157		.ops = &rt1011_aif_dai_ops,
2158	},
2159};
2160
2161static const struct snd_soc_component_driver soc_component_dev_rt1011 = {
2162	.probe = rt1011_probe,
2163	.remove = rt1011_remove,
2164	.suspend = rt1011_suspend,
2165	.resume = rt1011_resume,
2166	.set_bias_level = rt1011_set_bias_level,
2167	.controls = rt1011_snd_controls,
2168	.num_controls = ARRAY_SIZE(rt1011_snd_controls),
2169	.dapm_widgets = rt1011_dapm_widgets,
2170	.num_dapm_widgets = ARRAY_SIZE(rt1011_dapm_widgets),
2171	.dapm_routes = rt1011_dapm_routes,
2172	.num_dapm_routes = ARRAY_SIZE(rt1011_dapm_routes),
2173	.set_sysclk = rt1011_set_component_sysclk,
2174	.set_pll = rt1011_set_component_pll,
2175	.use_pmdown_time = 1,
2176	.endianness = 1,
 
2177};
2178
2179static const struct regmap_config rt1011_regmap = {
2180	.reg_bits = 16,
2181	.val_bits = 16,
2182	.max_register = RT1011_MAX_REG + 1,
2183	.volatile_reg = rt1011_volatile_register,
2184	.readable_reg = rt1011_readable_register,
2185	.cache_type = REGCACHE_MAPLE,
2186	.reg_defaults = rt1011_reg,
2187	.num_reg_defaults = ARRAY_SIZE(rt1011_reg),
2188	.use_single_read = true,
2189	.use_single_write = true,
2190};
2191
2192#if defined(CONFIG_OF)
2193static const struct of_device_id rt1011_of_match[] = {
2194	{ .compatible = "realtek,rt1011", },
2195	{},
2196};
2197MODULE_DEVICE_TABLE(of, rt1011_of_match);
2198#endif
2199
2200#ifdef CONFIG_ACPI
2201static const struct acpi_device_id rt1011_acpi_match[] = {
2202	{"10EC1011", 0,},
2203	{},
2204};
2205MODULE_DEVICE_TABLE(acpi, rt1011_acpi_match);
2206#endif
2207
2208static const struct i2c_device_id rt1011_i2c_id[] = {
2209	{ "rt1011" },
2210	{ }
2211};
2212MODULE_DEVICE_TABLE(i2c, rt1011_i2c_id);
2213
2214static int rt1011_calibrate(struct rt1011_priv *rt1011, unsigned char cali_flag)
2215{
2216	unsigned int value, count = 0, r0[3];
2217	unsigned int chk_cnt = 50; /* DONT change this */
2218	unsigned int dc_offset;
2219	unsigned int r0_integer, r0_factor, format;
2220	struct device *dev = regmap_get_device(rt1011->regmap);
2221	struct snd_soc_dapm_context *dapm =
2222		snd_soc_component_get_dapm(rt1011->component);
2223	int ret = 0;
2224
2225	snd_soc_dapm_mutex_lock(dapm);
2226	regcache_cache_bypass(rt1011->regmap, true);
2227
2228	regmap_write(rt1011->regmap, RT1011_RESET, 0x0000);
2229	regmap_write(rt1011->regmap, RT1011_SYSTEM_RESET_3, 0x740f);
2230	regmap_write(rt1011->regmap, RT1011_SYSTEM_RESET_3, 0x770f);
2231
2232	/* RC clock */
2233	regmap_write(rt1011->regmap, RT1011_CLK_2, 0x9400);
2234	regmap_write(rt1011->regmap, RT1011_PLL_1, 0x0800);
2235	regmap_write(rt1011->regmap, RT1011_PLL_2, 0x0020);
2236	regmap_write(rt1011->regmap, RT1011_CLK_DET, 0x0800);
2237
2238	/* ADC/DAC setting */
2239	regmap_write(rt1011->regmap, RT1011_ADC_SET_5, 0x0a20);
2240	regmap_write(rt1011->regmap, RT1011_DAC_SET_2, 0xe232);
 
2241	regmap_write(rt1011->regmap, RT1011_ADC_SET_4, 0xc000);
2242
2243	/* DC detection */
2244	regmap_write(rt1011->regmap, RT1011_SPK_PRO_DC_DET_1, 0xb00c);
2245	regmap_write(rt1011->regmap, RT1011_SPK_PRO_DC_DET_2, 0xcccc);
2246
2247	/* Power */
2248	regmap_write(rt1011->regmap, RT1011_POWER_1, 0xe0e0);
2249	regmap_write(rt1011->regmap, RT1011_POWER_3, 0x5003);
2250	regmap_write(rt1011->regmap, RT1011_POWER_9, 0xa860);
2251	regmap_write(rt1011->regmap, RT1011_DAC_SET_2, 0xa032);
2252
2253	/* POW_PLL / POW_BG / POW_BG_MBIAS_LV / POW_V/I */
2254	regmap_write(rt1011->regmap, RT1011_POWER_2, 0x0007);
2255	regmap_write(rt1011->regmap, RT1011_POWER_3, 0x5ff7);
2256	regmap_write(rt1011->regmap, RT1011_A_TEMP_SEN, 0x7f44);
2257	regmap_write(rt1011->regmap, RT1011_A_TIMING_1, 0x4054);
2258	regmap_write(rt1011->regmap, RT1011_BAT_GAIN_1, 0x309c);
2259
2260	/* DC offset from EFUSE */
2261	regmap_write(rt1011->regmap, RT1011_DC_CALIB_CLASSD_3, 0xcb00);
2262	regmap_write(rt1011->regmap, RT1011_BOOST_CON_1, 0xe080);
2263	regmap_write(rt1011->regmap, RT1011_POWER_4, 0x16f2);
2264	regmap_write(rt1011->regmap, RT1011_POWER_6, 0x36ad);
2265
2266	/* mixer */
2267	regmap_write(rt1011->regmap, RT1011_MIXER_1, 0x3f1d);
2268
2269	/* EFUSE read */
2270	regmap_write(rt1011->regmap, RT1011_EFUSE_CONTROL_1, 0x0d0a);
2271	msleep(30);
2272
2273	regmap_read(rt1011->regmap, RT1011_EFUSE_ADC_OFFSET_18_16, &value);
2274	dc_offset = value << 16;
2275	regmap_read(rt1011->regmap, RT1011_EFUSE_ADC_OFFSET_15_0, &value);
2276	dc_offset |= (value & 0xffff);
2277	dev_info(dev, "ADC offset=0x%x\n", dc_offset);
2278	regmap_read(rt1011->regmap, RT1011_EFUSE_DAC_OFFSET_G0_20_16, &value);
2279	dc_offset = value << 16;
2280	regmap_read(rt1011->regmap, RT1011_EFUSE_DAC_OFFSET_G0_15_0, &value);
2281	dc_offset |= (value & 0xffff);
2282	dev_info(dev, "Gain0 offset=0x%x\n", dc_offset);
2283	regmap_read(rt1011->regmap, RT1011_EFUSE_DAC_OFFSET_G1_20_16, &value);
2284	dc_offset = value << 16;
2285	regmap_read(rt1011->regmap, RT1011_EFUSE_DAC_OFFSET_G1_15_0, &value);
2286	dc_offset |= (value & 0xffff);
2287	dev_info(dev, "Gain1 offset=0x%x\n", dc_offset);
2288
2289	if (cali_flag) {
2290
2291		regmap_write(rt1011->regmap, RT1011_ADC_SET_1, 0x2925);
2292		/* Class D on */
2293		regmap_write(rt1011->regmap, RT1011_CLASS_D_POS, 0x010e);
2294		regmap_write(rt1011->regmap,
2295			RT1011_CLASSD_INTERNAL_SET_1, 0x1701);
2296
2297		/* STP enable */
2298		regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_0, 0x8000);
2299		regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_7, 0xf000);
2300		regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_4, 0x4040);
2301		regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_0, 0xc000);
2302		regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_6, 0x07c2);
2303
2304		r0[0] = r0[1] = r0[2] = count = 0;
2305		while (count < chk_cnt) {
2306			msleep(100);
2307			regmap_read(rt1011->regmap,
2308				RT1011_INIT_RECIPROCAL_SYN_24_16, &value);
2309			r0[count%3] = value << 16;
2310			regmap_read(rt1011->regmap,
2311				RT1011_INIT_RECIPROCAL_SYN_15_0, &value);
2312			r0[count%3] |= value;
2313
2314			if (r0[count%3] == 0)
2315				continue;
2316
2317			count++;
2318
2319			if (r0[0] == r0[1] && r0[1] == r0[2])
2320				break;
2321		}
2322		if (count > chk_cnt) {
2323			dev_err(dev, "Calibrate R0 Failure\n");
2324			ret = -EAGAIN;
2325		} else {
2326			format = 2147483648U; /* 2^24 * 128 */
2327			r0_integer = format / r0[0] / 128;
2328			r0_factor = ((format / r0[0] * 100) / 128)
2329							- (r0_integer * 100);
2330			rt1011->r0_reg = r0[0];
2331			rt1011->cali_done = 1;
2332			dev_info(dev, "r0 resistance about %d.%02d ohm, reg=0x%X\n",
2333				r0_integer, r0_factor, r0[0]);
2334		}
2335	}
2336
2337	/* depop */
2338	regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_0, 0x0000);
2339	msleep(400);
2340	regmap_write(rt1011->regmap, RT1011_POWER_9, 0xa840);
2341	regmap_write(rt1011->regmap, RT1011_SPK_TEMP_PROTECT_6, 0x0702);
2342	regmap_write(rt1011->regmap, RT1011_MIXER_1, 0xffdd);
2343	regmap_write(rt1011->regmap, RT1011_CLASSD_INTERNAL_SET_1, 0x0701);
2344	regmap_write(rt1011->regmap, RT1011_DAC_SET_3, 0xe004);
2345	regmap_write(rt1011->regmap, RT1011_A_TEMP_SEN, 0x7f40);
2346	regmap_write(rt1011->regmap, RT1011_POWER_1, 0x0000);
2347	regmap_write(rt1011->regmap, RT1011_POWER_2, 0x0000);
2348	regmap_write(rt1011->regmap, RT1011_POWER_3, 0x0002);
2349	regmap_write(rt1011->regmap, RT1011_POWER_4, 0x00f2);
2350
2351	regmap_write(rt1011->regmap, RT1011_RESET, 0x0000);
2352
2353	if (cali_flag) {
2354		if (count <= chk_cnt) {
2355			regmap_write(rt1011->regmap,
2356				RT1011_INIT_RECIPROCAL_REG_24_16,
2357				((r0[0]>>16) & 0x1ff));
2358			regmap_write(rt1011->regmap,
2359				RT1011_INIT_RECIPROCAL_REG_15_0,
2360				(r0[0] & 0xffff));
2361			regmap_write(rt1011->regmap,
2362				RT1011_SPK_TEMP_PROTECT_4, 0x4080);
2363		}
2364	}
2365
2366	regcache_cache_bypass(rt1011->regmap, false);
2367	regcache_mark_dirty(rt1011->regmap);
2368	regcache_sync(rt1011->regmap);
2369	snd_soc_dapm_mutex_unlock(dapm);
2370
2371	return ret;
2372}
2373
2374static void rt1011_calibration_work(struct work_struct *work)
2375{
2376	struct rt1011_priv *rt1011 =
2377		container_of(work, struct rt1011_priv, cali_work);
2378	struct snd_soc_component *component = rt1011->component;
2379	unsigned int r0_integer, r0_factor, format;
2380
2381	if (rt1011->r0_calib)
2382		rt1011_calibrate(rt1011, 0);
2383	else
2384		rt1011_calibrate(rt1011, 1);
2385
2386	/*
2387	 * This flag should reset after booting.
2388	 * The factory test will do calibration again and use this flag to check
2389	 * whether the calibration completed
2390	 */
2391	rt1011->cali_done = 0;
2392
2393	/* initial */
2394	rt1011_reg_init(component);
2395
2396	/* Apply temperature and calibration data from device property */
2397	if (rt1011->temperature_calib <= 0xff &&
2398		rt1011->temperature_calib > 0) {
2399		snd_soc_component_update_bits(component,
2400			RT1011_STP_INITIAL_RESISTANCE_TEMP, 0x3ff,
2401			(rt1011->temperature_calib << 2));
2402	}
2403
2404	if (rt1011->r0_calib) {
2405		rt1011->r0_reg = rt1011->r0_calib;
2406
2407		format = 2147483648U; /* 2^24 * 128 */
2408		r0_integer = format / rt1011->r0_reg / 128;
2409		r0_factor = ((format / rt1011->r0_reg * 100) / 128)
2410						- (r0_integer * 100);
2411		dev_info(component->dev, "DP r0 resistance about %d.%02d ohm, reg=0x%X\n",
2412			r0_integer, r0_factor, rt1011->r0_reg);
2413
2414		rt1011_r0_load(rt1011);
2415	}
2416
2417	snd_soc_component_write(component, RT1011_ADC_SET_1, 0x2925);
2418}
2419
2420static int rt1011_parse_dp(struct rt1011_priv *rt1011, struct device *dev)
2421{
2422	device_property_read_u32(dev, "realtek,temperature_calib",
2423		&rt1011->temperature_calib);
2424	device_property_read_u32(dev, "realtek,r0_calib",
2425		&rt1011->r0_calib);
2426
2427	dev_dbg(dev, "%s: r0_calib: 0x%x, temperature_calib: 0x%x",
2428		__func__, rt1011->r0_calib, rt1011->temperature_calib);
2429
2430	return 0;
2431}
2432
2433static int rt1011_i2c_probe(struct i2c_client *i2c)
2434{
2435	struct rt1011_priv *rt1011;
2436	int ret;
2437	unsigned int val;
2438
2439	rt1011 = devm_kzalloc(&i2c->dev, sizeof(struct rt1011_priv),
2440				GFP_KERNEL);
2441	if (!rt1011)
2442		return -ENOMEM;
2443
2444	i2c_set_clientdata(i2c, rt1011);
2445
2446	rt1011_parse_dp(rt1011, &i2c->dev);
2447
2448	rt1011->regmap = devm_regmap_init_i2c(i2c, &rt1011_regmap);
2449	if (IS_ERR(rt1011->regmap)) {
2450		ret = PTR_ERR(rt1011->regmap);
2451		dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
2452			ret);
2453		return ret;
2454	}
2455
2456	regmap_read(rt1011->regmap, RT1011_DEVICE_ID, &val);
2457	if (val != RT1011_DEVICE_ID_NUM) {
2458		dev_err(&i2c->dev,
2459			"Device with ID register %x is not rt1011\n", val);
2460		return -ENODEV;
2461	}
2462
2463	INIT_WORK(&rt1011->cali_work, rt1011_calibration_work);
2464
2465	return devm_snd_soc_register_component(&i2c->dev,
2466		&soc_component_dev_rt1011,
2467		rt1011_dai, ARRAY_SIZE(rt1011_dai));
2468
2469}
2470
2471static void rt1011_i2c_shutdown(struct i2c_client *client)
2472{
2473	struct rt1011_priv *rt1011 = i2c_get_clientdata(client);
2474
2475	rt1011_reset(rt1011->regmap);
2476}
 
2477
2478static struct i2c_driver rt1011_i2c_driver = {
2479	.driver = {
2480		.name = "rt1011",
2481		.of_match_table = of_match_ptr(rt1011_of_match),
2482		.acpi_match_table = ACPI_PTR(rt1011_acpi_match)
2483	},
2484	.probe = rt1011_i2c_probe,
2485	.shutdown = rt1011_i2c_shutdown,
2486	.id_table = rt1011_i2c_id,
2487};
2488module_i2c_driver(rt1011_i2c_driver);
2489
2490MODULE_DESCRIPTION("ASoC RT1011 amplifier driver");
2491MODULE_AUTHOR("Shuming Fan <shumingf@realtek.com>");
2492MODULE_LICENSE("GPL");