1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 * core.h - DesignWare USB3 DRD Core Header
   4 *
   5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
   6 *
   7 * Authors: Felipe Balbi <balbi@ti.com>,
   8 *	    Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   9 */
  10
  11#ifndef __DRIVERS_USB_DWC3_CORE_H
  12#define __DRIVERS_USB_DWC3_CORE_H
  13
  14#include <linux/device.h>
  15#include <linux/spinlock.h>
  16#include <linux/mutex.h>
  17#include <linux/ioport.h>
  18#include <linux/list.h>
  19#include <linux/bitops.h>
  20#include <linux/dma-mapping.h>
  21#include <linux/mm.h>
  22#include <linux/debugfs.h>
  23#include <linux/wait.h>
  24#include <linux/workqueue.h>
  25
  26#include <linux/usb/ch9.h>
  27#include <linux/usb/gadget.h>
  28#include <linux/usb/otg.h>
  29#include <linux/usb/role.h>
  30#include <linux/ulpi/interface.h>
  31
  32#include <linux/phy/phy.h>
  33
  34#include <linux/power_supply.h>
  35
  36/*
  37 * DWC3 Multiport controllers support up to 15 High-Speed PHYs
  38 * and 4 SuperSpeed PHYs.
  39 */
  40#define DWC3_USB2_MAX_PORTS	15
  41#define DWC3_USB3_MAX_PORTS	4
  42
  43#define DWC3_MSG_MAX	500
  44
  45/* Global constants */
  46#define DWC3_PULL_UP_TIMEOUT	500	/* ms */
  47#define DWC3_BOUNCE_SIZE	1024	/* size of a superspeed bulk */
  48#define DWC3_EP0_SETUP_SIZE	512
  49#define DWC3_ENDPOINTS_NUM	32
  50#define DWC3_XHCI_RESOURCES_NUM	2
  51#define DWC3_ISOC_MAX_RETRIES	5
  52
  53#define DWC3_SCRATCHBUF_SIZE	4096	/* each buffer is assumed to be 4KiB */
  54#define DWC3_EVENT_BUFFERS_SIZE	4096
  55#define DWC3_EVENT_TYPE_MASK	0xfe
  56
  57#define DWC3_EVENT_TYPE_DEV	0
  58#define DWC3_EVENT_TYPE_CARKIT	3
  59#define DWC3_EVENT_TYPE_I2C	4
  60
  61#define DWC3_DEVICE_EVENT_DISCONNECT		0
  62#define DWC3_DEVICE_EVENT_RESET			1
  63#define DWC3_DEVICE_EVENT_CONNECT_DONE		2
  64#define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE	3
  65#define DWC3_DEVICE_EVENT_WAKEUP		4
  66#define DWC3_DEVICE_EVENT_HIBER_REQ		5
  67#define DWC3_DEVICE_EVENT_SUSPEND		6
  68#define DWC3_DEVICE_EVENT_SOF			7
  69#define DWC3_DEVICE_EVENT_ERRATIC_ERROR		9
  70#define DWC3_DEVICE_EVENT_CMD_CMPL		10
  71#define DWC3_DEVICE_EVENT_OVERFLOW		11
  72
  73/* Controller's role while using the OTG block */
  74#define DWC3_OTG_ROLE_IDLE	0
  75#define DWC3_OTG_ROLE_HOST	1
  76#define DWC3_OTG_ROLE_DEVICE	2
  77
  78#define DWC3_GEVNTCOUNT_MASK	0xfffc
  79#define DWC3_GEVNTCOUNT_EHB	BIT(31)
  80#define DWC3_GSNPSID_MASK	0xffff0000
  81#define DWC3_GSNPSREV_MASK	0xffff
  82#define DWC3_GSNPS_ID(p)	(((p) & DWC3_GSNPSID_MASK) >> 16)
  83
  84/* DWC3 registers memory space boundaries */
  85#define DWC3_XHCI_REGS_START		0x0
  86#define DWC3_XHCI_REGS_END		0x7fff
  87#define DWC3_GLOBALS_REGS_START		0xc100
  88#define DWC3_GLOBALS_REGS_END		0xc6ff
  89#define DWC3_DEVICE_REGS_START		0xc700
  90#define DWC3_DEVICE_REGS_END		0xcbff
  91#define DWC3_OTG_REGS_START		0xcc00
  92#define DWC3_OTG_REGS_END		0xccff
  93
  94#define DWC3_RTK_RTD_GLOBALS_REGS_START	0x8100
  95
  96/* Global Registers */
  97#define DWC3_GSBUSCFG0		0xc100
  98#define DWC3_GSBUSCFG1		0xc104
  99#define DWC3_GTXTHRCFG		0xc108
 100#define DWC3_GRXTHRCFG		0xc10c
 101#define DWC3_GCTL		0xc110
 102#define DWC3_GEVTEN		0xc114
 103#define DWC3_GSTS		0xc118
 104#define DWC3_GUCTL1		0xc11c
 105#define DWC3_GSNPSID		0xc120
 106#define DWC3_GGPIO		0xc124
 107#define DWC3_GUID		0xc128
 108#define DWC3_GUCTL		0xc12c
 109#define DWC3_GBUSERRADDR0	0xc130
 110#define DWC3_GBUSERRADDR1	0xc134
 111#define DWC3_GPRTBIMAP0		0xc138
 112#define DWC3_GPRTBIMAP1		0xc13c
 113#define DWC3_GHWPARAMS0		0xc140
 114#define DWC3_GHWPARAMS1		0xc144
 115#define DWC3_GHWPARAMS2		0xc148
 116#define DWC3_GHWPARAMS3		0xc14c
 117#define DWC3_GHWPARAMS4		0xc150
 118#define DWC3_GHWPARAMS5		0xc154
 119#define DWC3_GHWPARAMS6		0xc158
 120#define DWC3_GHWPARAMS7		0xc15c
 121#define DWC3_GDBGFIFOSPACE	0xc160
 122#define DWC3_GDBGLTSSM		0xc164
 123#define DWC3_GDBGBMU		0xc16c
 124#define DWC3_GDBGLSPMUX		0xc170
 125#define DWC3_GDBGLSP		0xc174
 126#define DWC3_GDBGEPINFO0	0xc178
 127#define DWC3_GDBGEPINFO1	0xc17c
 128#define DWC3_GPRTBIMAP_HS0	0xc180
 129#define DWC3_GPRTBIMAP_HS1	0xc184
 130#define DWC3_GPRTBIMAP_FS0	0xc188
 131#define DWC3_GPRTBIMAP_FS1	0xc18c
 132#define DWC3_GUCTL2		0xc19c
 133
 134#define DWC3_VER_NUMBER		0xc1a0
 135#define DWC3_VER_TYPE		0xc1a4
 136
 137#define DWC3_GUSB2PHYCFG(n)	(0xc200 + ((n) * 0x04))
 138#define DWC3_GUSB2I2CCTL(n)	(0xc240 + ((n) * 0x04))
 139
 140#define DWC3_GUSB2PHYACC(n)	(0xc280 + ((n) * 0x04))
 141
 142#define DWC3_GUSB3PIPECTL(n)	(0xc2c0 + ((n) * 0x04))
 143
 144#define DWC3_GTXFIFOSIZ(n)	(0xc300 + ((n) * 0x04))
 145#define DWC3_GRXFIFOSIZ(n)	(0xc380 + ((n) * 0x04))
 146
 147#define DWC3_GEVNTADRLO(n)	(0xc400 + ((n) * 0x10))
 148#define DWC3_GEVNTADRHI(n)	(0xc404 + ((n) * 0x10))
 149#define DWC3_GEVNTSIZ(n)	(0xc408 + ((n) * 0x10))
 150#define DWC3_GEVNTCOUNT(n)	(0xc40c + ((n) * 0x10))
 151
 152#define DWC3_GHWPARAMS8		0xc600
 153#define DWC3_GUCTL3		0xc60c
 154#define DWC3_GFLADJ		0xc630
 155#define DWC3_GHWPARAMS9		0xc6e0
 156
 157/* Device Registers */
 158#define DWC3_DCFG		0xc700
 159#define DWC3_DCTL		0xc704
 160#define DWC3_DEVTEN		0xc708
 161#define DWC3_DSTS		0xc70c
 162#define DWC3_DGCMDPAR		0xc710
 163#define DWC3_DGCMD		0xc714
 164#define DWC3_DALEPENA		0xc720
 165#define DWC3_DCFG1		0xc740 /* DWC_usb32 only */
 166
 167#define DWC3_DEP_BASE(n)	(0xc800 + ((n) * 0x10))
 168#define DWC3_DEPCMDPAR2		0x00
 169#define DWC3_DEPCMDPAR1		0x04
 170#define DWC3_DEPCMDPAR0		0x08
 171#define DWC3_DEPCMD		0x0c
 172
 173#define DWC3_DEV_IMOD(n)	(0xca00 + ((n) * 0x4))
 174
 175/* OTG Registers */
 176#define DWC3_OCFG		0xcc00
 177#define DWC3_OCTL		0xcc04
 178#define DWC3_OEVT		0xcc08
 179#define DWC3_OEVTEN		0xcc0C
 180#define DWC3_OSTS		0xcc10
 181
 182#define DWC3_LLUCTL(n)		(0xd024 + ((n) * 0x80))
 183
 184/* Bit fields */
 185
 186/* Global SoC Bus Configuration INCRx Register 0 */
 187#define DWC3_GSBUSCFG0_INCR256BRSTENA	(1 << 7) /* INCR256 burst */
 188#define DWC3_GSBUSCFG0_INCR128BRSTENA	(1 << 6) /* INCR128 burst */
 189#define DWC3_GSBUSCFG0_INCR64BRSTENA	(1 << 5) /* INCR64 burst */
 190#define DWC3_GSBUSCFG0_INCR32BRSTENA	(1 << 4) /* INCR32 burst */
 191#define DWC3_GSBUSCFG0_INCR16BRSTENA	(1 << 3) /* INCR16 burst */
 192#define DWC3_GSBUSCFG0_INCR8BRSTENA	(1 << 2) /* INCR8 burst */
 193#define DWC3_GSBUSCFG0_INCR4BRSTENA	(1 << 1) /* INCR4 burst */
 194#define DWC3_GSBUSCFG0_INCRBRSTENA	(1 << 0) /* undefined length enable */
 195#define DWC3_GSBUSCFG0_INCRBRST_MASK	0xff
 196
 197/* Global SoC Bus Configuration Register: AHB-prot/AXI-cache/OCP-ReqInfo */
 198#define DWC3_GSBUSCFG0_REQINFO(n)	(((n) & 0xffff) << 16)
 199#define DWC3_GSBUSCFG0_REQINFO_UNSPECIFIED	0xffffffff
 200
 201/* Global Debug LSP MUX Select */
 202#define DWC3_GDBGLSPMUX_ENDBC		BIT(15)	/* Host only */
 203#define DWC3_GDBGLSPMUX_HOSTSELECT(n)	((n) & 0x3fff)
 204#define DWC3_GDBGLSPMUX_DEVSELECT(n)	(((n) & 0xf) << 4)
 205#define DWC3_GDBGLSPMUX_EPSELECT(n)	((n) & 0xf)
 206
 207/* Global Debug Queue/FIFO Space Available Register */
 208#define DWC3_GDBGFIFOSPACE_NUM(n)	((n) & 0x1f)
 209#define DWC3_GDBGFIFOSPACE_TYPE(n)	(((n) << 5) & 0x1e0)
 210#define DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(n) (((n) >> 16) & 0xffff)
 211
 212#define DWC3_TXFIFO		0
 213#define DWC3_RXFIFO		1
 214#define DWC3_TXREQQ		2
 215#define DWC3_RXREQQ		3
 216#define DWC3_RXINFOQ		4
 217#define DWC3_PSTATQ		5
 218#define DWC3_DESCFETCHQ		6
 219#define DWC3_EVENTQ		7
 220#define DWC3_AUXEVENTQ		8
 221
 222/* Global RX Threshold Configuration Register */
 223#define DWC3_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 19)
 224#define DWC3_GRXTHRCFG_RXPKTCNT(n) (((n) & 0xf) << 24)
 225#define DWC3_GRXTHRCFG_PKTCNTSEL BIT(29)
 226
 227/* Global TX Threshold Configuration Register */
 228#define DWC3_GTXTHRCFG_MAXTXBURSTSIZE(n) (((n) & 0xff) << 16)
 229#define DWC3_GTXTHRCFG_TXPKTCNT(n) (((n) & 0xf) << 24)
 230#define DWC3_GTXTHRCFG_PKTCNTSEL BIT(29)
 231
 232/* Global RX Threshold Configuration Register for DWC_usb31 only */
 233#define DWC31_GRXTHRCFG_MAXRXBURSTSIZE(n)	(((n) & 0x1f) << 16)
 234#define DWC31_GRXTHRCFG_RXPKTCNT(n)		(((n) & 0x1f) << 21)
 235#define DWC31_GRXTHRCFG_PKTCNTSEL		BIT(26)
 236#define DWC31_RXTHRNUMPKTSEL_HS_PRD		BIT(15)
 237#define DWC31_RXTHRNUMPKT_HS_PRD(n)		(((n) & 0x3) << 13)
 238#define DWC31_RXTHRNUMPKTSEL_PRD		BIT(10)
 239#define DWC31_RXTHRNUMPKT_PRD(n)		(((n) & 0x1f) << 5)
 240#define DWC31_MAXRXBURSTSIZE_PRD(n)		((n) & 0x1f)
 241
 242/* Global TX Threshold Configuration Register for DWC_usb31 only */
 243#define DWC31_GTXTHRCFG_MAXTXBURSTSIZE(n)	(((n) & 0x1f) << 16)
 244#define DWC31_GTXTHRCFG_TXPKTCNT(n)		(((n) & 0x1f) << 21)
 245#define DWC31_GTXTHRCFG_PKTCNTSEL		BIT(26)
 246#define DWC31_TXTHRNUMPKTSEL_HS_PRD		BIT(15)
 247#define DWC31_TXTHRNUMPKT_HS_PRD(n)		(((n) & 0x3) << 13)
 248#define DWC31_TXTHRNUMPKTSEL_PRD		BIT(10)
 249#define DWC31_TXTHRNUMPKT_PRD(n)		(((n) & 0x1f) << 5)
 250#define DWC31_MAXTXBURSTSIZE_PRD(n)		((n) & 0x1f)
 251
 252/* Global Configuration Register */
 253#define DWC3_GCTL_PWRDNSCALE(n)	((n) << 19)
 254#define DWC3_GCTL_PWRDNSCALE_MASK	GENMASK(31, 19)
 255#define DWC3_GCTL_U2RSTECN	BIT(16)
 256#define DWC3_GCTL_RAMCLKSEL(x)	(((x) & DWC3_GCTL_CLK_MASK) << 6)
 257#define DWC3_GCTL_CLK_BUS	(0)
 258#define DWC3_GCTL_CLK_PIPE	(1)
 259#define DWC3_GCTL_CLK_PIPEHALF	(2)
 260#define DWC3_GCTL_CLK_MASK	(3)
 261
 262#define DWC3_GCTL_PRTCAP(n)	(((n) & (3 << 12)) >> 12)
 263#define DWC3_GCTL_PRTCAPDIR(n)	((n) << 12)
 264#define DWC3_GCTL_PRTCAP_HOST	1
 265#define DWC3_GCTL_PRTCAP_DEVICE	2
 266#define DWC3_GCTL_PRTCAP_OTG	3
 267
 268#define DWC3_GCTL_CORESOFTRESET		BIT(11)
 269#define DWC3_GCTL_SOFITPSYNC		BIT(10)
 270#define DWC3_GCTL_SCALEDOWN(n)		((n) << 4)
 271#define DWC3_GCTL_SCALEDOWN_MASK	DWC3_GCTL_SCALEDOWN(3)
 272#define DWC3_GCTL_DISSCRAMBLE		BIT(3)
 273#define DWC3_GCTL_U2EXIT_LFPS		BIT(2)
 274#define DWC3_GCTL_GBLHIBERNATIONEN	BIT(1)
 275#define DWC3_GCTL_DSBLCLKGTNG		BIT(0)
 276
 
 
 
 277/* Global User Control 1 Register */
 278#define DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT	BIT(31)
 279#define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS	BIT(28)
 280#define DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK	BIT(26)
 281#define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW		BIT(24)
 282#define DWC3_GUCTL1_PARKMODE_DISABLE_SS		BIT(17)
 283#define DWC3_GUCTL1_PARKMODE_DISABLE_HS		BIT(16)
 284#define DWC3_GUCTL1_RESUME_OPMODE_HS_HOST	BIT(10)
 285
 286/* Global Status Register */
 287#define DWC3_GSTS_OTG_IP	BIT(10)
 288#define DWC3_GSTS_BC_IP		BIT(9)
 289#define DWC3_GSTS_ADP_IP	BIT(8)
 290#define DWC3_GSTS_HOST_IP	BIT(7)
 291#define DWC3_GSTS_DEVICE_IP	BIT(6)
 292#define DWC3_GSTS_CSR_TIMEOUT	BIT(5)
 293#define DWC3_GSTS_BUS_ERR_ADDR_VLD	BIT(4)
 294#define DWC3_GSTS_CURMOD(n)	((n) & 0x3)
 295#define DWC3_GSTS_CURMOD_DEVICE	0
 296#define DWC3_GSTS_CURMOD_HOST	1
 297
 298/* Global USB2 PHY Configuration Register */
 299#define DWC3_GUSB2PHYCFG_PHYSOFTRST	BIT(31)
 300#define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS	BIT(30)
 301#define DWC3_GUSB2PHYCFG_ULPIEXTVBUSDRV	BIT(17)
 302#define DWC3_GUSB2PHYCFG_SUSPHY		BIT(6)
 303#define DWC3_GUSB2PHYCFG_ULPI_UTMI	BIT(4)
 304#define DWC3_GUSB2PHYCFG_ENBLSLPM	BIT(8)
 305#define DWC3_GUSB2PHYCFG_PHYIF(n)	(n << 3)
 306#define DWC3_GUSB2PHYCFG_PHYIF_MASK	DWC3_GUSB2PHYCFG_PHYIF(1)
 307#define DWC3_GUSB2PHYCFG_USBTRDTIM(n)	(n << 10)
 308#define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK	DWC3_GUSB2PHYCFG_USBTRDTIM(0xf)
 309#define USBTRDTIM_UTMI_8_BIT		9
 310#define USBTRDTIM_UTMI_16_BIT		5
 311#define UTMI_PHYIF_16_BIT		1
 312#define UTMI_PHYIF_8_BIT		0
 313
 314/* Global USB2 PHY Vendor Control Register */
 315#define DWC3_GUSB2PHYACC_NEWREGREQ	BIT(25)
 316#define DWC3_GUSB2PHYACC_DONE		BIT(24)
 317#define DWC3_GUSB2PHYACC_BUSY		BIT(23)
 318#define DWC3_GUSB2PHYACC_WRITE		BIT(22)
 319#define DWC3_GUSB2PHYACC_ADDR(n)	(n << 16)
 320#define DWC3_GUSB2PHYACC_EXTEND_ADDR(n)	(n << 8)
 321#define DWC3_GUSB2PHYACC_DATA(n)	(n & 0xff)
 322
 323/* Global USB3 PIPE Control Register */
 324#define DWC3_GUSB3PIPECTL_PHYSOFTRST	BIT(31)
 325#define DWC3_GUSB3PIPECTL_U2SSINP3OK	BIT(29)
 326#define DWC3_GUSB3PIPECTL_DISRXDETINP3	BIT(28)
 327#define DWC3_GUSB3PIPECTL_UX_EXIT_PX	BIT(27)
 328#define DWC3_GUSB3PIPECTL_REQP1P2P3	BIT(24)
 329#define DWC3_GUSB3PIPECTL_DEP1P2P3(n)	((n) << 19)
 330#define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK	DWC3_GUSB3PIPECTL_DEP1P2P3(7)
 331#define DWC3_GUSB3PIPECTL_DEP1P2P3_EN	DWC3_GUSB3PIPECTL_DEP1P2P3(1)
 332#define DWC3_GUSB3PIPECTL_DEPOCHANGE	BIT(18)
 333#define DWC3_GUSB3PIPECTL_SUSPHY	BIT(17)
 334#define DWC3_GUSB3PIPECTL_LFPSFILT	BIT(9)
 335#define DWC3_GUSB3PIPECTL_RX_DETOPOLL	BIT(8)
 336#define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK	DWC3_GUSB3PIPECTL_TX_DEEPH(3)
 337#define DWC3_GUSB3PIPECTL_TX_DEEPH(n)	((n) << 1)
 338
 339/* Global TX Fifo Size Register */
 340#define DWC31_GTXFIFOSIZ_TXFRAMNUM	BIT(15)		/* DWC_usb31 only */
 341#define DWC31_GTXFIFOSIZ_TXFDEP(n)	((n) & 0x7fff)	/* DWC_usb31 only */
 342#define DWC3_GTXFIFOSIZ_TXFDEP(n)	((n) & 0xffff)
 343#define DWC3_GTXFIFOSIZ_TXFSTADDR(n)	((n) & 0xffff0000)
 344
 345/* Global RX Fifo Size Register */
 346#define DWC31_GRXFIFOSIZ_RXFDEP(n)	((n) & 0x7fff)	/* DWC_usb31 only */
 347#define DWC3_GRXFIFOSIZ_RXFDEP(n)	((n) & 0xffff)
 348
 349/* Global Event Size Registers */
 350#define DWC3_GEVNTSIZ_INTMASK		BIT(31)
 351#define DWC3_GEVNTSIZ_SIZE(n)		((n) & 0xffff)
 352
 353/* Global HWPARAMS0 Register */
 354#define DWC3_GHWPARAMS0_MODE(n)		((n) & 0x3)
 355#define DWC3_GHWPARAMS0_MODE_GADGET	0
 356#define DWC3_GHWPARAMS0_MODE_HOST	1
 357#define DWC3_GHWPARAMS0_MODE_DRD	2
 358#define DWC3_GHWPARAMS0_MBUS_TYPE(n)	(((n) >> 3) & 0x7)
 359#define DWC3_GHWPARAMS0_SBUS_TYPE(n)	(((n) >> 6) & 0x3)
 360#define DWC3_GHWPARAMS0_MDWIDTH(n)	(((n) >> 8) & 0xff)
 361#define DWC3_GHWPARAMS0_SDWIDTH(n)	(((n) >> 16) & 0xff)
 362#define DWC3_GHWPARAMS0_AWIDTH(n)	(((n) >> 24) & 0xff)
 363
 364/* Global HWPARAMS1 Register */
 365#define DWC3_GHWPARAMS1_EN_PWROPT(n)	(((n) & (3 << 24)) >> 24)
 366#define DWC3_GHWPARAMS1_EN_PWROPT_NO	0
 367#define DWC3_GHWPARAMS1_EN_PWROPT_CLK	1
 368#define DWC3_GHWPARAMS1_EN_PWROPT_HIB	2
 369#define DWC3_GHWPARAMS1_PWROPT(n)	((n) << 24)
 370#define DWC3_GHWPARAMS1_PWROPT_MASK	DWC3_GHWPARAMS1_PWROPT(3)
 371#define DWC3_GHWPARAMS1_ENDBC		BIT(31)
 372
 373/* Global HWPARAMS3 Register */
 374#define DWC3_GHWPARAMS3_SSPHY_IFC(n)		((n) & 3)
 375#define DWC3_GHWPARAMS3_SSPHY_IFC_DIS		0
 376#define DWC3_GHWPARAMS3_SSPHY_IFC_GEN1		1
 377#define DWC3_GHWPARAMS3_SSPHY_IFC_GEN2		2 /* DWC_usb31 only */
 378#define DWC3_GHWPARAMS3_HSPHY_IFC(n)		(((n) & (3 << 2)) >> 2)
 379#define DWC3_GHWPARAMS3_HSPHY_IFC_DIS		0
 380#define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI		1
 381#define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI		2
 382#define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI	3
 383#define DWC3_GHWPARAMS3_FSPHY_IFC(n)		(((n) & (3 << 4)) >> 4)
 384#define DWC3_GHWPARAMS3_FSPHY_IFC_DIS		0
 385#define DWC3_GHWPARAMS3_FSPHY_IFC_ENA		1
 386
 387/* Global HWPARAMS4 Register */
 388#define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n)	(((n) & (0x0f << 13)) >> 13)
 389#define DWC3_MAX_HIBER_SCRATCHBUFS		15
 390
 391/* Global HWPARAMS6 Register */
 392#define DWC3_GHWPARAMS6_BCSUPPORT		BIT(14)
 393#define DWC3_GHWPARAMS6_OTG3SUPPORT		BIT(13)
 394#define DWC3_GHWPARAMS6_ADPSUPPORT		BIT(12)
 395#define DWC3_GHWPARAMS6_HNPSUPPORT		BIT(11)
 396#define DWC3_GHWPARAMS6_SRPSUPPORT		BIT(10)
 397#define DWC3_GHWPARAMS6_EN_FPGA			BIT(7)
 398
 399/* DWC_usb32 only */
 400#define DWC3_GHWPARAMS6_MDWIDTH(n)		((n) & (0x3 << 8))
 401
 402/* Global HWPARAMS7 Register */
 403#define DWC3_GHWPARAMS7_RAM1_DEPTH(n)	((n) & 0xffff)
 404#define DWC3_GHWPARAMS7_RAM2_DEPTH(n)	(((n) >> 16) & 0xffff)
 405
 406/* Global HWPARAMS9 Register */
 407#define DWC3_GHWPARAMS9_DEV_TXF_FLUSH_BYPASS	BIT(0)
 408#define DWC3_GHWPARAMS9_DEV_MST			BIT(1)
 409
 410/* Global Frame Length Adjustment Register */
 411#define DWC3_GFLADJ_30MHZ_SDBND_SEL		BIT(7)
 412#define DWC3_GFLADJ_30MHZ_MASK			0x3f
 413#define DWC3_GFLADJ_REFCLK_FLADJ_MASK		GENMASK(21, 8)
 414#define DWC3_GFLADJ_REFCLK_LPM_SEL		BIT(23)
 415#define DWC3_GFLADJ_240MHZDECR			GENMASK(30, 24)
 416#define DWC3_GFLADJ_240MHZDECR_PLS1		BIT(31)
 417
 418/* Global User Control Register*/
 419#define DWC3_GUCTL_REFCLKPER_MASK		0xffc00000
 420#define DWC3_GUCTL_REFCLKPER_SEL		22
 421
 422/* Global User Control Register 2 */
 423#define DWC3_GUCTL2_RST_ACTBITLATER		BIT(14)
 424#define DWC3_GUCTL2_LC_TIMER			BIT(19)
 425
 426/* Global User Control Register 3 */
 427#define DWC3_GUCTL3_SPLITDISABLE		BIT(14)
 428
 429/* Device Configuration Register */
 430#define DWC3_DCFG_NUMLANES(n)	(((n) & 0x3) << 30) /* DWC_usb32 only */
 431
 432#define DWC3_DCFG_DEVADDR(addr)	((addr) << 3)
 433#define DWC3_DCFG_DEVADDR_MASK	DWC3_DCFG_DEVADDR(0x7f)
 434
 435#define DWC3_DCFG_SPEED_MASK	(7 << 0)
 436#define DWC3_DCFG_SUPERSPEED_PLUS (5 << 0)  /* DWC_usb31 only */
 437#define DWC3_DCFG_SUPERSPEED	(4 << 0)
 438#define DWC3_DCFG_HIGHSPEED	(0 << 0)
 439#define DWC3_DCFG_FULLSPEED	BIT(0)
 
 440
 441#define DWC3_DCFG_NUMP_SHIFT	17
 442#define DWC3_DCFG_NUMP(n)	(((n) >> DWC3_DCFG_NUMP_SHIFT) & 0x1f)
 443#define DWC3_DCFG_NUMP_MASK	(0x1f << DWC3_DCFG_NUMP_SHIFT)
 444#define DWC3_DCFG_LPM_CAP	BIT(22)
 445#define DWC3_DCFG_IGNSTRMPP	BIT(23)
 446
 447/* Device Control Register */
 448#define DWC3_DCTL_RUN_STOP	BIT(31)
 449#define DWC3_DCTL_CSFTRST	BIT(30)
 450#define DWC3_DCTL_LSFTRST	BIT(29)
 451
 452#define DWC3_DCTL_HIRD_THRES_MASK	(0x1f << 24)
 453#define DWC3_DCTL_HIRD_THRES(n)	((n) << 24)
 454
 455#define DWC3_DCTL_APPL1RES	BIT(23)
 456
 457/* These apply for core versions 1.87a and earlier */
 458#define DWC3_DCTL_TRGTULST_MASK		(0x0f << 17)
 459#define DWC3_DCTL_TRGTULST(n)		((n) << 17)
 460#define DWC3_DCTL_TRGTULST_U2		(DWC3_DCTL_TRGTULST(2))
 461#define DWC3_DCTL_TRGTULST_U3		(DWC3_DCTL_TRGTULST(3))
 462#define DWC3_DCTL_TRGTULST_SS_DIS	(DWC3_DCTL_TRGTULST(4))
 463#define DWC3_DCTL_TRGTULST_RX_DET	(DWC3_DCTL_TRGTULST(5))
 464#define DWC3_DCTL_TRGTULST_SS_INACT	(DWC3_DCTL_TRGTULST(6))
 465
 466/* These apply for core versions 1.94a and later */
 467#define DWC3_DCTL_NYET_THRES_MASK	(0xf << 20)
 468#define DWC3_DCTL_NYET_THRES(n)		(((n) & 0xf) << 20)
 469
 470#define DWC3_DCTL_KEEP_CONNECT		BIT(19)
 471#define DWC3_DCTL_L1_HIBER_EN		BIT(18)
 472#define DWC3_DCTL_CRS			BIT(17)
 473#define DWC3_DCTL_CSS			BIT(16)
 474
 475#define DWC3_DCTL_INITU2ENA		BIT(12)
 476#define DWC3_DCTL_ACCEPTU2ENA		BIT(11)
 477#define DWC3_DCTL_INITU1ENA		BIT(10)
 478#define DWC3_DCTL_ACCEPTU1ENA		BIT(9)
 479#define DWC3_DCTL_TSTCTRL_MASK		(0xf << 1)
 480
 481#define DWC3_DCTL_ULSTCHNGREQ_MASK	(0x0f << 5)
 482#define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
 483
 484#define DWC3_DCTL_ULSTCHNG_NO_ACTION	(DWC3_DCTL_ULSTCHNGREQ(0))
 485#define DWC3_DCTL_ULSTCHNG_SS_DISABLED	(DWC3_DCTL_ULSTCHNGREQ(4))
 486#define DWC3_DCTL_ULSTCHNG_RX_DETECT	(DWC3_DCTL_ULSTCHNGREQ(5))
 487#define DWC3_DCTL_ULSTCHNG_SS_INACTIVE	(DWC3_DCTL_ULSTCHNGREQ(6))
 488#define DWC3_DCTL_ULSTCHNG_RECOVERY	(DWC3_DCTL_ULSTCHNGREQ(8))
 489#define DWC3_DCTL_ULSTCHNG_COMPLIANCE	(DWC3_DCTL_ULSTCHNGREQ(10))
 490#define DWC3_DCTL_ULSTCHNG_LOOPBACK	(DWC3_DCTL_ULSTCHNGREQ(11))
 491
 492/* Device Event Enable Register */
 493#define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN	BIT(12)
 494#define DWC3_DEVTEN_EVNTOVERFLOWEN	BIT(11)
 495#define DWC3_DEVTEN_CMDCMPLTEN		BIT(10)
 496#define DWC3_DEVTEN_ERRTICERREN		BIT(9)
 497#define DWC3_DEVTEN_SOFEN		BIT(7)
 498#define DWC3_DEVTEN_U3L2L1SUSPEN	BIT(6)
 499#define DWC3_DEVTEN_HIBERNATIONREQEVTEN	BIT(5)
 500#define DWC3_DEVTEN_WKUPEVTEN		BIT(4)
 501#define DWC3_DEVTEN_ULSTCNGEN		BIT(3)
 502#define DWC3_DEVTEN_CONNECTDONEEN	BIT(2)
 503#define DWC3_DEVTEN_USBRSTEN		BIT(1)
 504#define DWC3_DEVTEN_DISCONNEVTEN	BIT(0)
 505
 506#define DWC3_DSTS_CONNLANES(n)		(((n) >> 30) & 0x3) /* DWC_usb32 only */
 507
 508/* Device Status Register */
 509#define DWC3_DSTS_DCNRD			BIT(29)
 510
 511/* This applies for core versions 1.87a and earlier */
 512#define DWC3_DSTS_PWRUPREQ		BIT(24)
 513
 514/* These apply for core versions 1.94a and later */
 515#define DWC3_DSTS_RSS			BIT(25)
 516#define DWC3_DSTS_SSS			BIT(24)
 517
 518#define DWC3_DSTS_COREIDLE		BIT(23)
 519#define DWC3_DSTS_DEVCTRLHLT		BIT(22)
 520
 521#define DWC3_DSTS_USBLNKST_MASK		(0x0f << 18)
 522#define DWC3_DSTS_USBLNKST(n)		(((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)
 523
 524#define DWC3_DSTS_RXFIFOEMPTY		BIT(17)
 525
 526#define DWC3_DSTS_SOFFN_MASK		(0x3fff << 3)
 527#define DWC3_DSTS_SOFFN(n)		(((n) & DWC3_DSTS_SOFFN_MASK) >> 3)
 528
 529#define DWC3_DSTS_CONNECTSPD		(7 << 0)
 530
 531#define DWC3_DSTS_SUPERSPEED_PLUS	(5 << 0) /* DWC_usb31 only */
 532#define DWC3_DSTS_SUPERSPEED		(4 << 0)
 533#define DWC3_DSTS_HIGHSPEED		(0 << 0)
 534#define DWC3_DSTS_FULLSPEED		BIT(0)
 
 535
 536/* Device Generic Command Register */
 537#define DWC3_DGCMD_SET_LMP		0x01
 538#define DWC3_DGCMD_SET_PERIODIC_PAR	0x02
 539#define DWC3_DGCMD_XMIT_FUNCTION	0x03
 540
 541/* These apply for core versions 1.94a and later */
 542#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO	0x04
 543#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI	0x05
 544
 545#define DWC3_DGCMD_SELECTED_FIFO_FLUSH	0x09
 546#define DWC3_DGCMD_ALL_FIFO_FLUSH	0x0a
 547#define DWC3_DGCMD_SET_ENDPOINT_NRDY	0x0c
 548#define DWC3_DGCMD_SET_ENDPOINT_PRIME	0x0d
 549#define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK	0x10
 550#define DWC3_DGCMD_DEV_NOTIFICATION	0x07
 551
 552#define DWC3_DGCMD_STATUS(n)		(((n) >> 12) & 0x0F)
 553#define DWC3_DGCMD_CMDACT		BIT(10)
 554#define DWC3_DGCMD_CMDIOC		BIT(8)
 555
 556/* Device Generic Command Parameter Register */
 557#define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT	BIT(0)
 558#define DWC3_DGCMDPAR_FIFO_NUM(n)		((n) << 0)
 559#define DWC3_DGCMDPAR_RX_FIFO			(0 << 5)
 560#define DWC3_DGCMDPAR_TX_FIFO			BIT(5)
 561#define DWC3_DGCMDPAR_LOOPBACK_DIS		(0 << 0)
 562#define DWC3_DGCMDPAR_LOOPBACK_ENA		BIT(0)
 563#define DWC3_DGCMDPAR_DN_FUNC_WAKE		BIT(0)
 564#define DWC3_DGCMDPAR_INTF_SEL(n)		((n) << 4)
 565
 566/* Device Endpoint Command Register */
 567#define DWC3_DEPCMD_PARAM_SHIFT		16
 568#define DWC3_DEPCMD_PARAM(x)		((x) << DWC3_DEPCMD_PARAM_SHIFT)
 569#define DWC3_DEPCMD_GET_RSC_IDX(x)	(((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
 570#define DWC3_DEPCMD_STATUS(x)		(((x) >> 12) & 0x0F)
 571#define DWC3_DEPCMD_HIPRI_FORCERM	BIT(11)
 572#define DWC3_DEPCMD_CLEARPENDIN		BIT(11)
 573#define DWC3_DEPCMD_CMDACT		BIT(10)
 574#define DWC3_DEPCMD_CMDIOC		BIT(8)
 575
 576#define DWC3_DEPCMD_DEPSTARTCFG		(0x09 << 0)
 577#define DWC3_DEPCMD_ENDTRANSFER		(0x08 << 0)
 578#define DWC3_DEPCMD_UPDATETRANSFER	(0x07 << 0)
 579#define DWC3_DEPCMD_STARTTRANSFER	(0x06 << 0)
 580#define DWC3_DEPCMD_CLEARSTALL		(0x05 << 0)
 581#define DWC3_DEPCMD_SETSTALL		(0x04 << 0)
 582/* This applies for core versions 1.90a and earlier */
 583#define DWC3_DEPCMD_GETSEQNUMBER	(0x03 << 0)
 584/* This applies for core versions 1.94a and later */
 585#define DWC3_DEPCMD_GETEPSTATE		(0x03 << 0)
 586#define DWC3_DEPCMD_SETTRANSFRESOURCE	(0x02 << 0)
 587#define DWC3_DEPCMD_SETEPCONFIG		(0x01 << 0)
 588
 589#define DWC3_DEPCMD_CMD(x)		((x) & 0xf)
 590
 591/* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
 592#define DWC3_DALEPENA_EP(n)		BIT(n)
 593
 594/* DWC_usb32 DCFG1 config */
 595#define DWC3_DCFG1_DIS_MST_ENH		BIT(1)
 596
 597#define DWC3_DEPCMD_TYPE_CONTROL	0
 598#define DWC3_DEPCMD_TYPE_ISOC		1
 599#define DWC3_DEPCMD_TYPE_BULK		2
 600#define DWC3_DEPCMD_TYPE_INTR		3
 601
 602#define DWC3_DEV_IMOD_COUNT_SHIFT	16
 603#define DWC3_DEV_IMOD_COUNT_MASK	(0xffff << 16)
 604#define DWC3_DEV_IMOD_INTERVAL_SHIFT	0
 605#define DWC3_DEV_IMOD_INTERVAL_MASK	(0xffff << 0)
 606
 607/* OTG Configuration Register */
 608#define DWC3_OCFG_DISPWRCUTTOFF		BIT(5)
 609#define DWC3_OCFG_HIBDISMASK		BIT(4)
 610#define DWC3_OCFG_SFTRSTMASK		BIT(3)
 611#define DWC3_OCFG_OTGVERSION		BIT(2)
 612#define DWC3_OCFG_HNPCAP		BIT(1)
 613#define DWC3_OCFG_SRPCAP		BIT(0)
 614
 615/* OTG CTL Register */
 616#define DWC3_OCTL_OTG3GOERR		BIT(7)
 617#define DWC3_OCTL_PERIMODE		BIT(6)
 618#define DWC3_OCTL_PRTPWRCTL		BIT(5)
 619#define DWC3_OCTL_HNPREQ		BIT(4)
 620#define DWC3_OCTL_SESREQ		BIT(3)
 621#define DWC3_OCTL_TERMSELIDPULSE	BIT(2)
 622#define DWC3_OCTL_DEVSETHNPEN		BIT(1)
 623#define DWC3_OCTL_HSTSETHNPEN		BIT(0)
 624
 625/* OTG Event Register */
 626#define DWC3_OEVT_DEVICEMODE		BIT(31)
 627#define DWC3_OEVT_XHCIRUNSTPSET		BIT(27)
 628#define DWC3_OEVT_DEVRUNSTPSET		BIT(26)
 629#define DWC3_OEVT_HIBENTRY		BIT(25)
 630#define DWC3_OEVT_CONIDSTSCHNG		BIT(24)
 631#define DWC3_OEVT_HRRCONFNOTIF		BIT(23)
 632#define DWC3_OEVT_HRRINITNOTIF		BIT(22)
 633#define DWC3_OEVT_ADEVIDLE		BIT(21)
 634#define DWC3_OEVT_ADEVBHOSTEND		BIT(20)
 635#define DWC3_OEVT_ADEVHOST		BIT(19)
 636#define DWC3_OEVT_ADEVHNPCHNG		BIT(18)
 637#define DWC3_OEVT_ADEVSRPDET		BIT(17)
 638#define DWC3_OEVT_ADEVSESSENDDET	BIT(16)
 639#define DWC3_OEVT_BDEVBHOSTEND		BIT(11)
 640#define DWC3_OEVT_BDEVHNPCHNG		BIT(10)
 641#define DWC3_OEVT_BDEVSESSVLDDET	BIT(9)
 642#define DWC3_OEVT_BDEVVBUSCHNG		BIT(8)
 643#define DWC3_OEVT_BSESSVLD		BIT(3)
 644#define DWC3_OEVT_HSTNEGSTS		BIT(2)
 645#define DWC3_OEVT_SESREQSTS		BIT(1)
 646#define DWC3_OEVT_ERROR			BIT(0)
 647
 648/* OTG Event Enable Register */
 649#define DWC3_OEVTEN_XHCIRUNSTPSETEN	BIT(27)
 650#define DWC3_OEVTEN_DEVRUNSTPSETEN	BIT(26)
 651#define DWC3_OEVTEN_HIBENTRYEN		BIT(25)
 652#define DWC3_OEVTEN_CONIDSTSCHNGEN	BIT(24)
 653#define DWC3_OEVTEN_HRRCONFNOTIFEN	BIT(23)
 654#define DWC3_OEVTEN_HRRINITNOTIFEN	BIT(22)
 655#define DWC3_OEVTEN_ADEVIDLEEN		BIT(21)
 656#define DWC3_OEVTEN_ADEVBHOSTENDEN	BIT(20)
 657#define DWC3_OEVTEN_ADEVHOSTEN		BIT(19)
 658#define DWC3_OEVTEN_ADEVHNPCHNGEN	BIT(18)
 659#define DWC3_OEVTEN_ADEVSRPDETEN	BIT(17)
 660#define DWC3_OEVTEN_ADEVSESSENDDETEN	BIT(16)
 661#define DWC3_OEVTEN_BDEVBHOSTENDEN	BIT(11)
 662#define DWC3_OEVTEN_BDEVHNPCHNGEN	BIT(10)
 663#define DWC3_OEVTEN_BDEVSESSVLDDETEN	BIT(9)
 664#define DWC3_OEVTEN_BDEVVBUSCHNGEN	BIT(8)
 665
 666/* OTG Status Register */
 667#define DWC3_OSTS_DEVRUNSTP		BIT(13)
 668#define DWC3_OSTS_XHCIRUNSTP		BIT(12)
 669#define DWC3_OSTS_PERIPHERALSTATE	BIT(4)
 670#define DWC3_OSTS_XHCIPRTPOWER		BIT(3)
 671#define DWC3_OSTS_BSESVLD		BIT(2)
 672#define DWC3_OSTS_VBUSVLD		BIT(1)
 673#define DWC3_OSTS_CONIDSTS		BIT(0)
 674
 675/* Force Gen1 speed on Gen2 link */
 676#define DWC3_LLUCTL_FORCE_GEN1		BIT(10)
 677
 678/* Structures */
 679
 680struct dwc3_trb;
 681
 682/**
 683 * struct dwc3_event_buffer - Software event buffer representation
 684 * @buf: _THE_ buffer
 685 * @cache: The buffer cache used in the threaded interrupt
 686 * @length: size of this buffer
 687 * @lpos: event offset
 688 * @count: cache of last read event count register
 689 * @flags: flags related to this event buffer
 690 * @dma: dma_addr_t
 691 * @dwc: pointer to DWC controller
 692 */
 693struct dwc3_event_buffer {
 694	void			*buf;
 695	void			*cache;
 696	unsigned int		length;
 697	unsigned int		lpos;
 698	unsigned int		count;
 699	unsigned int		flags;
 700
 701#define DWC3_EVENT_PENDING	BIT(0)
 702
 703	dma_addr_t		dma;
 704
 705	struct dwc3		*dwc;
 706};
 707
 708#define DWC3_EP_FLAG_STALLED	BIT(0)
 709#define DWC3_EP_FLAG_WEDGED	BIT(1)
 710
 711#define DWC3_EP_DIRECTION_TX	true
 712#define DWC3_EP_DIRECTION_RX	false
 713
 714#define DWC3_TRB_NUM		256
 715
 716/**
 717 * struct dwc3_ep - device side endpoint representation
 718 * @endpoint: usb endpoint
 719 * @cancelled_list: list of cancelled requests for this endpoint
 720 * @pending_list: list of pending requests for this endpoint
 721 * @started_list: list of started requests on this endpoint
 722 * @regs: pointer to first endpoint register
 723 * @trb_pool: array of transaction buffers
 724 * @trb_pool_dma: dma address of @trb_pool
 725 * @trb_enqueue: enqueue 'pointer' into TRB array
 726 * @trb_dequeue: dequeue 'pointer' into TRB array
 727 * @dwc: pointer to DWC controller
 728 * @saved_state: ep state saved during hibernation
 729 * @flags: endpoint flags (wedged, stalled, ...)
 730 * @number: endpoint number (1 - 15)
 731 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK
 732 * @resource_index: Resource transfer index
 733 * @frame_number: set to the frame number we want this transfer to start (ISOC)
 734 * @interval: the interval on which the ISOC transfer is started
 735 * @name: a human readable name e.g. ep1out-bulk
 736 * @direction: true for TX, false for RX
 737 * @stream_capable: true when streams are enabled
 738 * @combo_num: the test combination BIT[15:14] of the frame number to test
 739 *		isochronous START TRANSFER command failure workaround
 740 * @start_cmd_status: the status of testing START TRANSFER command with
 741 *		combo_num = 'b00
 742 */
 743struct dwc3_ep {
 744	struct usb_ep		endpoint;
 745	struct list_head	cancelled_list;
 746	struct list_head	pending_list;
 747	struct list_head	started_list;
 748
 749	void __iomem		*regs;
 750
 751	struct dwc3_trb		*trb_pool;
 752	dma_addr_t		trb_pool_dma;
 753	struct dwc3		*dwc;
 754
 755	u32			saved_state;
 756	unsigned int		flags;
 757#define DWC3_EP_ENABLED			BIT(0)
 758#define DWC3_EP_STALL			BIT(1)
 759#define DWC3_EP_WEDGE			BIT(2)
 760#define DWC3_EP_TRANSFER_STARTED	BIT(3)
 761#define DWC3_EP_END_TRANSFER_PENDING	BIT(4)
 762#define DWC3_EP_PENDING_REQUEST		BIT(5)
 763#define DWC3_EP_DELAY_START		BIT(6)
 764#define DWC3_EP_WAIT_TRANSFER_COMPLETE	BIT(7)
 765#define DWC3_EP_IGNORE_NEXT_NOSTREAM	BIT(8)
 766#define DWC3_EP_FORCE_RESTART_STREAM	BIT(9)
 767#define DWC3_EP_FIRST_STREAM_PRIMED	BIT(10)
 768#define DWC3_EP_PENDING_CLEAR_STALL	BIT(11)
 769#define DWC3_EP_TXFIFO_RESIZED		BIT(12)
 770#define DWC3_EP_DELAY_STOP             BIT(13)
 771#define DWC3_EP_RESOURCE_ALLOCATED	BIT(14)
 772
 773	/* This last one is specific to EP0 */
 774#define DWC3_EP0_DIR_IN			BIT(31)
 775
 776	/*
 777	 * IMPORTANT: we *know* we have 256 TRBs in our @trb_pool, so we will
 778	 * use a u8 type here. If anybody decides to increase number of TRBs to
 779	 * anything larger than 256 - I can't see why people would want to do
 780	 * this though - then this type needs to be changed.
 781	 *
 782	 * By using u8 types we ensure that our % operator when incrementing
 783	 * enqueue and dequeue get optimized away by the compiler.
 784	 */
 785	u8			trb_enqueue;
 786	u8			trb_dequeue;
 787
 788	u8			number;
 789	u8			type;
 790	u8			resource_index;
 791	u32			frame_number;
 792	u32			interval;
 793
 794	char			name[20];
 795
 796	unsigned		direction:1;
 797	unsigned		stream_capable:1;
 798
 799	/* For isochronous START TRANSFER workaround only */
 800	u8			combo_num;
 801	int			start_cmd_status;
 802};
 803
 804enum dwc3_phy {
 805	DWC3_PHY_UNKNOWN = 0,
 806	DWC3_PHY_USB3,
 807	DWC3_PHY_USB2,
 808};
 809
 810enum dwc3_ep0_next {
 811	DWC3_EP0_UNKNOWN = 0,
 812	DWC3_EP0_COMPLETE,
 813	DWC3_EP0_NRDY_DATA,
 814	DWC3_EP0_NRDY_STATUS,
 815};
 816
 817enum dwc3_ep0_state {
 818	EP0_UNCONNECTED		= 0,
 819	EP0_SETUP_PHASE,
 820	EP0_DATA_PHASE,
 821	EP0_STATUS_PHASE,
 822};
 823
 824enum dwc3_link_state {
 825	/* In SuperSpeed */
 826	DWC3_LINK_STATE_U0		= 0x00, /* in HS, means ON */
 827	DWC3_LINK_STATE_U1		= 0x01,
 828	DWC3_LINK_STATE_U2		= 0x02, /* in HS, means SLEEP */
 829	DWC3_LINK_STATE_U3		= 0x03, /* in HS, means SUSPEND */
 830	DWC3_LINK_STATE_SS_DIS		= 0x04,
 831	DWC3_LINK_STATE_RX_DET		= 0x05, /* in HS, means Early Suspend */
 832	DWC3_LINK_STATE_SS_INACT	= 0x06,
 833	DWC3_LINK_STATE_POLL		= 0x07,
 834	DWC3_LINK_STATE_RECOV		= 0x08,
 835	DWC3_LINK_STATE_HRESET		= 0x09,
 836	DWC3_LINK_STATE_CMPLY		= 0x0a,
 837	DWC3_LINK_STATE_LPBK		= 0x0b,
 838	DWC3_LINK_STATE_RESET		= 0x0e,
 839	DWC3_LINK_STATE_RESUME		= 0x0f,
 840	DWC3_LINK_STATE_MASK		= 0x0f,
 841};
 842
 843/* TRB Length, PCM and Status */
 844#define DWC3_TRB_SIZE_MASK	(0x00ffffff)
 845#define DWC3_TRB_SIZE_LENGTH(n)	((n) & DWC3_TRB_SIZE_MASK)
 846#define DWC3_TRB_SIZE_PCM1(n)	(((n) & 0x03) << 24)
 847#define DWC3_TRB_SIZE_TRBSTS(n)	(((n) & (0x0f << 28)) >> 28)
 848
 849#define DWC3_TRBSTS_OK			0
 850#define DWC3_TRBSTS_MISSED_ISOC		1
 851#define DWC3_TRBSTS_SETUP_PENDING	2
 852#define DWC3_TRB_STS_XFER_IN_PROG	4
 853
 854/* TRB Control */
 855#define DWC3_TRB_CTRL_HWO		BIT(0)
 856#define DWC3_TRB_CTRL_LST		BIT(1)
 857#define DWC3_TRB_CTRL_CHN		BIT(2)
 858#define DWC3_TRB_CTRL_CSP		BIT(3)
 859#define DWC3_TRB_CTRL_TRBCTL(n)		(((n) & 0x3f) << 4)
 860#define DWC3_TRB_CTRL_ISP_IMI		BIT(10)
 861#define DWC3_TRB_CTRL_IOC		BIT(11)
 862#define DWC3_TRB_CTRL_SID_SOFN(n)	(((n) & 0xffff) << 14)
 863#define DWC3_TRB_CTRL_GET_SID_SOFN(n)	(((n) & (0xffff << 14)) >> 14)
 864
 865#define DWC3_TRBCTL_TYPE(n)		((n) & (0x3f << 4))
 866#define DWC3_TRBCTL_NORMAL		DWC3_TRB_CTRL_TRBCTL(1)
 867#define DWC3_TRBCTL_CONTROL_SETUP	DWC3_TRB_CTRL_TRBCTL(2)
 868#define DWC3_TRBCTL_CONTROL_STATUS2	DWC3_TRB_CTRL_TRBCTL(3)
 869#define DWC3_TRBCTL_CONTROL_STATUS3	DWC3_TRB_CTRL_TRBCTL(4)
 870#define DWC3_TRBCTL_CONTROL_DATA	DWC3_TRB_CTRL_TRBCTL(5)
 871#define DWC3_TRBCTL_ISOCHRONOUS_FIRST	DWC3_TRB_CTRL_TRBCTL(6)
 872#define DWC3_TRBCTL_ISOCHRONOUS		DWC3_TRB_CTRL_TRBCTL(7)
 873#define DWC3_TRBCTL_LINK_TRB		DWC3_TRB_CTRL_TRBCTL(8)
 874
 875/**
 876 * struct dwc3_trb - transfer request block (hw format)
 877 * @bpl: DW0-3
 878 * @bph: DW4-7
 879 * @size: DW8-B
 880 * @ctrl: DWC-F
 881 */
 882struct dwc3_trb {
 883	u32		bpl;
 884	u32		bph;
 885	u32		size;
 886	u32		ctrl;
 887} __packed;
 888
 889/**
 890 * struct dwc3_hwparams - copy of HWPARAMS registers
 891 * @hwparams0: GHWPARAMS0
 892 * @hwparams1: GHWPARAMS1
 893 * @hwparams2: GHWPARAMS2
 894 * @hwparams3: GHWPARAMS3
 895 * @hwparams4: GHWPARAMS4
 896 * @hwparams5: GHWPARAMS5
 897 * @hwparams6: GHWPARAMS6
 898 * @hwparams7: GHWPARAMS7
 899 * @hwparams8: GHWPARAMS8
 900 * @hwparams9: GHWPARAMS9
 901 */
 902struct dwc3_hwparams {
 903	u32	hwparams0;
 904	u32	hwparams1;
 905	u32	hwparams2;
 906	u32	hwparams3;
 907	u32	hwparams4;
 908	u32	hwparams5;
 909	u32	hwparams6;
 910	u32	hwparams7;
 911	u32	hwparams8;
 912	u32	hwparams9;
 913};
 914
 915/* HWPARAMS0 */
 916#define DWC3_MODE(n)		((n) & 0x7)
 917
 
 
 918/* HWPARAMS1 */
 919#define DWC3_SPRAM_TYPE(n)	(((n) >> 23) & 1)
 920#define DWC3_NUM_INT(n)		(((n) & (0x3f << 15)) >> 15)
 921
 922/* HWPARAMS3 */
 923#define DWC3_NUM_IN_EPS_MASK	(0x1f << 18)
 924#define DWC3_NUM_EPS_MASK	(0x3f << 12)
 925#define DWC3_NUM_EPS(p)		(((p)->hwparams3 &		\
 926			(DWC3_NUM_EPS_MASK)) >> 12)
 927#define DWC3_NUM_IN_EPS(p)	(((p)->hwparams3 &		\
 928			(DWC3_NUM_IN_EPS_MASK)) >> 18)
 929
 930/* HWPARAMS6 */
 931#define DWC3_RAM0_DEPTH(n)	(((n) & (0xffff0000)) >> 16)
 932
 933/* HWPARAMS7 */
 934#define DWC3_RAM1_DEPTH(n)	((n) & 0xffff)
 935
 936/* HWPARAMS9 */
 937#define DWC3_MST_CAPABLE(p)	(!!((p)->hwparams9 &		\
 938			DWC3_GHWPARAMS9_DEV_MST))
 939
 940/**
 941 * struct dwc3_request - representation of a transfer request
 942 * @request: struct usb_request to be transferred
 943 * @list: a list_head used for request queueing
 944 * @dep: struct dwc3_ep owning this request
 
 945 * @start_sg: pointer to the sg which should be queued next
 946 * @num_pending_sgs: counter to pending sgs
 
 947 * @remaining: amount of data remaining
 948 * @status: internal dwc3 request status tracking
 949 * @epnum: endpoint number to which this request refers
 950 * @trb: pointer to struct dwc3_trb
 951 * @trb_dma: DMA address of @trb
 952 * @num_trbs: number of TRBs used by this request
 
 
 953 * @direction: IN or OUT direction flag
 954 * @mapped: true when request has been dma-mapped
 955 */
 956struct dwc3_request {
 957	struct usb_request	request;
 958	struct list_head	list;
 959	struct dwc3_ep		*dep;
 960	struct scatterlist	*sg;
 961	struct scatterlist	*start_sg;
 962
 963	unsigned int		num_pending_sgs;
 964	unsigned int		remaining;
 
 965
 966	unsigned int		status;
 967#define DWC3_REQUEST_STATUS_QUEUED		0
 968#define DWC3_REQUEST_STATUS_STARTED		1
 969#define DWC3_REQUEST_STATUS_DISCONNECTED	2
 970#define DWC3_REQUEST_STATUS_DEQUEUED		3
 971#define DWC3_REQUEST_STATUS_STALLED		4
 972#define DWC3_REQUEST_STATUS_COMPLETED		5
 973#define DWC3_REQUEST_STATUS_UNKNOWN		-1
 974
 975	u8			epnum;
 976	struct dwc3_trb		*trb;
 977	dma_addr_t		trb_dma;
 978
 979	unsigned int		num_trbs;
 980
 981	unsigned int		direction:1;
 982	unsigned int		mapped:1;
 
 983};
 984
 985/*
 986 * struct dwc3_scratchpad_array - hibernation scratchpad array
 987 * (format defined by hw)
 988 */
 989struct dwc3_scratchpad_array {
 990	__le64	dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS];
 991};
 992
 993/**
 994 * struct dwc3 - representation of our controller
 995 * @drd_work: workqueue used for role swapping
 996 * @ep0_trb: trb which is used for the ctrl_req
 997 * @bounce: address of bounce buffer
 
 998 * @setup_buf: used while precessing STD USB requests
 999 * @ep0_trb_addr: dma address of @ep0_trb
1000 * @bounce_addr: dma address of @bounce
1001 * @ep0_usb_req: dummy req used while handling STD USB requests
 
1002 * @ep0_in_setup: one control transfer is completed and enter setup phase
1003 * @lock: for synchronizing
1004 * @mutex: for mode switching
1005 * @dev: pointer to our struct device
1006 * @sysdev: pointer to the DMA-capable device
1007 * @xhci: pointer to our xHCI child
1008 * @xhci_resources: struct resources for our @xhci child
1009 * @ev_buf: struct dwc3_event_buffer pointer
1010 * @eps: endpoint array
1011 * @gadget: device side representation of the peripheral controller
1012 * @gadget_driver: pointer to the gadget driver
1013 * @bus_clk: clock for accessing the registers
1014 * @ref_clk: reference clock
1015 * @susp_clk: clock used when the SS phy is in low power (S3) state
1016 * @utmi_clk: clock used for USB2 PHY communication
1017 * @pipe_clk: clock used for USB3 PHY communication
1018 * @reset: reset control
1019 * @regs: base address for our registers
1020 * @regs_size: address space size
1021 * @fladj: frame length adjustment
1022 * @ref_clk_per: reference clock period configuration
1023 * @irq_gadget: peripheral controller's IRQ number
1024 * @otg_irq: IRQ number for OTG IRQs
1025 * @current_otg_role: current role of operation while using the OTG block
1026 * @desired_otg_role: desired role of operation while using the OTG block
1027 * @otg_restart_host: flag that OTG controller needs to restart host
 
1028 * @u1u2: only used on revisions <1.83a for workaround
1029 * @maximum_speed: maximum speed requested (mainly for testing purposes)
1030 * @max_ssp_rate: SuperSpeed Plus maximum signaling rate and lane count
1031 * @gadget_max_speed: maximum gadget speed requested
1032 * @gadget_ssp_rate: Gadget driver's maximum supported SuperSpeed Plus signaling
1033 *			rate and lane count.
1034 * @ip: controller's ID
1035 * @revision: controller's version of an IP
1036 * @version_type: VERSIONTYPE register contents, a sub release of a revision
1037 * @dr_mode: requested mode of operation
1038 * @current_dr_role: current role of operation when in dual-role mode
1039 * @desired_dr_role: desired role of operation when in dual-role mode
1040 * @edev: extcon handle
1041 * @edev_nb: extcon notifier
1042 * @hsphy_mode: UTMI phy mode, one of following:
1043 *		- USBPHY_INTERFACE_MODE_UTMI
1044 *		- USBPHY_INTERFACE_MODE_UTMIW
1045 * @role_sw: usb_role_switch handle
1046 * @role_switch_default_mode: default operation mode of controller while
1047 *			usb role is USB_ROLE_NONE.
1048 * @usb_psy: pointer to power supply interface.
1049 * @usb2_phy: pointer to USB2 PHY
1050 * @usb3_phy: pointer to USB3 PHY
1051 * @usb2_generic_phy: pointer to array of USB2 PHYs
1052 * @usb3_generic_phy: pointer to array of USB3 PHYs
1053 * @num_usb2_ports: number of USB2 ports
1054 * @num_usb3_ports: number of USB3 ports
1055 * @phys_ready: flag to indicate that PHYs are ready
1056 * @ulpi: pointer to ulpi interface
1057 * @ulpi_ready: flag to indicate that ULPI is initialized
1058 * @u2sel: parameter from Set SEL request.
1059 * @u2pel: parameter from Set SEL request.
1060 * @u1sel: parameter from Set SEL request.
1061 * @u1pel: parameter from Set SEL request.
1062 * @num_eps: number of endpoints
1063 * @ep0_next_event: hold the next expected event
1064 * @ep0state: state of endpoint zero
1065 * @link_state: link state
1066 * @speed: device speed (super, high, full, low)
1067 * @hwparams: copy of hwparams registers
 
1068 * @regset: debugfs pointer to regdump file
1069 * @dbg_lsp_select: current debug lsp mux register selection
1070 * @test_mode: true when we're entering a USB test mode
1071 * @test_mode_nr: test feature selector
1072 * @lpm_nyet_threshold: LPM NYET response threshold
1073 * @hird_threshold: HIRD threshold
1074 * @rx_thr_num_pkt: USB receive packet count
1075 * @rx_max_burst: max USB receive burst size
1076 * @tx_thr_num_pkt: USB transmit packet count
1077 * @tx_max_burst: max USB transmit burst size
1078 * @rx_thr_num_pkt_prd: periodic ESS receive packet count
1079 * @rx_max_burst_prd: max periodic ESS receive burst size
1080 * @tx_thr_num_pkt_prd: periodic ESS transmit packet count
1081 * @tx_max_burst_prd: max periodic ESS transmit burst size
1082 * @tx_fifo_resize_max_num: max number of fifos allocated during txfifo resize
1083 * @clear_stall_protocol: endpoint number that requires a delayed status phase
1084 * @hsphy_interface: "utmi" or "ulpi"
1085 * @connected: true when we're connected to a host, false otherwise
1086 * @softconnect: true when gadget connect is called, false when disconnect runs
1087 * @delayed_status: true when gadget driver asks for delayed status
1088 * @ep0_bounced: true when we used bounce buffer
1089 * @ep0_expect_in: true when we expect a DATA IN transfer
 
1090 * @sysdev_is_parent: true when dwc3 device has a parent driver
1091 * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that
1092 *			there's now way for software to detect this in runtime.
1093 * @is_utmi_l1_suspend: the core asserts output signal
1094 *	0	- utmi_sleep_n
1095 *	1	- utmi_l1_suspend_n
1096 * @is_fpga: true when we are using the FPGA board
1097 * @pending_events: true when we have pending IRQs to be handled
1098 * @do_fifo_resize: true when txfifo resizing is enabled for dwc3 endpoints
1099 * @pullups_connected: true when Run/Stop bit is set
1100 * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
1101 * @three_stage_setup: set if we perform a three phase setup
1102 * @dis_start_transfer_quirk: set if start_transfer failure SW workaround is
1103 *			not needed for DWC_usb31 version 1.70a-ea06 and below
1104 * @usb3_lpm_capable: set if hadrware supports Link Power Management
1105 * @usb2_lpm_disable: set to disable usb2 lpm for host
1106 * @usb2_gadget_lpm_disable: set to disable usb2 lpm for gadget
1107 * @disable_scramble_quirk: set if we enable the disable scramble quirk
1108 * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk
1109 * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
1110 * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk
1111 * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk
1112 * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk
1113 * @lfps_filter_quirk: set if we enable LFPS filter quirk
1114 * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk
1115 * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy
1116 * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy
1117 * @dis_enblslpm_quirk: set if we clear enblslpm in GUSB2PHYCFG,
1118 *                      disabling the suspend signal to the PHY.
1119 * @dis_u1_entry_quirk: set if link entering into U1 state needs to be disabled.
1120 * @dis_u2_entry_quirk: set if link entering into U2 state needs to be disabled.
1121 * @dis_rxdet_inp3_quirk: set if we disable Rx.Detect in P3
1122 * @async_callbacks: if set, indicate that async callbacks will be used.
1123 *
1124 * @dis_u2_freeclk_exists_quirk : set if we clear u2_freeclk_exists
1125 *			in GUSB2PHYCFG, specify that USB2 PHY doesn't
1126 *			provide a free-running PHY clock.
1127 * @dis_del_phy_power_chg_quirk: set if we disable delay phy power
1128 *			change quirk.
1129 * @dis_tx_ipgap_linecheck_quirk: set if we disable u2mac linestate
1130 *			check during HS transmit.
1131 * @resume_hs_terminations: Set if we enable quirk for fixing improper crc
1132 *			generation after resume from suspend.
1133 * @ulpi_ext_vbus_drv: Set to confiure the upli chip to drives CPEN pin
1134 *			VBUS with an external supply.
1135 * @parkmode_disable_ss_quirk: set if we need to disable all SuperSpeed
1136 *			instances in park mode.
1137 * @parkmode_disable_hs_quirk: set if we need to disable all HishSpeed
1138 *			instances in park mode.
1139 * @gfladj_refclk_lpm_sel: set if we need to enable SOF/ITP counter
1140 *                          running based on ref_clk
1141 * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
1142 * @tx_de_emphasis: Tx de-emphasis value
1143 *	0	- -6dB de-emphasis
1144 *	1	- -3.5dB de-emphasis
1145 *	2	- No de-emphasis
1146 *	3	- Reserved
1147 * @dis_metastability_quirk: set to disable metastability quirk.
1148 * @dis_split_quirk: set to disable split boundary.
1149 * @sys_wakeup: set if the device may do system wakeup.
1150 * @wakeup_configured: set if the device is configured for remote wakeup.
1151 * @suspended: set to track suspend event due to U3/L2.
1152 * @susphy_state: state of DWC3_GUSB2PHYCFG_SUSPHY + DWC3_GUSB3PIPECTL_SUSPHY
1153 *		  before PM suspend.
1154 * @imod_interval: set the interrupt moderation interval in 250ns
1155 *			increments or 0 to disable.
1156 * @max_cfg_eps: current max number of IN eps used across all USB configs.
1157 * @last_fifo_depth: last fifo depth used to determine next fifo ram start
1158 *		     address.
1159 * @num_ep_resized: carries the current number endpoints which have had its tx
1160 *		    fifo resized.
1161 * @debug_root: root debugfs directory for this device to put its files in.
1162 * @gsbuscfg0_reqinfo: store GSBUSCFG0.DATRDREQINFO, DESRDREQINFO,
1163 *		       DATWRREQINFO, and DESWRREQINFO value passed from
1164 *		       glue driver.
1165 */
1166struct dwc3 {
1167	struct work_struct	drd_work;
1168	struct dwc3_trb		*ep0_trb;
1169	void			*bounce;
 
1170	u8			*setup_buf;
1171	dma_addr_t		ep0_trb_addr;
1172	dma_addr_t		bounce_addr;
 
1173	struct dwc3_request	ep0_usb_req;
1174	struct completion	ep0_in_setup;
1175
1176	/* device lock */
1177	spinlock_t		lock;
1178
1179	/* mode switching lock */
1180	struct mutex		mutex;
1181
1182	struct device		*dev;
1183	struct device		*sysdev;
1184
1185	struct platform_device	*xhci;
1186	struct resource		xhci_resources[DWC3_XHCI_RESOURCES_NUM];
1187
1188	struct dwc3_event_buffer *ev_buf;
1189	struct dwc3_ep		*eps[DWC3_ENDPOINTS_NUM];
1190
1191	struct usb_gadget	*gadget;
1192	struct usb_gadget_driver *gadget_driver;
1193
1194	struct clk		*bus_clk;
1195	struct clk		*ref_clk;
1196	struct clk		*susp_clk;
1197	struct clk		*utmi_clk;
1198	struct clk		*pipe_clk;
1199
1200	struct reset_control	*reset;
1201
1202	struct usb_phy		*usb2_phy;
1203	struct usb_phy		*usb3_phy;
1204
1205	struct phy		*usb2_generic_phy[DWC3_USB2_MAX_PORTS];
1206	struct phy		*usb3_generic_phy[DWC3_USB3_MAX_PORTS];
1207
1208	u8			num_usb2_ports;
1209	u8			num_usb3_ports;
1210
1211	bool			phys_ready;
1212
1213	struct ulpi		*ulpi;
1214	bool			ulpi_ready;
1215
1216	void __iomem		*regs;
1217	size_t			regs_size;
1218
1219	enum usb_dr_mode	dr_mode;
1220	u32			current_dr_role;
1221	u32			desired_dr_role;
1222	struct extcon_dev	*edev;
1223	struct notifier_block	edev_nb;
1224	enum usb_phy_interface	hsphy_mode;
1225	struct usb_role_switch	*role_sw;
1226	enum usb_dr_mode	role_switch_default_mode;
1227
1228	struct power_supply	*usb_psy;
1229
1230	u32			fladj;
1231	u32			ref_clk_per;
1232	u32			irq_gadget;
1233	u32			otg_irq;
1234	u32			current_otg_role;
1235	u32			desired_otg_role;
1236	bool			otg_restart_host;
 
1237	u32			u1u2;
1238	u32			maximum_speed;
1239	u32			gadget_max_speed;
1240	enum usb_ssp_rate	max_ssp_rate;
1241	enum usb_ssp_rate	gadget_ssp_rate;
1242
1243	u32			ip;
1244
1245#define DWC3_IP			0x5533
1246#define DWC31_IP		0x3331
1247#define DWC32_IP		0x3332
1248
 
 
 
 
 
 
 
1249	u32			revision;
1250
1251#define DWC3_REVISION_ANY	0x0
1252#define DWC3_REVISION_173A	0x5533173a
1253#define DWC3_REVISION_175A	0x5533175a
1254#define DWC3_REVISION_180A	0x5533180a
1255#define DWC3_REVISION_183A	0x5533183a
1256#define DWC3_REVISION_185A	0x5533185a
1257#define DWC3_REVISION_187A	0x5533187a
1258#define DWC3_REVISION_188A	0x5533188a
1259#define DWC3_REVISION_190A	0x5533190a
1260#define DWC3_REVISION_194A	0x5533194a
1261#define DWC3_REVISION_200A	0x5533200a
1262#define DWC3_REVISION_202A	0x5533202a
1263#define DWC3_REVISION_210A	0x5533210a
1264#define DWC3_REVISION_220A	0x5533220a
1265#define DWC3_REVISION_230A	0x5533230a
1266#define DWC3_REVISION_240A	0x5533240a
1267#define DWC3_REVISION_250A	0x5533250a
1268#define DWC3_REVISION_260A	0x5533260a
1269#define DWC3_REVISION_270A	0x5533270a
1270#define DWC3_REVISION_280A	0x5533280a
1271#define DWC3_REVISION_290A	0x5533290a
1272#define DWC3_REVISION_300A	0x5533300a
1273#define DWC3_REVISION_310A	0x5533310a
1274#define DWC3_REVISION_320A	0x5533320a
1275#define DWC3_REVISION_330A	0x5533330a
1276
1277#define DWC31_REVISION_ANY	0x0
1278#define DWC31_REVISION_110A	0x3131302a
1279#define DWC31_REVISION_120A	0x3132302a
1280#define DWC31_REVISION_160A	0x3136302a
1281#define DWC31_REVISION_170A	0x3137302a
1282#define DWC31_REVISION_180A	0x3138302a
1283#define DWC31_REVISION_190A	0x3139302a
1284#define DWC31_REVISION_200A	0x3230302a
1285
1286#define DWC32_REVISION_ANY	0x0
1287#define DWC32_REVISION_100A	0x3130302a
1288
1289	u32			version_type;
1290
1291#define DWC31_VERSIONTYPE_ANY		0x0
1292#define DWC31_VERSIONTYPE_EA01		0x65613031
1293#define DWC31_VERSIONTYPE_EA02		0x65613032
1294#define DWC31_VERSIONTYPE_EA03		0x65613033
1295#define DWC31_VERSIONTYPE_EA04		0x65613034
1296#define DWC31_VERSIONTYPE_EA05		0x65613035
1297#define DWC31_VERSIONTYPE_EA06		0x65613036
1298
1299	enum dwc3_ep0_next	ep0_next_event;
1300	enum dwc3_ep0_state	ep0state;
1301	enum dwc3_link_state	link_state;
1302
1303	u16			u2sel;
1304	u16			u2pel;
1305	u8			u1sel;
1306	u8			u1pel;
1307
1308	u8			speed;
1309
1310	u8			num_eps;
1311
1312	struct dwc3_hwparams	hwparams;
 
1313	struct debugfs_regset32	*regset;
1314
1315	u32			dbg_lsp_select;
1316
1317	u8			test_mode;
1318	u8			test_mode_nr;
1319	u8			lpm_nyet_threshold;
1320	u8			hird_threshold;
1321	u8			rx_thr_num_pkt;
1322	u8			rx_max_burst;
1323	u8			tx_thr_num_pkt;
1324	u8			tx_max_burst;
1325	u8			rx_thr_num_pkt_prd;
1326	u8			rx_max_burst_prd;
1327	u8			tx_thr_num_pkt_prd;
1328	u8			tx_max_burst_prd;
1329	u8			tx_fifo_resize_max_num;
1330	u8			clear_stall_protocol;
1331
1332	const char		*hsphy_interface;
1333
1334	unsigned		connected:1;
1335	unsigned		softconnect:1;
1336	unsigned		delayed_status:1;
1337	unsigned		ep0_bounced:1;
1338	unsigned		ep0_expect_in:1;
 
1339	unsigned		sysdev_is_parent:1;
1340	unsigned		has_lpm_erratum:1;
1341	unsigned		is_utmi_l1_suspend:1;
1342	unsigned		is_fpga:1;
1343	unsigned		pending_events:1;
1344	unsigned		do_fifo_resize:1;
1345	unsigned		pullups_connected:1;
1346	unsigned		setup_packet_pending:1;
1347	unsigned		three_stage_setup:1;
1348	unsigned		dis_start_transfer_quirk:1;
1349	unsigned		usb3_lpm_capable:1;
1350	unsigned		usb2_lpm_disable:1;
1351	unsigned		usb2_gadget_lpm_disable:1;
1352
1353	unsigned		disable_scramble_quirk:1;
1354	unsigned		u2exit_lfps_quirk:1;
1355	unsigned		u2ss_inp3_quirk:1;
1356	unsigned		req_p1p2p3_quirk:1;
1357	unsigned                del_p1p2p3_quirk:1;
1358	unsigned		del_phy_power_chg_quirk:1;
1359	unsigned		lfps_filter_quirk:1;
1360	unsigned		rx_detect_poll_quirk:1;
1361	unsigned		dis_u3_susphy_quirk:1;
1362	unsigned		dis_u2_susphy_quirk:1;
1363	unsigned		dis_enblslpm_quirk:1;
1364	unsigned		dis_u1_entry_quirk:1;
1365	unsigned		dis_u2_entry_quirk:1;
1366	unsigned		dis_rxdet_inp3_quirk:1;
1367	unsigned		dis_u2_freeclk_exists_quirk:1;
1368	unsigned		dis_del_phy_power_chg_quirk:1;
1369	unsigned		dis_tx_ipgap_linecheck_quirk:1;
1370	unsigned		resume_hs_terminations:1;
1371	unsigned		ulpi_ext_vbus_drv:1;
1372	unsigned		parkmode_disable_ss_quirk:1;
1373	unsigned		parkmode_disable_hs_quirk:1;
1374	unsigned		gfladj_refclk_lpm_sel:1;
1375
1376	unsigned		tx_de_emphasis_quirk:1;
1377	unsigned		tx_de_emphasis:2;
1378
1379	unsigned		dis_metastability_quirk:1;
1380
1381	unsigned		dis_split_quirk:1;
1382	unsigned		async_callbacks:1;
1383	unsigned		sys_wakeup:1;
1384	unsigned		wakeup_configured:1;
1385	unsigned		suspended:1;
1386	unsigned		susphy_state:1;
1387
1388	u16			imod_interval;
1389
1390	int			max_cfg_eps;
1391	int			last_fifo_depth;
1392	int			num_ep_resized;
1393	struct dentry		*debug_root;
1394	u32			gsbuscfg0_reqinfo;
1395};
1396
1397#define INCRX_BURST_MODE 0
1398#define INCRX_UNDEF_LENGTH_BURST_MODE 1
1399
1400#define work_to_dwc(w)		(container_of((w), struct dwc3, drd_work))
1401
1402/* -------------------------------------------------------------------------- */
1403
1404struct dwc3_event_type {
1405	u32	is_devspec:1;
1406	u32	type:7;
1407	u32	reserved8_31:24;
1408} __packed;
1409
1410#define DWC3_DEPEVT_XFERCOMPLETE	0x01
1411#define DWC3_DEPEVT_XFERINPROGRESS	0x02
1412#define DWC3_DEPEVT_XFERNOTREADY	0x03
1413#define DWC3_DEPEVT_RXTXFIFOEVT		0x04
1414#define DWC3_DEPEVT_STREAMEVT		0x06
1415#define DWC3_DEPEVT_EPCMDCMPLT		0x07
1416
1417/**
1418 * struct dwc3_event_depevt - Device Endpoint Events
1419 * @one_bit: indicates this is an endpoint event (not used)
1420 * @endpoint_number: number of the endpoint
1421 * @endpoint_event: The event we have:
1422 *	0x00	- Reserved
1423 *	0x01	- XferComplete
1424 *	0x02	- XferInProgress
1425 *	0x03	- XferNotReady
1426 *	0x04	- RxTxFifoEvt (IN->Underrun, OUT->Overrun)
1427 *	0x05	- Reserved
1428 *	0x06	- StreamEvt
1429 *	0x07	- EPCmdCmplt
1430 * @reserved11_10: Reserved, don't use.
1431 * @status: Indicates the status of the event. Refer to databook for
1432 *	more information.
1433 * @parameters: Parameters of the current event. Refer to databook for
1434 *	more information.
1435 */
1436struct dwc3_event_depevt {
1437	u32	one_bit:1;
1438	u32	endpoint_number:5;
1439	u32	endpoint_event:4;
1440	u32	reserved11_10:2;
1441	u32	status:4;
1442
1443/* Within XferNotReady */
1444#define DEPEVT_STATUS_TRANSFER_ACTIVE	BIT(3)
1445
1446/* Within XferComplete or XferInProgress */
1447#define DEPEVT_STATUS_BUSERR	BIT(0)
1448#define DEPEVT_STATUS_SHORT	BIT(1)
1449#define DEPEVT_STATUS_IOC	BIT(2)
1450#define DEPEVT_STATUS_LST	BIT(3) /* XferComplete */
1451#define DEPEVT_STATUS_MISSED_ISOC BIT(3) /* XferInProgress */
1452
1453/* Stream event only */
1454#define DEPEVT_STREAMEVT_FOUND		1
1455#define DEPEVT_STREAMEVT_NOTFOUND	2
1456
1457/* Stream event parameter */
1458#define DEPEVT_STREAM_PRIME		0xfffe
1459#define DEPEVT_STREAM_NOSTREAM		0x0
1460
1461/* Control-only Status */
1462#define DEPEVT_STATUS_CONTROL_DATA	1
1463#define DEPEVT_STATUS_CONTROL_STATUS	2
1464#define DEPEVT_STATUS_CONTROL_PHASE(n)	((n) & 3)
1465
1466/* In response to Start Transfer */
1467#define DEPEVT_TRANSFER_NO_RESOURCE	1
1468#define DEPEVT_TRANSFER_BUS_EXPIRY	2
1469
1470	u32	parameters:16;
1471
1472/* For Command Complete Events */
1473#define DEPEVT_PARAMETER_CMD(n)	(((n) & (0xf << 8)) >> 8)
1474} __packed;
1475
1476/**
1477 * struct dwc3_event_devt - Device Events
1478 * @one_bit: indicates this is a non-endpoint event (not used)
1479 * @device_event: indicates it's a device event. Should read as 0x00
1480 * @type: indicates the type of device event.
1481 *	0	- DisconnEvt
1482 *	1	- USBRst
1483 *	2	- ConnectDone
1484 *	3	- ULStChng
1485 *	4	- WkUpEvt
1486 *	5	- Reserved
1487 *	6	- Suspend (EOPF on revisions 2.10a and prior)
1488 *	7	- SOF
1489 *	8	- Reserved
1490 *	9	- ErrticErr
1491 *	10	- CmdCmplt
1492 *	11	- EvntOverflow
1493 *	12	- VndrDevTstRcved
1494 * @reserved15_12: Reserved, not used
1495 * @event_info: Information about this event
1496 * @reserved31_25: Reserved, not used
1497 */
1498struct dwc3_event_devt {
1499	u32	one_bit:1;
1500	u32	device_event:7;
1501	u32	type:4;
1502	u32	reserved15_12:4;
1503	u32	event_info:9;
1504	u32	reserved31_25:7;
1505} __packed;
1506
1507/**
1508 * struct dwc3_event_gevt - Other Core Events
1509 * @one_bit: indicates this is a non-endpoint event (not used)
1510 * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event.
1511 * @phy_port_number: self-explanatory
1512 * @reserved31_12: Reserved, not used.
1513 */
1514struct dwc3_event_gevt {
1515	u32	one_bit:1;
1516	u32	device_event:7;
1517	u32	phy_port_number:4;
1518	u32	reserved31_12:20;
1519} __packed;
1520
1521/**
1522 * union dwc3_event - representation of Event Buffer contents
1523 * @raw: raw 32-bit event
1524 * @type: the type of the event
1525 * @depevt: Device Endpoint Event
1526 * @devt: Device Event
1527 * @gevt: Global Event
1528 */
1529union dwc3_event {
1530	u32				raw;
1531	struct dwc3_event_type		type;
1532	struct dwc3_event_depevt	depevt;
1533	struct dwc3_event_devt		devt;
1534	struct dwc3_event_gevt		gevt;
1535};
1536
1537/**
1538 * struct dwc3_gadget_ep_cmd_params - representation of endpoint command
1539 * parameters
1540 * @param2: third parameter
1541 * @param1: second parameter
1542 * @param0: first parameter
1543 */
1544struct dwc3_gadget_ep_cmd_params {
1545	u32	param2;
1546	u32	param1;
1547	u32	param0;
1548};
1549
1550/*
1551 * DWC3 Features to be used as Driver Data
1552 */
1553
1554#define DWC3_HAS_PERIPHERAL		BIT(0)
1555#define DWC3_HAS_XHCI			BIT(1)
1556#define DWC3_HAS_OTG			BIT(3)
1557
1558/* prototypes */
1559void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode, bool ignore_susphy);
1560void dwc3_set_mode(struct dwc3 *dwc, u32 mode);
1561u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type);
1562
1563#define DWC3_IP_IS(_ip)							\
1564	(dwc->ip == _ip##_IP)
1565
1566#define DWC3_VER_IS(_ip, _ver)						\
1567	(DWC3_IP_IS(_ip) && dwc->revision == _ip##_REVISION_##_ver)
1568
1569#define DWC3_VER_IS_PRIOR(_ip, _ver)					\
1570	(DWC3_IP_IS(_ip) && dwc->revision < _ip##_REVISION_##_ver)
1571
1572#define DWC3_VER_IS_WITHIN(_ip, _from, _to)				\
1573	(DWC3_IP_IS(_ip) &&						\
1574	 dwc->revision >= _ip##_REVISION_##_from &&			\
1575	 (!(_ip##_REVISION_##_to) ||					\
1576	  dwc->revision <= _ip##_REVISION_##_to))
1577
1578#define DWC3_VER_TYPE_IS_WITHIN(_ip, _ver, _from, _to)			\
1579	(DWC3_VER_IS(_ip, _ver) &&					\
1580	 dwc->version_type >= _ip##_VERSIONTYPE_##_from &&		\
1581	 (!(_ip##_VERSIONTYPE_##_to) ||					\
1582	  dwc->version_type <= _ip##_VERSIONTYPE_##_to))
1583
1584/**
1585 * dwc3_mdwidth - get MDWIDTH value in bits
1586 * @dwc: pointer to our context structure
1587 *
1588 * Return MDWIDTH configuration value in bits.
1589 */
1590static inline u32 dwc3_mdwidth(struct dwc3 *dwc)
1591{
1592	u32 mdwidth;
1593
1594	mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1595	if (DWC3_IP_IS(DWC32))
1596		mdwidth += DWC3_GHWPARAMS6_MDWIDTH(dwc->hwparams.hwparams6);
1597
1598	return mdwidth;
 
 
 
1599}
1600
1601bool dwc3_has_imod(struct dwc3 *dwc);
1602
1603int dwc3_event_buffers_setup(struct dwc3 *dwc);
1604void dwc3_event_buffers_cleanup(struct dwc3 *dwc);
1605
1606int dwc3_core_soft_reset(struct dwc3 *dwc);
1607void dwc3_enable_susphy(struct dwc3 *dwc, bool enable);
1608
1609#if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1610int dwc3_host_init(struct dwc3 *dwc);
1611void dwc3_host_exit(struct dwc3 *dwc);
1612#else
1613static inline int dwc3_host_init(struct dwc3 *dwc)
1614{ return 0; }
1615static inline void dwc3_host_exit(struct dwc3 *dwc)
1616{ }
1617#endif
1618
1619#if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1620int dwc3_gadget_init(struct dwc3 *dwc);
1621void dwc3_gadget_exit(struct dwc3 *dwc);
1622int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode);
1623int dwc3_gadget_get_link_state(struct dwc3 *dwc);
1624int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state);
1625int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd,
1626		struct dwc3_gadget_ep_cmd_params *params);
1627int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned int cmd,
1628		u32 param);
1629void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc);
1630void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep, int status);
1631#else
1632static inline int dwc3_gadget_init(struct dwc3 *dwc)
1633{ return 0; }
1634static inline void dwc3_gadget_exit(struct dwc3 *dwc)
1635{ }
1636static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
1637{ return 0; }
1638static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc)
1639{ return 0; }
1640static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc,
1641		enum dwc3_link_state state)
1642{ return 0; }
1643
1644static inline int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd,
1645		struct dwc3_gadget_ep_cmd_params *params)
1646{ return 0; }
1647static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc,
1648		int cmd, u32 param)
1649{ return 0; }
1650static inline void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc)
1651{ }
1652#endif
1653
1654#if IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1655int dwc3_drd_init(struct dwc3 *dwc);
1656void dwc3_drd_exit(struct dwc3 *dwc);
1657void dwc3_otg_init(struct dwc3 *dwc);
1658void dwc3_otg_exit(struct dwc3 *dwc);
1659void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus);
1660void dwc3_otg_host_init(struct dwc3 *dwc);
1661#else
1662static inline int dwc3_drd_init(struct dwc3 *dwc)
1663{ return 0; }
1664static inline void dwc3_drd_exit(struct dwc3 *dwc)
1665{ }
1666static inline void dwc3_otg_init(struct dwc3 *dwc)
1667{ }
1668static inline void dwc3_otg_exit(struct dwc3 *dwc)
1669{ }
1670static inline void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus)
1671{ }
1672static inline void dwc3_otg_host_init(struct dwc3 *dwc)
1673{ }
1674#endif
1675
1676/* power management interface */
1677#if !IS_ENABLED(CONFIG_USB_DWC3_HOST)
1678int dwc3_gadget_suspend(struct dwc3 *dwc);
1679int dwc3_gadget_resume(struct dwc3 *dwc);
 
1680#else
1681static inline int dwc3_gadget_suspend(struct dwc3 *dwc)
1682{
1683	return 0;
1684}
1685
1686static inline int dwc3_gadget_resume(struct dwc3 *dwc)
1687{
1688	return 0;
1689}
1690
 
 
 
1691#endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */
1692
1693#if IS_ENABLED(CONFIG_USB_DWC3_ULPI)
1694int dwc3_ulpi_init(struct dwc3 *dwc);
1695void dwc3_ulpi_exit(struct dwc3 *dwc);
1696#else
1697static inline int dwc3_ulpi_init(struct dwc3 *dwc)
1698{ return 0; }
1699static inline void dwc3_ulpi_exit(struct dwc3 *dwc)
1700{ }
1701#endif
1702
1703#endif /* __DRIVERS_USB_DWC3_CORE_H */