1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Driver for Atmel QSPI Controller
  4 *
  5 * Copyright (C) 2015 Atmel Corporation
  6 * Copyright (C) 2018 Cryptera A/S
  7 *
  8 * Author: Cyrille Pitchen <cyrille.pitchen@atmel.com>
  9 * Author: Piotr Bugalski <bugalski.piotr@gmail.com>
 10 *
 11 * This driver is based on drivers/mtd/spi-nor/fsl-quadspi.c from Freescale.
 12 */
 13
 14#include <linux/clk.h>
 15#include <linux/delay.h>
 16#include <linux/err.h>
 17#include <linux/interrupt.h>
 18#include <linux/io.h>
 19#include <linux/kernel.h>
 20#include <linux/module.h>
 21#include <linux/of.h>
 22#include <linux/of_platform.h>
 23#include <linux/platform_device.h>
 24#include <linux/pm_runtime.h>
 25#include <linux/spi/spi-mem.h>
 26
 27/* QSPI register offsets */
 28#define QSPI_CR      0x0000  /* Control Register */
 29#define QSPI_MR      0x0004  /* Mode Register */
 30#define QSPI_RD      0x0008  /* Receive Data Register */
 31#define QSPI_TD      0x000c  /* Transmit Data Register */
 32#define QSPI_SR      0x0010  /* Status Register */
 33#define QSPI_IER     0x0014  /* Interrupt Enable Register */
 34#define QSPI_IDR     0x0018  /* Interrupt Disable Register */
 35#define QSPI_IMR     0x001c  /* Interrupt Mask Register */
 36#define QSPI_SCR     0x0020  /* Serial Clock Register */
 37
 38#define QSPI_IAR     0x0030  /* Instruction Address Register */
 39#define QSPI_ICR     0x0034  /* Instruction Code Register */
 40#define QSPI_WICR    0x0034  /* Write Instruction Code Register */
 41#define QSPI_IFR     0x0038  /* Instruction Frame Register */
 42#define QSPI_RICR    0x003C  /* Read Instruction Code Register */
 43
 44#define QSPI_SMR     0x0040  /* Scrambling Mode Register */
 45#define QSPI_SKR     0x0044  /* Scrambling Key Register */
 46
 47#define QSPI_WPMR    0x00E4  /* Write Protection Mode Register */
 48#define QSPI_WPSR    0x00E8  /* Write Protection Status Register */
 49
 50#define QSPI_VERSION 0x00FC  /* Version Register */
 51
 52
 53/* Bitfields in QSPI_CR (Control Register) */
 54#define QSPI_CR_QSPIEN                  BIT(0)
 55#define QSPI_CR_QSPIDIS                 BIT(1)
 56#define QSPI_CR_SWRST                   BIT(7)
 57#define QSPI_CR_LASTXFER                BIT(24)
 58
 59/* Bitfields in QSPI_MR (Mode Register) */
 60#define QSPI_MR_SMM                     BIT(0)
 61#define QSPI_MR_LLB                     BIT(1)
 62#define QSPI_MR_WDRBT                   BIT(2)
 63#define QSPI_MR_SMRM                    BIT(3)
 64#define QSPI_MR_CSMODE_MASK             GENMASK(5, 4)
 65#define QSPI_MR_CSMODE_NOT_RELOADED     (0 << 4)
 66#define QSPI_MR_CSMODE_LASTXFER         (1 << 4)
 67#define QSPI_MR_CSMODE_SYSTEMATICALLY   (2 << 4)
 68#define QSPI_MR_NBBITS_MASK             GENMASK(11, 8)
 69#define QSPI_MR_NBBITS(n)               ((((n) - 8) << 8) & QSPI_MR_NBBITS_MASK)
 70#define QSPI_MR_DLYBCT_MASK             GENMASK(23, 16)
 71#define QSPI_MR_DLYBCT(n)               (((n) << 16) & QSPI_MR_DLYBCT_MASK)
 72#define QSPI_MR_DLYCS_MASK              GENMASK(31, 24)
 73#define QSPI_MR_DLYCS(n)                (((n) << 24) & QSPI_MR_DLYCS_MASK)
 74
 75/* Bitfields in QSPI_SR/QSPI_IER/QSPI_IDR/QSPI_IMR  */
 76#define QSPI_SR_RDRF                    BIT(0)
 77#define QSPI_SR_TDRE                    BIT(1)
 78#define QSPI_SR_TXEMPTY                 BIT(2)
 79#define QSPI_SR_OVRES                   BIT(3)
 80#define QSPI_SR_CSR                     BIT(8)
 81#define QSPI_SR_CSS                     BIT(9)
 82#define QSPI_SR_INSTRE                  BIT(10)
 83#define QSPI_SR_QSPIENS                 BIT(24)
 84
 85#define QSPI_SR_CMD_COMPLETED	(QSPI_SR_INSTRE | QSPI_SR_CSR)
 86
 87/* Bitfields in QSPI_SCR (Serial Clock Register) */
 88#define QSPI_SCR_CPOL                   BIT(0)
 89#define QSPI_SCR_CPHA                   BIT(1)
 90#define QSPI_SCR_SCBR_MASK              GENMASK(15, 8)
 91#define QSPI_SCR_SCBR(n)                (((n) << 8) & QSPI_SCR_SCBR_MASK)
 92#define QSPI_SCR_DLYBS_MASK             GENMASK(23, 16)
 93#define QSPI_SCR_DLYBS(n)               (((n) << 16) & QSPI_SCR_DLYBS_MASK)
 94
 95/* Bitfields in QSPI_ICR (Read/Write Instruction Code Register) */
 96#define QSPI_ICR_INST_MASK              GENMASK(7, 0)
 97#define QSPI_ICR_INST(inst)             (((inst) << 0) & QSPI_ICR_INST_MASK)
 98#define QSPI_ICR_OPT_MASK               GENMASK(23, 16)
 99#define QSPI_ICR_OPT(opt)               (((opt) << 16) & QSPI_ICR_OPT_MASK)
100
101/* Bitfields in QSPI_IFR (Instruction Frame Register) */
102#define QSPI_IFR_WIDTH_MASK             GENMASK(2, 0)
103#define QSPI_IFR_WIDTH_SINGLE_BIT_SPI   (0 << 0)
104#define QSPI_IFR_WIDTH_DUAL_OUTPUT      (1 << 0)
105#define QSPI_IFR_WIDTH_QUAD_OUTPUT      (2 << 0)
106#define QSPI_IFR_WIDTH_DUAL_IO          (3 << 0)
107#define QSPI_IFR_WIDTH_QUAD_IO          (4 << 0)
108#define QSPI_IFR_WIDTH_DUAL_CMD         (5 << 0)
109#define QSPI_IFR_WIDTH_QUAD_CMD         (6 << 0)
110#define QSPI_IFR_INSTEN                 BIT(4)
111#define QSPI_IFR_ADDREN                 BIT(5)
112#define QSPI_IFR_OPTEN                  BIT(6)
113#define QSPI_IFR_DATAEN                 BIT(7)
114#define QSPI_IFR_OPTL_MASK              GENMASK(9, 8)
115#define QSPI_IFR_OPTL_1BIT              (0 << 8)
116#define QSPI_IFR_OPTL_2BIT              (1 << 8)
117#define QSPI_IFR_OPTL_4BIT              (2 << 8)
118#define QSPI_IFR_OPTL_8BIT              (3 << 8)
119#define QSPI_IFR_ADDRL                  BIT(10)
120#define QSPI_IFR_TFRTYP_MEM		BIT(12)
121#define QSPI_IFR_SAMA5D2_WRITE_TRSFR	BIT(13)
122#define QSPI_IFR_CRM                    BIT(14)
123#define QSPI_IFR_NBDUM_MASK             GENMASK(20, 16)
124#define QSPI_IFR_NBDUM(n)               (((n) << 16) & QSPI_IFR_NBDUM_MASK)
125#define QSPI_IFR_APBTFRTYP_READ		BIT(24)	/* Defined in SAM9X60 */
126
127/* Bitfields in QSPI_SMR (Scrambling Mode Register) */
128#define QSPI_SMR_SCREN                  BIT(0)
129#define QSPI_SMR_RVDIS                  BIT(1)
130
131/* Bitfields in QSPI_WPMR (Write Protection Mode Register) */
132#define QSPI_WPMR_WPEN                  BIT(0)
133#define QSPI_WPMR_WPKEY_MASK            GENMASK(31, 8)
134#define QSPI_WPMR_WPKEY(wpkey)          (((wpkey) << 8) & QSPI_WPMR_WPKEY_MASK)
135
136/* Bitfields in QSPI_WPSR (Write Protection Status Register) */
137#define QSPI_WPSR_WPVS                  BIT(0)
138#define QSPI_WPSR_WPVSRC_MASK           GENMASK(15, 8)
139#define QSPI_WPSR_WPVSRC(src)           (((src) << 8) & QSPI_WPSR_WPVSRC)
140
141#define ATMEL_QSPI_TIMEOUT		1000	/* ms */
142
143struct atmel_qspi_caps {
144	bool has_qspick;
145	bool has_ricr;
146};
147
148struct atmel_qspi_ops;
149
150struct atmel_qspi {
151	void __iomem		*regs;
152	void __iomem		*mem;
153	struct clk		*pclk;
154	struct clk		*qspick;
155	struct platform_device	*pdev;
156	const struct atmel_qspi_caps *caps;
157	const struct atmel_qspi_ops *ops;
158	resource_size_t		mmap_size;
159	u32			pending;
160	u32			irq_mask;
161	u32			mr;
162	u32			scr;
163	struct completion	cmd_completion;
164};
165
166struct atmel_qspi_ops {
167	int (*set_cfg)(struct atmel_qspi *aq, const struct spi_mem_op *op,
168		       u32 *offset);
169	int (*transfer)(struct spi_mem *mem, const struct spi_mem_op *op,
170			u32 offset);
171};
172
173struct atmel_qspi_mode {
174	u8 cmd_buswidth;
175	u8 addr_buswidth;
176	u8 data_buswidth;
177	u32 config;
178};
179
180static const struct atmel_qspi_mode atmel_qspi_modes[] = {
181	{ 1, 1, 1, QSPI_IFR_WIDTH_SINGLE_BIT_SPI },
182	{ 1, 1, 2, QSPI_IFR_WIDTH_DUAL_OUTPUT },
183	{ 1, 1, 4, QSPI_IFR_WIDTH_QUAD_OUTPUT },
184	{ 1, 2, 2, QSPI_IFR_WIDTH_DUAL_IO },
185	{ 1, 4, 4, QSPI_IFR_WIDTH_QUAD_IO },
186	{ 2, 2, 2, QSPI_IFR_WIDTH_DUAL_CMD },
187	{ 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD },
188};
189
190#ifdef VERBOSE_DEBUG
191static const char *atmel_qspi_reg_name(u32 offset, char *tmp, size_t sz)
192{
193	switch (offset) {
194	case QSPI_CR:
195		return "CR";
196	case QSPI_MR:
197		return "MR";
198	case QSPI_RD:
199		return "RD";
200	case QSPI_TD:
201		return "TD";
202	case QSPI_SR:
203		return "SR";
204	case QSPI_IER:
205		return "IER";
206	case QSPI_IDR:
207		return "IDR";
208	case QSPI_IMR:
209		return "IMR";
210	case QSPI_SCR:
211		return "SCR";
212	case QSPI_IAR:
213		return "IAR";
214	case QSPI_ICR:
215		return "ICR/WICR";
216	case QSPI_IFR:
217		return "IFR";
218	case QSPI_RICR:
219		return "RICR";
220	case QSPI_SMR:
221		return "SMR";
222	case QSPI_SKR:
223		return "SKR";
224	case QSPI_WPMR:
225		return "WPMR";
226	case QSPI_WPSR:
227		return "WPSR";
228	case QSPI_VERSION:
229		return "VERSION";
230	default:
231		snprintf(tmp, sz, "0x%02x", offset);
232		break;
233	}
234
235	return tmp;
236}
237#endif /* VERBOSE_DEBUG */
238
239static u32 atmel_qspi_read(struct atmel_qspi *aq, u32 offset)
240{
241	u32 value = readl_relaxed(aq->regs + offset);
242
243#ifdef VERBOSE_DEBUG
244	char tmp[8];
245
246	dev_vdbg(&aq->pdev->dev, "read 0x%08x from %s\n", value,
247		 atmel_qspi_reg_name(offset, tmp, sizeof(tmp)));
248#endif /* VERBOSE_DEBUG */
249
250	return value;
251}
252
253static void atmel_qspi_write(u32 value, struct atmel_qspi *aq, u32 offset)
254{
255#ifdef VERBOSE_DEBUG
256	char tmp[8];
257
258	dev_vdbg(&aq->pdev->dev, "write 0x%08x into %s\n", value,
259		 atmel_qspi_reg_name(offset, tmp, sizeof(tmp)));
260#endif /* VERBOSE_DEBUG */
261
262	writel_relaxed(value, aq->regs + offset);
263}
264
265static inline bool atmel_qspi_is_compatible(const struct spi_mem_op *op,
266					    const struct atmel_qspi_mode *mode)
267{
268	if (op->cmd.buswidth != mode->cmd_buswidth)
269		return false;
270
271	if (op->addr.nbytes && op->addr.buswidth != mode->addr_buswidth)
272		return false;
273
274	if (op->data.nbytes && op->data.buswidth != mode->data_buswidth)
275		return false;
276
277	return true;
278}
279
280static int atmel_qspi_find_mode(const struct spi_mem_op *op)
281{
282	u32 i;
283
284	for (i = 0; i < ARRAY_SIZE(atmel_qspi_modes); i++)
285		if (atmel_qspi_is_compatible(op, &atmel_qspi_modes[i]))
286			return i;
287
288	return -EOPNOTSUPP;
289}
290
291static bool atmel_qspi_supports_op(struct spi_mem *mem,
292				   const struct spi_mem_op *op)
293{
294	if (!spi_mem_default_supports_op(mem, op))
295		return false;
296
297	if (atmel_qspi_find_mode(op) < 0)
298		return false;
299
300	/* special case not supported by hardware */
301	if (op->addr.nbytes == 2 && op->cmd.buswidth != op->addr.buswidth &&
302	    op->dummy.nbytes == 0)
303		return false;
304
305	return true;
306}
307
308static int atmel_qspi_set_cfg(struct atmel_qspi *aq,
309			      const struct spi_mem_op *op, u32 *offset)
310{
311	u32 iar, icr, ifr;
312	u32 dummy_cycles = 0;
313	int mode;
314
315	iar = 0;
316	icr = QSPI_ICR_INST(op->cmd.opcode);
317	ifr = QSPI_IFR_INSTEN;
318
319	mode = atmel_qspi_find_mode(op);
320	if (mode < 0)
321		return mode;
322	ifr |= atmel_qspi_modes[mode].config;
323
324	if (op->dummy.nbytes)
325		dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth;
326
327	/*
328	 * The controller allows 24 and 32-bit addressing while NAND-flash
329	 * requires 16-bit long. Handling 8-bit long addresses is done using
330	 * the option field. For the 16-bit addresses, the workaround depends
331	 * of the number of requested dummy bits. If there are 8 or more dummy
332	 * cycles, the address is shifted and sent with the first dummy byte.
333	 * Otherwise opcode is disabled and the first byte of the address
334	 * contains the command opcode (works only if the opcode and address
335	 * use the same buswidth). The limitation is when the 16-bit address is
336	 * used without enough dummy cycles and the opcode is using a different
337	 * buswidth than the address.
338	 */
339	if (op->addr.buswidth) {
340		switch (op->addr.nbytes) {
341		case 0:
342			break;
343		case 1:
344			ifr |= QSPI_IFR_OPTEN | QSPI_IFR_OPTL_8BIT;
345			icr |= QSPI_ICR_OPT(op->addr.val & 0xff);
346			break;
347		case 2:
348			if (dummy_cycles < 8 / op->addr.buswidth) {
349				ifr &= ~QSPI_IFR_INSTEN;
350				ifr |= QSPI_IFR_ADDREN;
351				iar = (op->cmd.opcode << 16) |
352					(op->addr.val & 0xffff);
353			} else {
354				ifr |= QSPI_IFR_ADDREN;
355				iar = (op->addr.val << 8) & 0xffffff;
356				dummy_cycles -= 8 / op->addr.buswidth;
357			}
358			break;
359		case 3:
360			ifr |= QSPI_IFR_ADDREN;
361			iar = op->addr.val & 0xffffff;
362			break;
363		case 4:
364			ifr |= QSPI_IFR_ADDREN | QSPI_IFR_ADDRL;
365			iar = op->addr.val & 0x7ffffff;
366			break;
367		default:
368			return -ENOTSUPP;
369		}
370	}
371
372	/* offset of the data access in the QSPI memory space */
373	*offset = iar;
374
375	/* Set number of dummy cycles */
376	if (dummy_cycles)
377		ifr |= QSPI_IFR_NBDUM(dummy_cycles);
378
379	/* Set data enable and data transfer type. */
380	if (op->data.nbytes) {
381		ifr |= QSPI_IFR_DATAEN;
382
383		if (op->addr.nbytes)
384			ifr |= QSPI_IFR_TFRTYP_MEM;
385	}
386
387	/*
388	 * If the QSPI controller is set in regular SPI mode, set it in
389	 * Serial Memory Mode (SMM).
390	 */
391	if (!(aq->mr & QSPI_MR_SMM)) {
392		aq->mr |= QSPI_MR_SMM;
393		atmel_qspi_write(aq->mr, aq, QSPI_MR);
394	}
395
396	/* Clear pending interrupts */
397	(void)atmel_qspi_read(aq, QSPI_SR);
398
399	/* Set QSPI Instruction Frame registers. */
400	if (op->addr.nbytes && !op->data.nbytes)
401		atmel_qspi_write(iar, aq, QSPI_IAR);
402
403	if (aq->caps->has_ricr) {
 
 
 
 
 
404		if (op->data.dir == SPI_MEM_DATA_IN)
405			atmel_qspi_write(icr, aq, QSPI_RICR);
406		else
407			atmel_qspi_write(icr, aq, QSPI_WICR);
 
408	} else {
409		if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
410			ifr |= QSPI_IFR_SAMA5D2_WRITE_TRSFR;
411
412		atmel_qspi_write(icr, aq, QSPI_ICR);
 
 
 
413	}
414
415	atmel_qspi_write(ifr, aq, QSPI_IFR);
416
417	return 0;
418}
419
420static int atmel_qspi_wait_for_completion(struct atmel_qspi *aq, u32 irq_mask)
421{
422	int err = 0;
423	u32 sr;
424
425	/* Poll INSTRuction End status */
426	sr = atmel_qspi_read(aq, QSPI_SR);
427	if ((sr & irq_mask) == irq_mask)
428		return 0;
429
430	/* Wait for INSTRuction End interrupt */
431	reinit_completion(&aq->cmd_completion);
432	aq->pending = sr & irq_mask;
433	aq->irq_mask = irq_mask;
434	atmel_qspi_write(irq_mask, aq, QSPI_IER);
435	if (!wait_for_completion_timeout(&aq->cmd_completion,
436					 msecs_to_jiffies(ATMEL_QSPI_TIMEOUT)))
437		err = -ETIMEDOUT;
438	atmel_qspi_write(irq_mask, aq, QSPI_IDR);
439
440	return err;
441}
442
443static int atmel_qspi_transfer(struct spi_mem *mem,
444			       const struct spi_mem_op *op, u32 offset)
445{
446	struct atmel_qspi *aq = spi_controller_get_devdata(mem->spi->controller);
447
448	/* Skip to the final steps if there is no data */
449	if (!op->data.nbytes)
450		return atmel_qspi_wait_for_completion(aq,
451						      QSPI_SR_CMD_COMPLETED);
452
453	/* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */
454	(void)atmel_qspi_read(aq, QSPI_IFR);
455
456	/* Send/Receive data */
457	if (op->data.dir == SPI_MEM_DATA_IN) {
458		memcpy_fromio(op->data.buf.in, aq->mem + offset,
459			      op->data.nbytes);
460
461		/* Synchronize AHB and APB accesses again */
462		rmb();
463	} else {
464		memcpy_toio(aq->mem + offset, op->data.buf.out,
465			    op->data.nbytes);
 
 
466
467		/* Synchronize AHB and APB accesses again */
468		wmb();
469	}
470
471	/* Release the chip-select */
472	atmel_qspi_write(QSPI_CR_LASTXFER, aq, QSPI_CR);
473
474	return atmel_qspi_wait_for_completion(aq, QSPI_SR_CMD_COMPLETED);
475}
476
477static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
478{
479	struct atmel_qspi *aq = spi_controller_get_devdata(mem->spi->controller);
480	u32 offset;
481	int err;
482
483	/*
484	 * Check if the address exceeds the MMIO window size. An improvement
485	 * would be to add support for regular SPI mode and fall back to it
486	 * when the flash memories overrun the controller's memory space.
487	 */
488	if (op->addr.val + op->data.nbytes > aq->mmap_size)
489		return -EOPNOTSUPP;
490
491	if (op->addr.nbytes > 4)
492		return -EOPNOTSUPP;
493
494	err = pm_runtime_resume_and_get(&aq->pdev->dev);
495	if (err < 0)
496		return err;
497
498	err = aq->ops->set_cfg(aq, op, &offset);
499	if (err)
500		goto pm_runtime_put;
501
502	err = aq->ops->transfer(mem, op, offset);
 
 
 
503
504pm_runtime_put:
505	pm_runtime_mark_last_busy(&aq->pdev->dev);
506	pm_runtime_put_autosuspend(&aq->pdev->dev);
507	return err;
508}
509
510static const char *atmel_qspi_get_name(struct spi_mem *spimem)
511{
512	return dev_name(spimem->spi->dev.parent);
513}
514
515static const struct spi_controller_mem_ops atmel_qspi_mem_ops = {
516	.supports_op = atmel_qspi_supports_op,
517	.exec_op = atmel_qspi_exec_op,
518	.get_name = atmel_qspi_get_name
519};
520
521static int atmel_qspi_setup(struct spi_device *spi)
522{
523	struct spi_controller *ctrl = spi->controller;
524	struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
525	unsigned long src_rate;
526	u32 scbr;
527	int ret;
528
529	if (ctrl->busy)
530		return -EBUSY;
531
532	if (!spi->max_speed_hz)
533		return -EINVAL;
534
535	src_rate = clk_get_rate(aq->pclk);
536	if (!src_rate)
537		return -EINVAL;
538
539	/* Compute the QSPI baudrate */
540	scbr = DIV_ROUND_UP(src_rate, spi->max_speed_hz);
541	if (scbr > 0)
542		scbr--;
543
544	ret = pm_runtime_resume_and_get(ctrl->dev.parent);
545	if (ret < 0)
546		return ret;
547
548	aq->scr &= ~QSPI_SCR_SCBR_MASK;
549	aq->scr |= QSPI_SCR_SCBR(scbr);
550	atmel_qspi_write(aq->scr, aq, QSPI_SCR);
551
552	pm_runtime_mark_last_busy(ctrl->dev.parent);
553	pm_runtime_put_autosuspend(ctrl->dev.parent);
554
555	return 0;
556}
557
558static int atmel_qspi_set_cs_timing(struct spi_device *spi)
559{
560	struct spi_controller *ctrl = spi->controller;
561	struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
562	unsigned long clk_rate;
563	u32 cs_inactive;
564	u32 cs_setup;
565	u32 cs_hold;
566	int delay;
567	int ret;
568
569	clk_rate = clk_get_rate(aq->pclk);
570	if (!clk_rate)
571		return -EINVAL;
572
573	/* hold */
574	delay = spi_delay_to_ns(&spi->cs_hold, NULL);
575	if (aq->mr & QSPI_MR_SMM) {
576		if (delay > 0)
577			dev_warn(&aq->pdev->dev,
578				 "Ignoring cs_hold, must be 0 in Serial Memory Mode.\n");
579		cs_hold = 0;
580	} else {
581		delay = spi_delay_to_ns(&spi->cs_hold, NULL);
582		if (delay < 0)
583			return delay;
584
585		cs_hold = DIV_ROUND_UP((delay * DIV_ROUND_UP(clk_rate, 1000000)), 32000);
586	}
587
588	/* setup */
589	delay = spi_delay_to_ns(&spi->cs_setup, NULL);
590	if (delay < 0)
591		return delay;
592
593	cs_setup = DIV_ROUND_UP((delay * DIV_ROUND_UP(clk_rate, 1000000)),
594				1000);
595
596	/* inactive */
597	delay = spi_delay_to_ns(&spi->cs_inactive, NULL);
598	if (delay < 0)
599		return delay;
600	cs_inactive = DIV_ROUND_UP((delay * DIV_ROUND_UP(clk_rate, 1000000)), 1000);
601
602	ret = pm_runtime_resume_and_get(ctrl->dev.parent);
603	if (ret < 0)
604		return ret;
605
606	aq->scr &= ~QSPI_SCR_DLYBS_MASK;
607	aq->scr |= QSPI_SCR_DLYBS(cs_setup);
608	atmel_qspi_write(aq->scr, aq, QSPI_SCR);
609
610	aq->mr &= ~(QSPI_MR_DLYBCT_MASK | QSPI_MR_DLYCS_MASK);
611	aq->mr |= QSPI_MR_DLYBCT(cs_hold) | QSPI_MR_DLYCS(cs_inactive);
612	atmel_qspi_write(aq->mr, aq, QSPI_MR);
613
614	pm_runtime_mark_last_busy(ctrl->dev.parent);
615	pm_runtime_put_autosuspend(ctrl->dev.parent);
616
617	return 0;
618}
619
620static void atmel_qspi_init(struct atmel_qspi *aq)
621{
622	/* Reset the QSPI controller */
623	atmel_qspi_write(QSPI_CR_SWRST, aq, QSPI_CR);
624
625	/* Set the QSPI controller by default in Serial Memory Mode */
626	aq->mr |= QSPI_MR_SMM;
627	atmel_qspi_write(aq->mr, aq, QSPI_MR);
628
629	/* Enable the QSPI controller */
630	atmel_qspi_write(QSPI_CR_QSPIEN, aq, QSPI_CR);
631}
632
633static irqreturn_t atmel_qspi_interrupt(int irq, void *dev_id)
634{
635	struct atmel_qspi *aq = dev_id;
636	u32 status, mask, pending;
637
638	status = atmel_qspi_read(aq, QSPI_SR);
639	mask = atmel_qspi_read(aq, QSPI_IMR);
640	pending = status & mask;
641
642	if (!pending)
643		return IRQ_NONE;
644
645	aq->pending |= pending;
646	if ((aq->pending & aq->irq_mask) == aq->irq_mask)
647		complete(&aq->cmd_completion);
648
649	return IRQ_HANDLED;
650}
651
652static const struct atmel_qspi_ops atmel_qspi_ops = {
653	.set_cfg = atmel_qspi_set_cfg,
654	.transfer = atmel_qspi_transfer,
655};
656
657static int atmel_qspi_probe(struct platform_device *pdev)
658{
659	struct spi_controller *ctrl;
660	struct atmel_qspi *aq;
661	struct resource *res;
662	int irq, err = 0;
663
664	ctrl = devm_spi_alloc_host(&pdev->dev, sizeof(*aq));
665	if (!ctrl)
666		return -ENOMEM;
667
668	ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD;
669	ctrl->setup = atmel_qspi_setup;
670	ctrl->set_cs_timing = atmel_qspi_set_cs_timing;
671	ctrl->bus_num = -1;
672	ctrl->mem_ops = &atmel_qspi_mem_ops;
673	ctrl->num_chipselect = 1;
674	ctrl->dev.of_node = pdev->dev.of_node;
675	platform_set_drvdata(pdev, ctrl);
676
677	aq = spi_controller_get_devdata(ctrl);
678
679	init_completion(&aq->cmd_completion);
680	aq->pdev = pdev;
681	aq->ops = &atmel_qspi_ops;
682
683	/* Map the registers */
684	aq->regs = devm_platform_ioremap_resource_byname(pdev, "qspi_base");
685	if (IS_ERR(aq->regs))
686		return dev_err_probe(&pdev->dev, PTR_ERR(aq->regs),
687				     "missing registers\n");
 
 
 
688
689	/* Map the AHB memory */
690	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_mmap");
691	aq->mem = devm_ioremap_resource(&pdev->dev, res);
692	if (IS_ERR(aq->mem))
693		return dev_err_probe(&pdev->dev, PTR_ERR(aq->mem),
694				     "missing AHB memory\n");
695
696	aq->mmap_size = resource_size(res);
697
698	/* Get the peripheral clock */
699	aq->pclk = devm_clk_get(&pdev->dev, "pclk");
700	if (IS_ERR(aq->pclk))
701		aq->pclk = devm_clk_get(&pdev->dev, NULL);
702
703	if (IS_ERR(aq->pclk))
704		return dev_err_probe(&pdev->dev, PTR_ERR(aq->pclk),
705				     "missing peripheral clock\n");
 
 
706
707	/* Enable the peripheral clock */
708	err = clk_prepare_enable(aq->pclk);
709	if (err)
710		return dev_err_probe(&pdev->dev, err,
711				     "failed to enable the peripheral clock\n");
 
712
713	aq->caps = of_device_get_match_data(&pdev->dev);
714	if (!aq->caps) {
715		dev_err(&pdev->dev, "Could not retrieve QSPI caps\n");
716		err = -EINVAL;
717		goto disable_pclk;
718	}
719
720	if (aq->caps->has_qspick) {
721		/* Get the QSPI system clock */
722		aq->qspick = devm_clk_get(&pdev->dev, "qspick");
723		if (IS_ERR(aq->qspick)) {
724			dev_err(&pdev->dev, "missing system clock\n");
725			err = PTR_ERR(aq->qspick);
726			goto disable_pclk;
727		}
728
729		/* Enable the QSPI system clock */
730		err = clk_prepare_enable(aq->qspick);
731		if (err) {
732			dev_err(&pdev->dev,
733				"failed to enable the QSPI system clock\n");
734			goto disable_pclk;
735		}
736	}
737
738	/* Request the IRQ */
739	irq = platform_get_irq(pdev, 0);
740	if (irq < 0) {
741		err = irq;
742		goto disable_qspick;
743	}
744	err = devm_request_irq(&pdev->dev, irq, atmel_qspi_interrupt,
745			       0, dev_name(&pdev->dev), aq);
746	if (err)
747		goto disable_qspick;
748
749	pm_runtime_set_autosuspend_delay(&pdev->dev, 500);
750	pm_runtime_use_autosuspend(&pdev->dev);
751	pm_runtime_set_active(&pdev->dev);
752	pm_runtime_enable(&pdev->dev);
753	pm_runtime_get_noresume(&pdev->dev);
754
755	atmel_qspi_init(aq);
756
757	err = spi_register_controller(ctrl);
758	if (err) {
759		pm_runtime_put_noidle(&pdev->dev);
760		pm_runtime_disable(&pdev->dev);
761		pm_runtime_set_suspended(&pdev->dev);
762		pm_runtime_dont_use_autosuspend(&pdev->dev);
763		goto disable_qspick;
764	}
765	pm_runtime_mark_last_busy(&pdev->dev);
766	pm_runtime_put_autosuspend(&pdev->dev);
767
768	return 0;
769
770disable_qspick:
771	clk_disable_unprepare(aq->qspick);
772disable_pclk:
773	clk_disable_unprepare(aq->pclk);
 
 
774
775	return err;
776}
777
778static void atmel_qspi_remove(struct platform_device *pdev)
779{
780	struct spi_controller *ctrl = platform_get_drvdata(pdev);
781	struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
782	int ret;
783
784	spi_unregister_controller(ctrl);
785
786	ret = pm_runtime_get_sync(&pdev->dev);
787	if (ret >= 0) {
788		atmel_qspi_write(QSPI_CR_QSPIDIS, aq, QSPI_CR);
789		clk_disable(aq->qspick);
790		clk_disable(aq->pclk);
791	} else {
792		/*
793		 * atmel_qspi_runtime_{suspend,resume} just disable and enable
794		 * the two clks respectively. So after resume failed these are
795		 * off, and we skip hardware access and disabling these clks again.
796		 */
797		dev_warn(&pdev->dev, "Failed to resume device on remove\n");
798	}
799
800	clk_unprepare(aq->qspick);
801	clk_unprepare(aq->pclk);
802
803	pm_runtime_disable(&pdev->dev);
804	pm_runtime_dont_use_autosuspend(&pdev->dev);
805	pm_runtime_put_noidle(&pdev->dev);
806}
807
808static int __maybe_unused atmel_qspi_suspend(struct device *dev)
809{
810	struct spi_controller *ctrl = dev_get_drvdata(dev);
811	struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
812	int ret;
813
814	ret = pm_runtime_resume_and_get(dev);
815	if (ret < 0)
816		return ret;
817
818	atmel_qspi_write(QSPI_CR_QSPIDIS, aq, QSPI_CR);
819
820	pm_runtime_mark_last_busy(dev);
821	pm_runtime_force_suspend(dev);
822
823	clk_unprepare(aq->qspick);
824	clk_unprepare(aq->pclk);
825
826	return 0;
827}
828
829static int __maybe_unused atmel_qspi_resume(struct device *dev)
830{
831	struct spi_controller *ctrl = dev_get_drvdata(dev);
832	struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
833	int ret;
834
835	ret = clk_prepare(aq->pclk);
836	if (ret)
837		return ret;
838
839	ret = clk_prepare(aq->qspick);
840	if (ret) {
841		clk_unprepare(aq->pclk);
842		return ret;
843	}
844
845	ret = pm_runtime_force_resume(dev);
846	if (ret < 0)
847		return ret;
848
849	atmel_qspi_init(aq);
850
851	atmel_qspi_write(aq->scr, aq, QSPI_SCR);
852
853	pm_runtime_mark_last_busy(dev);
854	pm_runtime_put_autosuspend(dev);
855
856	return 0;
857}
858
859static int __maybe_unused atmel_qspi_runtime_suspend(struct device *dev)
860{
861	struct spi_controller *ctrl = dev_get_drvdata(dev);
862	struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
863
864	clk_disable(aq->qspick);
865	clk_disable(aq->pclk);
866
867	return 0;
868}
869
870static int __maybe_unused atmel_qspi_runtime_resume(struct device *dev)
871{
872	struct spi_controller *ctrl = dev_get_drvdata(dev);
873	struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
874	int ret;
875
876	ret = clk_enable(aq->pclk);
877	if (ret)
878		return ret;
879
880	ret = clk_enable(aq->qspick);
881	if (ret)
882		clk_disable(aq->pclk);
883
884	return ret;
885}
886
887static const struct dev_pm_ops __maybe_unused atmel_qspi_pm_ops = {
888	SET_SYSTEM_SLEEP_PM_OPS(atmel_qspi_suspend, atmel_qspi_resume)
889	SET_RUNTIME_PM_OPS(atmel_qspi_runtime_suspend,
890			   atmel_qspi_runtime_resume, NULL)
891};
892
893static const struct atmel_qspi_caps atmel_sama5d2_qspi_caps = {};
894
895static const struct atmel_qspi_caps atmel_sam9x60_qspi_caps = {
896	.has_qspick = true,
897	.has_ricr = true,
898};
899
900static const struct of_device_id atmel_qspi_dt_ids[] = {
901	{
902		.compatible = "atmel,sama5d2-qspi",
903		.data = &atmel_sama5d2_qspi_caps,
904	},
905	{
906		.compatible = "microchip,sam9x60-qspi",
907		.data = &atmel_sam9x60_qspi_caps,
908	},
909	{ /* sentinel */ }
910};
911
912MODULE_DEVICE_TABLE(of, atmel_qspi_dt_ids);
913
914static struct platform_driver atmel_qspi_driver = {
915	.driver = {
916		.name	= "atmel_qspi",
917		.of_match_table	= atmel_qspi_dt_ids,
918		.pm	= pm_ptr(&atmel_qspi_pm_ops),
919	},
920	.probe		= atmel_qspi_probe,
921	.remove		= atmel_qspi_remove,
922};
923module_platform_driver(atmel_qspi_driver);
924
925MODULE_AUTHOR("Cyrille Pitchen <cyrille.pitchen@atmel.com>");
926MODULE_AUTHOR("Piotr Bugalski <bugalski.piotr@gmail.com");
927MODULE_DESCRIPTION("Atmel QSPI Controller driver");
928MODULE_LICENSE("GPL v2");