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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * ACPI probing code for ARM performance counters.
4 *
5 * Copyright (C) 2017 ARM Ltd.
6 */
7
8#include <linux/acpi.h>
9#include <linux/cpumask.h>
10#include <linux/init.h>
11#include <linux/irq.h>
12#include <linux/irqdesc.h>
13#include <linux/percpu.h>
14#include <linux/perf/arm_pmu.h>
15
16#include <asm/cpu.h>
17#include <asm/cputype.h>
18
19static DEFINE_PER_CPU(struct arm_pmu *, probed_pmus);
20static DEFINE_PER_CPU(int, pmu_irqs);
21
22static int arm_pmu_acpi_register_irq(int cpu)
23{
24 struct acpi_madt_generic_interrupt *gicc;
25 int gsi, trigger;
26
27 gicc = acpi_cpu_get_madt_gicc(cpu);
28
29 gsi = gicc->performance_interrupt;
30
31 /*
32 * Per the ACPI spec, the MADT cannot describe a PMU that doesn't
33 * have an interrupt. QEMU advertises this by using a GSI of zero,
34 * which is not known to be valid on any hardware despite being
35 * valid per the spec. Take the pragmatic approach and reject a
36 * GSI of zero for now.
37 */
38 if (!gsi)
39 return 0;
40
41 if (gicc->flags & ACPI_MADT_PERFORMANCE_IRQ_MODE)
42 trigger = ACPI_EDGE_SENSITIVE;
43 else
44 trigger = ACPI_LEVEL_SENSITIVE;
45
46 /*
47 * Helpfully, the MADT GICC doesn't have a polarity flag for the
48 * "performance interrupt". Luckily, on compliant GICs the polarity is
49 * a fixed value in HW (for both SPIs and PPIs) that we cannot change
50 * from SW.
51 *
52 * Here we pass in ACPI_ACTIVE_HIGH to keep the core code happy. This
53 * may not match the real polarity, but that should not matter.
54 *
55 * Other interrupt controllers are not supported with ACPI.
56 */
57 return acpi_register_gsi(NULL, gsi, trigger, ACPI_ACTIVE_HIGH);
58}
59
60static void arm_pmu_acpi_unregister_irq(int cpu)
61{
62 struct acpi_madt_generic_interrupt *gicc;
63 int gsi;
64
65 gicc = acpi_cpu_get_madt_gicc(cpu);
66
67 gsi = gicc->performance_interrupt;
68 if (gsi)
69 acpi_unregister_gsi(gsi);
70}
71
72static int __maybe_unused
73arm_acpi_register_pmu_device(struct platform_device *pdev, u8 len,
74 u16 (*parse_gsi)(struct acpi_madt_generic_interrupt *))
75{
76 int cpu, this_hetid, hetid, irq, ret;
77 u16 this_gsi = 0, gsi = 0;
78
79 /*
80 * Ensure that platform device must have IORESOURCE_IRQ
81 * resource to hold gsi interrupt.
82 */
83 if (pdev->num_resources != 1)
84 return -ENXIO;
85
86 if (pdev->resource[0].flags != IORESOURCE_IRQ)
87 return -ENXIO;
88
89 /*
90 * Sanity check all the GICC tables for the same interrupt
91 * number. For now, only support homogeneous ACPI machines.
92 */
93 for_each_possible_cpu(cpu) {
94 struct acpi_madt_generic_interrupt *gicc;
95
96 gicc = acpi_cpu_get_madt_gicc(cpu);
97 if (gicc->header.length < len)
98 return gsi ? -ENXIO : 0;
99
100 this_gsi = parse_gsi(gicc);
101 this_hetid = find_acpi_cpu_topology_hetero_id(cpu);
102 if (!gsi) {
103 hetid = this_hetid;
104 gsi = this_gsi;
105 } else if (hetid != this_hetid || gsi != this_gsi) {
106 pr_warn("ACPI: %s: must be homogeneous\n", pdev->name);
107 return -ENXIO;
108 }
109 }
110
111 if (!this_gsi)
112 return 0;
113
114 irq = acpi_register_gsi(NULL, gsi, ACPI_LEVEL_SENSITIVE, ACPI_ACTIVE_HIGH);
115 if (irq < 0) {
116 pr_warn("ACPI: %s Unable to register interrupt: %d\n", pdev->name, gsi);
117 return -ENXIO;
118 }
119
120 pdev->resource[0].start = irq;
121 ret = platform_device_register(pdev);
122 if (ret)
123 acpi_unregister_gsi(gsi);
124
125 return ret;
126}
127
128#if IS_ENABLED(CONFIG_ARM_SPE_PMU)
129static struct resource spe_resources[] = {
130 {
131 /* irq */
132 .flags = IORESOURCE_IRQ,
133 }
134};
135
136static struct platform_device spe_dev = {
137 .name = ARMV8_SPE_PDEV_NAME,
138 .id = -1,
139 .resource = spe_resources,
140 .num_resources = ARRAY_SIZE(spe_resources)
141};
142
143static u16 arm_spe_parse_gsi(struct acpi_madt_generic_interrupt *gicc)
144{
145 return gicc->spe_interrupt;
146}
147
148/*
149 * For lack of a better place, hook the normal PMU MADT walk
150 * and create a SPE device if we detect a recent MADT with
151 * a homogeneous PPI mapping.
152 */
153static void arm_spe_acpi_register_device(void)
154{
155 int ret = arm_acpi_register_pmu_device(&spe_dev, ACPI_MADT_GICC_SPE,
156 arm_spe_parse_gsi);
157 if (ret)
158 pr_warn("ACPI: SPE: Unable to register device\n");
159}
160#else
161static inline void arm_spe_acpi_register_device(void)
162{
163}
164#endif /* CONFIG_ARM_SPE_PMU */
165
166#if IS_ENABLED(CONFIG_CORESIGHT_TRBE)
167static struct resource trbe_resources[] = {
168 {
169 /* irq */
170 .flags = IORESOURCE_IRQ,
171 }
172};
173
174static struct platform_device trbe_dev = {
175 .name = ARMV8_TRBE_PDEV_NAME,
176 .id = -1,
177 .resource = trbe_resources,
178 .num_resources = ARRAY_SIZE(trbe_resources)
179};
180
181static u16 arm_trbe_parse_gsi(struct acpi_madt_generic_interrupt *gicc)
182{
183 return gicc->trbe_interrupt;
184}
185
186static void arm_trbe_acpi_register_device(void)
187{
188 int ret = arm_acpi_register_pmu_device(&trbe_dev, ACPI_MADT_GICC_TRBE,
189 arm_trbe_parse_gsi);
190 if (ret)
191 pr_warn("ACPI: TRBE: Unable to register device\n");
192}
193#else
194static inline void arm_trbe_acpi_register_device(void)
195{
196
197}
198#endif /* CONFIG_CORESIGHT_TRBE */
199
200static int arm_pmu_acpi_parse_irqs(void)
201{
202 int irq, cpu, irq_cpu, err;
203
204 for_each_possible_cpu(cpu) {
205 irq = arm_pmu_acpi_register_irq(cpu);
206 if (irq < 0) {
207 err = irq;
208 pr_warn("Unable to parse ACPI PMU IRQ for CPU%d: %d\n",
209 cpu, err);
210 goto out_err;
211 } else if (irq == 0) {
212 pr_warn("No ACPI PMU IRQ for CPU%d\n", cpu);
213 }
214
215 /*
216 * Log and request the IRQ so the core arm_pmu code can manage
217 * it. We'll have to sanity-check IRQs later when we associate
218 * them with their PMUs.
219 */
220 per_cpu(pmu_irqs, cpu) = irq;
221 err = armpmu_request_irq(irq, cpu);
222 if (err)
223 goto out_err;
224 }
225
226 return 0;
227
228out_err:
229 for_each_possible_cpu(cpu) {
230 irq = per_cpu(pmu_irqs, cpu);
231 if (!irq)
232 continue;
233
234 arm_pmu_acpi_unregister_irq(cpu);
235
236 /*
237 * Blat all copies of the IRQ so that we only unregister the
238 * corresponding GSI once (e.g. when we have PPIs).
239 */
240 for_each_possible_cpu(irq_cpu) {
241 if (per_cpu(pmu_irqs, irq_cpu) == irq)
242 per_cpu(pmu_irqs, irq_cpu) = 0;
243 }
244 }
245
246 return err;
247}
248
249static struct arm_pmu *arm_pmu_acpi_find_pmu(void)
250{
251 unsigned long cpuid = read_cpuid_id();
252 struct arm_pmu *pmu;
253 int cpu;
254
255 for_each_possible_cpu(cpu) {
256 pmu = per_cpu(probed_pmus, cpu);
257 if (!pmu || pmu->acpi_cpuid != cpuid)
258 continue;
259
260 return pmu;
261 }
262
263 return NULL;
264}
265
266/*
267 * Check whether the new IRQ is compatible with those already associated with
268 * the PMU (e.g. we don't have mismatched PPIs).
269 */
270static bool pmu_irq_matches(struct arm_pmu *pmu, int irq)
271{
272 struct pmu_hw_events __percpu *hw_events = pmu->hw_events;
273 int cpu;
274
275 if (!irq)
276 return true;
277
278 for_each_cpu(cpu, &pmu->supported_cpus) {
279 int other_irq = per_cpu(hw_events->irq, cpu);
280 if (!other_irq)
281 continue;
282
283 if (irq == other_irq)
284 continue;
285 if (!irq_is_percpu_devid(irq) && !irq_is_percpu_devid(other_irq))
286 continue;
287
288 pr_warn("mismatched PPIs detected\n");
289 return false;
290 }
291
292 return true;
293}
294
295static void arm_pmu_acpi_associate_pmu_cpu(struct arm_pmu *pmu,
296 unsigned int cpu)
297{
298 int irq = per_cpu(pmu_irqs, cpu);
299
300 per_cpu(probed_pmus, cpu) = pmu;
301
302 if (pmu_irq_matches(pmu, irq)) {
303 struct pmu_hw_events __percpu *hw_events;
304 hw_events = pmu->hw_events;
305 per_cpu(hw_events->irq, cpu) = irq;
306 }
307
308 cpumask_set_cpu(cpu, &pmu->supported_cpus);
309}
310
311/*
312 * This must run before the common arm_pmu hotplug logic, so that we can
313 * associate a CPU and its interrupt before the common code tries to manage the
314 * affinity and so on.
315 *
316 * Note that hotplug events are serialized, so we cannot race with another CPU
317 * coming up. The perf core won't open events while a hotplug event is in
318 * progress.
319 */
320static int arm_pmu_acpi_cpu_starting(unsigned int cpu)
321{
322 struct arm_pmu *pmu;
323
324 /* If we've already probed this CPU, we have nothing to do */
325 if (per_cpu(probed_pmus, cpu))
326 return 0;
327
328 pmu = arm_pmu_acpi_find_pmu();
329 if (!pmu) {
330 pr_warn_ratelimited("Unable to associate CPU%d with a PMU\n",
331 cpu);
332 return 0;
333 }
334
335 arm_pmu_acpi_associate_pmu_cpu(pmu, cpu);
336 return 0;
337}
338
339static void arm_pmu_acpi_probe_matching_cpus(struct arm_pmu *pmu,
340 unsigned long cpuid)
341{
342 int cpu;
343
344 for_each_online_cpu(cpu) {
345 unsigned long cpu_cpuid = per_cpu(cpu_data, cpu).reg_midr;
346
347 if (cpu_cpuid == cpuid)
348 arm_pmu_acpi_associate_pmu_cpu(pmu, cpu);
349 }
350}
351
352int arm_pmu_acpi_probe(armpmu_init_fn init_fn)
353{
354 int pmu_idx = 0;
355 unsigned int cpu;
356 int ret;
357
358 ret = arm_pmu_acpi_parse_irqs();
359 if (ret)
360 return ret;
361
362 ret = cpuhp_setup_state_nocalls(CPUHP_AP_PERF_ARM_ACPI_STARTING,
363 "perf/arm/pmu_acpi:starting",
364 arm_pmu_acpi_cpu_starting, NULL);
365 if (ret)
366 return ret;
367
368 /*
369 * Initialise and register the set of PMUs which we know about right
370 * now. Ideally we'd do this in arm_pmu_acpi_cpu_starting() so that we
371 * could handle late hotplug, but this may lead to deadlock since we
372 * might try to register a hotplug notifier instance from within a
373 * hotplug notifier.
374 *
375 * There's also the problem of having access to the right init_fn,
376 * without tying this too deeply into the "real" PMU driver.
377 *
378 * For the moment, as with the platform/DT case, we need at least one
379 * of a PMU's CPUs to be online at probe time.
380 */
381 for_each_online_cpu(cpu) {
382 struct arm_pmu *pmu = per_cpu(probed_pmus, cpu);
383 unsigned long cpuid;
384 char *base_name;
385
386 /* If we've already probed this CPU, we have nothing to do */
387 if (pmu)
388 continue;
389
390 pmu = armpmu_alloc();
391 if (!pmu) {
392 pr_warn("Unable to allocate PMU for CPU%d\n",
393 cpu);
394 return -ENOMEM;
395 }
396
397 cpuid = per_cpu(cpu_data, cpu).reg_midr;
398 pmu->acpi_cpuid = cpuid;
399
400 arm_pmu_acpi_probe_matching_cpus(pmu, cpuid);
401
402 ret = init_fn(pmu);
403 if (ret == -ENODEV) {
404 /* PMU not handled by this driver, or not present */
405 continue;
406 } else if (ret) {
407 pr_warn("Unable to initialise PMU for CPU%d\n", cpu);
408 return ret;
409 }
410
411 base_name = pmu->name;
412 pmu->name = kasprintf(GFP_KERNEL, "%s_%d", base_name, pmu_idx++);
413 if (!pmu->name) {
414 pr_warn("Unable to allocate PMU name for CPU%d\n", cpu);
415 return -ENOMEM;
416 }
417
418 ret = armpmu_register(pmu);
419 if (ret) {
420 pr_warn("Failed to register PMU for CPU%d\n", cpu);
421 kfree(pmu->name);
422 return ret;
423 }
424 }
425
426 return ret;
427}
428
429static int arm_pmu_acpi_init(void)
430{
431 if (acpi_disabled)
432 return 0;
433
434 arm_spe_acpi_register_device();
435 arm_trbe_acpi_register_device();
436
437 return 0;
438}
439subsys_initcall(arm_pmu_acpi_init)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * ACPI probing code for ARM performance counters.
4 *
5 * Copyright (C) 2017 ARM Ltd.
6 */
7
8#include <linux/acpi.h>
9#include <linux/cpumask.h>
10#include <linux/init.h>
11#include <linux/irq.h>
12#include <linux/irqdesc.h>
13#include <linux/percpu.h>
14#include <linux/perf/arm_pmu.h>
15
16#include <asm/cputype.h>
17
18static DEFINE_PER_CPU(struct arm_pmu *, probed_pmus);
19static DEFINE_PER_CPU(int, pmu_irqs);
20
21static int arm_pmu_acpi_register_irq(int cpu)
22{
23 struct acpi_madt_generic_interrupt *gicc;
24 int gsi, trigger;
25
26 gicc = acpi_cpu_get_madt_gicc(cpu);
27 if (WARN_ON(!gicc))
28 return -EINVAL;
29
30 gsi = gicc->performance_interrupt;
31
32 /*
33 * Per the ACPI spec, the MADT cannot describe a PMU that doesn't
34 * have an interrupt. QEMU advertises this by using a GSI of zero,
35 * which is not known to be valid on any hardware despite being
36 * valid per the spec. Take the pragmatic approach and reject a
37 * GSI of zero for now.
38 */
39 if (!gsi)
40 return 0;
41
42 if (gicc->flags & ACPI_MADT_PERFORMANCE_IRQ_MODE)
43 trigger = ACPI_EDGE_SENSITIVE;
44 else
45 trigger = ACPI_LEVEL_SENSITIVE;
46
47 /*
48 * Helpfully, the MADT GICC doesn't have a polarity flag for the
49 * "performance interrupt". Luckily, on compliant GICs the polarity is
50 * a fixed value in HW (for both SPIs and PPIs) that we cannot change
51 * from SW.
52 *
53 * Here we pass in ACPI_ACTIVE_HIGH to keep the core code happy. This
54 * may not match the real polarity, but that should not matter.
55 *
56 * Other interrupt controllers are not supported with ACPI.
57 */
58 return acpi_register_gsi(NULL, gsi, trigger, ACPI_ACTIVE_HIGH);
59}
60
61static void arm_pmu_acpi_unregister_irq(int cpu)
62{
63 struct acpi_madt_generic_interrupt *gicc;
64 int gsi;
65
66 gicc = acpi_cpu_get_madt_gicc(cpu);
67 if (!gicc)
68 return;
69
70 gsi = gicc->performance_interrupt;
71 acpi_unregister_gsi(gsi);
72}
73
74#if IS_ENABLED(CONFIG_ARM_SPE_PMU)
75static struct resource spe_resources[] = {
76 {
77 /* irq */
78 .flags = IORESOURCE_IRQ,
79 }
80};
81
82static struct platform_device spe_dev = {
83 .name = ARMV8_SPE_PDEV_NAME,
84 .id = -1,
85 .resource = spe_resources,
86 .num_resources = ARRAY_SIZE(spe_resources)
87};
88
89/*
90 * For lack of a better place, hook the normal PMU MADT walk
91 * and create a SPE device if we detect a recent MADT with
92 * a homogeneous PPI mapping.
93 */
94static void arm_spe_acpi_register_device(void)
95{
96 int cpu, hetid, irq, ret;
97 bool first = true;
98 u16 gsi = 0;
99
100 /*
101 * Sanity check all the GICC tables for the same interrupt number.
102 * For now, we only support homogeneous ACPI/SPE machines.
103 */
104 for_each_possible_cpu(cpu) {
105 struct acpi_madt_generic_interrupt *gicc;
106
107 gicc = acpi_cpu_get_madt_gicc(cpu);
108 if (gicc->header.length < ACPI_MADT_GICC_SPE)
109 return;
110
111 if (first) {
112 gsi = gicc->spe_interrupt;
113 if (!gsi)
114 return;
115 hetid = find_acpi_cpu_topology_hetero_id(cpu);
116 first = false;
117 } else if ((gsi != gicc->spe_interrupt) ||
118 (hetid != find_acpi_cpu_topology_hetero_id(cpu))) {
119 pr_warn("ACPI: SPE must be homogeneous\n");
120 return;
121 }
122 }
123
124 irq = acpi_register_gsi(NULL, gsi, ACPI_LEVEL_SENSITIVE,
125 ACPI_ACTIVE_HIGH);
126 if (irq < 0) {
127 pr_warn("ACPI: SPE Unable to register interrupt: %d\n", gsi);
128 return;
129 }
130
131 spe_resources[0].start = irq;
132 ret = platform_device_register(&spe_dev);
133 if (ret < 0) {
134 pr_warn("ACPI: SPE: Unable to register device\n");
135 acpi_unregister_gsi(gsi);
136 }
137}
138#else
139static inline void arm_spe_acpi_register_device(void)
140{
141}
142#endif /* CONFIG_ARM_SPE_PMU */
143
144static int arm_pmu_acpi_parse_irqs(void)
145{
146 int irq, cpu, irq_cpu, err;
147
148 for_each_possible_cpu(cpu) {
149 irq = arm_pmu_acpi_register_irq(cpu);
150 if (irq < 0) {
151 err = irq;
152 pr_warn("Unable to parse ACPI PMU IRQ for CPU%d: %d\n",
153 cpu, err);
154 goto out_err;
155 } else if (irq == 0) {
156 pr_warn("No ACPI PMU IRQ for CPU%d\n", cpu);
157 }
158
159 /*
160 * Log and request the IRQ so the core arm_pmu code can manage
161 * it. We'll have to sanity-check IRQs later when we associate
162 * them with their PMUs.
163 */
164 per_cpu(pmu_irqs, cpu) = irq;
165 armpmu_request_irq(irq, cpu);
166 }
167
168 return 0;
169
170out_err:
171 for_each_possible_cpu(cpu) {
172 irq = per_cpu(pmu_irqs, cpu);
173 if (!irq)
174 continue;
175
176 arm_pmu_acpi_unregister_irq(cpu);
177
178 /*
179 * Blat all copies of the IRQ so that we only unregister the
180 * corresponding GSI once (e.g. when we have PPIs).
181 */
182 for_each_possible_cpu(irq_cpu) {
183 if (per_cpu(pmu_irqs, irq_cpu) == irq)
184 per_cpu(pmu_irqs, irq_cpu) = 0;
185 }
186 }
187
188 return err;
189}
190
191static struct arm_pmu *arm_pmu_acpi_find_alloc_pmu(void)
192{
193 unsigned long cpuid = read_cpuid_id();
194 struct arm_pmu *pmu;
195 int cpu;
196
197 for_each_possible_cpu(cpu) {
198 pmu = per_cpu(probed_pmus, cpu);
199 if (!pmu || pmu->acpi_cpuid != cpuid)
200 continue;
201
202 return pmu;
203 }
204
205 pmu = armpmu_alloc_atomic();
206 if (!pmu) {
207 pr_warn("Unable to allocate PMU for CPU%d\n",
208 smp_processor_id());
209 return NULL;
210 }
211
212 pmu->acpi_cpuid = cpuid;
213
214 return pmu;
215}
216
217/*
218 * Check whether the new IRQ is compatible with those already associated with
219 * the PMU (e.g. we don't have mismatched PPIs).
220 */
221static bool pmu_irq_matches(struct arm_pmu *pmu, int irq)
222{
223 struct pmu_hw_events __percpu *hw_events = pmu->hw_events;
224 int cpu;
225
226 if (!irq)
227 return true;
228
229 for_each_cpu(cpu, &pmu->supported_cpus) {
230 int other_irq = per_cpu(hw_events->irq, cpu);
231 if (!other_irq)
232 continue;
233
234 if (irq == other_irq)
235 continue;
236 if (!irq_is_percpu_devid(irq) && !irq_is_percpu_devid(other_irq))
237 continue;
238
239 pr_warn("mismatched PPIs detected\n");
240 return false;
241 }
242
243 return true;
244}
245
246/*
247 * This must run before the common arm_pmu hotplug logic, so that we can
248 * associate a CPU and its interrupt before the common code tries to manage the
249 * affinity and so on.
250 *
251 * Note that hotplug events are serialized, so we cannot race with another CPU
252 * coming up. The perf core won't open events while a hotplug event is in
253 * progress.
254 */
255static int arm_pmu_acpi_cpu_starting(unsigned int cpu)
256{
257 struct arm_pmu *pmu;
258 struct pmu_hw_events __percpu *hw_events;
259 int irq;
260
261 /* If we've already probed this CPU, we have nothing to do */
262 if (per_cpu(probed_pmus, cpu))
263 return 0;
264
265 irq = per_cpu(pmu_irqs, cpu);
266
267 pmu = arm_pmu_acpi_find_alloc_pmu();
268 if (!pmu)
269 return -ENOMEM;
270
271 per_cpu(probed_pmus, cpu) = pmu;
272
273 if (pmu_irq_matches(pmu, irq)) {
274 hw_events = pmu->hw_events;
275 per_cpu(hw_events->irq, cpu) = irq;
276 }
277
278 cpumask_set_cpu(cpu, &pmu->supported_cpus);
279
280 /*
281 * Ideally, we'd probe the PMU here when we find the first matching
282 * CPU. We can't do that for several reasons; see the comment in
283 * arm_pmu_acpi_init().
284 *
285 * So for the time being, we're done.
286 */
287 return 0;
288}
289
290int arm_pmu_acpi_probe(armpmu_init_fn init_fn)
291{
292 int pmu_idx = 0;
293 int cpu, ret;
294
295 /*
296 * Initialise and register the set of PMUs which we know about right
297 * now. Ideally we'd do this in arm_pmu_acpi_cpu_starting() so that we
298 * could handle late hotplug, but this may lead to deadlock since we
299 * might try to register a hotplug notifier instance from within a
300 * hotplug notifier.
301 *
302 * There's also the problem of having access to the right init_fn,
303 * without tying this too deeply into the "real" PMU driver.
304 *
305 * For the moment, as with the platform/DT case, we need at least one
306 * of a PMU's CPUs to be online at probe time.
307 */
308 for_each_possible_cpu(cpu) {
309 struct arm_pmu *pmu = per_cpu(probed_pmus, cpu);
310 char *base_name;
311
312 if (!pmu || pmu->name)
313 continue;
314
315 ret = init_fn(pmu);
316 if (ret == -ENODEV) {
317 /* PMU not handled by this driver, or not present */
318 continue;
319 } else if (ret) {
320 pr_warn("Unable to initialise PMU for CPU%d\n", cpu);
321 return ret;
322 }
323
324 base_name = pmu->name;
325 pmu->name = kasprintf(GFP_KERNEL, "%s_%d", base_name, pmu_idx++);
326 if (!pmu->name) {
327 pr_warn("Unable to allocate PMU name for CPU%d\n", cpu);
328 return -ENOMEM;
329 }
330
331 ret = armpmu_register(pmu);
332 if (ret) {
333 pr_warn("Failed to register PMU for CPU%d\n", cpu);
334 kfree(pmu->name);
335 return ret;
336 }
337 }
338
339 return 0;
340}
341
342static int arm_pmu_acpi_init(void)
343{
344 int ret;
345
346 if (acpi_disabled)
347 return 0;
348
349 arm_spe_acpi_register_device();
350
351 ret = arm_pmu_acpi_parse_irqs();
352 if (ret)
353 return ret;
354
355 ret = cpuhp_setup_state(CPUHP_AP_PERF_ARM_ACPI_STARTING,
356 "perf/arm/pmu_acpi:starting",
357 arm_pmu_acpi_cpu_starting, NULL);
358
359 return ret;
360}
361subsys_initcall(arm_pmu_acpi_init)